config.ini revision 11570
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=atomic 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=AtomicSimpleCPU 58children=checker dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload 59branchPred=Null 60checker=system.cpu.checker 61clk_domain=system.cpu_clk_domain 62cpu_id=0 63default_p_state=UNDEFINED 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dstage2_mmu=system.cpu.dstage2_mmu 68dtb=system.cpu.dtb 69eventq_index=0 70fastmem=false 71function_trace=false 72function_trace_start=0 73interrupts=system.cpu.interrupts 74isa=system.cpu.isa 75istage2_mmu=system.cpu.istage2_mmu 76itb=system.cpu.itb 77max_insts_all_threads=0 78max_insts_any_thread=0 79max_loads_all_threads=0 80max_loads_any_thread=0 81numThreads=1 82p_state_clk_gate_bins=20 83p_state_clk_gate_max=1000000000000 84p_state_clk_gate_min=1000 85power_model=Null 86profile=0 87progress_interval=0 88simpoint_start_insts= 89simulate_data_stalls=false 90simulate_inst_stalls=false 91socket_id=0 92switched_out=false 93system=system 94tracer=system.cpu.tracer 95width=1 96workload=system.cpu.workload 97dcache_port=system.membus.slave[2] 98icache_port=system.membus.slave[1] 99 100[system.cpu.checker] 101type=DummyChecker 102children=dstage2_mmu dtb isa istage2_mmu itb tracer 103checker=Null 104clk_domain=system.cpu_clk_domain 105cpu_id=-1 106default_p_state=UNDEFINED 107do_checkpoint_insts=true 108do_quiesce=true 109do_statistics_insts=true 110dstage2_mmu=system.cpu.checker.dstage2_mmu 111dtb=system.cpu.checker.dtb 112eventq_index=0 113exitOnError=false 114function_trace=false 115function_trace_start=0 116interrupts= 117isa=system.cpu.checker.isa 118istage2_mmu=system.cpu.checker.istage2_mmu 119itb=system.cpu.checker.itb 120max_insts_all_threads=0 121max_insts_any_thread=0 122max_loads_all_threads=0 123max_loads_any_thread=0 124numThreads=1 125p_state_clk_gate_bins=20 126p_state_clk_gate_max=1000000000000 127p_state_clk_gate_min=1000 128power_model=Null 129profile=0 130progress_interval=0 131simpoint_start_insts= 132socket_id=0 133switched_out=false 134system=system 135tracer=system.cpu.checker.tracer 136updateOnError=false 137warnOnlyOnLoadError=true 138workload=system.cpu.workload 139 140[system.cpu.checker.dstage2_mmu] 141type=ArmStage2MMU 142children=stage2_tlb 143eventq_index=0 144stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb 145sys=system 146tlb=system.cpu.checker.dtb 147 148[system.cpu.checker.dstage2_mmu.stage2_tlb] 149type=ArmTLB 150children=walker 151eventq_index=0 152is_stage2=true 153size=32 154walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker 155 156[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] 157type=ArmTableWalker 158clk_domain=system.cpu_clk_domain 159default_p_state=UNDEFINED 160eventq_index=0 161is_stage2=true 162num_squash_per_cycle=2 163p_state_clk_gate_bins=20 164p_state_clk_gate_max=1000000000000 165p_state_clk_gate_min=1000 166power_model=Null 167sys=system 168 169[system.cpu.checker.dtb] 170type=ArmTLB 171children=walker 172eventq_index=0 173is_stage2=false 174size=64 175walker=system.cpu.checker.dtb.walker 176 177[system.cpu.checker.dtb.walker] 178type=ArmTableWalker 179clk_domain=system.cpu_clk_domain 180default_p_state=UNDEFINED 181eventq_index=0 182is_stage2=false 183num_squash_per_cycle=2 184p_state_clk_gate_bins=20 185p_state_clk_gate_max=1000000000000 186p_state_clk_gate_min=1000 187power_model=Null 188sys=system 189 190[system.cpu.checker.isa] 191type=ArmISA 192decoderFlavour=Generic 193eventq_index=0 194fpsid=1090793632 195id_aa64afr0_el1=0 196id_aa64afr1_el1=0 197id_aa64dfr0_el1=1052678 198id_aa64dfr1_el1=0 199id_aa64isar0_el1=0 200id_aa64isar1_el1=0 201id_aa64mmfr0_el1=15728642 202id_aa64mmfr1_el1=0 203id_aa64pfr0_el1=17 204id_aa64pfr1_el1=0 205id_isar0=34607377 206id_isar1=34677009 207id_isar2=555950401 208id_isar3=17899825 209id_isar4=268501314 210id_isar5=0 211id_mmfr0=270536963 212id_mmfr1=0 213id_mmfr2=19070976 214id_mmfr3=34611729 215id_pfr0=49 216id_pfr1=4113 217midr=1091551472 218pmu=Null 219system=system 220 221[system.cpu.checker.istage2_mmu] 222type=ArmStage2MMU 223children=stage2_tlb 224eventq_index=0 225stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb 226sys=system 227tlb=system.cpu.checker.itb 228 229[system.cpu.checker.istage2_mmu.stage2_tlb] 230type=ArmTLB 231children=walker 232eventq_index=0 233is_stage2=true 234size=32 235walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker 236 237[system.cpu.checker.istage2_mmu.stage2_tlb.walker] 238type=ArmTableWalker 239clk_domain=system.cpu_clk_domain 240default_p_state=UNDEFINED 241eventq_index=0 242is_stage2=true 243num_squash_per_cycle=2 244p_state_clk_gate_bins=20 245p_state_clk_gate_max=1000000000000 246p_state_clk_gate_min=1000 247power_model=Null 248sys=system 249 250[system.cpu.checker.itb] 251type=ArmTLB 252children=walker 253eventq_index=0 254is_stage2=false 255size=64 256walker=system.cpu.checker.itb.walker 257 258[system.cpu.checker.itb.walker] 259type=ArmTableWalker 260clk_domain=system.cpu_clk_domain 261default_p_state=UNDEFINED 262eventq_index=0 263is_stage2=false 264num_squash_per_cycle=2 265p_state_clk_gate_bins=20 266p_state_clk_gate_max=1000000000000 267p_state_clk_gate_min=1000 268power_model=Null 269sys=system 270 271[system.cpu.checker.tracer] 272type=ExeTracer 273eventq_index=0 274 275[system.cpu.dstage2_mmu] 276type=ArmStage2MMU 277children=stage2_tlb 278eventq_index=0 279stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 280sys=system 281tlb=system.cpu.dtb 282 283[system.cpu.dstage2_mmu.stage2_tlb] 284type=ArmTLB 285children=walker 286eventq_index=0 287is_stage2=true 288size=32 289walker=system.cpu.dstage2_mmu.stage2_tlb.walker 290 291[system.cpu.dstage2_mmu.stage2_tlb.walker] 292type=ArmTableWalker 293clk_domain=system.cpu_clk_domain 294default_p_state=UNDEFINED 295eventq_index=0 296is_stage2=true 297num_squash_per_cycle=2 298p_state_clk_gate_bins=20 299p_state_clk_gate_max=1000000000000 300p_state_clk_gate_min=1000 301power_model=Null 302sys=system 303 304[system.cpu.dtb] 305type=ArmTLB 306children=walker 307eventq_index=0 308is_stage2=false 309size=64 310walker=system.cpu.dtb.walker 311 312[system.cpu.dtb.walker] 313type=ArmTableWalker 314clk_domain=system.cpu_clk_domain 315default_p_state=UNDEFINED 316eventq_index=0 317is_stage2=false 318num_squash_per_cycle=2 319p_state_clk_gate_bins=20 320p_state_clk_gate_max=1000000000000 321p_state_clk_gate_min=1000 322power_model=Null 323sys=system 324port=system.membus.slave[4] 325 326[system.cpu.interrupts] 327type=ArmInterrupts 328eventq_index=0 329 330[system.cpu.isa] 331type=ArmISA 332decoderFlavour=Generic 333eventq_index=0 334fpsid=1090793632 335id_aa64afr0_el1=0 336id_aa64afr1_el1=0 337id_aa64dfr0_el1=1052678 338id_aa64dfr1_el1=0 339id_aa64isar0_el1=0 340id_aa64isar1_el1=0 341id_aa64mmfr0_el1=15728642 342id_aa64mmfr1_el1=0 343id_aa64pfr0_el1=17 344id_aa64pfr1_el1=0 345id_isar0=34607377 346id_isar1=34677009 347id_isar2=555950401 348id_isar3=17899825 349id_isar4=268501314 350id_isar5=0 351id_mmfr0=270536963 352id_mmfr1=0 353id_mmfr2=19070976 354id_mmfr3=34611729 355id_pfr0=49 356id_pfr1=4113 357midr=1091551472 358pmu=Null 359system=system 360 361[system.cpu.istage2_mmu] 362type=ArmStage2MMU 363children=stage2_tlb 364eventq_index=0 365stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 366sys=system 367tlb=system.cpu.itb 368 369[system.cpu.istage2_mmu.stage2_tlb] 370type=ArmTLB 371children=walker 372eventq_index=0 373is_stage2=true 374size=32 375walker=system.cpu.istage2_mmu.stage2_tlb.walker 376 377[system.cpu.istage2_mmu.stage2_tlb.walker] 378type=ArmTableWalker 379clk_domain=system.cpu_clk_domain 380default_p_state=UNDEFINED 381eventq_index=0 382is_stage2=true 383num_squash_per_cycle=2 384p_state_clk_gate_bins=20 385p_state_clk_gate_max=1000000000000 386p_state_clk_gate_min=1000 387power_model=Null 388sys=system 389 390[system.cpu.itb] 391type=ArmTLB 392children=walker 393eventq_index=0 394is_stage2=false 395size=64 396walker=system.cpu.itb.walker 397 398[system.cpu.itb.walker] 399type=ArmTableWalker 400clk_domain=system.cpu_clk_domain 401default_p_state=UNDEFINED 402eventq_index=0 403is_stage2=false 404num_squash_per_cycle=2 405p_state_clk_gate_bins=20 406p_state_clk_gate_max=1000000000000 407p_state_clk_gate_min=1000 408power_model=Null 409sys=system 410port=system.membus.slave[3] 411 412[system.cpu.tracer] 413type=ExeTracer 414eventq_index=0 415 416[system.cpu.workload] 417type=LiveProcess 418cmd=hello 419cwd= 420drivers= 421egid=100 422env= 423errout=cerr 424euid=100 425eventq_index=0 426executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello 427gid=100 428input=cin 429kvmInSE=false 430max_stack_size=67108864 431output=cout 432pid=100 433ppid=99 434simpoint=0 435system=system 436uid=100 437useArchPT=false 438 439[system.cpu_clk_domain] 440type=SrcClockDomain 441clock=500 442domain_id=-1 443eventq_index=0 444init_perf_level=0 445voltage_domain=system.voltage_domain 446 447[system.dvfs_handler] 448type=DVFSHandler 449domains= 450enable=false 451eventq_index=0 452sys_clk_domain=system.clk_domain 453transition_latency=100000000 454 455[system.membus] 456type=CoherentXBar 457clk_domain=system.clk_domain 458default_p_state=UNDEFINED 459eventq_index=0 460forward_latency=4 461frontend_latency=3 462p_state_clk_gate_bins=20 463p_state_clk_gate_max=1000000000000 464p_state_clk_gate_min=1000 465point_of_coherency=true 466power_model=Null 467response_latency=2 468snoop_filter=Null 469snoop_response_latency=4 470system=system 471use_default_range=false 472width=16 473master=system.physmem.port 474slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port 475 476[system.physmem] 477type=SimpleMemory 478bandwidth=73.000000 479clk_domain=system.clk_domain 480conf_table_reported=true 481default_p_state=UNDEFINED 482eventq_index=0 483in_addr_map=true 484latency=30000 485latency_var=0 486null=false 487p_state_clk_gate_bins=20 488p_state_clk_gate_max=1000000000000 489p_state_clk_gate_min=1000 490power_model=Null 491range=0:134217727 492port=system.membus.master[0] 493 494[system.voltage_domain] 495type=VoltageDomain 496eventq_index=0 497voltage=1.000000 498 499