stats.txt revision 8673
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 5.112043 # Number of seconds simulated 410585Sandreas.hansson@arm.comsim_ticks 5112043255000 # Number of ticks simulated 510585Sandreas.hansson@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 68721SN/Ahost_inst_rate 2860366 # Simulator instruction rate (inst/s) 710892Sandreas.hansson@arm.comhost_tick_rate 35739722021 # Simulator tick rate (ticks/s) 810892Sandreas.hansson@arm.comhost_mem_usage 375540 # Number of bytes of host memory used 910892Sandreas.hansson@arm.comhost_seconds 143.04 # Real time elapsed on the host 1010892Sandreas.hansson@arm.comsim_insts 409133277 # Number of instructions simulated 1110892Sandreas.hansson@arm.comsystem.l2c.replacements 164044 # number of replacements 1210585Sandreas.hansson@arm.comsystem.l2c.tagsinuse 36842.944085 # Cycle average of tags in use 1310585Sandreas.hansson@arm.comsystem.l2c.total_refs 3332458 # Total number of references to valid blocks. 1410036SAli.Saidi@ARM.comsystem.l2c.sampled_refs 196390 # Sample count of references to valid blocks. 1510036SAli.Saidi@ARM.comsystem.l2c.avg_refs 16.968573 # Average number of references to valid blocks. 1610892Sandreas.hansson@arm.comsystem.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1710892Sandreas.hansson@arm.comsystem.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context 1810892Sandreas.hansson@arm.comsystem.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context 1910585Sandreas.hansson@arm.comsystem.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy 2010352Sandreas.hansson@arm.comsystem.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy 2110892Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits 2210892Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::1 9538 # number of ReadReq hits 2310892Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits 2410892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::0 1529403 # number of Writeback hits 2510892Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 1529403 # number of Writeback hits 2610892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits 2710892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits 2810892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits 2910892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits 3010585Sandreas.hansson@arm.comsystem.l2c.demand_hits::0 2211865 # number of demand (read+write) hits 3110352Sandreas.hansson@arm.comsystem.l2c.demand_hits::1 9538 # number of demand (read+write) hits 3210892Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2221403 # number of demand (read+write) hits 3310892Sandreas.hansson@arm.comsystem.l2c.overall_hits::0 2211865 # number of overall hits 3410892Sandreas.hansson@arm.comsystem.l2c.overall_hits::1 9538 # number of overall hits 3510892Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2221403 # number of overall hits 3610892Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::0 55972 # number of ReadReq misses 3710892Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::1 27 # number of ReadReq misses 3810585Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 55999 # number of ReadReq misses 3910409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses 4010892Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses 4110892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses 4210892Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses 4310892Sandreas.hansson@arm.comsystem.l2c.demand_misses::0 200611 # number of demand (read+write) misses 4410892Sandreas.hansson@arm.comsystem.l2c.demand_misses::1 27 # number of demand (read+write) misses 4510892Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 200638 # number of demand (read+write) misses 4610892Sandreas.hansson@arm.comsystem.l2c.overall_misses::0 200611 # number of overall misses 4710892Sandreas.hansson@arm.comsystem.l2c.overall_misses::1 27 # number of overall misses 4810892Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 200638 # number of overall misses 4910892Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 5010585Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency 0 # number of overall miss cycles 5110585Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses) 5210892Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses) 5310036SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) 548721SN/Asystem.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses) 558721SN/Asystem.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) 568721SN/Asystem.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses) 578721SN/Asystem.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) 5810585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses) 5910409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) 608721SN/Asystem.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses 6110409Sandreas.hansson@arm.comsystem.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses 6210585Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses 6310409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses 6410409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses 6510409Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses 6610585Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses 6710409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses 6810409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses 6910409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses 7010585Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses 7110409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses 728721SN/Asystem.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses 7310585Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses 748721SN/Asystem.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses 758721SN/Asystem.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses 768721SN/Asystem.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses 778721SN/Asystem.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 788721SN/Asystem.l2c.demand_avg_miss_latency::1 0 # average overall miss latency 798721SN/Asystem.l2c.demand_avg_miss_latency::total 0 # average overall miss latency 808721SN/Asystem.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 818721SN/Asystem.l2c.overall_avg_miss_latency::1 0 # average overall miss latency 826024SN/Asystem.l2c.overall_avg_miss_latency::total 0 # average overall miss latency 836024SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 848721SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 858721SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 8610585Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 878721SN/Asystem.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 888721SN/Asystem.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 8910585Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 9010585Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 9110585Sandreas.hansson@arm.comsystem.l2c.writebacks 144472 # number of writebacks 9210409Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 9310585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits 0 # number of overall MSHR hits 9410585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 9510585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses 0 # number of overall MSHR misses 9610409Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 9710585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 9810585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 9910409Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 10010409Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 10110585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 10210585Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses 10310585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 10410585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 10510585Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses 10610409Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 10710409Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 10810585Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 10910585Sandreas.hansson@arm.comsystem.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 11010585Sandreas.hansson@arm.comsystem.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 11110585Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 11210409Sandreas.hansson@arm.comsystem.iocache.replacements 47570 # number of replacements 11310409Sandreas.hansson@arm.comsystem.iocache.tagsinuse 0.042409 # Cycle average of tags in use 11410409Sandreas.hansson@arm.comsystem.iocache.total_refs 0 # Total number of references to valid blocks. 11510409Sandreas.hansson@arm.comsystem.iocache.sampled_refs 47586 # Sample count of references to valid blocks. 11610409Sandreas.hansson@arm.comsystem.iocache.avg_refs 0 # Average number of references to valid blocks. 11710409Sandreas.hansson@arm.comsystem.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. 11810409Sandreas.hansson@arm.comsystem.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context 11910409Sandreas.hansson@arm.comsystem.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy 12010409Sandreas.hansson@arm.comsystem.iocache.demand_hits::0 0 # number of demand (read+write) hits 12110409Sandreas.hansson@arm.comsystem.iocache.demand_hits::1 0 # number of demand (read+write) hits 12210409Sandreas.hansson@arm.comsystem.iocache.demand_hits::total 0 # number of demand (read+write) hits 12310409Sandreas.hansson@arm.comsystem.iocache.overall_hits::0 0 # number of overall hits 12410409Sandreas.hansson@arm.comsystem.iocache.overall_hits::1 0 # number of overall hits 12510409Sandreas.hansson@arm.comsystem.iocache.overall_hits::total 0 # number of overall hits 12610409Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::1 905 # number of ReadReq misses 12710409Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 905 # number of ReadReq misses 12810409Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::1 46720 # number of WriteReq misses 12910409Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 13010409Sandreas.hansson@arm.comsystem.iocache.demand_misses::0 0 # number of demand (read+write) misses 13110409Sandreas.hansson@arm.comsystem.iocache.demand_misses::1 47625 # number of demand (read+write) misses 13210409Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 47625 # number of demand (read+write) misses 13310409Sandreas.hansson@arm.comsystem.iocache.overall_misses::0 0 # number of overall misses 13410409Sandreas.hansson@arm.comsystem.iocache.overall_misses::1 47625 # number of overall misses 13510409Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 47625 # number of overall misses 13610409Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 13710409Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency 0 # number of overall miss cycles 13810409Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) 13910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) 14010585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) 14110585Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 14210220Sandreas.hansson@arm.comsystem.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 14310585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses 1442968SN/Asystem.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses 14510409Sandreas.hansson@arm.comsystem.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 14610585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses 14710409Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses 14810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 14910409Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 15010409Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 15110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 15210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 15310409Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 15410409Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 15510409Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 15610409Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 15710409Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::1 0 # average overall miss latency 15810409Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 15910585Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 16010409Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::1 0 # average overall miss latency 16110409Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 16210409Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 16310585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 16410585Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 16510409Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 1666127SN/Asystem.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1676127SN/Asystem.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1686127SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 16910585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 17010585Sandreas.hansson@arm.comsystem.iocache.writebacks 46667 # number of writebacks 17110409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 17210409Sandreas.hansson@arm.comsystem.iocache.overall_mshr_hits 0 # number of overall MSHR hits 17310409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 17410409Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses 0 # number of overall MSHR misses 17510409Sandreas.hansson@arm.comsystem.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 17610409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 17710409Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 17810409Sandreas.hansson@arm.comsystem.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 17910409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 18010409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 18110409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 18210409Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 18310409Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 18410409Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 18510409Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 18610409Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 18710409Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 18810409Sandreas.hansson@arm.comsystem.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 18910409Sandreas.hansson@arm.comsystem.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 19010409Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 19110409Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 19210409Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 19310409Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 19410409Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 19510409Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 19610409Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 19710409Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 19810409Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1996291SN/Asystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2006291SN/Asystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 20110409Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 2028721SN/Asystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 20310409Sandreas.hansson@arm.comsystem.cpu.numCycles 10224086531 # number of cpu cycles simulated 20410409Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 20510409Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 20610409Sandreas.hansson@arm.comsystem.cpu.num_insts 409133277 # Number of instructions executed 20710409Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses 20810409Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 20910409Sandreas.hansson@arm.comsystem.cpu.num_func_calls 0 # number of times a function call or return occured 21010585Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls 21110409Sandreas.hansson@arm.comsystem.cpu.num_int_insts 374297244 # number of integer instructions 21210409Sandreas.hansson@arm.comsystem.cpu.num_fp_insts 0 # number of float instructions 21310409Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 801267455 # number of times the integer registers were read 21410409Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 401624559 # number of times the integer registers were written 21510409Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 21610409Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 21710409Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 35626519 # number of memory refs 21810409Sandreas.hansson@arm.comsystem.cpu.num_load_insts 27217784 # Number of load instructions 21910585Sandreas.hansson@arm.comsystem.cpu.num_store_insts 8408735 # Number of store instructions 22010409Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles 22110585Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles 2228721SN/Asystem.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles 22310585Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.955646 # Percentage of idle cycles 22410585Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 2258721SN/Asystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 22610585Sandreas.hansson@arm.comsystem.cpu.icache.replacements 790795 # number of replacements 2278721SN/Asystem.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use 2288983Snate@binkert.orgsystem.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. 22910585Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. 23010585Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. 23110585Sandreas.hansson@arm.comsystem.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. 2328721SN/Asystem.cpu.icache.occ_blocks::0 510.627676 # Average occupied blocks per context 23310409Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy 23410585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::0 243365777 # number of ReadReq hits 23510585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits 23610585Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::0 243365777 # number of demand (read+write) hits 23710585Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 23810585Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits 23910585Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::0 243365777 # number of overall hits 24010585Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::1 0 # number of overall hits 24110585Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 243365777 # number of overall hits 24210585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::0 791314 # number of ReadReq misses 24310585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses 24410585Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::0 791314 # number of demand (read+write) misses 24510585Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 24610585Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses 24710585Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::0 791314 # number of overall misses 24810585Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::1 0 # number of overall misses 24910585Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 791314 # number of overall misses 25010585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 25110585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency 0 # number of overall miss cycles 25210585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::0 244157091 # number of ReadReq accesses(hits+misses) 25310585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) 25410585Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::0 244157091 # number of demand (read+write) accesses 25510585Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 25610585Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses 25710585Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::0 244157091 # number of overall (read+write) accesses 25810585Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 25910585Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses 26010585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::0 0.003241 # miss rate for ReadReq accesses 26110585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::0 0.003241 # miss rate for demand accesses 26210585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 26310585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 26410585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::0 0.003241 # miss rate for overall accesses 26510585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 26610585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 26710585Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency 26810585Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 26910585Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency 27010585Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency 27110585Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 27210585Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency 27310585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 27410585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 27510585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 27610585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 27710585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 27810585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 27910585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 28010585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 28110585Sandreas.hansson@arm.comsystem.cpu.icache.writebacks 809 # number of writebacks 28210585Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 28310585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 28410585Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 28510585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses 28610585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 28710585Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 28810585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 28910585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 29010585Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 29110585Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 29210585Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 29310585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 29410585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 29510585Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 29610585Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 29710585Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 29810585Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 29910585Sandreas.hansson@arm.comsystem.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 30010585Sandreas.hansson@arm.comsystem.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 30110585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 30210585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.replacements 3435 # number of replacements 30310585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use 30410585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. 30510585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. 30610892Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. 30710892Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. 30810585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.occ_blocks::1 3.021701 # Average occupied blocks per context 30910585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.occ_percent::1 0.188856 # Average percentage of cache occupancy 31010585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_hits::1 7947 # number of ReadReq hits 31110585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits 31210585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits 31310585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 31410409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 31510585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_hits::1 7949 # number of demand (read+write) hits 31610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits 31710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits 31810036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.overall_hits::1 7949 # number of overall hits 31910409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits 32010409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_misses::1 4278 # number of ReadReq misses 32110409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses 32210036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 32310585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_misses::1 4278 # number of demand (read+write) misses 32410585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses 32510585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses 32610585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_misses::1 4278 # number of overall misses 32710585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses 32810585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles 32910585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles 33010585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::1 12225 # number of ReadReq accesses(hits+misses) 33110585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) 33210585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) 33310585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 33410585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 33510585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::1 12227 # number of demand (read+write) accesses 33610585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 33710585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 33810585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::1 12227 # number of overall (read+write) accesses 33910585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 34010585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.349939 # miss rate for ReadReq accesses 34110585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 34210585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_rate::1 0.349881 # miss rate for demand accesses 34310409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 34410409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 34510409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_rate::1 0.349881 # miss rate for overall accesses 34610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 34710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency 34810409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency 3498721SN/Asystem.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency 3508721SN/Asystem.cpu.itb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency 3518721SN/Asystem.cpu.itb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency 3528721SN/Asystem.cpu.itb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency 3538983Snate@binkert.orgsystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3548983Snate@binkert.orgsystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3558721SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 3568721SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 3578721SN/Asystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 3588721SN/Asystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 3598721SN/Asystem.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 3608721SN/Asystem.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 3618721SN/Asystem.cpu.itb_walker_cache.writebacks 518 # number of writebacks 36210585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 36310409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 3648721SN/Asystem.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 36510409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses 36610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 36710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 36810409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 36910409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 37010585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 37110409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 37210409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 37310409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 37410409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 37510409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 3768721SN/Asystem.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 37710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 3788721SN/Asystem.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 3798721SN/Asystem.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 3808721SN/Asystem.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 3818721SN/Asystem.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 3828721SN/Asystem.cpu.dtb_walker_cache.replacements 7755 # number of replacements 3838721SN/Asystem.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use 3848721SN/Asystem.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. 3858721SN/Asystem.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. 3866024SN/Asystem.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. 3876024SN/Asystem.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. 3888721SN/Asystem.cpu.dtb_walker_cache.occ_blocks::1 5.010998 # Average occupied blocks per context 3898721SN/Asystem.cpu.dtb_walker_cache.occ_percent::1 0.313187 # Average percentage of cache occupancy 39010585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::1 12875 # number of ReadReq hits 3918721SN/Asystem.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits 3928721SN/Asystem.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 39310585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::1 12875 # number of demand (read+write) hits 39410585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits 39510585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits 39610409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::1 12875 # number of overall hits 39710409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits 39810585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_misses::1 8933 # number of ReadReq misses 39910585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses 40010409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 40110585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_misses::1 8933 # number of demand (read+write) misses 40210585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses 40310409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses 40410409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_misses::1 8933 # number of overall misses 40510585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses 40610585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles 40710409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles 40810585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::1 21808 # number of ReadReq accesses(hits+misses) 40910585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 41010409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 41110409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::1 21808 # number of demand (read+write) accesses 41210585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 41310409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 41410585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::1 21808 # number of overall (read+write) accesses 41510409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses 41610409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.409620 # miss rate for ReadReq accesses 41710409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 41810409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::1 0.409620 # miss rate for demand accesses 41910409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 42010409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 42110409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::1 0.409620 # miss rate for overall accesses 42210409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 42310409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency 42410409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency 42510409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency 42610409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency 42710409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency 42810409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency 42910409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 43010409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 43110409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 43210409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 43310409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 43410409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 43510409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 43610409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 43710409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.writebacks 2517 # number of writebacks 43810409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 43910409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 44010409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 44110409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses 44210409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 44310585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 44410409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 44510409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 44610220Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 44710585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 4482968SN/Asystem.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 44910409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 45010409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 45110409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 45210409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 45310409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 45410409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 45510409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 45610409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 45710409Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 45810409Sandreas.hansson@arm.comsystem.cpu.dcache.replacements 1621277 # number of replacements 45910409Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use 46010409Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. 46110585Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. 46210409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. 46310409Sandreas.hansson@arm.comsystem.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 46410585Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context 46510585Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy 46610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::0 12057024 # number of ReadReq hits 4676127SN/Asystem.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits 4686127SN/Asystem.cpu.dcache.WriteReq_hits::0 8082938 # number of WriteReq hits 46910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits 47010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::0 20139962 # number of demand (read+write) hits 47110409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 47210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits 47310409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::0 20139962 # number of overall hits 47410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::1 0 # number of overall hits 47510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 20139962 # number of overall hits 47610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::0 1308207 # number of ReadReq misses 47710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses 47810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::0 315850 # number of WriteReq misses 47910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses 48010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::0 1624057 # number of demand (read+write) misses 48110409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 48210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses 48310409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::0 1624057 # number of overall misses 48410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::1 0 # number of overall misses 48510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1624057 # number of overall misses 48610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 48710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles 48810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::0 13365231 # number of ReadReq accesses(hits+misses) 4898721SN/Asystem.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) 49010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::0 8398788 # number of WriteReq accesses(hits+misses) 49110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) 49210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::0 21764019 # number of demand (read+write) accesses 49310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 49410409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses 49510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::0 21764019 # number of overall (read+write) accesses 49610409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 49710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses 49810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::0 0.097881 # miss rate for ReadReq accesses 49910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses 50010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::0 0.074621 # miss rate for demand accesses 50110409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 50210409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 50310409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::0 0.074621 # miss rate for overall accesses 50410409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 5058721SN/Asystem.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 50610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 50710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 50810409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 50910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 51010409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 51110409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 51210409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 51310409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5148721SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 51510409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 51610409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 51710585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 51810409Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 51910585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 52010409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks 1525559 # number of writebacks 52110585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 52210585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 52310585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 52410585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses 52510585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 52610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 52710585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 52810585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 52910585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 53010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 53110409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 53210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 53310409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 53410585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 53510585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 53610585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 53710585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 53810409Sandreas.hansson@arm.comsystem.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 53910409Sandreas.hansson@arm.comsystem.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 54010585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 54110585Sandreas.hansson@arm.com 54210409Sandreas.hansson@arm.com---------- End Simulation Statistics ---------- 54310409Sandreas.hansson@arm.com