stats.txt revision 8673
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 2860366 # Simulator instruction rate (inst/s) 7host_tick_rate 35739722021 # Simulator tick rate (ticks/s) 8host_mem_usage 375540 # Number of bytes of host memory used 9host_seconds 143.04 # Real time elapsed on the host 10sim_insts 409133277 # Number of instructions simulated 11system.l2c.replacements 164044 # number of replacements 12system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use 13system.l2c.total_refs 3332458 # Total number of references to valid blocks. 14system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. 15system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. 16system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 17system.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context 18system.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context 19system.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy 20system.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy 21system.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits 22system.l2c.ReadReq_hits::1 9538 # number of ReadReq hits 23system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits 24system.l2c.Writeback_hits::0 1529403 # number of Writeback hits 25system.l2c.Writeback_hits::total 1529403 # number of Writeback hits 26system.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits 27system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits 28system.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits 29system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits 30system.l2c.demand_hits::0 2211865 # number of demand (read+write) hits 31system.l2c.demand_hits::1 9538 # number of demand (read+write) hits 32system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits 33system.l2c.overall_hits::0 2211865 # number of overall hits 34system.l2c.overall_hits::1 9538 # number of overall hits 35system.l2c.overall_hits::total 2221403 # number of overall hits 36system.l2c.ReadReq_misses::0 55972 # number of ReadReq misses 37system.l2c.ReadReq_misses::1 27 # number of ReadReq misses 38system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses 39system.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses 40system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses 41system.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses 42system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses 43system.l2c.demand_misses::0 200611 # number of demand (read+write) misses 44system.l2c.demand_misses::1 27 # number of demand (read+write) misses 45system.l2c.demand_misses::total 200638 # number of demand (read+write) misses 46system.l2c.overall_misses::0 200611 # number of overall misses 47system.l2c.overall_misses::1 27 # number of overall misses 48system.l2c.overall_misses::total 200638 # number of overall misses 49system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 50system.l2c.overall_miss_latency 0 # number of overall miss cycles 51system.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses) 52system.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses) 53system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) 54system.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses) 55system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) 56system.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses) 57system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) 58system.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses) 59system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) 60system.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses 61system.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses 62system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses 63system.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses 64system.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses 65system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses 66system.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses 67system.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses 68system.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses 69system.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses 70system.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses 71system.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses 72system.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses 73system.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses 74system.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses 75system.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses 76system.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses 77system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 78system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency 79system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency 80system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 81system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency 82system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency 83system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 84system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 85system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 86system.l2c.blocked::no_targets 0 # number of cycles access was blocked 87system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 88system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 89system.l2c.fast_writes 0 # number of fast writes performed 90system.l2c.cache_copies 0 # number of cache copies performed 91system.l2c.writebacks 144472 # number of writebacks 92system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 93system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 94system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 95system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 96system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 97system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 98system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 99system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 100system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 101system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 102system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses 103system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 104system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 105system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses 106system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 107system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 108system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 109system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 110system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 111system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 112system.iocache.replacements 47570 # number of replacements 113system.iocache.tagsinuse 0.042409 # Cycle average of tags in use 114system.iocache.total_refs 0 # Total number of references to valid blocks. 115system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. 116system.iocache.avg_refs 0 # Average number of references to valid blocks. 117system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. 118system.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context 119system.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy 120system.iocache.demand_hits::0 0 # number of demand (read+write) hits 121system.iocache.demand_hits::1 0 # number of demand (read+write) hits 122system.iocache.demand_hits::total 0 # number of demand (read+write) hits 123system.iocache.overall_hits::0 0 # number of overall hits 124system.iocache.overall_hits::1 0 # number of overall hits 125system.iocache.overall_hits::total 0 # number of overall hits 126system.iocache.ReadReq_misses::1 905 # number of ReadReq misses 127system.iocache.ReadReq_misses::total 905 # number of ReadReq misses 128system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses 129system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 130system.iocache.demand_misses::0 0 # number of demand (read+write) misses 131system.iocache.demand_misses::1 47625 # number of demand (read+write) misses 132system.iocache.demand_misses::total 47625 # number of demand (read+write) misses 133system.iocache.overall_misses::0 0 # number of overall misses 134system.iocache.overall_misses::1 47625 # number of overall misses 135system.iocache.overall_misses::total 47625 # number of overall misses 136system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 137system.iocache.overall_miss_latency 0 # number of overall miss cycles 138system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) 139system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) 140system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) 141system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 142system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 143system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses 144system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses 145system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 146system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses 147system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses 148system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 149system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 150system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 151system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 152system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 153system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 154system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 155system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 156system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 157system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency 158system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 159system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 160system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency 161system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 162system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 163system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 164system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 165system.iocache.blocked::no_targets 0 # number of cycles access was blocked 166system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 167system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 168system.iocache.fast_writes 0 # number of fast writes performed 169system.iocache.cache_copies 0 # number of cache copies performed 170system.iocache.writebacks 46667 # number of writebacks 171system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 172system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 173system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 174system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 175system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 176system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 177system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 178system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 179system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 180system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 181system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 182system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 183system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 184system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 185system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 186system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 187system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 188system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 189system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 190system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 191system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 192system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 193system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 194system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 195system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 196system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 197system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 198system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 199system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 200system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 201system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 202system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 203system.cpu.numCycles 10224086531 # number of cpu cycles simulated 204system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 205system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 206system.cpu.num_insts 409133277 # Number of instructions executed 207system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses 208system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 209system.cpu.num_func_calls 0 # number of times a function call or return occured 210system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls 211system.cpu.num_int_insts 374297244 # number of integer instructions 212system.cpu.num_fp_insts 0 # number of float instructions 213system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read 214system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written 215system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 216system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 217system.cpu.num_mem_refs 35626519 # number of memory refs 218system.cpu.num_load_insts 27217784 # Number of load instructions 219system.cpu.num_store_insts 8408735 # Number of store instructions 220system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles 221system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles 222system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles 223system.cpu.idle_fraction 0.955646 # Percentage of idle cycles 224system.cpu.kern.inst.arm 0 # number of arm instructions executed 225system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 226system.cpu.icache.replacements 790795 # number of replacements 227system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use 228system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. 229system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. 230system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. 231system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. 232system.cpu.icache.occ_blocks::0 510.627676 # Average occupied blocks per context 233system.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy 234system.cpu.icache.ReadReq_hits::0 243365777 # number of ReadReq hits 235system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits 236system.cpu.icache.demand_hits::0 243365777 # number of demand (read+write) hits 237system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 238system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits 239system.cpu.icache.overall_hits::0 243365777 # number of overall hits 240system.cpu.icache.overall_hits::1 0 # number of overall hits 241system.cpu.icache.overall_hits::total 243365777 # number of overall hits 242system.cpu.icache.ReadReq_misses::0 791314 # number of ReadReq misses 243system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses 244system.cpu.icache.demand_misses::0 791314 # number of demand (read+write) misses 245system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 246system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses 247system.cpu.icache.overall_misses::0 791314 # number of overall misses 248system.cpu.icache.overall_misses::1 0 # number of overall misses 249system.cpu.icache.overall_misses::total 791314 # number of overall misses 250system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 251system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles 252system.cpu.icache.ReadReq_accesses::0 244157091 # number of ReadReq accesses(hits+misses) 253system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) 254system.cpu.icache.demand_accesses::0 244157091 # number of demand (read+write) accesses 255system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 256system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses 257system.cpu.icache.overall_accesses::0 244157091 # number of overall (read+write) accesses 258system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 259system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses 260system.cpu.icache.ReadReq_miss_rate::0 0.003241 # miss rate for ReadReq accesses 261system.cpu.icache.demand_miss_rate::0 0.003241 # miss rate for demand accesses 262system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 263system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 264system.cpu.icache.overall_miss_rate::0 0.003241 # miss rate for overall accesses 265system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 266system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 267system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency 268system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 269system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency 270system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency 271system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 272system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency 273system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 274system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 275system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 276system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 277system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 278system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 279system.cpu.icache.fast_writes 0 # number of fast writes performed 280system.cpu.icache.cache_copies 0 # number of cache copies performed 281system.cpu.icache.writebacks 809 # number of writebacks 282system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 283system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 284system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 285system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses 286system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 287system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 288system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 289system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 290system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 291system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 292system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 293system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 294system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 295system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 296system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 297system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 298system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 299system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 300system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 301system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 302system.cpu.itb_walker_cache.replacements 3435 # number of replacements 303system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use 304system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. 305system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. 306system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. 307system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. 308system.cpu.itb_walker_cache.occ_blocks::1 3.021701 # Average occupied blocks per context 309system.cpu.itb_walker_cache.occ_percent::1 0.188856 # Average percentage of cache occupancy 310system.cpu.itb_walker_cache.ReadReq_hits::1 7947 # number of ReadReq hits 311system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits 312system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits 313system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 314system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 315system.cpu.itb_walker_cache.demand_hits::1 7949 # number of demand (read+write) hits 316system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits 317system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits 318system.cpu.itb_walker_cache.overall_hits::1 7949 # number of overall hits 319system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits 320system.cpu.itb_walker_cache.ReadReq_misses::1 4278 # number of ReadReq misses 321system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses 322system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 323system.cpu.itb_walker_cache.demand_misses::1 4278 # number of demand (read+write) misses 324system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses 325system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses 326system.cpu.itb_walker_cache.overall_misses::1 4278 # number of overall misses 327system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses 328system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles 329system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles 330system.cpu.itb_walker_cache.ReadReq_accesses::1 12225 # number of ReadReq accesses(hits+misses) 331system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) 332system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) 333system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 334system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 335system.cpu.itb_walker_cache.demand_accesses::1 12227 # number of demand (read+write) accesses 336system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 337system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 338system.cpu.itb_walker_cache.overall_accesses::1 12227 # number of overall (read+write) accesses 339system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 340system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.349939 # miss rate for ReadReq accesses 341system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 342system.cpu.itb_walker_cache.demand_miss_rate::1 0.349881 # miss rate for demand accesses 343system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 344system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 345system.cpu.itb_walker_cache.overall_miss_rate::1 0.349881 # miss rate for overall accesses 346system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 347system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency 348system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency 349system.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency 350system.cpu.itb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency 351system.cpu.itb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency 352system.cpu.itb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency 353system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 354system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 355system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 356system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 357system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 358system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 359system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 360system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 361system.cpu.itb_walker_cache.writebacks 518 # number of writebacks 362system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 363system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 364system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 365system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses 366system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 367system.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 368system.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 369system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 370system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 371system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 372system.cpu.itb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 373system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 374system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 375system.cpu.itb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 376system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 377system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 378system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 379system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 380system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 381system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 382system.cpu.dtb_walker_cache.replacements 7755 # number of replacements 383system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use 384system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. 385system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. 386system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. 387system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. 388system.cpu.dtb_walker_cache.occ_blocks::1 5.010998 # Average occupied blocks per context 389system.cpu.dtb_walker_cache.occ_percent::1 0.313187 # Average percentage of cache occupancy 390system.cpu.dtb_walker_cache.ReadReq_hits::1 12875 # number of ReadReq hits 391system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits 392system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 393system.cpu.dtb_walker_cache.demand_hits::1 12875 # number of demand (read+write) hits 394system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits 395system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits 396system.cpu.dtb_walker_cache.overall_hits::1 12875 # number of overall hits 397system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits 398system.cpu.dtb_walker_cache.ReadReq_misses::1 8933 # number of ReadReq misses 399system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses 400system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 401system.cpu.dtb_walker_cache.demand_misses::1 8933 # number of demand (read+write) misses 402system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses 403system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses 404system.cpu.dtb_walker_cache.overall_misses::1 8933 # number of overall misses 405system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses 406system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles 407system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles 408system.cpu.dtb_walker_cache.ReadReq_accesses::1 21808 # number of ReadReq accesses(hits+misses) 409system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 410system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 411system.cpu.dtb_walker_cache.demand_accesses::1 21808 # number of demand (read+write) accesses 412system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 413system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 414system.cpu.dtb_walker_cache.overall_accesses::1 21808 # number of overall (read+write) accesses 415system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses 416system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.409620 # miss rate for ReadReq accesses 417system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 418system.cpu.dtb_walker_cache.demand_miss_rate::1 0.409620 # miss rate for demand accesses 419system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 420system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 421system.cpu.dtb_walker_cache.overall_miss_rate::1 0.409620 # miss rate for overall accesses 422system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 423system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency 424system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency 425system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency 426system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency 427system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency 428system.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency 429system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 430system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 431system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 432system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 433system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 434system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 435system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 436system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 437system.cpu.dtb_walker_cache.writebacks 2517 # number of writebacks 438system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 439system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 440system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 441system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses 442system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 443system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 444system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 445system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 446system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 447system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 448system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 449system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 450system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 451system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 452system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 453system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 454system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 455system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 456system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 457system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.cpu.dcache.replacements 1621277 # number of replacements 459system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use 460system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. 461system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. 462system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. 463system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 464system.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context 465system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy 466system.cpu.dcache.ReadReq_hits::0 12057024 # number of ReadReq hits 467system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits 468system.cpu.dcache.WriteReq_hits::0 8082938 # number of WriteReq hits 469system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits 470system.cpu.dcache.demand_hits::0 20139962 # number of demand (read+write) hits 471system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 472system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits 473system.cpu.dcache.overall_hits::0 20139962 # number of overall hits 474system.cpu.dcache.overall_hits::1 0 # number of overall hits 475system.cpu.dcache.overall_hits::total 20139962 # number of overall hits 476system.cpu.dcache.ReadReq_misses::0 1308207 # number of ReadReq misses 477system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses 478system.cpu.dcache.WriteReq_misses::0 315850 # number of WriteReq misses 479system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses 480system.cpu.dcache.demand_misses::0 1624057 # number of demand (read+write) misses 481system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 482system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses 483system.cpu.dcache.overall_misses::0 1624057 # number of overall misses 484system.cpu.dcache.overall_misses::1 0 # number of overall misses 485system.cpu.dcache.overall_misses::total 1624057 # number of overall misses 486system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 487system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles 488system.cpu.dcache.ReadReq_accesses::0 13365231 # number of ReadReq accesses(hits+misses) 489system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) 490system.cpu.dcache.WriteReq_accesses::0 8398788 # number of WriteReq accesses(hits+misses) 491system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) 492system.cpu.dcache.demand_accesses::0 21764019 # number of demand (read+write) accesses 493system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 494system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses 495system.cpu.dcache.overall_accesses::0 21764019 # number of overall (read+write) accesses 496system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 497system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses 498system.cpu.dcache.ReadReq_miss_rate::0 0.097881 # miss rate for ReadReq accesses 499system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses 500system.cpu.dcache.demand_miss_rate::0 0.074621 # miss rate for demand accesses 501system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 502system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 503system.cpu.dcache.overall_miss_rate::0 0.074621 # miss rate for overall accesses 504system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 505system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 506system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 507system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 508system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 509system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 510system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 512system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 518system.cpu.dcache.fast_writes 0 # number of fast writes performed 519system.cpu.dcache.cache_copies 0 # number of cache copies performed 520system.cpu.dcache.writebacks 1525559 # number of writebacks 521system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 522system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 523system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 524system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses 525system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 526system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 527system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 528system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 529system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 530system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 531system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 532system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 533system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 534system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 535system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 536system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 537system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 538system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 539system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 540system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 541 542---------- End Simulation Statistics ---------- 543