stats.txt revision 10036
17927SN/A 27927SN/A---------- Begin Simulation Statistics ---------- 39901Sandreas@sandberg.pp.sesim_seconds 5.112126 # Number of seconds simulated 49962Sandreas.hansson@arm.comsim_ticks 5112126264500 # Number of ticks simulated 59962Sandreas.hansson@arm.comfinal_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67927SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710036SAli.Saidi@ARM.comhost_inst_rate 1777208 # Simulator instruction rate (inst/s) 810036SAli.Saidi@ARM.comhost_op_rate 3638722 # Simulator op (including micro ops) rate (op/s) 910036SAli.Saidi@ARM.comhost_tick_rate 45442487875 # Simulator tick rate (ticks/s) 1010036SAli.Saidi@ARM.comhost_mem_usage 590176 # Number of bytes of host memory used 1110036SAli.Saidi@ARM.comhost_seconds 112.50 # Real time elapsed on the host 129901Sandreas@sandberg.pp.sesim_insts 199929810 # Number of instructions simulated 139962Sandreas.hansson@arm.comsim_ops 409343850 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory 179901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 189079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 199625Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 209901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory 219901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::total 13883648 # Number of bytes read from this memory 229625Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 239625Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory 249901Sandreas@sandberg.pp.sesystem.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory 259901Sandreas@sandberg.pp.sesystem.physmem.bytes_written::total 9268672 # Number of bytes written to this memory 269901Sandreas@sandberg.pp.sesystem.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory 279901Sandreas@sandberg.pp.sesystem.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 289079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 299625Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory 309901Sandreas@sandberg.pp.sesystem.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory 319901Sandreas@sandberg.pp.sesystem.physmem.num_reads::total 216932 # Number of read requests responded to by this memory 329901Sandreas@sandberg.pp.sesystem.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory 339901Sandreas@sandberg.pp.sesystem.physmem.num_writes::total 144823 # Number of write requests responded to by this memory 349901Sandreas@sandberg.pp.sesystem.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) 359901Sandreas@sandberg.pp.sesystem.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 369079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 379625Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 389901Sandreas@sandberg.pp.sesystem.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) 399962Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2715827 # Total read bandwidth from this memory (bytes/s) 409625Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 419625Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 429901Sandreas@sandberg.pp.sesystem.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) 439901Sandreas@sandberg.pp.sesystem.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) 449901Sandreas@sandberg.pp.sesystem.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) 459901Sandreas@sandberg.pp.sesystem.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) 469901Sandreas@sandberg.pp.sesystem.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 479079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 489625Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 499901Sandreas@sandberg.pp.sesystem.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) 509901Sandreas@sandberg.pp.sesystem.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) 519901Sandreas@sandberg.pp.sesystem.membus.throughput 9634332 # Throughput (bytes/s) 529901Sandreas@sandberg.pp.sesystem.membus.data_through_bus 49251923 # Total data (bytes) 539729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 549838Sandreas.hansson@arm.comsystem.iocache.tags.replacements 47569 # number of replacements 559901Sandreas@sandberg.pp.sesystem.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use 569838Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 579838Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 589838Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 599901Sandreas@sandberg.pp.sesystem.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. 609901Sandreas@sandberg.pp.sesystem.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor 619797Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 629838Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 6310036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 6410036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 6510036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 6610036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 428616 # Number of tag accesses 6710036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 428616 # Number of data accesses 689797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 699797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 904 # number of ReadReq misses 708835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 718613SN/Asystem.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 729797Sandreas.hansson@arm.comsystem.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 739797Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 47624 # number of demand (read+write) misses 749797Sandreas.hansson@arm.comsystem.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 759797Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 47624 # number of overall misses 769797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 779797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) 788835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 798613SN/Asystem.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 809797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 819797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 829797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 839797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses 848835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 859055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 868835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 879055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 888835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 899055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 908835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 919055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 928613SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 938613SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 948613SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 958613SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 968983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 978983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 988613SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 998613SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 1008835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 46667 # number of writebacks 1018835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 46667 # number of writebacks 1028613SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1038613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1048613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1059797Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 1068613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1078613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1088613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1098613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1108613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1118613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1128613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1138613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1148613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1159901Sandreas@sandberg.pp.sesystem.iobus.throughput 2555207 # Throughput (bytes/s) 1169901Sandreas@sandberg.pp.sesystem.iobus.data_through_bus 13062542 # Total data (bytes) 11710036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 11810036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 1199988Snilay@cs.wisc.edusystem.cpu.numCycles 10224253904 # number of cpu cycles simulated 1208613SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1218613SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1229901Sandreas@sandberg.pp.sesystem.cpu.committedInsts 199929810 # Number of instructions committed 1239962Sandreas.hansson@arm.comsystem.cpu.committedOps 409343850 # Number of ops (including micro ops) committed 1249962Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 374364636 # Number of integer alu accesses 1258613SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 1269901Sandreas@sandberg.pp.sesystem.cpu.num_func_calls 2307717 # number of times a function call or return occured 1279962Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 39976328 # number of instructions that are conditional controls 1289962Sandreas.hansson@arm.comsystem.cpu.num_int_insts 374364636 # number of integer instructions 1298613SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 1309962Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 682285475 # number of times the integer registers were read 1319962Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 323369236 # number of times the integer registers were written 1328613SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 1338613SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 1349962Sandreas.hansson@arm.comsystem.cpu.num_cc_register_reads 233715040 # number of times the CC registers were read 1359962Sandreas.hansson@arm.comsystem.cpu.num_cc_register_writes 157233555 # number of times the CC registers were written 1369901Sandreas@sandberg.pp.sesystem.cpu.num_mem_refs 35660913 # number of memory refs 1379901Sandreas@sandberg.pp.sesystem.cpu.num_load_insts 27238816 # Number of load instructions 1389901Sandreas@sandberg.pp.sesystem.cpu.num_store_insts 8422097 # Number of store instructions 1399988Snilay@cs.wisc.edusystem.cpu.num_idle_cycles 9770518213.691833 # Number of idle cycles 1409988Snilay@cs.wisc.edusystem.cpu.num_busy_cycles 453735690.308166 # Number of busy cycles 1419901Sandreas@sandberg.pp.sesystem.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles 1429901Sandreas@sandberg.pp.sesystem.cpu.idle_fraction 0.955622 # Percentage of idle cycles 1438613SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 1448613SN/Asystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1459962Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 790558 # number of replacements 1469901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use 1479962Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 243525778 # Total number of references to valid blocks. 1489962Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 791070 # Sample count of references to valid blocks. 1499962Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 307.843526 # Average number of references to valid blocks. 1509901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 1519901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 1529901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 1539901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy 15410036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 15510036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 15610036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 15710036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id 15810036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 15910036SAli.Saidi@ARM.comsystem.cpu.icache.tags.tag_accesses 245107932 # Number of tag accesses 16010036SAli.Saidi@ARM.comsystem.cpu.icache.tags.data_accesses 245107932 # Number of data accesses 1619962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 243525778 # number of ReadReq hits 1629962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 243525778 # number of ReadReq hits 1639962Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 243525778 # number of demand (read+write) hits 1649962Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 243525778 # number of demand (read+write) hits 1659962Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 243525778 # number of overall hits 1669962Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 243525778 # number of overall hits 1679962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 791077 # number of ReadReq misses 1689962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 791077 # number of ReadReq misses 1699962Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 791077 # number of demand (read+write) misses 1709962Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 791077 # number of demand (read+write) misses 1719962Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 791077 # number of overall misses 1729962Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 791077 # number of overall misses 1739962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 244316855 # number of ReadReq accesses(hits+misses) 1749962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 244316855 # number of ReadReq accesses(hits+misses) 1759962Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 244316855 # number of demand (read+write) accesses 1769962Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 244316855 # number of demand (read+write) accesses 1779962Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 244316855 # number of overall (read+write) accesses 1789962Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 244316855 # number of overall (read+write) accesses 1799625Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 1809625Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 1819625Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 1829625Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 1839625Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 1849625Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 1858613SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1868613SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1878613SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1888613SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1898983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1908983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1918613SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1928613SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1938613SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1949797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements 1959962Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.tagsinuse 3.026303 # Cycle average of tags in use 1969838Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 1979797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 1989838Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. 1999962Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000 # Cycle when the warmup percentage was hit. 2009962Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026303 # Average occupied blocks per requestor 2019901Sandreas@sandberg.pp.sesystem.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy 2029901Sandreas@sandberg.pp.sesystem.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy 20310036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 20410036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 20510036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 20610036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 20710036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id 20810036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses 20910036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.tags.data_accesses 28774 # Number of data accesses 2109625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 2119625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 2128835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 2138613SN/Asystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 2149625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 2159625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits 2169625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits 2179625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits 2189625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses 2199625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses 2209625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses 2219625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses 2229625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses 2239625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses 2249625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) 2259625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) 2268835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 2278613SN/Asystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 2289625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses 2299625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses 2309625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses 2319625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses 2329625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses 2339625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses 2349625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses 2359625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses 2369625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses 2379625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses 2388613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2398613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2408613SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 2418613SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 2428983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2438983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2448613SN/Asystem.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 2458613SN/Asystem.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 2469625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 2479625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 2488613SN/Asystem.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 2499797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements 2509962Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use 2519901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. 2529797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. 2539901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. 2549962Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000 # Cycle when the warmup percentage was hit. 2559962Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor 2569797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 2579797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 25810036SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 25910036SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 26010036SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 26110036SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 26210036SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id 26310036SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.tags.tag_accesses 52398 # Number of tag accesses 26410036SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.tags.data_accesses 52398 # Number of data accesses 2659901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits 2669901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits 2679901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits 2689901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits 2699901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits 2709901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits 2719901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses 2729901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses 2739901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses 2749901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses 2759901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses 2769901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses 2779901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses) 2789901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses) 2799901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses 2809901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses 2819901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses 2829901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses 2839901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses 2849901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses 2859901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses 2869901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses 2879901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses 2889901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses 2898613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2908613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2918613SN/Asystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 2928613SN/Asystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 2938983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2948983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2958613SN/Asystem.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 2968613SN/Asystem.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 2979901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks 2989901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks 2998613SN/Asystem.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 3009962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1622097 # number of replacements 3019838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use 3029962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 20175179 # Total number of references to valid blocks. 3039962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1622609 # Sample count of references to valid blocks. 3049962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 12.433790 # Average number of references to valid blocks. 3059838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 3069838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 3079838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 3089838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 30910036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31010036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id 31110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id 31210036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id 31310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 31410036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.tag_accesses 88813841 # Number of tag accesses 31510036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.data_accesses 88813841 # Number of data accesses 3169962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 12077531 # number of ReadReq hits 3179962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 12077531 # number of ReadReq hits 3189962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 8095378 # number of WriteReq hits 3199962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 8095378 # number of WriteReq hits 3209962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 20172909 # number of demand (read+write) hits 3219962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 20172909 # number of demand (read+write) hits 3229962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 20172909 # number of overall hits 3239962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 20172909 # number of overall hits 3249962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1308430 # number of ReadReq misses 3259962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1308430 # number of ReadReq misses 3269962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 316465 # number of WriteReq misses 3279962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 316465 # number of WriteReq misses 3289962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1624895 # number of demand (read+write) misses 3299962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1624895 # number of demand (read+write) misses 3309962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1624895 # number of overall misses 3319962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1624895 # number of overall misses 3329901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses) 3339901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses) 3349901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses) 3359901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses) 3369901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses 3379901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses 3389901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses 3399901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses 3409901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses 3419901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses 3429962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses 3439962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses 3449901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses 3459901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses 3469901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses 3479901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses 3488613SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3498613SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3508613SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 3518613SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 3528983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3538983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3548613SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 3558613SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 3569962Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1535825 # number of writebacks 3579962Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1535825 # number of writebacks 3588613SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 3599962Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 54625221 # Throughput (bytes/s) 3609962Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 279225555 # Total data (bytes) 3619797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 3629901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.replacements 105999 # number of replacements 3639962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 64822.034013 # Cycle average of tags in use 3649962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3456623 # Total number of references to valid blocks. 3659901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks. 3669962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 20.317898 # Average number of references to valid blocks. 3679838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3689962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 51908.839094 # Average occupied blocks per requestor 3699901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor 3709901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor 3719962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.539598 # Average occupied blocks per requestor 3729962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 10422.520587 # Average occupied blocks per requestor 3739901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy 3749797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 3759797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 3769797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 3779901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy 3789901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy 37910036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 # Occupied blocks per task id 38010036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 38110036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id 38210036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id 38310036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 20892 # Occupied blocks per task id 38410036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 39453 # Occupied blocks per task id 38510036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id 38610036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tag_accesses 32198887 # Number of tag accesses 38710036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 32198887 # Number of data accesses 3889901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits 3899625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 3909962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 777739 # number of ReadReq hits 3919962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 1275554 # number of ReadReq hits 3929962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2062599 # number of ReadReq hits 3939962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 1538784 # number of Writeback hits 3949962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 1538784 # number of Writeback hits 3959625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 3969625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 3979962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 179732 # number of ReadExReq hits 3989962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 179732 # number of ReadExReq hits 3999901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits 4009625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 4019962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 777739 # number of demand (read+write) hits 4029962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1455286 # number of demand (read+write) hits 4039962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2242331 # number of demand (read+write) hits 4049901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits 4059625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 4069962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 777739 # number of overall hits 4079962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1455286 # number of overall hits 4089962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2242331 # number of overall hits 4099901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 4109289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 4119625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 4129672Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 4139901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses 4149901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses 4159901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses 4169901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses 4179901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses 4189901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 4199289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 4209625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 4219901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses 4229901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses 4239901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 4249289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 4259625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 4269901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses 4279901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::total 180035 # number of overall misses 4289901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) 4299625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 4309962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 791064 # number of ReadReq accesses(hits+misses) 4319962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1307800 # number of ReadReq accesses(hits+misses) 4329962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2108176 # number of ReadReq accesses(hits+misses) 4339962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 1538784 # number of Writeback accesses(hits+misses) 4349962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 1538784 # number of Writeback accesses(hits+misses) 4359901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 4369901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) 4379962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 314190 # number of ReadExReq accesses(hits+misses) 4389962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 314190 # number of ReadExReq accesses(hits+misses) 4399901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses 4409625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 4419962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 791064 # number of demand (read+write) accesses 4429962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1621990 # number of demand (read+write) accesses 4439962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2422366 # number of demand (read+write) accesses 4449901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses 4459625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 4469962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 791064 # number of overall (read+write) accesses 4479962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1621990 # number of overall (read+write) accesses 4489962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2422366 # number of overall (read+write) accesses 4499901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses 4509625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 4519962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses 4529797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 4539901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses 4549901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses 4559901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses 4569962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427951 # miss rate for ReadExReq accesses 4579962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.427951 # miss rate for ReadExReq accesses 4589901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 4599625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 4609962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses 4619962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.102777 # miss rate for demand accesses 4629962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.074322 # miss rate for demand accesses 4639901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 4649625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 4659962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses 4669962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.102777 # miss rate for overall accesses 4679962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.074322 # miss rate for overall accesses 4689289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4699289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4709289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 4719289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 4729289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4739289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4749289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 4759289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 4769901Sandreas@sandberg.pp.sesystem.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks 4779901Sandreas@sandberg.pp.sesystem.cpu.l2cache.writebacks::total 98156 # number of writebacks 4789289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 4797927SN/A 4807927SN/A---------- End Simulation Statistics ---------- 481