stats.txt revision 10036
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112126 # Number of seconds simulated 4sim_ticks 5112126264500 # Number of ticks simulated 5final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1777208 # Simulator instruction rate (inst/s) 8host_op_rate 3638722 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45442487875 # Simulator tick rate (ticks/s) 10host_mem_usage 590176 # Number of bytes of host memory used 11host_seconds 112.50 # Real time elapsed on the host 12sim_insts 199929810 # Number of instructions simulated 13sim_ops 409343850 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory 21system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory 26system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory 34system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2715827 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) 51system.membus.throughput 9634332 # Throughput (bytes/s) 52system.membus.data_through_bus 49251923 # Total data (bytes) 53system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 54system.iocache.tags.replacements 47569 # number of replacements 55system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use 56system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 57system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 58system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 59system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. 60system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor 61system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 62system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 63system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 64system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 65system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 66system.iocache.tags.tag_accesses 428616 # Number of tag accesses 67system.iocache.tags.data_accesses 428616 # Number of data accesses 68system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 69system.iocache.ReadReq_misses::total 904 # number of ReadReq misses 70system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 71system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 72system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 73system.iocache.demand_misses::total 47624 # number of demand (read+write) misses 74system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 75system.iocache.overall_misses::total 47624 # number of overall misses 76system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 77system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) 78system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 79system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 80system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 81system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 82system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 83system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses 84system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 85system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 86system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 87system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 88system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 89system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 90system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 91system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 92system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 93system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 94system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 95system.iocache.blocked::no_targets 0 # number of cycles access was blocked 96system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 97system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 98system.iocache.fast_writes 0 # number of fast writes performed 99system.iocache.cache_copies 0 # number of cache copies performed 100system.iocache.writebacks::writebacks 46667 # number of writebacks 101system.iocache.writebacks::total 46667 # number of writebacks 102system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 103system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 104system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 105system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 106system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 107system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 108system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 109system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 110system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 111system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 112system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 113system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 114system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 115system.iobus.throughput 2555207 # Throughput (bytes/s) 116system.iobus.data_through_bus 13062542 # Total data (bytes) 117system.cpu_clk_domain.clock 500 # Clock period in ticks 118system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 119system.cpu.numCycles 10224253904 # number of cpu cycles simulated 120system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 121system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 122system.cpu.committedInsts 199929810 # Number of instructions committed 123system.cpu.committedOps 409343850 # Number of ops (including micro ops) committed 124system.cpu.num_int_alu_accesses 374364636 # Number of integer alu accesses 125system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 126system.cpu.num_func_calls 2307717 # number of times a function call or return occured 127system.cpu.num_conditional_control_insts 39976328 # number of instructions that are conditional controls 128system.cpu.num_int_insts 374364636 # number of integer instructions 129system.cpu.num_fp_insts 0 # number of float instructions 130system.cpu.num_int_register_reads 682285475 # number of times the integer registers were read 131system.cpu.num_int_register_writes 323369236 # number of times the integer registers were written 132system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 133system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 134system.cpu.num_cc_register_reads 233715040 # number of times the CC registers were read 135system.cpu.num_cc_register_writes 157233555 # number of times the CC registers were written 136system.cpu.num_mem_refs 35660913 # number of memory refs 137system.cpu.num_load_insts 27238816 # Number of load instructions 138system.cpu.num_store_insts 8422097 # Number of store instructions 139system.cpu.num_idle_cycles 9770518213.691833 # Number of idle cycles 140system.cpu.num_busy_cycles 453735690.308166 # Number of busy cycles 141system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles 142system.cpu.idle_fraction 0.955622 # Percentage of idle cycles 143system.cpu.kern.inst.arm 0 # number of arm instructions executed 144system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 145system.cpu.icache.tags.replacements 790558 # number of replacements 146system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use 147system.cpu.icache.tags.total_refs 243525778 # Total number of references to valid blocks. 148system.cpu.icache.tags.sampled_refs 791070 # Sample count of references to valid blocks. 149system.cpu.icache.tags.avg_refs 307.843526 # Average number of references to valid blocks. 150system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 151system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 152system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 153system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy 154system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 155system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 156system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 157system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id 158system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 159system.cpu.icache.tags.tag_accesses 245107932 # Number of tag accesses 160system.cpu.icache.tags.data_accesses 245107932 # Number of data accesses 161system.cpu.icache.ReadReq_hits::cpu.inst 243525778 # number of ReadReq hits 162system.cpu.icache.ReadReq_hits::total 243525778 # number of ReadReq hits 163system.cpu.icache.demand_hits::cpu.inst 243525778 # number of demand (read+write) hits 164system.cpu.icache.demand_hits::total 243525778 # number of demand (read+write) hits 165system.cpu.icache.overall_hits::cpu.inst 243525778 # number of overall hits 166system.cpu.icache.overall_hits::total 243525778 # number of overall hits 167system.cpu.icache.ReadReq_misses::cpu.inst 791077 # number of ReadReq misses 168system.cpu.icache.ReadReq_misses::total 791077 # number of ReadReq misses 169system.cpu.icache.demand_misses::cpu.inst 791077 # number of demand (read+write) misses 170system.cpu.icache.demand_misses::total 791077 # number of demand (read+write) misses 171system.cpu.icache.overall_misses::cpu.inst 791077 # number of overall misses 172system.cpu.icache.overall_misses::total 791077 # number of overall misses 173system.cpu.icache.ReadReq_accesses::cpu.inst 244316855 # number of ReadReq accesses(hits+misses) 174system.cpu.icache.ReadReq_accesses::total 244316855 # number of ReadReq accesses(hits+misses) 175system.cpu.icache.demand_accesses::cpu.inst 244316855 # number of demand (read+write) accesses 176system.cpu.icache.demand_accesses::total 244316855 # number of demand (read+write) accesses 177system.cpu.icache.overall_accesses::cpu.inst 244316855 # number of overall (read+write) accesses 178system.cpu.icache.overall_accesses::total 244316855 # number of overall (read+write) accesses 179system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 180system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 181system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 182system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 183system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 184system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 185system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 186system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 187system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 188system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 189system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 190system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 191system.cpu.icache.fast_writes 0 # number of fast writes performed 192system.cpu.icache.cache_copies 0 # number of cache copies performed 193system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 194system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements 195system.cpu.itb_walker_cache.tags.tagsinuse 3.026303 # Cycle average of tags in use 196system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 197system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 198system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. 199system.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000 # Cycle when the warmup percentage was hit. 200system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026303 # Average occupied blocks per requestor 201system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy 202system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy 203system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 204system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 205system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 206system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 207system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id 208system.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses 209system.cpu.itb_walker_cache.tags.data_accesses 28774 # Number of data accesses 210system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 211system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 212system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 213system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 214system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 215system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits 216system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits 217system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits 218system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses 219system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses 220system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses 221system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses 222system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses 223system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses 224system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) 225system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) 226system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 227system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 228system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses 229system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses 230system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses 231system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses 232system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses 233system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses 234system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses 235system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses 236system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses 237system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses 238system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 239system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 240system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 241system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 242system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 243system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 244system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 245system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 246system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 247system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 248system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 249system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements 250system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use 251system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. 252system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. 253system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. 254system.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000 # Cycle when the warmup percentage was hit. 255system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor 256system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 257system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 258system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 259system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 260system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 261system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 262system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id 263system.cpu.dtb_walker_cache.tags.tag_accesses 52398 # Number of tag accesses 264system.cpu.dtb_walker_cache.tags.data_accesses 52398 # Number of data accesses 265system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits 266system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits 267system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits 268system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits 269system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits 270system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits 271system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses 272system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses 273system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses 274system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses 275system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses 276system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses 277system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses) 278system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses) 279system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses 280system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses 281system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses 282system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses 283system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses 284system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses 285system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses 286system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses 287system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses 288system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses 289system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 290system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 291system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 292system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 293system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 294system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 295system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 296system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 297system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks 298system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks 299system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 300system.cpu.dcache.tags.replacements 1622097 # number of replacements 301system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use 302system.cpu.dcache.tags.total_refs 20175179 # Total number of references to valid blocks. 303system.cpu.dcache.tags.sampled_refs 1622609 # Sample count of references to valid blocks. 304system.cpu.dcache.tags.avg_refs 12.433790 # Average number of references to valid blocks. 305system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 306system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 307system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 308system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 309system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 310system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id 311system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id 312system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id 313system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 314system.cpu.dcache.tags.tag_accesses 88813841 # Number of tag accesses 315system.cpu.dcache.tags.data_accesses 88813841 # Number of data accesses 316system.cpu.dcache.ReadReq_hits::cpu.data 12077531 # number of ReadReq hits 317system.cpu.dcache.ReadReq_hits::total 12077531 # number of ReadReq hits 318system.cpu.dcache.WriteReq_hits::cpu.data 8095378 # number of WriteReq hits 319system.cpu.dcache.WriteReq_hits::total 8095378 # number of WriteReq hits 320system.cpu.dcache.demand_hits::cpu.data 20172909 # number of demand (read+write) hits 321system.cpu.dcache.demand_hits::total 20172909 # number of demand (read+write) hits 322system.cpu.dcache.overall_hits::cpu.data 20172909 # number of overall hits 323system.cpu.dcache.overall_hits::total 20172909 # number of overall hits 324system.cpu.dcache.ReadReq_misses::cpu.data 1308430 # number of ReadReq misses 325system.cpu.dcache.ReadReq_misses::total 1308430 # number of ReadReq misses 326system.cpu.dcache.WriteReq_misses::cpu.data 316465 # number of WriteReq misses 327system.cpu.dcache.WriteReq_misses::total 316465 # number of WriteReq misses 328system.cpu.dcache.demand_misses::cpu.data 1624895 # number of demand (read+write) misses 329system.cpu.dcache.demand_misses::total 1624895 # number of demand (read+write) misses 330system.cpu.dcache.overall_misses::cpu.data 1624895 # number of overall misses 331system.cpu.dcache.overall_misses::total 1624895 # number of overall misses 332system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses) 333system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses) 334system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses) 335system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses) 336system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses 337system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses 338system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses 339system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses 340system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses 341system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses 342system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses 343system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses 344system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses 345system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses 346system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses 347system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses 348system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu.dcache.fast_writes 0 # number of fast writes performed 355system.cpu.dcache.cache_copies 0 # number of cache copies performed 356system.cpu.dcache.writebacks::writebacks 1535825 # number of writebacks 357system.cpu.dcache.writebacks::total 1535825 # number of writebacks 358system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 359system.cpu.toL2Bus.throughput 54625221 # Throughput (bytes/s) 360system.cpu.toL2Bus.data_through_bus 279225555 # Total data (bytes) 361system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 362system.cpu.l2cache.tags.replacements 105999 # number of replacements 363system.cpu.l2cache.tags.tagsinuse 64822.034013 # Cycle average of tags in use 364system.cpu.l2cache.tags.total_refs 3456623 # Total number of references to valid blocks. 365system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks. 366system.cpu.l2cache.tags.avg_refs 20.317898 # Average number of references to valid blocks. 367system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 368system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839094 # Average occupied blocks per requestor 369system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor 370system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor 371system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.539598 # Average occupied blocks per requestor 372system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.520587 # Average occupied blocks per requestor 373system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy 374system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 375system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 376system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 377system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy 378system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy 379system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 # Occupied blocks per task id 380system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 381system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id 382system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id 383system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20892 # Occupied blocks per task id 384system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39453 # Occupied blocks per task id 385system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id 386system.cpu.l2cache.tags.tag_accesses 32198887 # Number of tag accesses 387system.cpu.l2cache.tags.data_accesses 32198887 # Number of data accesses 388system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits 389system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 390system.cpu.l2cache.ReadReq_hits::cpu.inst 777739 # number of ReadReq hits 391system.cpu.l2cache.ReadReq_hits::cpu.data 1275554 # number of ReadReq hits 392system.cpu.l2cache.ReadReq_hits::total 2062599 # number of ReadReq hits 393system.cpu.l2cache.Writeback_hits::writebacks 1538784 # number of Writeback hits 394system.cpu.l2cache.Writeback_hits::total 1538784 # number of Writeback hits 395system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 396system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 397system.cpu.l2cache.ReadExReq_hits::cpu.data 179732 # number of ReadExReq hits 398system.cpu.l2cache.ReadExReq_hits::total 179732 # number of ReadExReq hits 399system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits 400system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 401system.cpu.l2cache.demand_hits::cpu.inst 777739 # number of demand (read+write) hits 402system.cpu.l2cache.demand_hits::cpu.data 1455286 # number of demand (read+write) hits 403system.cpu.l2cache.demand_hits::total 2242331 # number of demand (read+write) hits 404system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits 405system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 406system.cpu.l2cache.overall_hits::cpu.inst 777739 # number of overall hits 407system.cpu.l2cache.overall_hits::cpu.data 1455286 # number of overall hits 408system.cpu.l2cache.overall_hits::total 2242331 # number of overall hits 409system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 410system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 411system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 412system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 413system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses 414system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses 415system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses 416system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses 417system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses 418system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 419system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 420system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 421system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses 422system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses 423system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 424system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 425system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 426system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses 427system.cpu.l2cache.overall_misses::total 180035 # number of overall misses 428system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) 429system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 430system.cpu.l2cache.ReadReq_accesses::cpu.inst 791064 # number of ReadReq accesses(hits+misses) 431system.cpu.l2cache.ReadReq_accesses::cpu.data 1307800 # number of ReadReq accesses(hits+misses) 432system.cpu.l2cache.ReadReq_accesses::total 2108176 # number of ReadReq accesses(hits+misses) 433system.cpu.l2cache.Writeback_accesses::writebacks 1538784 # number of Writeback accesses(hits+misses) 434system.cpu.l2cache.Writeback_accesses::total 1538784 # number of Writeback accesses(hits+misses) 435system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 436system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) 437system.cpu.l2cache.ReadExReq_accesses::cpu.data 314190 # number of ReadExReq accesses(hits+misses) 438system.cpu.l2cache.ReadExReq_accesses::total 314190 # number of ReadExReq accesses(hits+misses) 439system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses 440system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 441system.cpu.l2cache.demand_accesses::cpu.inst 791064 # number of demand (read+write) accesses 442system.cpu.l2cache.demand_accesses::cpu.data 1621990 # number of demand (read+write) accesses 443system.cpu.l2cache.demand_accesses::total 2422366 # number of demand (read+write) accesses 444system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses 445system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 446system.cpu.l2cache.overall_accesses::cpu.inst 791064 # number of overall (read+write) accesses 447system.cpu.l2cache.overall_accesses::cpu.data 1621990 # number of overall (read+write) accesses 448system.cpu.l2cache.overall_accesses::total 2422366 # number of overall (read+write) accesses 449system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses 450system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 451system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses 452system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 453system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses 454system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses 455system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses 456system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427951 # miss rate for ReadExReq accesses 457system.cpu.l2cache.ReadExReq_miss_rate::total 0.427951 # miss rate for ReadExReq accesses 458system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 459system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 460system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses 461system.cpu.l2cache.demand_miss_rate::cpu.data 0.102777 # miss rate for demand accesses 462system.cpu.l2cache.demand_miss_rate::total 0.074322 # miss rate for demand accesses 463system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 464system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 465system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses 466system.cpu.l2cache.overall_miss_rate::cpu.data 0.102777 # miss rate for overall accesses 467system.cpu.l2cache.overall_miss_rate::total 0.074322 # miss rate for overall accesses 468system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 469system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 470system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 471system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 472system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 473system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 474system.cpu.l2cache.fast_writes 0 # number of fast writes performed 475system.cpu.l2cache.cache_copies 0 # number of cache copies performed 476system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks 477system.cpu.l2cache.writebacks::total 98156 # number of writebacks 478system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 479 480---------- End Simulation Statistics ---------- 481