stats.txt revision 9568
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 39134Ssaidi@eecs.umich.edusim_seconds 0.912097 # Number of seconds simulated 49134Ssaidi@eecs.umich.edusim_ticks 912096763500 # Number of ticks simulated 59134Ssaidi@eecs.umich.edufinal_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 79568Sandreas.hansson@arm.comhost_inst_rate 1025890 # Simulator instruction rate (inst/s) 89568Sandreas.hansson@arm.comhost_op_rate 1320831 # Simulator op (including micro ops) rate (op/s) 99568Sandreas.hansson@arm.comhost_tick_rate 15183699019 # Simulator tick rate (ticks/s) 109568Sandreas.hansson@arm.comhost_mem_usage 392232 # Number of bytes of host memory used 119568Sandreas.hansson@arm.comhost_seconds 60.07 # Real time elapsed on the host 129134Ssaidi@eecs.umich.edusim_insts 61625970 # Number of instructions simulated 139134Ssaidi@eecs.umich.edusim_ops 79343340 # Number of ops (including micro ops) simulated 149134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 159134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 169134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 179134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory 189449SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory 199134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 209134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory 219134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory 229449SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 49638500 # Number of bytes read from this memory 239134Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory 249134Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory 259134Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory 269134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory 279134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 289134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 299134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::total 7222864 # Number of bytes written to this memory 309134Ssaidi@eecs.umich.edusystem.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 319134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 329134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 339134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory 349449SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory 359134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 369134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory 379134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory 389449SAli.Saidi@ARM.comsystem.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory 399134Ssaidi@eecs.umich.edusystem.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory 409134Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 419134Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 429134Ssaidi@eecs.umich.edusystem.physmem.num_writes::total 822331 # Number of write requests responded to by this memory 439134Ssaidi@eecs.umich.edusystem.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) 449134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) 459134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) 469134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) 479449SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s) 489134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) 499134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) 509134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) 519449SAli.Saidi@ARM.comsystem.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s) 529134Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) 539134Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) 549134Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) 559134Ssaidi@eecs.umich.edusystem.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) 569134Ssaidi@eecs.umich.edusystem.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) 579134Ssaidi@eecs.umich.edusystem.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) 589134Ssaidi@eecs.umich.edusystem.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) 599134Ssaidi@eecs.umich.edusystem.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) 609134Ssaidi@eecs.umich.edusystem.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) 619134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) 629134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) 639134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) 649449SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s) 659134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) 669134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) 679134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) 689449SAli.Saidi@ARM.comsystem.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) 699312Sandreas.hansson@arm.comsystem.physmem.readReqs 0 # Total number of read requests seen 709312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 719312Sandreas.hansson@arm.comsystem.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady 729312Sandreas.hansson@arm.comsystem.physmem.bytesRead 0 # Total number of bytes read from memory 739312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 749312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 759312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 769312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 779312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 789312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 799312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 809312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 819312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 829312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 839312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 849312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 859312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 869312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 879312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 889312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 899312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 909312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 919312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 929312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 939312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 949312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 959312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 969312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 979312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 989312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 999312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 1009312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 1019312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 1029312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 1039312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 1049312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 1059312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 1069312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 1079312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 1089312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 1099312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 1109312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 1119312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 1129312Sandreas.hansson@arm.comsystem.physmem.totGap 0 # Total gap between requests 1139312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 1149312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 1159312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 1169312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 1179312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 1189312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 1199312Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 0 # Categorize read packet sizes 1209568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 1219568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 1229568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 1239568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 1249568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 1259568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 1269568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1679312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1689312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1699312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1709312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1719312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1729312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1739312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1749312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1759312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1769312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1779312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1789312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1799312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1809312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1819312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1829312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1839312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1849312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1859312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1869312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1879312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1889312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1899312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1909312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1919312Sandreas.hansson@arm.comsystem.physmem.totQLat 0 # Total cycles spent in queuing delays 1929312Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 0 # Sum of mem lat for all requests 1939312Sandreas.hansson@arm.comsystem.physmem.totBusLat 0 # Total cycles spent in databus access 1949312Sandreas.hansson@arm.comsystem.physmem.totBankLat 0 # Total cycles spent in bank access 1959312Sandreas.hansson@arm.comsystem.physmem.avgQLat nan # Average queueing delay per request 1969312Sandreas.hansson@arm.comsystem.physmem.avgBankLat nan # Average bank access latency per request 1979312Sandreas.hansson@arm.comsystem.physmem.avgBusLat nan # Average bus latency per request 1989312Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat nan # Average memory access latency 1999312Sandreas.hansson@arm.comsystem.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 2009312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 2019312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 2029312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 2039490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 2049312Sandreas.hansson@arm.comsystem.physmem.busUtil 0.00 # Data bus utilization in percentage 2059312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.00 # Average read queue length over time 2069312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 2079312Sandreas.hansson@arm.comsystem.physmem.readRowHits 0 # Number of row buffer hits during reads 2089312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 2099312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate nan # Row buffer hit rate for reads 2109312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 2119312Sandreas.hansson@arm.comsystem.physmem.avgGap nan # Average gap between requests 2129481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 2139481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 2149481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 2159481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 2169481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 2179481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 2189481Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 2199481Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 2209481Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 2219481Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 2229481Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 2239481Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 2249481Snilay@cs.wisc.edusystem.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 2259481Snilay@cs.wisc.edusystem.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 2269481Snilay@cs.wisc.edusystem.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 2279481Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 2289481Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 2299481Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 2309449SAli.Saidi@ARM.comsystem.l2c.replacements 70658 # number of replacements 2319449SAli.Saidi@ARM.comsystem.l2c.tagsinuse 51560.149653 # Cycle average of tags in use 2329449SAli.Saidi@ARM.comsystem.l2c.total_refs 1623339 # Total number of references to valid blocks. 2339449SAli.Saidi@ARM.comsystem.l2c.sampled_refs 135810 # Sample count of references to valid blocks. 2349449SAli.Saidi@ARM.comsystem.l2c.avg_refs 11.953015 # Average number of references to valid blocks. 2358844SAli.Saidi@ARM.comsystem.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2369449SAli.Saidi@ARM.comsystem.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor 2379079SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor 2389134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor 2399449SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor 2409449SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor 2419134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor 2429134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor 2439134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor 2449449SAli.Saidi@ARM.comsystem.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy 2459079SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 2469079SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 2479449SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy 2489449SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy 2499079SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 2509134Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy 2519134Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy 2529449SAli.Saidi@ARM.comsystem.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy 2539134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits 2549134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits 2559134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits 2569134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits 2579134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits 2589134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits 2599134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits 2609134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits 2619134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits 2629134Ssaidi@eecs.umich.edusystem.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits 2639134Ssaidi@eecs.umich.edusystem.l2c.Writeback_hits::total 567807 # number of Writeback hits 2649134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 2659134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits 2669134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits 2679134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits 2689134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits 2699134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits 2709449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits 2719134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits 2729449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits 2739134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits 2749134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits 2759134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits 2769449SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits 2779134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits 2789134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits 2799134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits 2809134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits 2819449SAli.Saidi@ARM.comsystem.l2c.demand_hits::total 1317466 # number of demand (read+write) hits 2829134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits 2839134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits 2849134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.inst 421038 # number of overall hits 2859449SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.data 233336 # number of overall hits 2869134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits 2879134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits 2889134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.inst 430511 # number of overall hits 2899134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.data 219723 # number of overall hits 2909449SAli.Saidi@ARM.comsystem.l2c.overall_hits::total 1317466 # number of overall hits 2919079SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 2929134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 2939134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses 2949134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses 2959079SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 2969134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses 2979134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses 2989134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::total 22454 # number of ReadReq misses 2999134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses 3009134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses 3019134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses 3029134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses 3039134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses 3049134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses 3059449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses 3069134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses 3079449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses 3089079SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 3099134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 3109134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses 3119449SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses 3129079SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 3139134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses 3149134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses 3159449SAli.Saidi@ARM.comsystem.l2c.demand_misses::total 163290 # number of demand (read+write) misses 3169079SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 3179134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 3189134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.inst 7432 # number of overall misses 3199449SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.data 98856 # number of overall misses 3209079SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 3219134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu1.inst 3347 # number of overall misses 3229134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu1.data 53648 # number of overall misses 3239449SAli.Saidi@ARM.comsystem.l2c.overall_misses::total 163290 # number of overall misses 3249134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) 3259134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) 3269134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) 3279134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses) 3289134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) 3299134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) 3309134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) 3319134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses) 3329134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) 3339134Ssaidi@eecs.umich.edusystem.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) 3349134Ssaidi@eecs.umich.edusystem.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) 3359134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) 3369134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) 3379134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) 3389134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) 3399134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) 3409134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) 3419134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses) 3429134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses) 3439134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) 3449134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses 3459134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses 3469134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses 3479134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses 3489134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses 3499134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses 3509134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses 3519134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses 3529134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses 3539134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses 3549134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses 3559134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses 3569134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses 3579134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses 3589134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses 3599134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses 3609134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses 3619134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses 3629134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses 3639134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses 3649134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses 3659134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses 3669134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses 3679134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses 3689134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses 3699134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses 3709134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses 3719134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses 3729134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses 3739134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses 3749134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses 3759134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses 3769449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses 3779134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses 3789449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses 3799134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses 3809134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses 3819134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses 3829449SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses 3839134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses 3849134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses 3859134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses 3869449SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses 3879134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses 3889134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses 3899134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses 3909449SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses 3919134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses 3929134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses 3939134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses 3949449SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses 3958844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3968844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3978844SAli.Saidi@ARM.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 3988844SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 3998983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4008983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4018844SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 4028844SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 4039134Ssaidi@eecs.umich.edusystem.l2c.writebacks::writebacks 65559 # number of writebacks 4049134Ssaidi@eecs.umich.edusystem.l2c.writebacks::total 65559 # number of writebacks 4058844SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 4068844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4078844SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 4088844SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 4098844SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 4108844SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 4118844SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 0 # Number of DMA write transactions. 4128844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 4138844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 4149134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_hits 7975768 # DTB read hits 4159134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_misses 3611 # DTB read misses 4169134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_hits 5966574 # DTB write hits 4179134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_misses 672 # DTB write misses 4188844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 4198844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4208844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4218844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 4229134Ssaidi@eecs.umich.edusystem.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB 4238844SAli.Saidi@ARM.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4249134Ssaidi@eecs.umich.edusystem.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch 4258844SAli.Saidi@ARM.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4269134Ssaidi@eecs.umich.edusystem.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 4279134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_accesses 7979379 # DTB read accesses 4289134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_accesses 5967246 # DTB write accesses 4298844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 4309134Ssaidi@eecs.umich.edusystem.cpu0.dtb.hits 13942342 # DTB hits 4319134Ssaidi@eecs.umich.edusystem.cpu0.dtb.misses 4283 # DTB misses 4329134Ssaidi@eecs.umich.edusystem.cpu0.dtb.accesses 13946625 # DTB accesses 4339134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_hits 30238804 # ITB inst hits 4349134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_misses 2175 # ITB inst misses 4358844SAli.Saidi@ARM.comsystem.cpu0.itb.read_hits 0 # DTB read hits 4368844SAli.Saidi@ARM.comsystem.cpu0.itb.read_misses 0 # DTB read misses 4378844SAli.Saidi@ARM.comsystem.cpu0.itb.write_hits 0 # DTB write hits 4388844SAli.Saidi@ARM.comsystem.cpu0.itb.write_misses 0 # DTB write misses 4398844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 4408844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4418844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4428844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 4439134Ssaidi@eecs.umich.edusystem.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB 4448844SAli.Saidi@ARM.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4458844SAli.Saidi@ARM.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4468844SAli.Saidi@ARM.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4478844SAli.Saidi@ARM.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4488844SAli.Saidi@ARM.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 4498844SAli.Saidi@ARM.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 4509134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_accesses 30240979 # ITB inst accesses 4519134Ssaidi@eecs.umich.edusystem.cpu0.itb.hits 30238804 # DTB hits 4529134Ssaidi@eecs.umich.edusystem.cpu0.itb.misses 2175 # DTB misses 4539134Ssaidi@eecs.umich.edusystem.cpu0.itb.accesses 30240979 # DTB accesses 4549134Ssaidi@eecs.umich.edusystem.cpu0.numCycles 1823633059 # number of cpu cycles simulated 4558844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 4568844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 4579134Ssaidi@eecs.umich.edusystem.cpu0.committedInsts 29750005 # Number of instructions committed 4589134Ssaidi@eecs.umich.edusystem.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed 4599134Ssaidi@eecs.umich.edusystem.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses 4609134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses 4619134Ssaidi@eecs.umich.edusystem.cpu0.num_func_calls 1241903 # number of times a function call or return occured 4629265SAli.Saidi@ARM.comsystem.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls 4639134Ssaidi@eecs.umich.edusystem.cpu0.num_int_insts 34471201 # number of integer instructions 4649134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_insts 5449 # number of float instructions 4659134Ssaidi@eecs.umich.edusystem.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read 4669134Ssaidi@eecs.umich.edusystem.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written 4679134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read 4689134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 4699134Ssaidi@eecs.umich.edusystem.cpu0.num_mem_refs 14626951 # number of memory refs 4709134Ssaidi@eecs.umich.edusystem.cpu0.num_load_insts 8357226 # Number of load instructions 4719134Ssaidi@eecs.umich.edusystem.cpu0.num_store_insts 6269725 # Number of store instructions 4729134Ssaidi@eecs.umich.edusystem.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles 4739134Ssaidi@eecs.umich.edusystem.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles 4749134Ssaidi@eecs.umich.edusystem.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles 4759134Ssaidi@eecs.umich.edusystem.cpu0.idle_fraction 0.978250 # Percentage of idle cycles 4768844SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 4779134Ssaidi@eecs.umich.edusystem.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed 4789449SAli.Saidi@ARM.comsystem.cpu0.icache.replacements 428546 # number of replacements 4799449SAli.Saidi@ARM.comsystem.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use 4809134Ssaidi@eecs.umich.edusystem.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks. 4819449SAli.Saidi@ARM.comsystem.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks. 4829449SAli.Saidi@ARM.comsystem.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks. 4839134Ssaidi@eecs.umich.edusystem.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. 4849449SAli.Saidi@ARM.comsystem.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor 4859449SAli.Saidi@ARM.comsystem.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy 4869449SAli.Saidi@ARM.comsystem.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy 4879134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits 4889134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits 4899134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits 4909134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits 4919134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits 4929134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_hits::total 29811115 # number of overall hits 4939134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses 4949134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses 4959134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses 4969134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses 4979134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses 4989134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::total 429059 # number of overall misses 4999134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) 5009134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) 5019134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses 5029134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses 5039134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses 5049134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses 5059134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses 5069134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses 5079134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses 5089134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses 5099134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses 5109134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses 5118844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5128844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5138844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5148844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 5158983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5168983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5178844SAli.Saidi@ARM.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 5188844SAli.Saidi@ARM.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 5198844SAli.Saidi@ARM.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5209134Ssaidi@eecs.umich.edusystem.cpu0.dcache.replacements 323609 # number of replacements 5219134Ssaidi@eecs.umich.edusystem.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use 5229134Ssaidi@eecs.umich.edusystem.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks. 5239134Ssaidi@eecs.umich.edusystem.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks. 5249134Ssaidi@eecs.umich.edusystem.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks. 5258844SAli.Saidi@ARM.comsystem.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. 5269134Ssaidi@eecs.umich.edusystem.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor 5279134Ssaidi@eecs.umich.edusystem.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy 5289134Ssaidi@eecs.umich.edusystem.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy 5299134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits 5309134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits 5319134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits 5329134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits 5339134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits 5349134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits 5359134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits 5369134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits 5379134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits 5389134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits 5399134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits 5409134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_hits::total 12143186 # number of overall hits 5419134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses 5429134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses 5439134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses 5449134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses 5459134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses 5469134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses 5479134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses 5489134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses 5499134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses 5509134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses 5519134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses 5529134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_misses::total 364509 # number of overall misses 5539134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) 5549134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) 5559134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) 5569134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) 5579134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) 5589134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) 5599134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses) 5609134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses) 5619134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses 5629134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses 5639134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses 5649134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses 5659134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses 5669134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses 5679134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses 5689134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses 5699134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses 5709134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses 5719134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses 5729134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses 5739134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses 5749134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses 5759134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses 5769134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses 5778844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5788844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5798844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5808844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 5818983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5828983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5838844SAli.Saidi@ARM.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 5848844SAli.Saidi@ARM.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 5859134Ssaidi@eecs.umich.edusystem.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks 5869134Ssaidi@eecs.umich.edusystem.cpu0.dcache.writebacks::total 300958 # number of writebacks 5878844SAli.Saidi@ARM.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5888844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 5898844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 5909134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_hits 7364781 # DTB read hits 5919134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_misses 3705 # DTB read misses 5929134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_hits 5489656 # DTB write hits 5939134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_misses 1595 # DTB write misses 5948844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 5958844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 5968844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 5978844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 5989134Ssaidi@eecs.umich.edusystem.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB 5998844SAli.Saidi@ARM.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 6009134Ssaidi@eecs.umich.edusystem.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch 6018844SAli.Saidi@ARM.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 6029134Ssaidi@eecs.umich.edusystem.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 6039134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_accesses 7368486 # DTB read accesses 6049134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_accesses 5491251 # DTB write accesses 6058844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 6069134Ssaidi@eecs.umich.edusystem.cpu1.dtb.hits 12854437 # DTB hits 6079134Ssaidi@eecs.umich.edusystem.cpu1.dtb.misses 5300 # DTB misses 6089134Ssaidi@eecs.umich.edusystem.cpu1.dtb.accesses 12859737 # DTB accesses 6099134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_hits 32412306 # ITB inst hits 6109134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_misses 2200 # ITB inst misses 6118844SAli.Saidi@ARM.comsystem.cpu1.itb.read_hits 0 # DTB read hits 6128844SAli.Saidi@ARM.comsystem.cpu1.itb.read_misses 0 # DTB read misses 6138844SAli.Saidi@ARM.comsystem.cpu1.itb.write_hits 0 # DTB write hits 6148844SAli.Saidi@ARM.comsystem.cpu1.itb.write_misses 0 # DTB write misses 6158844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 6168844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 6178844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 6188844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 6199134Ssaidi@eecs.umich.edusystem.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB 6208844SAli.Saidi@ARM.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 6218844SAli.Saidi@ARM.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 6228844SAli.Saidi@ARM.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 6238844SAli.Saidi@ARM.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 6248844SAli.Saidi@ARM.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 6258844SAli.Saidi@ARM.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 6269134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_accesses 32414506 # ITB inst accesses 6279134Ssaidi@eecs.umich.edusystem.cpu1.itb.hits 32412306 # DTB hits 6289134Ssaidi@eecs.umich.edusystem.cpu1.itb.misses 2200 # DTB misses 6299134Ssaidi@eecs.umich.edusystem.cpu1.itb.accesses 32414506 # DTB accesses 6309134Ssaidi@eecs.umich.edusystem.cpu1.numCycles 1824154149 # number of cpu cycles simulated 6318844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 6328844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 6339134Ssaidi@eecs.umich.edusystem.cpu1.committedInsts 31875965 # Number of instructions committed 6349134Ssaidi@eecs.umich.edusystem.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed 6359134Ssaidi@eecs.umich.edusystem.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses 6369134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses 6379134Ssaidi@eecs.umich.edusystem.cpu1.num_func_calls 955227 # number of times a function call or return occured 6389265SAli.Saidi@ARM.comsystem.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls 6399134Ssaidi@eecs.umich.edusystem.cpu1.num_int_insts 35797832 # number of integer instructions 6409134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_insts 4436 # number of float instructions 6419134Ssaidi@eecs.umich.edusystem.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read 6429134Ssaidi@eecs.umich.edusystem.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written 6439134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read 6449134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written 6459134Ssaidi@eecs.umich.edusystem.cpu1.num_mem_refs 13370713 # number of memory refs 6469134Ssaidi@eecs.umich.edusystem.cpu1.num_load_insts 7642673 # Number of load instructions 6479134Ssaidi@eecs.umich.edusystem.cpu1.num_store_insts 5728040 # Number of store instructions 6489134Ssaidi@eecs.umich.edusystem.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles 6499134Ssaidi@eecs.umich.edusystem.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles 6509134Ssaidi@eecs.umich.edusystem.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles 6519134Ssaidi@eecs.umich.edusystem.cpu1.idle_fraction 0.977638 # Percentage of idle cycles 6528844SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 6539134Ssaidi@eecs.umich.edusystem.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed 6549134Ssaidi@eecs.umich.edusystem.cpu1.icache.replacements 433942 # number of replacements 6559134Ssaidi@eecs.umich.edusystem.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use 6569134Ssaidi@eecs.umich.edusystem.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks. 6579134Ssaidi@eecs.umich.edusystem.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks. 6589134Ssaidi@eecs.umich.edusystem.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks. 6599134Ssaidi@eecs.umich.edusystem.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. 6609134Ssaidi@eecs.umich.edusystem.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor 6619134Ssaidi@eecs.umich.edusystem.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy 6629134Ssaidi@eecs.umich.edusystem.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy 6639134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits 6649134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits 6659134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits 6669134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits 6679134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits 6689134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_hits::total 31979125 # number of overall hits 6699134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses 6709134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses 6719134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses 6729134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses 6739134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses 6749134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::total 434454 # number of overall misses 6759134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) 6769134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) 6779134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses 6789134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses 6799134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses 6809134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses 6819134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses 6829134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses 6839134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses 6849134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses 6859134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses 6869134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses 6878844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6888844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6898844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 6908844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 6918983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6928983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6938844SAli.Saidi@ARM.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 6948844SAli.Saidi@ARM.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 6958844SAli.Saidi@ARM.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6969134Ssaidi@eecs.umich.edusystem.cpu1.dcache.replacements 294289 # number of replacements 6979134Ssaidi@eecs.umich.edusystem.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use 6989134Ssaidi@eecs.umich.edusystem.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks. 6999134Ssaidi@eecs.umich.edusystem.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks. 7009134Ssaidi@eecs.umich.edusystem.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks. 7019134Ssaidi@eecs.umich.edusystem.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. 7029134Ssaidi@eecs.umich.edusystem.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor 7039134Ssaidi@eecs.umich.edusystem.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy 7049134Ssaidi@eecs.umich.edusystem.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy 7059134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits 7069134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits 7079134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits 7089134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits 7099134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits 7109134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits 7119134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits 7129134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits 7139134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits 7149134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits 7159134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits 7169134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_hits::total 11522522 # number of overall hits 7179134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses 7189134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses 7199134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses 7209134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses 7219134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses 7229134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses 7239134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses 7249134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses 7259134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses 7269134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses 7279134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses 7289134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_misses::total 324195 # number of overall misses 7299134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) 7309134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) 7319134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) 7329134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) 7339134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) 7349134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) 7359134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses) 7369134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses) 7379134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses 7389134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses 7399134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses 7409134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses 7419134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses 7429134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses 7439134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses 7449134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses 7459134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses 7469134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses 7479134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses 7489134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses 7499134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses 7509134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses 7519134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses 7529134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses 7538844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7548844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7558844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 7568844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 7578983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7588983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7598844SAli.Saidi@ARM.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 7608844SAli.Saidi@ARM.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 7619134Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks 7629134Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::total 266849 # number of writebacks 7638844SAli.Saidi@ARM.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 7648844SAli.Saidi@ARM.comsystem.iocache.replacements 0 # number of replacements 7658844SAli.Saidi@ARM.comsystem.iocache.tagsinuse 0 # Cycle average of tags in use 7668844SAli.Saidi@ARM.comsystem.iocache.total_refs 0 # Total number of references to valid blocks. 7678844SAli.Saidi@ARM.comsystem.iocache.sampled_refs 0 # Sample count of references to valid blocks. 7688983Snate@binkert.orgsystem.iocache.avg_refs nan # Average number of references to valid blocks. 7698844SAli.Saidi@ARM.comsystem.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7708844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7718844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7728844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 7738844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 7748983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7758983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7768844SAli.Saidi@ARM.comsystem.iocache.fast_writes 0 # number of fast writes performed 7778844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 7788844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 7798844SAli.Saidi@ARM.com 7808844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 781