stats.txt revision 9568
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.912097 # Number of seconds simulated 4sim_ticks 912096763500 # Number of ticks simulated 5final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1025890 # Simulator instruction rate (inst/s) 8host_op_rate 1320831 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 15183699019 # Simulator tick rate (ticks/s) 10host_mem_usage 392232 # Number of bytes of host memory used 11host_seconds 60.07 # Real time elapsed on the host 12sim_insts 61625970 # Number of instructions simulated 13sim_ops 79343340 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory 22system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 822331 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 0 # Total number of read requests seen 70system.physmem.writeReqs 0 # Total number of write requests seen 71system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 0 # Total number of bytes read from memory 73system.physmem.bytesWritten 0 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 112system.physmem.totGap 0 # Total gap between requests 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 0 # Categorize read packet sizes 116system.physmem.readPktSize::3 0 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes 119system.physmem.readPktSize::6 0 # Categorize read packet sizes 120system.physmem.writePktSize::0 0 # Categorize write packet sizes 121system.physmem.writePktSize::1 0 # Categorize write packet sizes 122system.physmem.writePktSize::2 0 # Categorize write packet sizes 123system.physmem.writePktSize::3 0 # Categorize write packet sizes 124system.physmem.writePktSize::4 0 # Categorize write packet sizes 125system.physmem.writePktSize::5 0 # Categorize write packet sizes 126system.physmem.writePktSize::6 0 # Categorize write packet sizes 127system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 159system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 191system.physmem.totQLat 0 # Total cycles spent in queuing delays 192system.physmem.totMemAccLat 0 # Sum of mem lat for all requests 193system.physmem.totBusLat 0 # Total cycles spent in databus access 194system.physmem.totBankLat 0 # Total cycles spent in bank access 195system.physmem.avgQLat nan # Average queueing delay per request 196system.physmem.avgBankLat nan # Average bank access latency per request 197system.physmem.avgBusLat nan # Average bus latency per request 198system.physmem.avgMemAccLat nan # Average memory access latency 199system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 200system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 201system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 202system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 203system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 204system.physmem.busUtil 0.00 # Data bus utilization in percentage 205system.physmem.avgRdQLen 0.00 # Average read queue length over time 206system.physmem.avgWrQLen 0.00 # Average write queue length over time 207system.physmem.readRowHits 0 # Number of row buffer hits during reads 208system.physmem.writeRowHits 0 # Number of row buffer hits during writes 209system.physmem.readRowHitRate nan # Row buffer hit rate for reads 210system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 211system.physmem.avgGap nan # Average gap between requests 212system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 213system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 214system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 215system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 216system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 217system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 218system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 219system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 220system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 221system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 222system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 223system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 224system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 225system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 226system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 227system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 228system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 229system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 230system.l2c.replacements 70658 # number of replacements 231system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use 232system.l2c.total_refs 1623339 # Total number of references to valid blocks. 233system.l2c.sampled_refs 135810 # Sample count of references to valid blocks. 234system.l2c.avg_refs 11.953015 # Average number of references to valid blocks. 235system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 236system.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor 237system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor 238system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor 239system.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor 240system.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor 241system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor 242system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor 243system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor 244system.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy 245system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 246system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 247system.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy 248system.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy 249system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 250system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy 251system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy 252system.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy 253system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits 254system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits 255system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits 256system.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits 257system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits 258system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits 259system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits 260system.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits 261system.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits 262system.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits 263system.l2c.Writeback_hits::total 567807 # number of Writeback hits 264system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 265system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits 266system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits 267system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits 268system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits 269system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits 270system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits 271system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits 272system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits 273system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits 274system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits 275system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits 276system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits 277system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits 278system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits 279system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits 280system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits 281system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits 282system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits 283system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits 284system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits 285system.l2c.overall_hits::cpu0.data 233336 # number of overall hits 286system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits 287system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits 288system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits 289system.l2c.overall_hits::cpu1.data 219723 # number of overall hits 290system.l2c.overall_hits::total 1317466 # number of overall hits 291system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 292system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 293system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses 294system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses 295system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 296system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses 297system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses 298system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses 299system.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses 300system.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses 301system.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses 302system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses 303system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses 304system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses 305system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses 306system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses 307system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses 308system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 309system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 310system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses 311system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses 312system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 313system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses 314system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses 315system.l2c.demand_misses::total 163290 # number of demand (read+write) misses 316system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 317system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 318system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses 319system.l2c.overall_misses::cpu0.data 98856 # number of overall misses 320system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 321system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses 322system.l2c.overall_misses::cpu1.data 53648 # number of overall misses 323system.l2c.overall_misses::total 163290 # number of overall misses 324system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) 325system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) 326system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) 327system.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses) 328system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) 329system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) 330system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) 331system.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses) 332system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) 333system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) 334system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) 335system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) 336system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) 337system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) 338system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) 339system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) 340system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) 341system.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses) 342system.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses) 343system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) 344system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses 345system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses 346system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses 347system.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses 348system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses 349system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses 350system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses 351system.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses 352system.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses 353system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses 354system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses 355system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses 356system.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses 357system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses 358system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses 359system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses 360system.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses 361system.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses 362system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses 363system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses 364system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses 365system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses 366system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses 367system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses 368system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses 369system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses 370system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses 371system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses 372system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses 373system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses 374system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses 375system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses 376system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses 377system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses 378system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses 379system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses 380system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses 381system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses 382system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses 383system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses 384system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses 385system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses 386system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses 387system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses 388system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses 389system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses 390system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses 391system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses 392system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses 393system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses 394system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses 395system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 398system.l2c.blocked::no_targets 0 # number of cycles access was blocked 399system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 401system.l2c.fast_writes 0 # number of fast writes performed 402system.l2c.cache_copies 0 # number of cache copies performed 403system.l2c.writebacks::writebacks 65559 # number of writebacks 404system.l2c.writebacks::total 65559 # number of writebacks 405system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 406system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 407system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 408system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 409system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 410system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 411system.cf0.dma_write_txs 0 # Number of DMA write transactions. 412system.cpu0.dtb.inst_hits 0 # ITB inst hits 413system.cpu0.dtb.inst_misses 0 # ITB inst misses 414system.cpu0.dtb.read_hits 7975768 # DTB read hits 415system.cpu0.dtb.read_misses 3611 # DTB read misses 416system.cpu0.dtb.write_hits 5966574 # DTB write hits 417system.cpu0.dtb.write_misses 672 # DTB write misses 418system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 419system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 420system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 421system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 422system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB 423system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 424system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch 425system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 426system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 427system.cpu0.dtb.read_accesses 7979379 # DTB read accesses 428system.cpu0.dtb.write_accesses 5967246 # DTB write accesses 429system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 430system.cpu0.dtb.hits 13942342 # DTB hits 431system.cpu0.dtb.misses 4283 # DTB misses 432system.cpu0.dtb.accesses 13946625 # DTB accesses 433system.cpu0.itb.inst_hits 30238804 # ITB inst hits 434system.cpu0.itb.inst_misses 2175 # ITB inst misses 435system.cpu0.itb.read_hits 0 # DTB read hits 436system.cpu0.itb.read_misses 0 # DTB read misses 437system.cpu0.itb.write_hits 0 # DTB write hits 438system.cpu0.itb.write_misses 0 # DTB write misses 439system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 440system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 441system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 442system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 443system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB 444system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 445system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 446system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 447system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 448system.cpu0.itb.read_accesses 0 # DTB read accesses 449system.cpu0.itb.write_accesses 0 # DTB write accesses 450system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses 451system.cpu0.itb.hits 30238804 # DTB hits 452system.cpu0.itb.misses 2175 # DTB misses 453system.cpu0.itb.accesses 30240979 # DTB accesses 454system.cpu0.numCycles 1823633059 # number of cpu cycles simulated 455system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 456system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 457system.cpu0.committedInsts 29750005 # Number of instructions committed 458system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed 459system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses 460system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses 461system.cpu0.num_func_calls 1241903 # number of times a function call or return occured 462system.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls 463system.cpu0.num_int_insts 34471201 # number of integer instructions 464system.cpu0.num_fp_insts 5449 # number of float instructions 465system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read 466system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written 467system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read 468system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 469system.cpu0.num_mem_refs 14626951 # number of memory refs 470system.cpu0.num_load_insts 8357226 # Number of load instructions 471system.cpu0.num_store_insts 6269725 # Number of store instructions 472system.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles 473system.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles 474system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles 475system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles 476system.cpu0.kern.inst.arm 0 # number of arm instructions executed 477system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed 478system.cpu0.icache.replacements 428546 # number of replacements 479system.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use 480system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks. 481system.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks. 482system.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks. 483system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. 484system.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor 485system.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy 486system.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy 487system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits 488system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits 489system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits 490system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits 491system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits 492system.cpu0.icache.overall_hits::total 29811115 # number of overall hits 493system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses 494system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses 495system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses 496system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses 497system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses 498system.cpu0.icache.overall_misses::total 429059 # number of overall misses 499system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) 500system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) 501system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses 502system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses 503system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses 504system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses 505system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses 506system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses 507system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses 508system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses 509system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses 510system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses 511system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 512system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 513system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 514system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 515system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 516system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 517system.cpu0.icache.fast_writes 0 # number of fast writes performed 518system.cpu0.icache.cache_copies 0 # number of cache copies performed 519system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 520system.cpu0.dcache.replacements 323609 # number of replacements 521system.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use 522system.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks. 523system.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks. 524system.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks. 525system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. 526system.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor 527system.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy 528system.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy 529system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits 530system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits 531system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits 532system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits 533system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits 534system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits 535system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits 536system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits 537system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits 538system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits 539system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits 540system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits 541system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses 542system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses 543system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses 544system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses 545system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses 546system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses 547system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses 548system.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses 549system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses 550system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses 551system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses 552system.cpu0.dcache.overall_misses::total 364509 # number of overall misses 553system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) 554system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) 555system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) 556system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) 557system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) 558system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) 559system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses) 560system.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses) 561system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses 562system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses 563system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses 564system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses 565system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses 566system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses 567system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses 568system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses 569system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses 570system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses 571system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses 572system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses 573system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses 574system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses 575system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses 576system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses 577system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 578system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 579system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 580system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 581system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 582system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 583system.cpu0.dcache.fast_writes 0 # number of fast writes performed 584system.cpu0.dcache.cache_copies 0 # number of cache copies performed 585system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks 586system.cpu0.dcache.writebacks::total 300958 # number of writebacks 587system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 588system.cpu1.dtb.inst_hits 0 # ITB inst hits 589system.cpu1.dtb.inst_misses 0 # ITB inst misses 590system.cpu1.dtb.read_hits 7364781 # DTB read hits 591system.cpu1.dtb.read_misses 3705 # DTB read misses 592system.cpu1.dtb.write_hits 5489656 # DTB write hits 593system.cpu1.dtb.write_misses 1595 # DTB write misses 594system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 595system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 596system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 597system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 598system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB 599system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 600system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch 601system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 602system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 603system.cpu1.dtb.read_accesses 7368486 # DTB read accesses 604system.cpu1.dtb.write_accesses 5491251 # DTB write accesses 605system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 606system.cpu1.dtb.hits 12854437 # DTB hits 607system.cpu1.dtb.misses 5300 # DTB misses 608system.cpu1.dtb.accesses 12859737 # DTB accesses 609system.cpu1.itb.inst_hits 32412306 # ITB inst hits 610system.cpu1.itb.inst_misses 2200 # ITB inst misses 611system.cpu1.itb.read_hits 0 # DTB read hits 612system.cpu1.itb.read_misses 0 # DTB read misses 613system.cpu1.itb.write_hits 0 # DTB write hits 614system.cpu1.itb.write_misses 0 # DTB write misses 615system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 616system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 617system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 618system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 619system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB 620system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 621system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 622system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 623system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 624system.cpu1.itb.read_accesses 0 # DTB read accesses 625system.cpu1.itb.write_accesses 0 # DTB write accesses 626system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses 627system.cpu1.itb.hits 32412306 # DTB hits 628system.cpu1.itb.misses 2200 # DTB misses 629system.cpu1.itb.accesses 32414506 # DTB accesses 630system.cpu1.numCycles 1824154149 # number of cpu cycles simulated 631system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 632system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 633system.cpu1.committedInsts 31875965 # Number of instructions committed 634system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed 635system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses 636system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses 637system.cpu1.num_func_calls 955227 # number of times a function call or return occured 638system.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls 639system.cpu1.num_int_insts 35797832 # number of integer instructions 640system.cpu1.num_fp_insts 4436 # number of float instructions 641system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read 642system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written 643system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read 644system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written 645system.cpu1.num_mem_refs 13370713 # number of memory refs 646system.cpu1.num_load_insts 7642673 # Number of load instructions 647system.cpu1.num_store_insts 5728040 # Number of store instructions 648system.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles 649system.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles 650system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles 651system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles 652system.cpu1.kern.inst.arm 0 # number of arm instructions executed 653system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed 654system.cpu1.icache.replacements 433942 # number of replacements 655system.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use 656system.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks. 657system.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks. 658system.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks. 659system.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. 660system.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor 661system.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy 662system.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy 663system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits 664system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits 665system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits 666system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits 667system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits 668system.cpu1.icache.overall_hits::total 31979125 # number of overall hits 669system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses 670system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses 671system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses 672system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses 673system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses 674system.cpu1.icache.overall_misses::total 434454 # number of overall misses 675system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) 676system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) 677system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses 678system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses 679system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses 680system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses 681system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses 682system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses 683system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses 684system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses 685system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses 686system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses 687system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 688system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 689system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 690system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 691system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 692system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 693system.cpu1.icache.fast_writes 0 # number of fast writes performed 694system.cpu1.icache.cache_copies 0 # number of cache copies performed 695system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 696system.cpu1.dcache.replacements 294289 # number of replacements 697system.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use 698system.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks. 699system.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks. 700system.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks. 701system.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. 702system.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor 703system.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy 704system.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy 705system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits 706system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits 707system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits 708system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits 709system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits 710system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits 711system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits 712system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits 713system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits 714system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits 715system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits 716system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits 717system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses 718system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses 719system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses 720system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses 721system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses 722system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses 723system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses 724system.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses 725system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses 726system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses 727system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses 728system.cpu1.dcache.overall_misses::total 324195 # number of overall misses 729system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) 730system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) 731system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) 732system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) 733system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) 734system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) 735system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses) 736system.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses) 737system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses 738system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses 739system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses 740system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses 741system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses 742system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses 743system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses 744system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses 745system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses 746system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses 747system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses 748system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses 749system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses 750system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses 751system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses 752system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses 753system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 754system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 756system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 758system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu1.dcache.fast_writes 0 # number of fast writes performed 760system.cpu1.dcache.cache_copies 0 # number of cache copies performed 761system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks 762system.cpu1.dcache.writebacks::total 266849 # number of writebacks 763system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 764system.iocache.replacements 0 # number of replacements 765system.iocache.tagsinuse 0 # Cycle average of tags in use 766system.iocache.total_refs 0 # Total number of references to valid blocks. 767system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 768system.iocache.avg_refs nan # Average number of references to valid blocks. 769system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 770system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 771system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 772system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 773system.iocache.blocked::no_targets 0 # number of cycles access was blocked 774system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 775system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 776system.iocache.fast_writes 0 # number of fast writes performed 777system.iocache.cache_copies 0 # number of cache copies performed 778system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 779 780---------- End Simulation Statistics ---------- 781