stats.txt revision 10220
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated 4sim_ticks 1829332258000 # Number of ticks simulated 5final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2367650 # Simulator instruction rate (inst/s) 8host_op_rate 2367648 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 72140813877 # Simulator tick rate (ticks/s) 10host_mem_usage 343680 # Number of bytes of host memory used 11host_seconds 25.36 # Real time elapsed on the host 12sim_insts 60038305 # Number of instructions simulated 13sim_ops 60038305 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 19system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory 26system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) 43system.membus.throughput 42552540 # Throughput (bytes/s) 44system.membus.data_through_bus 77842734 # Total data (bytes) 45system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 46system.iocache.tags.replacements 41686 # number of replacements 47system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use 48system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 49system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 50system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 51system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. 52system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor 53system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 54system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 55system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 56system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 57system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 58system.iocache.tags.tag_accesses 375534 # Number of tag accesses 59system.iocache.tags.data_accesses 375534 # Number of data accesses 60system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 61system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 62system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 63system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 64system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 65system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 66system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 67system.iocache.overall_misses::total 41726 # number of overall misses 68system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 69system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 70system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 71system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 72system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 73system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 74system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 75system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 76system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 77system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 78system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 79system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 80system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 81system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 82system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 83system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 84system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 85system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 86system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 87system.iocache.blocked::no_targets 0 # number of cycles access was blocked 88system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 89system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90system.iocache.fast_writes 0 # number of fast writes performed 91system.iocache.cache_copies 0 # number of cache copies performed 92system.iocache.writebacks::writebacks 41512 # number of writebacks 93system.iocache.writebacks::total 41512 # number of writebacks 94system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 95system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 96system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 97system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 98system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 99system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 100system.disk0.dma_write_txs 395 # Number of DMA write transactions. 101system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 102system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 103system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 104system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 105system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 106system.disk2.dma_write_txs 1 # Number of DMA write transactions. 107system.cpu_clk_domain.clock 500 # Clock period in ticks 108system.cpu.dtb.fetch_hits 0 # ITB hits 109system.cpu.dtb.fetch_misses 0 # ITB misses 110system.cpu.dtb.fetch_acv 0 # ITB acv 111system.cpu.dtb.fetch_accesses 0 # ITB accesses 112system.cpu.dtb.read_hits 9710427 # DTB read hits 113system.cpu.dtb.read_misses 10329 # DTB read misses 114system.cpu.dtb.read_acv 210 # DTB read access violations 115system.cpu.dtb.read_accesses 728856 # DTB read accesses 116system.cpu.dtb.write_hits 6352498 # DTB write hits 117system.cpu.dtb.write_misses 1142 # DTB write misses 118system.cpu.dtb.write_acv 157 # DTB write access violations 119system.cpu.dtb.write_accesses 291931 # DTB write accesses 120system.cpu.dtb.data_hits 16062925 # DTB hits 121system.cpu.dtb.data_misses 11471 # DTB misses 122system.cpu.dtb.data_acv 367 # DTB access violations 123system.cpu.dtb.data_accesses 1020787 # DTB accesses 124system.cpu.itb.fetch_hits 4974648 # ITB hits 125system.cpu.itb.fetch_misses 5006 # ITB misses 126system.cpu.itb.fetch_acv 184 # ITB acv 127system.cpu.itb.fetch_accesses 4979654 # ITB accesses 128system.cpu.itb.read_hits 0 # DTB read hits 129system.cpu.itb.read_misses 0 # DTB read misses 130system.cpu.itb.read_acv 0 # DTB read access violations 131system.cpu.itb.read_accesses 0 # DTB read accesses 132system.cpu.itb.write_hits 0 # DTB write hits 133system.cpu.itb.write_misses 0 # DTB write misses 134system.cpu.itb.write_acv 0 # DTB write access violations 135system.cpu.itb.write_accesses 0 # DTB write accesses 136system.cpu.itb.data_hits 0 # DTB hits 137system.cpu.itb.data_misses 0 # DTB misses 138system.cpu.itb.data_acv 0 # DTB access violations 139system.cpu.itb.data_accesses 0 # DTB accesses 140system.cpu.numCycles 3658664517 # number of cpu cycles simulated 141system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 142system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 143system.cpu.committedInsts 60038305 # Number of instructions committed 144system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed 145system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses 146system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 147system.cpu.num_func_calls 1484182 # number of times a function call or return occured 148system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls 149system.cpu.num_int_insts 55913521 # number of integer instructions 150system.cpu.num_fp_insts 324460 # number of float instructions 151system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read 152system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written 153system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 154system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 155system.cpu.num_mem_refs 16115709 # number of memory refs 156system.cpu.num_load_insts 9747513 # Number of load instructions 157system.cpu.num_store_insts 6368196 # Number of store instructions 158system.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles 159system.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles 160system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles 161system.cpu.idle_fraction 0.983585 # Percentage of idle cycles 162system.cpu.Branches 9064385 # Number of branches fetched 163system.cpu.op_class::No_OpClass 3199104 5.33% 5.33% # Class of executed instruction 164system.cpu.op_class::IntAlu 39460699 65.71% 71.04% # Class of executed instruction 165system.cpu.op_class::IntMult 60680 0.10% 71.14% # Class of executed instruction 166system.cpu.op_class::IntDiv 0 0.00% 71.14% # Class of executed instruction 167system.cpu.op_class::FloatAdd 25609 0.04% 71.18% # Class of executed instruction 168system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction 169system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction 170system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction 171system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction 172system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction 173system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction 174system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction 175system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction 176system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction 177system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction 178system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction 179system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction 180system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction 181system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction 182system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction 183system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction 184system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction 185system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction 186system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction 187system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction 188system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction 189system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction 190system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction 191system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction 192system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction 193system.cpu.op_class::MemRead 9975081 16.61% 87.80% # Class of executed instruction 194system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction 195system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction 196system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 197system.cpu.op_class::total 60050143 # Class of executed instruction 198system.cpu.kern.inst.arm 0 # number of arm instructions executed 199system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 200system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed 201system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 202system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 203system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 204system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl 205system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl 206system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 207system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 208system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 209system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 210system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 211system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl 212system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 213system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 214system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl 215system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl 216system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 217system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 218system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 219system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 220system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl 221system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 222system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 223system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 224system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 225system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 226system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 227system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 228system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 229system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 230system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 231system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 232system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 233system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 234system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 235system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 236system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 237system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 238system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 239system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 240system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 241system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 242system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 243system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 244system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 245system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 246system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 247system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 248system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 249system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 250system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 251system.cpu.kern.syscall::total 326 # number of syscalls executed 252system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 253system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 254system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 255system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 256system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 257system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 258system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 259system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed 260system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 261system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 262system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 263system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 264system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 265system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 266system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 267system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 268system.cpu.kern.callpal::total 192180 # number of callpals executed 269system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 270system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 271system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 272system.cpu.kern.mode_good::kernel 1909 273system.cpu.kern.mode_good::user 1738 274system.cpu.kern.mode_good::idle 171 275system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches 276system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 277system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 278system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches 279system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode 280system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 281system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode 282system.cpu.kern.swap_context 4178 # number of times the context was actually changed 283system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 284system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 285system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 286system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 287system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 288system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 289system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 290system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 291system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 292system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 293system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 294system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 295system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 296system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 297system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 298system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 299system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 300system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 301system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 302system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 303system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 304system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 305system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 306system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 307system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 308system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 309system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 310system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 311system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 312system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 313system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 314system.iobus.throughput 1480181 # Throughput (bytes/s) 315system.iobus.data_through_bus 2707742 # Total data (bytes) 316system.cpu.icache.tags.replacements 919594 # number of replacements 317system.cpu.icache.tags.tagsinuse 511.215243 # Cycle average of tags in use 318system.cpu.icache.tags.total_refs 59129922 # Total number of references to valid blocks. 319system.cpu.icache.tags.sampled_refs 920106 # Sample count of references to valid blocks. 320system.cpu.icache.tags.avg_refs 64.264250 # Average number of references to valid blocks. 321system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 322system.cpu.icache.tags.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor 323system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 324system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 325system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 326system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 327system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 328system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id 329system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 330system.cpu.icache.tags.tag_accesses 60970364 # Number of tag accesses 331system.cpu.icache.tags.data_accesses 60970364 # Number of data accesses 332system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits 333system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits 334system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits 335system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits 336system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits 337system.cpu.icache.overall_hits::total 59129922 # number of overall hits 338system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses 339system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses 340system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses 341system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses 342system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses 343system.cpu.icache.overall_misses::total 920221 # number of overall misses 344system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) 345system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) 346system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses 347system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses 348system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses 349system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses 350system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 351system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 352system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 353system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 354system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 355system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 356system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 357system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 358system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 359system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 360system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 361system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 362system.cpu.icache.fast_writes 0 # number of fast writes performed 363system.cpu.icache.cache_copies 0 # number of cache copies performed 364system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 365system.cpu.l2cache.tags.replacements 992301 # number of replacements 366system.cpu.l2cache.tags.tagsinuse 65424.374305 # Cycle average of tags in use 367system.cpu.l2cache.tags.total_refs 2433239 # Total number of references to valid blocks. 368system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. 369system.cpu.l2cache.tags.avg_refs 2.301014 # Average number of references to valid blocks. 370system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 371system.cpu.l2cache.tags.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor 372system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor 373system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor 374system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy 375system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy 376system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 377system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy 378system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 379system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id 380system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id 381system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id 382system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id 383system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id 384system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 385system.cpu.l2cache.tags.tag_accesses 31737437 # Number of tag accesses 386system.cpu.l2cache.tags.data_accesses 31737437 # Number of data accesses 387system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits 388system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits 389system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits 390system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits 391system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits 392system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 393system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 394system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits 395system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits 396system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits 397system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits 398system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits 399system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits 400system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits 401system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits 402system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses 403system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 404system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses 405system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 406system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 407system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses 408system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses 409system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses 410system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses 411system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses 412system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses 413system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses 414system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses 415system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) 416system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) 417system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) 418system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) 419system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) 420system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 421system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 422system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) 423system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) 424system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses 425system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses 426system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses 427system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses 428system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses 429system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses 430system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses 431system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses 432system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses 433system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 434system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses 435system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses 436system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses 437system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses 438system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses 439system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses 440system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses 441system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses 442system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses 443system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 444system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 445system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 446system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 447system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 448system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 449system.cpu.l2cache.fast_writes 0 # number of fast writes performed 450system.cpu.l2cache.cache_copies 0 # number of cache copies performed 451system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks 452system.cpu.l2cache.writebacks::total 74291 # number of writebacks 453system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 454system.cpu.dcache.tags.replacements 2042702 # number of replacements 455system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 456system.cpu.dcache.tags.total_refs 14038431 # Total number of references to valid blocks. 457system.cpu.dcache.tags.sampled_refs 2043214 # Sample count of references to valid blocks. 458system.cpu.dcache.tags.avg_refs 6.870759 # Average number of references to valid blocks. 459system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 460system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 461system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 462system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 463system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 464system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 465system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 466system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 467system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 468system.cpu.dcache.tags.tag_accesses 66369799 # Number of tag accesses 469system.cpu.dcache.tags.data_accesses 66369799 # Number of data accesses 470system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits 471system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits 472system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits 473system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits 474system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 475system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 476system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 477system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 478system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits 479system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits 480system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits 481system.cpu.dcache.overall_hits::total 13655992 # number of overall hits 482system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses 483system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses 484system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses 485system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses 486system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 487system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 488system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses 489system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses 490system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses 491system.cpu.dcache.overall_misses::total 2026069 # number of overall misses 492system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) 493system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) 494system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) 495system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) 496system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 497system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 498system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 499system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 500system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses 501system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses 502system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses 503system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses 504system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 505system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 506system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 507system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses 508system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 509system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses 510system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 511system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 512system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 513system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 514system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 517system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 518system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 519system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 520system.cpu.dcache.fast_writes 0 # number of fast writes performed 521system.cpu.dcache.cache_copies 0 # number of cache copies performed 522system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks 523system.cpu.dcache.writebacks::total 833491 # number of writebacks 524system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 525system.cpu.toL2Bus.throughput 132867917 # Throughput (bytes/s) 526system.cpu.toL2Bus.data_through_bus 243049454 # Total data (bytes) 527system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) 528 529---------- End Simulation Statistics ---------- 530