stats.txt revision 9988
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.829332 # Number of seconds simulated 49962Sandreas.hansson@arm.comsim_ticks 1829332258000 # Number of ticks simulated 59962Sandreas.hansson@arm.comfinal_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79988Snilay@cs.wisc.eduhost_inst_rate 1538182 # Simulator instruction rate (inst/s) 89988Snilay@cs.wisc.eduhost_op_rate 1538181 # Simulator op (including micro ops) rate (op/s) 99988Snilay@cs.wisc.eduhost_tick_rate 46867449524 # Simulator tick rate (ticks/s) 109988Snilay@cs.wisc.eduhost_mem_usage 350908 # Number of bytes of host memory used 119988Snilay@cs.wisc.eduhost_seconds 39.03 # Real time elapsed on the host 129797Sandreas.hansson@arm.comsim_insts 60038305 # Number of instructions simulated 139797Sandreas.hansson@arm.comsim_ops 60038305 # Number of ops (including micro ops) simulated 149797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory 159797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 179797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 70349696 # Number of bytes read from this memory 189797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory 209797Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory 219797Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7411392 # Number of bytes written to this memory 229797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory 239797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory 249079SAli.Saidi@ARM.comsystem.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 259797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory 269797Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory 279797Sandreas.hansson@arm.comsystem.physmem.num_writes::total 115803 # Number of write requests responded to by this memory 289797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) 299797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) 309797Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) 319797Sandreas.hansson@arm.comsystem.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) 329797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) 339797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) 349797Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) 359797Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) 369797Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) 379797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) 389797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) 399797Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) 409797Sandreas.hansson@arm.comsystem.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) 419797Sandreas.hansson@arm.comsystem.membus.throughput 42552540 # Throughput (bytes/s) 429797Sandreas.hansson@arm.comsystem.membus.data_through_bus 77842734 # Total data (bytes) 439729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 449885Sstever@gmail.comsystem.iocache.tags.replacements 41686 # number of replacements 459885Sstever@gmail.comsystem.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use 469885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 479885Sstever@gmail.comsystem.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 489885Sstever@gmail.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 499885Sstever@gmail.comsystem.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. 509885Sstever@gmail.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor 519885Sstever@gmail.comsystem.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 529885Sstever@gmail.comsystem.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 538835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 548721SN/Asystem.iocache.ReadReq_misses::total 174 # number of ReadReq misses 558835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 568721SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 578835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 588721SN/Asystem.iocache.demand_misses::total 41726 # number of demand (read+write) misses 598835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 608721SN/Asystem.iocache.overall_misses::total 41726 # number of overall misses 618835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 628721SN/Asystem.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 638835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 648721SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 658835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 668721SN/Asystem.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 678835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 688721SN/Asystem.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 698835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 709055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 718835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 729055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 738835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 749055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 758835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 769055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 778721SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788721SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 798721SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 808721SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 818983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 828983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 838721SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 848721SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 858835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 868835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 878721SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 888721SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 898721SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 908721SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 918721SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 928721SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 938721SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 948721SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 958721SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 968721SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 978721SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 988721SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 998721SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 1008721SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 1018721SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 1028721SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 1038721SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 1049797Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9710427 # DTB read hits 1058721SN/Asystem.cpu.dtb.read_misses 10329 # DTB read misses 1068721SN/Asystem.cpu.dtb.read_acv 210 # DTB read access violations 1078721SN/Asystem.cpu.dtb.read_accesses 728856 # DTB read accesses 1089797Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6352498 # DTB write hits 1098721SN/Asystem.cpu.dtb.write_misses 1142 # DTB write misses 1108721SN/Asystem.cpu.dtb.write_acv 157 # DTB write access violations 1118721SN/Asystem.cpu.dtb.write_accesses 291931 # DTB write accesses 1129797Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16062925 # DTB hits 1136024SN/Asystem.cpu.dtb.data_misses 11471 # DTB misses 1148721SN/Asystem.cpu.dtb.data_acv 367 # DTB access violations 1158721SN/Asystem.cpu.dtb.data_accesses 1020787 # DTB accesses 1169797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 4974648 # ITB hits 1178721SN/Asystem.cpu.itb.fetch_misses 5006 # ITB misses 1188721SN/Asystem.cpu.itb.fetch_acv 184 # ITB acv 1199797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 4979654 # ITB accesses 1208721SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 1218721SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 1228721SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 1238721SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 1248721SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 1258721SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 1268721SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 1278721SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 1286024SN/Asystem.cpu.itb.data_hits 0 # DTB hits 1296024SN/Asystem.cpu.itb.data_misses 0 # DTB misses 1308721SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 1318721SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 1329988Snilay@cs.wisc.edusystem.cpu.numCycles 3658664517 # number of cpu cycles simulated 1338721SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1348721SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1359797Sandreas.hansson@arm.comsystem.cpu.committedInsts 60038305 # Number of instructions committed 1369797Sandreas.hansson@arm.comsystem.cpu.committedOps 60038305 # Number of ops (including micro ops) committed 1379797Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses 1388721SN/Asystem.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 1399797Sandreas.hansson@arm.comsystem.cpu.num_func_calls 1484182 # number of times a function call or return occured 1409797Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls 1419797Sandreas.hansson@arm.comsystem.cpu.num_int_insts 55913521 # number of integer instructions 1428721SN/Asystem.cpu.num_fp_insts 324460 # number of float instructions 1439797Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 76953934 # number of times the integer registers were read 1449797Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 41740225 # number of times the integer registers were written 1458721SN/Asystem.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 1468721SN/Asystem.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 1479797Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 16115709 # number of memory refs 1489797Sandreas.hansson@arm.comsystem.cpu.num_load_insts 9747513 # Number of load instructions 1499797Sandreas.hansson@arm.comsystem.cpu.num_store_insts 6368196 # Number of store instructions 1509988Snilay@cs.wisc.edusystem.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles 1519988Snilay@cs.wisc.edusystem.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles 1529797Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles 1539797Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.983585 # Percentage of idle cycles 1542968SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 1558721SN/Asystem.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 1569797Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed 1576291SN/Asystem.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 1586291SN/Asystem.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 1596291SN/Asystem.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 1609797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl 1619797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl 1626291SN/Asystem.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 1636291SN/Asystem.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 1646291SN/Asystem.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 1656291SN/Asystem.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 1666127SN/Asystem.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 1679962Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl 1686291SN/Asystem.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 1696291SN/Asystem.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 1709797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl 1719962Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl 1726127SN/Asystem.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 1736127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1746127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1759797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 1769797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl 1776291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1786291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1796291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1806291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1816291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1826291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1836291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1846291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 1856291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 1866291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 1876291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 1886291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 1896291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 1906291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 1916291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 1926291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 1936291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 1946291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 1956291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 1966291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 1976291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 1986291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 1996291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 2006291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 2016291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 2026291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 2036291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 2046291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 2056291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 2066291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 2076127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 2088721SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2098721SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 2108721SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 2118721SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 2128721SN/Asystem.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 2138721SN/Asystem.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 2148721SN/Asystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 2159797Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed 2168721SN/Asystem.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 2178721SN/Asystem.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 2188721SN/Asystem.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 2198721SN/Asystem.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 2208721SN/Asystem.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 2218721SN/Asystem.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 2228721SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 2238721SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 2249797Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 192180 # number of callpals executed 2259797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 2269797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1738 # number of protection mode switches 2279797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 2289797Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1909 2299797Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1738 2308721SN/Asystem.cpu.kern.mode_good::idle 171 2319797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches 2328721SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2339797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 2349797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches 2359797Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode 2369797Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 2379962Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode 2388721SN/Asystem.cpu.kern.swap_context 4178 # number of times the context was actually changed 2392968SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2402968SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2412968SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2422968SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2438721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2448983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2458721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 2468721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2478983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2488721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2498721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2508983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2518721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2528721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2538983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2548721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2558721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2568983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2578721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2588721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2598983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2608721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2618721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2628983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2638721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2648721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2658983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2668721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2678983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2688721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 2692968SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 2709797Sandreas.hansson@arm.comsystem.iobus.throughput 1480181 # Throughput (bytes/s) 2719729Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2707742 # Total data (bytes) 2729962Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 919594 # number of replacements 2739962Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.215243 # Cycle average of tags in use 2749962Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 59129922 # Total number of references to valid blocks. 2759962Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 920106 # Sample count of references to valid blocks. 2769962Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 64.264250 # Average number of references to valid blocks. 2779885Sstever@gmail.comsystem.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 2789962Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor 2799885Sstever@gmail.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 2809885Sstever@gmail.comsystem.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 2819962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits 2829962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits 2839962Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits 2849962Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits 2859962Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits 2869962Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 59129922 # number of overall hits 2879962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses 2889962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses 2899962Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses 2909962Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses 2919962Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses 2929962Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 920221 # number of overall misses 2939797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) 2949797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) 2959797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses 2969797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses 2979797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses 2989797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses 2998835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 3009055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 3018835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 3029055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 3038835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 3049055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 3058721SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3068721SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3078721SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3088721SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3098983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3108983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3118721SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3128721SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3138721SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3149885Sstever@gmail.comsystem.cpu.l2cache.tags.replacements 992301 # number of replacements 3159962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65424.374305 # Cycle average of tags in use 3169962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2433239 # Total number of references to valid blocks. 3179885Sstever@gmail.comsystem.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. 3189962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 2.301014 # Average number of references to valid blocks. 3199885Sstever@gmail.comsystem.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 3209962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor 3219962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor 3229962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor 3239797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy 3249797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy 3259797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 3269885Sstever@gmail.comsystem.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy 3279962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits 3289962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits 3299962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits 3309962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits 3319962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits 3329289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 3339289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 3349962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits 3359962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits 3369962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits 3379962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits 3389962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits 3399962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits 3409962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits 3419962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1905255 # number of overall hits 3429797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses 3439289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 3449797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses 3459289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 3469289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 3479797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses 3489797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses 3499797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses 3509797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses 3519797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses 3529797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses 3539797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses 3549797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1058163 # number of overall misses 3559962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) 3569962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) 3579962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) 3589962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) 3599962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) 3609289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 3619289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 3629962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) 3639962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) 3649962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses 3659962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses 3669962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses 3679962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses 3689962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses 3699962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses 3709962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses 3719962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses 3729962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses 3739289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 3749289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses 3759962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses 3769962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses 3779962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses 3789962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses 3799962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses 3809962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses 3819962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses 3829962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses 3839289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3849289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3859289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 3869289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 3879289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3889289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3899289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 3909289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 3919797Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks 3929797Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 74291 # number of writebacks 3939289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 3949962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 2042702 # number of replacements 3959885Sstever@gmail.comsystem.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 3969962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 14038431 # Total number of references to valid blocks. 3979962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 2043214 # Sample count of references to valid blocks. 3989962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 6.870759 # Average number of references to valid blocks. 3999885Sstever@gmail.comsystem.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 4009885Sstever@gmail.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 4019885Sstever@gmail.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 4029885Sstever@gmail.comsystem.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 4039962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits 4049962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits 4059962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits 4069962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits 4079797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 4089797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 4099797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 4109797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 4119962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits 4129962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits 4139962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits 4149962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 13655992 # number of overall hits 4159962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses 4169962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses 4179962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses 4189962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses 4199481Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 4209481Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 4219962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses 4229962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses 4239962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses 4249962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 2026069 # number of overall misses 4259797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) 4269797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) 4279797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) 4289797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) 4299797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 4309797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 4319797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 4329797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 4339797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses 4349797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses 4359797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses 4369797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses 4379481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 4389481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 4399797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 4409797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses 4419797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 4429797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses 4439481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 4449481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 4459481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 4469481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 4479481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4489481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4499481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4509481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4519481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4529481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4539481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4549481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4559962Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 833491 # number of writebacks 4569962Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 833491 # number of writebacks 4579481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4589962Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 132867917 # Throughput (bytes/s) 4599962Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 243049454 # Total data (bytes) 4609729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) 4612968SN/A 4622968SN/A---------- End Simulation Statistics ---------- 463