stats.txt revision 9924
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.829332 # Number of seconds simulated 49797Sandreas.hansson@arm.comsim_ticks 1829332269000 # Number of ticks simulated 59797Sandreas.hansson@arm.comfinal_tick 1829332269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79885Sstever@gmail.comhost_inst_rate 2947908 # Simulator instruction rate (inst/s) 89885Sstever@gmail.comhost_op_rate 2947905 # Simulator op (including micro ops) rate (op/s) 99885Sstever@gmail.comhost_tick_rate 89820884398 # Simulator tick rate (ticks/s) 109885Sstever@gmail.comhost_mem_usage 305960 # Number of bytes of host memory used 119885Sstever@gmail.comhost_seconds 20.37 # Real time elapsed on the host 129797Sandreas.hansson@arm.comsim_insts 60038305 # Number of instructions simulated 139797Sandreas.hansson@arm.comsim_ops 60038305 # Number of ops (including micro ops) simulated 149797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory 159797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 179797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 70349696 # Number of bytes read from this memory 189797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory 209797Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory 219797Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7411392 # Number of bytes written to this memory 229797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory 239797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory 249079SAli.Saidi@ARM.comsystem.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 259797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory 269797Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory 279797Sandreas.hansson@arm.comsystem.physmem.num_writes::total 115803 # Number of write requests responded to by this memory 289797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) 299797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s) 309797Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s) 319797Sandreas.hansson@arm.comsystem.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s) 329797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) 339797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) 349797Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) 359797Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) 369797Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) 379797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) 389797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) 399797Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) 409797Sandreas.hansson@arm.comsystem.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) 419838Sandreas.hansson@arm.comsystem.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller 429838Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 439838Sandreas.hansson@arm.comsystem.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 449838Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 459312Sandreas.hansson@arm.comsystem.physmem.bytesRead 0 # Total number of bytes read from memory 469312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 479312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 489312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 499838Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 509312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 519312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 529312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 539312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 549312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 729312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 739312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 749312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 759312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 769312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 779312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 789312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 799312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 809312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 819312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 829312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 839312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 849312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 859312Sandreas.hansson@arm.comsystem.physmem.totGap 0 # Total gap between requests 869312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 0 # Categorize read packet sizes 939568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 949568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 959568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 969568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 979568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 989568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 999568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1649729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation 1659729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation 1669729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation 1679312Sandreas.hansson@arm.comsystem.physmem.totQLat 0 # Total cycles spent in queuing delays 1689312Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 0 # Sum of mem lat for all requests 1699312Sandreas.hansson@arm.comsystem.physmem.totBusLat 0 # Total cycles spent in databus access 1709312Sandreas.hansson@arm.comsystem.physmem.totBankLat 0 # Total cycles spent in bank access 1719312Sandreas.hansson@arm.comsystem.physmem.avgQLat nan # Average queueing delay per request 1729312Sandreas.hansson@arm.comsystem.physmem.avgBankLat nan # Average bank access latency per request 1739312Sandreas.hansson@arm.comsystem.physmem.avgBusLat nan # Average bus latency per request 1749312Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat nan # Average memory access latency 1759312Sandreas.hansson@arm.comsystem.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 1769312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1779312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 1789312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1799490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1809312Sandreas.hansson@arm.comsystem.physmem.busUtil 0.00 # Data bus utilization in percentage 1819312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.00 # Average read queue length over time 1829312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1839312Sandreas.hansson@arm.comsystem.physmem.readRowHits 0 # Number of row buffer hits during reads 1849312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1859312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate nan # Row buffer hit rate for reads 1869312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1879312Sandreas.hansson@arm.comsystem.physmem.avgGap nan # Average gap between requests 1889797Sandreas.hansson@arm.comsystem.membus.throughput 42552540 # Throughput (bytes/s) 1899797Sandreas.hansson@arm.comsystem.membus.data_through_bus 77842734 # Total data (bytes) 1909729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 1919885Sstever@gmail.comsystem.iocache.tags.replacements 41686 # number of replacements 1929885Sstever@gmail.comsystem.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use 1939885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1949885Sstever@gmail.comsystem.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 1959885Sstever@gmail.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1969885Sstever@gmail.comsystem.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. 1979885Sstever@gmail.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor 1989885Sstever@gmail.comsystem.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 1999885Sstever@gmail.comsystem.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 2008835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 2018721SN/Asystem.iocache.ReadReq_misses::total 174 # number of ReadReq misses 2028835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 2038721SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 2048835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 2058721SN/Asystem.iocache.demand_misses::total 41726 # number of demand (read+write) misses 2068835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 2078721SN/Asystem.iocache.overall_misses::total 41726 # number of overall misses 2088835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 2098721SN/Asystem.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 2108835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 2118721SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 2128835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 2138721SN/Asystem.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 2148835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 2158721SN/Asystem.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 2168835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 2179055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2188835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 2199055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2208835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 2219055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2228835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 2239055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2248721SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2258721SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2268721SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2278721SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2288983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2298983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2308721SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2318721SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2328835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 2338835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 2348721SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2358721SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2368721SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 2378721SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 2388721SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 2398721SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 2408721SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 2418721SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2428721SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2438721SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2448721SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 2458721SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 2468721SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 2478721SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2488721SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2498721SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2508721SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 2519797Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9710427 # DTB read hits 2528721SN/Asystem.cpu.dtb.read_misses 10329 # DTB read misses 2538721SN/Asystem.cpu.dtb.read_acv 210 # DTB read access violations 2548721SN/Asystem.cpu.dtb.read_accesses 728856 # DTB read accesses 2559797Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6352498 # DTB write hits 2568721SN/Asystem.cpu.dtb.write_misses 1142 # DTB write misses 2578721SN/Asystem.cpu.dtb.write_acv 157 # DTB write access violations 2588721SN/Asystem.cpu.dtb.write_accesses 291931 # DTB write accesses 2599797Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16062925 # DTB hits 2606024SN/Asystem.cpu.dtb.data_misses 11471 # DTB misses 2618721SN/Asystem.cpu.dtb.data_acv 367 # DTB access violations 2628721SN/Asystem.cpu.dtb.data_accesses 1020787 # DTB accesses 2639797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 4974648 # ITB hits 2648721SN/Asystem.cpu.itb.fetch_misses 5006 # ITB misses 2658721SN/Asystem.cpu.itb.fetch_acv 184 # ITB acv 2669797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 4979654 # ITB accesses 2678721SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2688721SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2698721SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2708721SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2718721SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2728721SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2738721SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2748721SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2756024SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2766024SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2778721SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2788721SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2799797Sandreas.hansson@arm.comsystem.cpu.numCycles 3658664430 # number of cpu cycles simulated 2808721SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2818721SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2829797Sandreas.hansson@arm.comsystem.cpu.committedInsts 60038305 # Number of instructions committed 2839797Sandreas.hansson@arm.comsystem.cpu.committedOps 60038305 # Number of ops (including micro ops) committed 2849797Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses 2858721SN/Asystem.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 2869797Sandreas.hansson@arm.comsystem.cpu.num_func_calls 1484182 # number of times a function call or return occured 2879797Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls 2889797Sandreas.hansson@arm.comsystem.cpu.num_int_insts 55913521 # number of integer instructions 2898721SN/Asystem.cpu.num_fp_insts 324460 # number of float instructions 2909797Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 76953934 # number of times the integer registers were read 2919797Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 41740225 # number of times the integer registers were written 2928721SN/Asystem.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 2938721SN/Asystem.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 2949797Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 16115709 # number of memory refs 2959797Sandreas.hansson@arm.comsystem.cpu.num_load_insts 9747513 # Number of load instructions 2969797Sandreas.hansson@arm.comsystem.cpu.num_store_insts 6368196 # Number of store instructions 2979797Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 3598609001.180807 # Number of idle cycles 2989797Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles 2999797Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles 3009797Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.983585 # Percentage of idle cycles 3012968SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 3028721SN/Asystem.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 3039797Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed 3046291SN/Asystem.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 3056291SN/Asystem.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 3066291SN/Asystem.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 3079797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl 3089797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl 3096291SN/Asystem.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 3106291SN/Asystem.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 3116291SN/Asystem.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 3126291SN/Asystem.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 3136127SN/Asystem.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 3149797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1811927418500 99.05% 99.05% # number of cycles we spent at this ipl 3156291SN/Asystem.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 3166291SN/Asystem.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 3179797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl 3189797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1829332061500 # number of cycles we spent at this ipl 3196127SN/Asystem.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 3206127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 3216127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 3229797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 3239797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl 3246291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 3256291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 3266291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 3276291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 3286291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 3296291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 3306291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 3316291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 3326291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 3336291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 3346291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 3356291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 3366291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 3376291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 3386291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 3396291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 3406291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 3416291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 3426291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 3436291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 3446291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 3456291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 3466291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 3476291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 3486291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 3496291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 3506291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 3516291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 3526291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 3536291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 3546127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 3558721SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 3568721SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 3578721SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 3588721SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 3598721SN/Asystem.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 3608721SN/Asystem.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 3618721SN/Asystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 3629797Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed 3638721SN/Asystem.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 3648721SN/Asystem.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 3658721SN/Asystem.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 3668721SN/Asystem.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 3678721SN/Asystem.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 3688721SN/Asystem.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 3698721SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 3708721SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 3719797Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 192180 # number of callpals executed 3729797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 3739797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1738 # number of protection mode switches 3749797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 3759797Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1909 3769797Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1738 3778721SN/Asystem.cpu.kern.mode_good::idle 171 3789797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches 3798721SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 3809797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 3819797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches 3829797Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode 3839797Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 3849797Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1801032784000 98.45% 100.00% # number of ticks spent at the given mode 3858721SN/Asystem.cpu.kern.swap_context 4178 # number of times the context was actually changed 3862968SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3872968SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3882968SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3892968SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3908721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3918983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3928721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 3938721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3948983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3958721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3968721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3978983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3988721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3998721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 4008983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 4018721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 4028721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 4038983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 4048721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 4058721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 4068983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 4078721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 4088721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 4098983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 4108721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 4118721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 4128983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 4138721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 4148983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 4158721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 4162968SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 4179797Sandreas.hansson@arm.comsystem.iobus.throughput 1480181 # Throughput (bytes/s) 4189729Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2707742 # Total data (bytes) 4199885Sstever@gmail.comsystem.cpu.icache.tags.replacements 919609 # number of replacements 4209885Sstever@gmail.comsystem.cpu.icache.tags.tagsinuse 511.215244 # Cycle average of tags in use 4219885Sstever@gmail.comsystem.cpu.icache.tags.total_refs 59129907 # Total number of references to valid blocks. 4229885Sstever@gmail.comsystem.cpu.icache.tags.sampled_refs 920121 # Sample count of references to valid blocks. 4239885Sstever@gmail.comsystem.cpu.icache.tags.avg_refs 64.263186 # Average number of references to valid blocks. 4249885Sstever@gmail.comsystem.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 4259885Sstever@gmail.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.215244 # Average occupied blocks per requestor 4269885Sstever@gmail.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 4279885Sstever@gmail.comsystem.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 4289797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 59129907 # number of ReadReq hits 4299797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 59129907 # number of ReadReq hits 4309797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 59129907 # number of demand (read+write) hits 4319797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 59129907 # number of demand (read+write) hits 4329797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 59129907 # number of overall hits 4339797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 59129907 # number of overall hits 4349797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 920236 # number of ReadReq misses 4359797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 920236 # number of ReadReq misses 4369797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 920236 # number of demand (read+write) misses 4379797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 920236 # number of demand (read+write) misses 4389797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 920236 # number of overall misses 4399797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 920236 # number of overall misses 4409797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) 4419797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) 4429797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses 4439797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses 4449797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses 4459797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses 4468835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 4479055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 4488835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 4499055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 4508835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 4519055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 4528721SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4538721SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4548721SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 4558721SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 4568983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4578983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4588721SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 4598721SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 4608721SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4619885Sstever@gmail.comsystem.cpu.l2cache.tags.replacements 992301 # number of replacements 4629885Sstever@gmail.comsystem.cpu.l2cache.tags.tagsinuse 65424.374219 # Cycle average of tags in use 4639885Sstever@gmail.comsystem.cpu.l2cache.tags.total_refs 2433263 # Total number of references to valid blocks. 4649885Sstever@gmail.comsystem.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. 4659885Sstever@gmail.comsystem.cpu.l2cache.tags.avg_refs 2.301036 # Average number of references to valid blocks. 4669885Sstever@gmail.comsystem.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 4679797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 56309.127841 # Average occupied blocks per requestor 4689885Sstever@gmail.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.327126 # Average occupied blocks per requestor 4699885Sstever@gmail.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 4247.919252 # Average occupied blocks per requestor 4709797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy 4719797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy 4729797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 4739885Sstever@gmail.comsystem.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy 4749797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 906812 # number of ReadReq hits 4759797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits 4769797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1718044 # number of ReadReq hits 4779797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 833497 # number of Writeback hits 4789797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 833497 # number of Writeback hits 4799289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 4809289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 4819797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 187230 # number of ReadExReq hits 4829797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 187230 # number of ReadExReq hits 4839797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 906812 # number of demand (read+write) hits 4849797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 998462 # number of demand (read+write) hits 4859797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1905274 # number of demand (read+write) hits 4869797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 906812 # number of overall hits 4879797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 998462 # number of overall hits 4889797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1905274 # number of overall hits 4899797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses 4909289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 4919797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses 4929289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 4939289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 4949797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses 4959797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses 4969797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses 4979797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses 4989797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses 4999797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses 5009797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses 5019797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1058163 # number of overall misses 5029797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 920218 # number of ReadReq accesses(hits+misses) 5039797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) 5049797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2659090 # number of ReadReq accesses(hits+misses) 5059797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 833497 # number of Writeback accesses(hits+misses) 5069797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 833497 # number of Writeback accesses(hits+misses) 5079289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 5089289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 5099797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses) 5109797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses) 5119797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 920218 # number of demand (read+write) accesses 5129797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2043219 # number of demand (read+write) accesses 5139797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2963437 # number of demand (read+write) accesses 5149797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 920218 # number of overall (read+write) accesses 5159797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2043219 # number of overall (read+write) accesses 5169797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2963437 # number of overall (read+write) accesses 5179797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses 5189797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses 5199797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses 5209289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 5219289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses 5229797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384814 # miss rate for ReadExReq accesses 5239797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.384814 # miss rate for ReadExReq accesses 5249797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses 5259797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.511329 # miss rate for demand accesses 5269797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.357073 # miss rate for demand accesses 5279797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses 5289797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.511329 # miss rate for overall accesses 5299797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.357073 # miss rate for overall accesses 5309289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5319289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5329289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5339289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5349289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5359289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5369289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5379289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5389797Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks 5399797Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 74291 # number of writebacks 5409289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 5419885Sstever@gmail.comsystem.cpu.dcache.tags.replacements 2042706 # number of replacements 5429885Sstever@gmail.comsystem.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 5439885Sstever@gmail.comsystem.cpu.dcache.tags.total_refs 14038427 # Total number of references to valid blocks. 5449885Sstever@gmail.comsystem.cpu.dcache.tags.sampled_refs 2043218 # Sample count of references to valid blocks. 5459885Sstever@gmail.comsystem.cpu.dcache.tags.avg_refs 6.870744 # Average number of references to valid blocks. 5469885Sstever@gmail.comsystem.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 5479885Sstever@gmail.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 5489885Sstever@gmail.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 5499885Sstever@gmail.comsystem.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 5509797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7807777 # number of ReadReq hits 5519797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7807777 # number of ReadReq hits 5529797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 5848211 # number of WriteReq hits 5539797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 5848211 # number of WriteReq hits 5549797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 5559797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 5569797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 5579797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 5589797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 13655988 # number of demand (read+write) hits 5599797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 13655988 # number of demand (read+write) hits 5609797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 13655988 # number of overall hits 5619797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 13655988 # number of overall hits 5629797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses 5639797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses 5649797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses 5659797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses 5669481Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 5679481Snilay@cs.wisc.edusystem.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 5689797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2026073 # number of demand (read+write) misses 5699797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 2026073 # number of demand (read+write) misses 5709797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2026073 # number of overall misses 5719797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 2026073 # number of overall misses 5729797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) 5739797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) 5749797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) 5759797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) 5769797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 5779797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 5789797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 5799797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 5809797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses 5819797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses 5829797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses 5839797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses 5849481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 5859481Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 5869797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 5879797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses 5889797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 5899797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses 5909481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 5919481Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 5929481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 5939481Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 5949481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5959481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5969481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5979481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 5989481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5999481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6009481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 6019481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 6029797Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 833497 # number of writebacks 6039797Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 833497 # number of writebacks 6049481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 6059797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 132868790 # Throughput (bytes/s) 6069797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 243051054 # Total data (bytes) 6079729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) 6082968SN/A 6092968SN/A---------- End Simulation Statistics ---------- 610