stats.txt revision 8241
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 4724073 # Simulator instruction rate (inst/s) 4host_mem_usage 291084 # Number of bytes of host memory used 5host_seconds 12.71 # Real time elapsed on the host 6host_tick_rate 143937379014 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 60038305 # Number of instructions simulated 9sim_seconds 1.829332 # Number of seconds simulated 10sim_ticks 1829332258000 # Number of ticks simulated 11system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses) 12system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 13system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits 14system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 15system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses 16system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses 17system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 18system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses) 19system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) 20system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits 21system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits 22system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses 23system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses 24system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses 25system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) 26system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 27system.cpu.dcache.StoreCondReq_hits::0 199282 # number of StoreCondReq hits 28system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 29system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) 30system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) 31system.cpu.dcache.WriteReq_hits::0 5848212 # number of WriteReq hits 32system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits 33system.cpu.dcache.WriteReq_miss_rate::0 0.049469 # miss rate for WriteReq accesses 34system.cpu.dcache.WriteReq_misses::0 304362 # number of WriteReq misses 35system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses 36system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 37system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 38system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. 39system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 40system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 41system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 42system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 43system.cpu.dcache.cache_copies 0 # number of cache copies performed 44system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses 45system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 46system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses 47system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 48system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 49system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 50system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 51system.cpu.dcache.demand_hits::0 13655994 # number of demand (read+write) hits 52system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 53system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits 54system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 55system.cpu.dcache.demand_miss_rate::0 0.129196 # miss rate for demand accesses 56system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 57system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 58system.cpu.dcache.demand_misses::0 2026067 # number of demand (read+write) misses 59system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 60system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses 61system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 62system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 63system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 64system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 65system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 66system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 67system.cpu.dcache.fast_writes 0 # number of fast writes performed 68system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 69system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 70system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context 71system.cpu.dcache.occ_percent::0 0.999996 # Average percentage of cache occupancy 72system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses 73system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 74system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses 75system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 76system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 77system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 78system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 79system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 80system.cpu.dcache.overall_hits::0 13655994 # number of overall hits 81system.cpu.dcache.overall_hits::1 0 # number of overall hits 82system.cpu.dcache.overall_hits::total 13655994 # number of overall hits 83system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles 84system.cpu.dcache.overall_miss_rate::0 0.129196 # miss rate for overall accesses 85system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 86system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 87system.cpu.dcache.overall_misses::0 2026067 # number of overall misses 88system.cpu.dcache.overall_misses::1 0 # number of overall misses 89system.cpu.dcache.overall_misses::total 2026067 # number of overall misses 90system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 91system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 92system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 93system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 94system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 95system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses 96system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 97system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 98system.cpu.dcache.replacements 2042700 # number of replacements 99system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. 100system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 101system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use 102system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. 103system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 104system.cpu.dcache.writebacks 825183 # number of writebacks 105system.cpu.dtb.data_accesses 1020787 # DTB accesses 106system.cpu.dtb.data_acv 367 # DTB access violations 107system.cpu.dtb.data_hits 16062925 # DTB hits 108system.cpu.dtb.data_misses 11471 # DTB misses 109system.cpu.dtb.fetch_accesses 0 # ITB accesses 110system.cpu.dtb.fetch_acv 0 # ITB acv 111system.cpu.dtb.fetch_hits 0 # ITB hits 112system.cpu.dtb.fetch_misses 0 # ITB misses 113system.cpu.dtb.read_accesses 728856 # DTB read accesses 114system.cpu.dtb.read_acv 210 # DTB read access violations 115system.cpu.dtb.read_hits 9710427 # DTB read hits 116system.cpu.dtb.read_misses 10329 # DTB read misses 117system.cpu.dtb.write_accesses 291931 # DTB write accesses 118system.cpu.dtb.write_acv 157 # DTB write access violations 119system.cpu.dtb.write_hits 6352498 # DTB write hits 120system.cpu.dtb.write_misses 1142 # DTB write misses 121system.cpu.icache.ReadReq_accesses::0 60050143 # number of ReadReq accesses(hits+misses) 122system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) 123system.cpu.icache.ReadReq_hits::0 59129922 # number of ReadReq hits 124system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits 125system.cpu.icache.ReadReq_miss_rate::0 0.015324 # miss rate for ReadReq accesses 126system.cpu.icache.ReadReq_misses::0 920221 # number of ReadReq misses 127system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses 128system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 129system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 130system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. 131system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 132system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 133system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 134system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 135system.cpu.icache.cache_copies 0 # number of cache copies performed 136system.cpu.icache.demand_accesses::0 60050143 # number of demand (read+write) accesses 137system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 138system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses 139system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency 140system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 141system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency 142system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 143system.cpu.icache.demand_hits::0 59129922 # number of demand (read+write) hits 144system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 145system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits 146system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 147system.cpu.icache.demand_miss_rate::0 0.015324 # miss rate for demand accesses 148system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 149system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 150system.cpu.icache.demand_misses::0 920221 # number of demand (read+write) misses 151system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 152system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses 153system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 154system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 155system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 156system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 157system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 158system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 159system.cpu.icache.fast_writes 0 # number of fast writes performed 160system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 161system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 162system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context 163system.cpu.icache.occ_percent::0 0.998467 # Average percentage of cache occupancy 164system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses 165system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 166system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses 167system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency 168system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 169system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency 170system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 171system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 172system.cpu.icache.overall_hits::0 59129922 # number of overall hits 173system.cpu.icache.overall_hits::1 0 # number of overall hits 174system.cpu.icache.overall_hits::total 59129922 # number of overall hits 175system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles 176system.cpu.icache.overall_miss_rate::0 0.015324 # miss rate for overall accesses 177system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 178system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 179system.cpu.icache.overall_misses::0 920221 # number of overall misses 180system.cpu.icache.overall_misses::1 0 # number of overall misses 181system.cpu.icache.overall_misses::total 920221 # number of overall misses 182system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 183system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 184system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 185system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 186system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 187system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses 188system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 189system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 190system.cpu.icache.replacements 919594 # number of replacements 191system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. 192system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 193system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use 194system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. 195system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 196system.cpu.icache.writebacks 108 # number of writebacks 197system.cpu.idle_fraction 0.983585 # Percentage of idle cycles 198system.cpu.itb.data_accesses 0 # DTB accesses 199system.cpu.itb.data_acv 0 # DTB access violations 200system.cpu.itb.data_hits 0 # DTB hits 201system.cpu.itb.data_misses 0 # DTB misses 202system.cpu.itb.fetch_accesses 4979654 # ITB accesses 203system.cpu.itb.fetch_acv 184 # ITB acv 204system.cpu.itb.fetch_hits 4974648 # ITB hits 205system.cpu.itb.fetch_misses 5006 # ITB misses 206system.cpu.itb.read_accesses 0 # DTB read accesses 207system.cpu.itb.read_acv 0 # DTB read access violations 208system.cpu.itb.read_hits 0 # DTB read hits 209system.cpu.itb.read_misses 0 # DTB read misses 210system.cpu.itb.write_accesses 0 # DTB write accesses 211system.cpu.itb.write_acv 0 # DTB write access violations 212system.cpu.itb.write_hits 0 # DTB write hits 213system.cpu.itb.write_misses 0 # DTB write misses 214system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 215system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 216system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 217system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 218system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 219system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 220system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 221system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed 222system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 223system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 224system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 225system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 226system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 227system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 228system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 229system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 230system.cpu.kern.callpal::total 192180 # number of callpals executed 231system.cpu.kern.inst.arm 0 # number of arm instructions executed 232system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed 233system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 234system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 235system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 236system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 237system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl 238system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl 239system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 240system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 241system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 242system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 243system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 244system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl 245system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 246system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 247system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl 248system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl 249system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 250system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 251system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 252system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 253system.cpu.kern.mode_good::kernel 1909 254system.cpu.kern.mode_good::user 1738 255system.cpu.kern.mode_good::idle 171 256system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 257system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 258system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 259system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches 260system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 261system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 262system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches 263system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode 264system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 265system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode 266system.cpu.kern.swap_context 4178 # number of times the context was actually changed 267system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 268system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 269system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 270system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 271system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 272system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 273system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 274system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 275system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 276system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 277system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 278system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 279system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 280system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 281system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 282system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 283system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 284system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 285system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 286system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 287system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 288system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 289system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 290system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 291system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 292system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 293system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 294system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 295system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 296system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 297system.cpu.kern.syscall::total 326 # number of syscalls executed 298system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles 299system.cpu.numCycles 3658664408 # number of cpu cycles simulated 300system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 301system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 302system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles 303system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls 304system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 305system.cpu.num_fp_insts 324460 # number of float instructions 306system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 307system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 308system.cpu.num_func_calls 1484182 # number of times a function call or return occured 309system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles 310system.cpu.num_insts 60038305 # Number of instructions executed 311system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses 312system.cpu.num_int_insts 55913521 # number of integer instructions 313system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read 314system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written 315system.cpu.num_load_insts 9747513 # Number of load instructions 316system.cpu.num_mem_refs 16115709 # number of memory refs 317system.cpu.num_store_insts 6368196 # Number of store instructions 318system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 319system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 320system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 321system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 322system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 323system.disk0.dma_write_txs 395 # Number of DMA write transactions. 324system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 325system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 326system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 327system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 328system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 329system.disk2.dma_write_txs 1 # Number of DMA write transactions. 330system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) 331system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 332system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 333system.iocache.ReadReq_misses::1 174 # number of ReadReq misses 334system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 335system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) 336system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 337system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 338system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses 339system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 340system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 341system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 342system.iocache.avg_refs 0 # Average number of references to valid blocks. 343system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 344system.iocache.blocked::no_targets 0 # number of cycles access was blocked 345system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 346system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 347system.iocache.cache_copies 0 # number of cache copies performed 348system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 349system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses 350system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 351system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 352system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency 353system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 354system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 355system.iocache.demand_hits::0 0 # number of demand (read+write) hits 356system.iocache.demand_hits::1 0 # number of demand (read+write) hits 357system.iocache.demand_hits::total 0 # number of demand (read+write) hits 358system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 359system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 360system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 361system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 362system.iocache.demand_misses::0 0 # number of demand (read+write) misses 363system.iocache.demand_misses::1 41726 # number of demand (read+write) misses 364system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 365system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 366system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 367system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 368system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 369system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 370system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 371system.iocache.fast_writes 0 # number of fast writes performed 372system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 373system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 374system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context 375system.iocache.occ_percent::1 0.076598 # Average percentage of cache occupancy 376system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 377system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses 378system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses 379system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 380system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency 381system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 382system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 383system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 384system.iocache.overall_hits::0 0 # number of overall hits 385system.iocache.overall_hits::1 0 # number of overall hits 386system.iocache.overall_hits::total 0 # number of overall hits 387system.iocache.overall_miss_latency 0 # number of overall miss cycles 388system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 389system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 390system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 391system.iocache.overall_misses::0 0 # number of overall misses 392system.iocache.overall_misses::1 41726 # number of overall misses 393system.iocache.overall_misses::total 41726 # number of overall misses 394system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 395system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 396system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 397system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 398system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 399system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 400system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 401system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 402system.iocache.replacements 41686 # number of replacements 403system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. 404system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 405system.iocache.tagsinuse 1.225570 # Cycle average of tags in use 406system.iocache.total_refs 0 # Total number of references to valid blocks. 407system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. 408system.iocache.writebacks 41512 # number of writebacks 409system.l2c.ReadExReq_accesses::0 304242 # number of ReadExReq accesses(hits+misses) 410system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) 411system.l2c.ReadExReq_hits::0 185383 # number of ReadExReq hits 412system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits 413system.l2c.ReadExReq_miss_rate::0 0.390673 # miss rate for ReadExReq accesses 414system.l2c.ReadExReq_misses::0 118859 # number of ReadExReq misses 415system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses 416system.l2c.ReadReq_accesses::0 2659024 # number of ReadReq accesses(hits+misses) 417system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses) 418system.l2c.ReadReq_hits::0 1699395 # number of ReadReq hits 419system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits 420system.l2c.ReadReq_miss_rate::0 0.360895 # miss rate for ReadReq accesses 421system.l2c.ReadReq_misses::0 959629 # number of ReadReq misses 422system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses 423system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses) 424system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) 425system.l2c.UpgradeReq_hits::0 1 # number of UpgradeReq hits 426system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits 427system.l2c.UpgradeReq_miss_rate::0 0.923077 # miss rate for UpgradeReq accesses 428system.l2c.UpgradeReq_misses::0 12 # number of UpgradeReq misses 429system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses 430system.l2c.Writeback_accesses::0 825291 # number of Writeback accesses(hits+misses) 431system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses) 432system.l2c.Writeback_hits::0 825291 # number of Writeback hits 433system.l2c.Writeback_hits::total 825291 # number of Writeback hits 434system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 435system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 436system.l2c.avg_refs 2.126306 # Average number of references to valid blocks. 437system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 438system.l2c.blocked::no_targets 0 # number of cycles access was blocked 439system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 440system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 441system.l2c.cache_copies 0 # number of cache copies performed 442system.l2c.demand_accesses::0 2963266 # number of demand (read+write) accesses 443system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses 444system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses 445system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 446system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency 447system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency 448system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 449system.l2c.demand_hits::0 1884778 # number of demand (read+write) hits 450system.l2c.demand_hits::1 0 # number of demand (read+write) hits 451system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits 452system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 453system.l2c.demand_miss_rate::0 0.363952 # miss rate for demand accesses 454system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses 455system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses 456system.l2c.demand_misses::0 1078488 # number of demand (read+write) misses 457system.l2c.demand_misses::1 0 # number of demand (read+write) misses 458system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses 459system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 460system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 461system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 462system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 463system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 464system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 465system.l2c.fast_writes 0 # number of fast writes performed 466system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 467system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 468system.l2c.occ_blocks::0 10193.605493 # Average occupied blocks per context 469system.l2c.occ_blocks::1 23613.410409 # Average occupied blocks per context 470system.l2c.occ_percent::0 0.155542 # Average percentage of cache occupancy 471system.l2c.occ_percent::1 0.360312 # Average percentage of cache occupancy 472system.l2c.overall_accesses::0 2963266 # number of overall (read+write) accesses 473system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses 474system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses 475system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 476system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency 477system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency 478system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 479system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 480system.l2c.overall_hits::0 1884778 # number of overall hits 481system.l2c.overall_hits::1 0 # number of overall hits 482system.l2c.overall_hits::total 1884778 # number of overall hits 483system.l2c.overall_miss_latency 0 # number of overall miss cycles 484system.l2c.overall_miss_rate::0 0.363952 # miss rate for overall accesses 485system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses 486system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses 487system.l2c.overall_misses::0 1078488 # number of overall misses 488system.l2c.overall_misses::1 0 # number of overall misses 489system.l2c.overall_misses::total 1078488 # number of overall misses 490system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 491system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 492system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 493system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 494system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 495system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 496system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 497system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 498system.l2c.replacements 1045877 # number of replacements 499system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks. 500system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 501system.l2c.tagsinuse 33807.015903 # Cycle average of tags in use 502system.l2c.total_refs 2291835 # Total number of references to valid blocks. 503system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. 504system.l2c.writebacks 117189 # number of writebacks 505system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 506system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 507system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 508system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 509system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 510system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 511system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 512system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 513system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 514system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 515system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 516system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 517system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 518system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 519system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 520system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 521system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 522system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 523system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 524system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 525system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 526system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 527system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 528system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 529system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 530system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 531system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 532system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 533system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 534system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 535system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 536 537---------- End Simulation Statistics ---------- 538