stats.txt revision 6127
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 4025289 # Simulator instruction rate (inst/s) 4host_mem_usage 293608 # Number of bytes of host memory used 5host_seconds 14.92 # Real time elapsed on the host 6host_tick_rate 122645865621 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 60038305 # Number of instructions simulated 9sim_seconds 1.829332 # Number of seconds simulated 10sim_ticks 1829332258000 # Number of ticks simulated 11system.cpu.dcache.LoadLockedReq_accesses 200303 # number of LoadLockedReq accesses(hits+misses) 12system.cpu.dcache.LoadLockedReq_hits 183141 # number of LoadLockedReq hits 13system.cpu.dcache.LoadLockedReq_miss_rate 0.085680 # miss rate for LoadLockedReq accesses 14system.cpu.dcache.LoadLockedReq_misses 17162 # number of LoadLockedReq misses 15system.cpu.dcache.ReadReq_accesses 9529487 # number of ReadReq accesses(hits+misses) 16system.cpu.dcache.ReadReq_hits 7807782 # number of ReadReq hits 17system.cpu.dcache.ReadReq_miss_rate 0.180671 # miss rate for ReadReq accesses 18system.cpu.dcache.ReadReq_misses 1721705 # number of ReadReq misses 19system.cpu.dcache.StoreCondReq_accesses 199282 # number of StoreCondReq accesses(hits+misses) 20system.cpu.dcache.StoreCondReq_hits 169415 # number of StoreCondReq hits 21system.cpu.dcache.StoreCondReq_miss_rate 0.149873 # miss rate for StoreCondReq accesses 22system.cpu.dcache.StoreCondReq_misses 29867 # number of StoreCondReq misses 23system.cpu.dcache.WriteReq_accesses 6152574 # number of WriteReq accesses(hits+misses) 24system.cpu.dcache.WriteReq_hits 5753150 # number of WriteReq hits 25system.cpu.dcache.WriteReq_miss_rate 0.064920 # miss rate for WriteReq accesses 26system.cpu.dcache.WriteReq_misses 399424 # number of WriteReq misses 27system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 28system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 29system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. 30system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 31system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 32system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 33system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 34system.cpu.dcache.cache_copies 0 # number of cache copies performed 35system.cpu.dcache.demand_accesses 15682061 # number of demand (read+write) accesses 36system.cpu.dcache.demand_avg_miss_latency 0 # average overall miss latency 37system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 38system.cpu.dcache.demand_hits 13560932 # number of demand (read+write) hits 39system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 40system.cpu.dcache.demand_miss_rate 0.135258 # miss rate for demand accesses 41system.cpu.dcache.demand_misses 2121129 # number of demand (read+write) misses 42system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 43system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 44system.cpu.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 45system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 46system.cpu.dcache.fast_writes 0 # number of fast writes performed 47system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 48system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 49system.cpu.dcache.overall_accesses 15682061 # number of overall (read+write) accesses 50system.cpu.dcache.overall_avg_miss_latency 0 # average overall miss latency 51system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 52system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 53system.cpu.dcache.overall_hits 13560932 # number of overall hits 54system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles 55system.cpu.dcache.overall_miss_rate 0.135258 # miss rate for overall accesses 56system.cpu.dcache.overall_misses 2121129 # number of overall misses 57system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 58system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 59system.cpu.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 60system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses 61system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 62system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 63system.cpu.dcache.replacements 2042700 # number of replacements 64system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. 65system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 66system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use 67system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. 68system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 69system.cpu.dcache.writebacks 428893 # number of writebacks 70system.cpu.dtb.data_accesses 1020787 # DTB accesses 71system.cpu.dtb.data_acv 367 # DTB access violations 72system.cpu.dtb.data_hits 16062925 # DTB hits 73system.cpu.dtb.data_misses 11471 # DTB misses 74system.cpu.dtb.fetch_accesses 0 # ITB accesses 75system.cpu.dtb.fetch_acv 0 # ITB acv 76system.cpu.dtb.fetch_hits 0 # ITB hits 77system.cpu.dtb.fetch_misses 0 # ITB misses 78system.cpu.dtb.read_accesses 728856 # DTB read accesses 79system.cpu.dtb.read_acv 210 # DTB read access violations 80system.cpu.dtb.read_hits 9710427 # DTB read hits 81system.cpu.dtb.read_misses 10329 # DTB read misses 82system.cpu.dtb.write_accesses 291931 # DTB write accesses 83system.cpu.dtb.write_acv 157 # DTB write access violations 84system.cpu.dtb.write_hits 6352498 # DTB write hits 85system.cpu.dtb.write_misses 1142 # DTB write misses 86system.cpu.icache.ReadReq_accesses 60050143 # number of ReadReq accesses(hits+misses) 87system.cpu.icache.ReadReq_hits 59129922 # number of ReadReq hits 88system.cpu.icache.ReadReq_miss_rate 0.015324 # miss rate for ReadReq accesses 89system.cpu.icache.ReadReq_misses 920221 # number of ReadReq misses 90system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 91system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 92system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. 93system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 94system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 95system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 96system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97system.cpu.icache.cache_copies 0 # number of cache copies performed 98system.cpu.icache.demand_accesses 60050143 # number of demand (read+write) accesses 99system.cpu.icache.demand_avg_miss_latency 0 # average overall miss latency 100system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 101system.cpu.icache.demand_hits 59129922 # number of demand (read+write) hits 102system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 103system.cpu.icache.demand_miss_rate 0.015324 # miss rate for demand accesses 104system.cpu.icache.demand_misses 920221 # number of demand (read+write) misses 105system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 106system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 107system.cpu.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 108system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 109system.cpu.icache.fast_writes 0 # number of fast writes performed 110system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 111system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 112system.cpu.icache.overall_accesses 60050143 # number of overall (read+write) accesses 113system.cpu.icache.overall_avg_miss_latency 0 # average overall miss latency 114system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 115system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 116system.cpu.icache.overall_hits 59129922 # number of overall hits 117system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles 118system.cpu.icache.overall_miss_rate 0.015324 # miss rate for overall accesses 119system.cpu.icache.overall_misses 920221 # number of overall misses 120system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 121system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 122system.cpu.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 123system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses 124system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 125system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 126system.cpu.icache.replacements 919594 # number of replacements 127system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. 128system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 129system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use 130system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. 131system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 132system.cpu.icache.writebacks 0 # number of writebacks 133system.cpu.idle_fraction 0.983585 # Percentage of idle cycles 134system.cpu.itb.data_accesses 0 # DTB accesses 135system.cpu.itb.data_acv 0 # DTB access violations 136system.cpu.itb.data_hits 0 # DTB hits 137system.cpu.itb.data_misses 0 # DTB misses 138system.cpu.itb.fetch_accesses 4979654 # ITB accesses 139system.cpu.itb.fetch_acv 184 # ITB acv 140system.cpu.itb.fetch_hits 4974648 # ITB hits 141system.cpu.itb.fetch_misses 5006 # ITB misses 142system.cpu.itb.read_accesses 0 # DTB read accesses 143system.cpu.itb.read_acv 0 # DTB read access violations 144system.cpu.itb.read_hits 0 # DTB read hits 145system.cpu.itb.read_misses 0 # DTB read misses 146system.cpu.itb.write_accesses 0 # DTB write accesses 147system.cpu.itb.write_acv 0 # DTB write access violations 148system.cpu.itb.write_hits 0 # DTB write hits 149system.cpu.itb.write_misses 0 # DTB write misses 150system.cpu.kern.callpal::cserve 1 0.00% # number of callpals executed 151system.cpu.kern.callpal::wrmces 1 0.00% # number of callpals executed 152system.cpu.kern.callpal::wrfen 1 0.00% # number of callpals executed 153system.cpu.kern.callpal::wrvptptr 1 0.00% # number of callpals executed 154system.cpu.kern.callpal::swpctx 4177 2.17% # number of callpals executed 155system.cpu.kern.callpal::tbi 54 0.03% # number of callpals executed 156system.cpu.kern.callpal::wrent 7 0.00% # number of callpals executed 157system.cpu.kern.callpal::swpipl 175249 91.19% # number of callpals executed 158system.cpu.kern.callpal::rdps 6771 3.52% # number of callpals executed 159system.cpu.kern.callpal::wrkgp 1 0.00% # number of callpals executed 160system.cpu.kern.callpal::wrusp 7 0.00% # number of callpals executed 161system.cpu.kern.callpal::rdusp 9 0.00% # number of callpals executed 162system.cpu.kern.callpal::whami 2 0.00% # number of callpals executed 163system.cpu.kern.callpal::rti 5203 2.71% # number of callpals executed 164system.cpu.kern.callpal::callsys 515 0.27% # number of callpals executed 165system.cpu.kern.callpal::imb 181 0.09% # number of callpals executed 166system.cpu.kern.callpal::total 192180 # number of callpals executed 167system.cpu.kern.inst.arm 0 # number of arm instructions executed 168system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed 169system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 170system.cpu.kern.ipl_count::0 74830 40.99% # number of times we switched to this ipl 171system.cpu.kern.ipl_count::21 243 0.13% # number of times we switched to this ipl 172system.cpu.kern.ipl_count::22 1866 1.02% # number of times we switched to this ipl 173system.cpu.kern.ipl_count::31 105623 57.86% # number of times we switched to this ipl 174system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl 175system.cpu.kern.ipl_good::0 73463 49.29% # number of times we switched to this ipl from a different ipl 176system.cpu.kern.ipl_good::21 243 0.16% # number of times we switched to this ipl from a different ipl 177system.cpu.kern.ipl_good::22 1866 1.25% # number of times we switched to this ipl from a different ipl 178system.cpu.kern.ipl_good::31 73463 49.29% # number of times we switched to this ipl from a different ipl 179system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 180system.cpu.kern.ipl_ticks::0 1811927407500 99.05% # number of cycles we spent at this ipl 181system.cpu.kern.ipl_ticks::21 20110000 0.00% # number of cycles we spent at this ipl 182system.cpu.kern.ipl_ticks::22 80238000 0.00% # number of cycles we spent at this ipl 183system.cpu.kern.ipl_ticks::31 17304295000 0.95% # number of cycles we spent at this ipl 184system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl 185system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 186system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 187system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 188system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 189system.cpu.kern.mode_good::kernel 1909 190system.cpu.kern.mode_good::user 1738 191system.cpu.kern.mode_good::idle 171 192system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 193system.cpu.kern.mode_switch::user 1738 # number of protection mode switches 194system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 195system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches 196system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 197system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 198system.cpu.kern.mode_switch_good::total 1.402439 # fraction of useful protection mode switches 199system.cpu.kern.mode_ticks::kernel 26834202500 1.47% # number of ticks spent at the given mode 200system.cpu.kern.mode_ticks::user 1465074000 0.08% # number of ticks spent at the given mode 201system.cpu.kern.mode_ticks::idle 1801032773000 98.45% # number of ticks spent at the given mode 202system.cpu.kern.swap_context 4178 # number of times the context was actually changed 203system.cpu.kern.syscall::2 8 2.45% # number of syscalls executed 204system.cpu.kern.syscall::3 30 9.20% # number of syscalls executed 205system.cpu.kern.syscall::4 4 1.23% # number of syscalls executed 206system.cpu.kern.syscall::6 42 12.88% # number of syscalls executed 207system.cpu.kern.syscall::12 1 0.31% # number of syscalls executed 208system.cpu.kern.syscall::15 1 0.31% # number of syscalls executed 209system.cpu.kern.syscall::17 15 4.60% # number of syscalls executed 210system.cpu.kern.syscall::19 10 3.07% # number of syscalls executed 211system.cpu.kern.syscall::20 6 1.84% # number of syscalls executed 212system.cpu.kern.syscall::23 4 1.23% # number of syscalls executed 213system.cpu.kern.syscall::24 6 1.84% # number of syscalls executed 214system.cpu.kern.syscall::33 11 3.37% # number of syscalls executed 215system.cpu.kern.syscall::41 2 0.61% # number of syscalls executed 216system.cpu.kern.syscall::45 54 16.56% # number of syscalls executed 217system.cpu.kern.syscall::47 6 1.84% # number of syscalls executed 218system.cpu.kern.syscall::48 10 3.07% # number of syscalls executed 219system.cpu.kern.syscall::54 10 3.07% # number of syscalls executed 220system.cpu.kern.syscall::58 1 0.31% # number of syscalls executed 221system.cpu.kern.syscall::59 7 2.15% # number of syscalls executed 222system.cpu.kern.syscall::71 54 16.56% # number of syscalls executed 223system.cpu.kern.syscall::73 3 0.92% # number of syscalls executed 224system.cpu.kern.syscall::74 16 4.91% # number of syscalls executed 225system.cpu.kern.syscall::87 1 0.31% # number of syscalls executed 226system.cpu.kern.syscall::90 3 0.92% # number of syscalls executed 227system.cpu.kern.syscall::92 9 2.76% # number of syscalls executed 228system.cpu.kern.syscall::97 2 0.61% # number of syscalls executed 229system.cpu.kern.syscall::98 2 0.61% # number of syscalls executed 230system.cpu.kern.syscall::132 4 1.23% # number of syscalls executed 231system.cpu.kern.syscall::144 2 0.61% # number of syscalls executed 232system.cpu.kern.syscall::147 2 0.61% # number of syscalls executed 233system.cpu.kern.syscall::total 326 # number of syscalls executed 234system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles 235system.cpu.numCycles 3658664408 # number of cpu cycles simulated 236system.cpu.num_insts 60038305 # Number of instructions executed 237system.cpu.num_refs 16311238 # Number of memory references 238system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 239system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 240system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 241system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 242system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 243system.disk0.dma_write_txs 395 # Number of DMA write transactions. 244system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 245system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 246system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 247system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 248system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 249system.disk2.dma_write_txs 1 # Number of DMA write transactions. 250system.iocache.ReadReq_accesses 174 # number of ReadReq accesses(hits+misses) 251system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses 252system.iocache.ReadReq_misses 174 # number of ReadReq misses 253system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) 254system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses 255system.iocache.WriteReq_misses 41552 # number of WriteReq misses 256system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 257system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 258system.iocache.avg_refs 0 # Average number of references to valid blocks. 259system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 260system.iocache.blocked::no_targets 0 # number of cycles access was blocked 261system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 262system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 263system.iocache.cache_copies 0 # number of cache copies performed 264system.iocache.demand_accesses 41726 # number of demand (read+write) accesses 265system.iocache.demand_avg_miss_latency 0 # average overall miss latency 266system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 267system.iocache.demand_hits 0 # number of demand (read+write) hits 268system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 269system.iocache.demand_miss_rate 1 # miss rate for demand accesses 270system.iocache.demand_misses 41726 # number of demand (read+write) misses 271system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 272system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 273system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 274system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 275system.iocache.fast_writes 0 # number of fast writes performed 276system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 277system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 278system.iocache.overall_accesses 41726 # number of overall (read+write) accesses 279system.iocache.overall_avg_miss_latency 0 # average overall miss latency 280system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 281system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 282system.iocache.overall_hits 0 # number of overall hits 283system.iocache.overall_miss_latency 0 # number of overall miss cycles 284system.iocache.overall_miss_rate 1 # miss rate for overall accesses 285system.iocache.overall_misses 41726 # number of overall misses 286system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 287system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 288system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 289system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 290system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 291system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 292system.iocache.replacements 41686 # number of replacements 293system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. 294system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 295system.iocache.tagsinuse 1.225570 # Cycle average of tags in use 296system.iocache.total_refs 0 # Total number of references to valid blocks. 297system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. 298system.iocache.writebacks 41512 # number of writebacks 299system.l2c.ReadExReq_accesses 304346 # number of ReadExReq accesses(hits+misses) 300system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 301system.l2c.ReadExReq_misses 304346 # number of ReadExReq misses 302system.l2c.ReadReq_accesses 2659071 # number of ReadReq accesses(hits+misses) 303system.l2c.ReadReq_hits 1696652 # number of ReadReq hits 304system.l2c.ReadReq_miss_rate 0.361938 # miss rate for ReadReq accesses 305system.l2c.ReadReq_misses 962419 # number of ReadReq misses 306system.l2c.UpgradeReq_accesses 124945 # number of UpgradeReq accesses(hits+misses) 307system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 308system.l2c.UpgradeReq_misses 124945 # number of UpgradeReq misses 309system.l2c.Writeback_accesses 428893 # number of Writeback accesses(hits+misses) 310system.l2c.Writeback_hits 428893 # number of Writeback hits 311system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 312system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 313system.l2c.avg_refs 1.727246 # Average number of references to valid blocks. 314system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 315system.l2c.blocked::no_targets 0 # number of cycles access was blocked 316system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 317system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 318system.l2c.cache_copies 0 # number of cache copies performed 319system.l2c.demand_accesses 2963417 # number of demand (read+write) accesses 320system.l2c.demand_avg_miss_latency 0 # average overall miss latency 321system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 322system.l2c.demand_hits 1696652 # number of demand (read+write) hits 323system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 324system.l2c.demand_miss_rate 0.427468 # miss rate for demand accesses 325system.l2c.demand_misses 1266765 # number of demand (read+write) misses 326system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 327system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 328system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 329system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 330system.l2c.fast_writes 0 # number of fast writes performed 331system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 332system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 333system.l2c.overall_accesses 2963417 # number of overall (read+write) accesses 334system.l2c.overall_avg_miss_latency 0 # average overall miss latency 335system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 336system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 337system.l2c.overall_hits 1696652 # number of overall hits 338system.l2c.overall_miss_latency 0 # number of overall miss cycles 339system.l2c.overall_miss_rate 0.427468 # miss rate for overall accesses 340system.l2c.overall_misses 1266765 # number of overall misses 341system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 342system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 343system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 344system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 345system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 346system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 347system.l2c.replacements 1050724 # number of replacements 348system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks. 349system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 350system.l2c.tagsinuse 30228.585605 # Cycle average of tags in use 351system.l2c.total_refs 1867269 # Total number of references to valid blocks. 352system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. 353system.l2c.writebacks 119147 # number of writebacks 354system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post 355system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post 356system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post 357system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post 358system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post 359system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post 360system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post 361system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post 362system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post 363system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 364system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 365system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 366system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 367system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 368system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 369system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 370system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 371system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 372system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 373system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 374system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 375system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 376system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 377system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 378system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 379system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 380system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 381system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 382system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 383system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 384system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 385 386---------- End Simulation Statistics ---------- 387