stats.txt revision 11606
12968SN/A
22968SN/A---------- Begin Simulation Statistics ----------
39797Sandreas.hansson@arm.comsim_seconds                                  1.829332                       # Number of seconds simulated
411606Sandreas.sandberg@arm.comsim_ticks                                1829332003500                       # Number of ticks simulated
511606Sandreas.sandberg@arm.comfinal_tick                               1829332003500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
68721SN/Asim_freq                                 1000000000000                       # Frequency of simulated ticks
711606Sandreas.sandberg@arm.comhost_inst_rate                                1751464                       # Simulator instruction rate (inst/s)
811606Sandreas.sandberg@arm.comhost_op_rate                                  1751464                       # Simulator op (including micro ops) rate (op/s)
911606Sandreas.sandberg@arm.comhost_tick_rate                            53365900898                       # Simulator tick rate (ticks/s)
1011606Sandreas.sandberg@arm.comhost_mem_usage                                 334408                       # Number of bytes of host memory used
1111606Sandreas.sandberg@arm.comhost_seconds                                    34.28                       # Real time elapsed on the host
1211336Sandreas.hansson@arm.comsim_insts                                    60038469                       # Number of instructions simulated
1311336Sandreas.hansson@arm.comsim_ops                                      60038469                       # Number of ops (including micro ops) simulated
1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage                       1                       # Voltage in Volts
1510036SAli.Saidi@ARM.comsystem.clk_domain.clock                          1000                       # Clock period in ticks
1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst            850496                       # Number of bytes read from this memory
1811336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data          66835072                       # Number of bytes read from this memory
1910352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide            960                       # Number of bytes read from this memory
2011336Sandreas.hansson@arm.comsystem.physmem.bytes_read::total             67686528                       # Number of bytes read from this memory
2111201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst       850496                       # Number of instructions bytes read from this memory
2211201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total          850496                       # Number of instructions bytes read from this memory
2311336Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks      7415744                       # Number of bytes written to this memory
2411336Sandreas.hansson@arm.comsystem.physmem.bytes_written::total           7415744                       # Number of bytes written to this memory
2511201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst              13289                       # Number of read requests responded to by this memory
2611336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data            1044298                       # Number of read requests responded to by this memory
2710352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide              15                       # Number of read requests responded to by this memory
2811336Sandreas.hansson@arm.comsystem.physmem.num_reads::total               1057602                       # Number of read requests responded to by this memory
2911336Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks          115871                       # Number of write requests responded to by this memory
3011336Sandreas.hansson@arm.comsystem.physmem.num_writes::total               115871                       # Number of write requests responded to by this memory
3111201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst               464922                       # Total read bandwidth from this memory (bytes/s)
3211336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data             36535234                       # Total read bandwidth from this memory (bytes/s)
3310352Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide               525                       # Total read bandwidth from this memory (bytes/s)
3411336Sandreas.hansson@arm.comsystem.physmem.bw_read::total                37000680                       # Total read bandwidth from this memory (bytes/s)
3511201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst          464922                       # Instruction read bandwidth from this memory (bytes/s)
3611201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total             464922                       # Instruction read bandwidth from this memory (bytes/s)
3711336Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks           4053799                       # Write bandwidth from this memory (bytes/s)
3811336Sandreas.hansson@arm.comsystem.physmem.bw_write::total                4053799                       # Write bandwidth from this memory (bytes/s)
3911336Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks           4053799                       # Total bandwidth to/from this memory (bytes/s)
4011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst              464922                       # Total bandwidth to/from this memory (bytes/s)
4111336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data            36535234                       # Total bandwidth to/from this memory (bytes/s)
4210585Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide              525                       # Total bandwidth to/from this memory (bytes/s)
4311336Sandreas.hansson@arm.comsystem.physmem.bw_total::total               41054479                       # Total bandwidth to/from this memory (bytes/s)
4411606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
4511606Sandreas.sandberg@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
4610036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock                       500                       # Clock period in ticks
478721SN/Asystem.cpu.dtb.fetch_hits                           0                       # ITB hits
488721SN/Asystem.cpu.dtb.fetch_misses                         0                       # ITB misses
498721SN/Asystem.cpu.dtb.fetch_acv                            0                       # ITB acv
508721SN/Asystem.cpu.dtb.fetch_accesses                       0                       # ITB accesses
5111336Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits                      9710423                       # DTB read hits
528721SN/Asystem.cpu.dtb.read_misses                      10329                       # DTB read misses
538721SN/Asystem.cpu.dtb.read_acv                           210                       # DTB read access violations
548721SN/Asystem.cpu.dtb.read_accesses                   728856                       # DTB read accesses
5510409Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits                     6352496                       # DTB write hits
568721SN/Asystem.cpu.dtb.write_misses                      1142                       # DTB write misses
578721SN/Asystem.cpu.dtb.write_acv                          157                       # DTB write access violations
588721SN/Asystem.cpu.dtb.write_accesses                  291931                       # DTB write accesses
5911336Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits                     16062919                       # DTB hits
606024SN/Asystem.cpu.dtb.data_misses                      11471                       # DTB misses
618721SN/Asystem.cpu.dtb.data_acv                           367                       # DTB access violations
628721SN/Asystem.cpu.dtb.data_accesses                  1020787                       # DTB accesses
6311336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits                     4974637                       # ITB hits
648721SN/Asystem.cpu.itb.fetch_misses                      5006                       # ITB misses
658721SN/Asystem.cpu.itb.fetch_acv                          184                       # ITB acv
6611336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses                 4979643                       # ITB accesses
678721SN/Asystem.cpu.itb.read_hits                            0                       # DTB read hits
688721SN/Asystem.cpu.itb.read_misses                          0                       # DTB read misses
698721SN/Asystem.cpu.itb.read_acv                             0                       # DTB read access violations
708721SN/Asystem.cpu.itb.read_accesses                        0                       # DTB read accesses
718721SN/Asystem.cpu.itb.write_hits                           0                       # DTB write hits
728721SN/Asystem.cpu.itb.write_misses                         0                       # DTB write misses
738721SN/Asystem.cpu.itb.write_acv                            0                       # DTB write access violations
748721SN/Asystem.cpu.itb.write_accesses                       0                       # DTB write accesses
756024SN/Asystem.cpu.itb.data_hits                            0                       # DTB hits
766024SN/Asystem.cpu.itb.data_misses                          0                       # DTB misses
778721SN/Asystem.cpu.itb.data_acv                             0                       # DTB access violations
788721SN/Asystem.cpu.itb.data_accesses                        0                       # DTB accesses
7911530Sandreas.sandberg@arm.comsystem.cpu.numPwrStateTransitions               12714                       # Number of power state transitions
8011530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::samples          6357                       # Distribution of time spent in the clock gated state
8111606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::mean     283043477.146767                       # Distribution of time spent in the clock gated state
8211606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::stdev    441371906.848107                       # Distribution of time spent in the clock gated state
8311530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10         6357    100.00%    100.00% # Distribution of time spent in the clock gated state
8411530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::min_value       386000                       # Distribution of time spent in the clock gated state
8511530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::max_value   2000000000                       # Distribution of time spent in the clock gated state
8611530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::total            6357                       # Distribution of time spent in the clock gated state
8711530Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON     30024619278                       # Cumulative time (in ticks) in various power states
8811606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 1799307384222                       # Cumulative time (in ticks) in various power states
8911606Sandreas.sandberg@arm.comsystem.cpu.numCycles                       3658670365                       # number of cpu cycles simulated
908721SN/Asystem.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
918721SN/Asystem.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
922968SN/Asystem.cpu.kern.inst.arm                            0                       # number of arm instructions executed
938721SN/Asystem.cpu.kern.inst.quiesce                     6357                       # number of quiesce instructions executed
9411336Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei                     211318                       # number of hwrei instructions executed
956291SN/Asystem.cpu.kern.ipl_count::0                    74830     40.99%     40.99% # number of times we switched to this ipl
966291SN/Asystem.cpu.kern.ipl_count::21                     243      0.13%     41.12% # number of times we switched to this ipl
976291SN/Asystem.cpu.kern.ipl_count::22                    1866      1.02%     42.14% # number of times we switched to this ipl
9811336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31                  105622     57.86%    100.00% # number of times we switched to this ipl
9911336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total               182561                       # number of times we switched to this ipl
1006291SN/Asystem.cpu.kern.ipl_good::0                     73463     49.29%     49.29% # number of times we switched to this ipl from a different ipl
1016291SN/Asystem.cpu.kern.ipl_good::21                      243      0.16%     49.46% # number of times we switched to this ipl from a different ipl
1026291SN/Asystem.cpu.kern.ipl_good::22                     1866      1.25%     50.71% # number of times we switched to this ipl from a different ipl
1036291SN/Asystem.cpu.kern.ipl_good::31                    73463     49.29%    100.00% # number of times we switched to this ipl from a different ipl
1046127SN/Asystem.cpu.kern.ipl_good::total                149035                       # number of times we switched to this ipl from a different ipl
10511606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_ticks::0             1811929137500     99.05%     99.05% # number of cycles we spent at this ipl
1066291SN/Asystem.cpu.kern.ipl_ticks::21                20110000      0.00%     99.05% # number of cycles we spent at this ipl
1076291SN/Asystem.cpu.kern.ipl_ticks::22                80238000      0.00%     99.05% # number of cycles we spent at this ipl
10811336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31             17302310500      0.95%    100.00% # number of cycles we spent at this ipl
10911606Sandreas.sandberg@arm.comsystem.cpu.kern.ipl_ticks::total         1829331796000                       # number of cycles we spent at this ipl
1106127SN/Asystem.cpu.kern.ipl_used::0                  0.981732                       # fraction of swpipl calls that actually changed the ipl
1116127SN/Asystem.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
1126127SN/Asystem.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
11311336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31                 0.695527                       # fraction of swpipl calls that actually changed the ipl
11411336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total              0.816357                       # fraction of swpipl calls that actually changed the ipl
1156291SN/Asystem.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
1166291SN/Asystem.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
1176291SN/Asystem.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
1186291SN/Asystem.cpu.kern.syscall::6                         42     12.88%     25.77% # number of syscalls executed
1196291SN/Asystem.cpu.kern.syscall::12                         1      0.31%     26.07% # number of syscalls executed
1206291SN/Asystem.cpu.kern.syscall::15                         1      0.31%     26.38% # number of syscalls executed
1216291SN/Asystem.cpu.kern.syscall::17                        15      4.60%     30.98% # number of syscalls executed
1226291SN/Asystem.cpu.kern.syscall::19                        10      3.07%     34.05% # number of syscalls executed
1236291SN/Asystem.cpu.kern.syscall::20                         6      1.84%     35.89% # number of syscalls executed
1246291SN/Asystem.cpu.kern.syscall::23                         4      1.23%     37.12% # number of syscalls executed
1256291SN/Asystem.cpu.kern.syscall::24                         6      1.84%     38.96% # number of syscalls executed
1266291SN/Asystem.cpu.kern.syscall::33                        11      3.37%     42.33% # number of syscalls executed
1276291SN/Asystem.cpu.kern.syscall::41                         2      0.61%     42.94% # number of syscalls executed
1286291SN/Asystem.cpu.kern.syscall::45                        54     16.56%     59.51% # number of syscalls executed
1296291SN/Asystem.cpu.kern.syscall::47                         6      1.84%     61.35% # number of syscalls executed
1306291SN/Asystem.cpu.kern.syscall::48                        10      3.07%     64.42% # number of syscalls executed
1316291SN/Asystem.cpu.kern.syscall::54                        10      3.07%     67.48% # number of syscalls executed
1326291SN/Asystem.cpu.kern.syscall::58                         1      0.31%     67.79% # number of syscalls executed
1336291SN/Asystem.cpu.kern.syscall::59                         7      2.15%     69.94% # number of syscalls executed
1346291SN/Asystem.cpu.kern.syscall::71                        54     16.56%     86.50% # number of syscalls executed
1356291SN/Asystem.cpu.kern.syscall::73                         3      0.92%     87.42% # number of syscalls executed
1366291SN/Asystem.cpu.kern.syscall::74                        16      4.91%     92.33% # number of syscalls executed
1376291SN/Asystem.cpu.kern.syscall::87                         1      0.31%     92.64% # number of syscalls executed
1386291SN/Asystem.cpu.kern.syscall::90                         3      0.92%     93.56% # number of syscalls executed
1396291SN/Asystem.cpu.kern.syscall::92                         9      2.76%     96.32% # number of syscalls executed
1406291SN/Asystem.cpu.kern.syscall::97                         2      0.61%     96.93% # number of syscalls executed
1416291SN/Asystem.cpu.kern.syscall::98                         2      0.61%     97.55% # number of syscalls executed
1426291SN/Asystem.cpu.kern.syscall::132                        4      1.23%     98.77% # number of syscalls executed
1436291SN/Asystem.cpu.kern.syscall::144                        2      0.61%     99.39% # number of syscalls executed
1446291SN/Asystem.cpu.kern.syscall::147                        2      0.61%    100.00% # number of syscalls executed
1456127SN/Asystem.cpu.kern.syscall::total                    326                       # number of syscalls executed
1468721SN/Asystem.cpu.kern.callpal::cserve                     1      0.00%      0.00% # number of callpals executed
1478721SN/Asystem.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
1488721SN/Asystem.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
1498721SN/Asystem.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
1508721SN/Asystem.cpu.kern.callpal::swpctx                  4177      2.17%      2.18% # number of callpals executed
1518721SN/Asystem.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
1528721SN/Asystem.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
15311336Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl                175248     91.19%     93.40% # number of callpals executed
1548721SN/Asystem.cpu.kern.callpal::rdps                    6771      3.52%     96.92% # number of callpals executed
1558721SN/Asystem.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
1568721SN/Asystem.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
1578721SN/Asystem.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
1588721SN/Asystem.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
1598721SN/Asystem.cpu.kern.callpal::rti                     5203      2.71%     99.64% # number of callpals executed
1608721SN/Asystem.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
1618721SN/Asystem.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
16211336Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total                 192179                       # number of callpals executed
1639797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel              5949                       # number of protection mode switches
16411336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user                1737                       # number of protection mode switches
1659797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
16611336Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel                1908                      
16711336Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user                  1737                      
1688721SN/Asystem.cpu.kern.mode_good::idle                   171                      
16911336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel     0.320726                       # fraction of useful protection mode switches
1708721SN/Asystem.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
1719797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle       0.081545                       # fraction of useful protection mode switches
17211336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total      0.390064                       # fraction of useful protection mode switches
17311336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel        26833316500      1.47%      1.47% # number of ticks spent at the given mode
17411336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user           1465069000      0.08%      1.55% # number of ticks spent at the given mode
17511606Sandreas.sandberg@arm.comsystem.cpu.kern.mode_ticks::idle         1801033409500     98.45%    100.00% # number of ticks spent at the given mode
1768721SN/Asystem.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
17711336Sandreas.hansson@arm.comsystem.cpu.committedInsts                    60038469                       # Number of instructions committed
17811336Sandreas.hansson@arm.comsystem.cpu.committedOps                      60038469                       # Number of ops (including micro ops) committed
17911336Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses              55913692                       # Number of integer alu accesses
18011201Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
18111201Sandreas.hansson@arm.comsystem.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
18211336Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts      7110791                       # number of instructions that are conditional controls
18311336Sandreas.hansson@arm.comsystem.cpu.num_int_insts                     55913692                       # number of integer instructions
18411201Sandreas.hansson@arm.comsystem.cpu.num_fp_insts                        324460                       # number of float instructions
18511336Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads            76954245                       # number of times the integer registers were read
18611336Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes           41740352                       # number of times the integer registers were written
18711201Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
18811201Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
18911336Sandreas.hansson@arm.comsystem.cpu.num_mem_refs                      16115703                       # number of memory refs
19011336Sandreas.hansson@arm.comsystem.cpu.num_load_insts                     9747509                       # Number of load instructions
19111201Sandreas.hansson@arm.comsystem.cpu.num_store_insts                    6368194                       # Number of store instructions
19211606Sandreas.sandberg@arm.comsystem.cpu.num_idle_cycles               3598621022.088898                       # Number of idle cycles
19311606Sandreas.sandberg@arm.comsystem.cpu.num_busy_cycles               60049342.911102                       # Number of busy cycles
19411201Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction                 0.016413                       # Percentage of non-idle cycles
19511201Sandreas.hansson@arm.comsystem.cpu.idle_fraction                     0.983587                       # Percentage of idle cycles
19611336Sandreas.hansson@arm.comsystem.cpu.Branches                           9064428                       # Number of branches fetched
19711336Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass               3199100      5.33%      5.33% # Class of executed instruction
19811336Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu                  39448406     65.69%     71.02% # Class of executed instruction
19911201Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult                    60677      0.10%     71.12% # Class of executed instruction
20011201Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv                         0      0.00%     71.12% # Class of executed instruction
20111201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd                   38087      0.06%     71.18% # Class of executed instruction
20211201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp                       0      0.00%     71.18% # Class of executed instruction
20311201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt                       0      0.00%     71.18% # Class of executed instruction
20411201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult                      0      0.00%     71.18% # Class of executed instruction
20511201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv                    3636      0.01%     71.19% # Class of executed instruction
20611201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt                      0      0.00%     71.19% # Class of executed instruction
20711201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd                        0      0.00%     71.19% # Class of executed instruction
20811201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc                     0      0.00%     71.19% # Class of executed instruction
20911201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu                        0      0.00%     71.19% # Class of executed instruction
21011201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp                        0      0.00%     71.19% # Class of executed instruction
21111201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt                        0      0.00%     71.19% # Class of executed instruction
21211201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc                       0      0.00%     71.19% # Class of executed instruction
21311201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult                       0      0.00%     71.19% # Class of executed instruction
21411201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc                    0      0.00%     71.19% # Class of executed instruction
21511201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift                      0      0.00%     71.19% # Class of executed instruction
21611201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc                   0      0.00%     71.19% # Class of executed instruction
21711201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt                       0      0.00%     71.19% # Class of executed instruction
21811201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd                   0      0.00%     71.19% # Class of executed instruction
21911201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu                   0      0.00%     71.19% # Class of executed instruction
22011201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp                   0      0.00%     71.19% # Class of executed instruction
22111201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt                   0      0.00%     71.19% # Class of executed instruction
22211201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv                   0      0.00%     71.19% # Class of executed instruction
22311201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc                  0      0.00%     71.19% # Class of executed instruction
22411201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult                  0      0.00%     71.19% # Class of executed instruction
22511201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc               0      0.00%     71.19% # Class of executed instruction
22611201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt                  0      0.00%     71.19% # Class of executed instruction
22711336Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead                  9975077     16.61%     87.80% # Class of executed instruction
22811201Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite                 6374115     10.61%     98.42% # Class of executed instruction
22911336Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess                 951209      1.58%    100.00% # Class of executed instruction
23011201Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
23111336Sandreas.hansson@arm.comsystem.cpu.op_class::total                   60050307                       # Class of executed instruction
23211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
23311336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements           2042707                       # number of replacements
23410585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse           511.997802                       # Cycle average of tags in use
23511336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs            14038420                       # Total number of references to valid blocks.
23611336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs           2043219                       # Sample count of references to valid blocks.
23711336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs              6.870737                       # Average number of references to valid blocks.
23810585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle          10840000                       # Cycle when the warmup percentage was hit.
23910585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
24010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
24110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
24210585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
24310585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0          443                       # Occupied blocks per task id
24410585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1           66                       # Occupied blocks per task id
24510585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
24610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
24711336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses          66369780                       # Number of tag accesses
24811336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses         66369780                       # Number of data accesses
24911606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
25011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data      7807772                       # number of ReadReq hits
25111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::total         7807772                       # number of ReadReq hits
25211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data      5848209                       # number of WriteReq hits
25311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::total        5848209                       # number of WriteReq hits
25411336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
25511336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
25610585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
25710585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
25811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data      13655981                       # number of demand (read+write) hits
25911336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total         13655981                       # number of demand (read+write) hits
26011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data     13655981                       # number of overall hits
26111336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total        13655981                       # number of overall hits
26211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data      1721711                       # number of ReadReq misses
26311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_misses::total       1721711                       # number of ReadReq misses
26411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data       304363                       # number of WriteReq misses
26511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::total       304363                       # number of WriteReq misses
26611336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
26711336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
26811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data      2026074                       # number of demand (read+write) misses
26911336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total        2026074                       # number of demand (read+write) misses
27011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data      2026074                       # number of overall misses
27111336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total       2026074                       # number of overall misses
27211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data      9529483                       # number of ReadReq accesses(hits+misses)
27311336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total      9529483                       # number of ReadReq accesses(hits+misses)
27410585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data      6152572                       # number of WriteReq accesses(hits+misses)
27510585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total      6152572                       # number of WriteReq accesses(hits+misses)
27610585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
27710585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
27810585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
27910585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
28011336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data     15682055                       # number of demand (read+write) accesses
28111336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total     15682055                       # number of demand (read+write) accesses
28211336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data     15682055                       # number of overall (read+write) accesses
28311336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total     15682055                       # number of overall (read+write) accesses
28411336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180672                       # miss rate for ReadReq accesses
28511336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total     0.180672                       # miss rate for ReadReq accesses
28611336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
28711336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total     0.049469                       # miss rate for WriteReq accesses
28811336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
28911336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total     0.085680                       # miss rate for LoadLockedReq accesses
29011336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data     0.129197                       # miss rate for demand accesses
29111336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total     0.129197                       # miss rate for demand accesses
29211336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data     0.129197                       # miss rate for overall accesses
29311336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total     0.129197                       # miss rate for overall accesses
29410585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
29510585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
29610585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
29710585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
29810585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
29910585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
30011606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::writebacks       833476                       # number of writebacks
30111606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::total            833476                       # number of writebacks
30211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
30311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.replacements            919606                       # number of replacements
30411336Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse           511.215257                       # Cycle average of tags in use
30511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.total_refs            59130074                       # Total number of references to valid blocks.
30611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.sampled_refs            920118                       # Sample count of references to valid blocks.
30711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.avg_refs             64.263577                       # Average number of references to valid blocks.
30810585Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle        9686452000                       # Cycle when the warmup percentage was hit.
30911336Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst   511.215257                       # Average occupied blocks per requestor
31010585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst     0.998467                       # Average percentage of cache occupancy
31110585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total     0.998467                       # Average percentage of cache occupancy
31210585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
31310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
31410585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1          117                       # Occupied blocks per task id
31510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2          332                       # Occupied blocks per task id
31610585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
31711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tag_accesses          60970540                       # Number of tag accesses
31811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.data_accesses         60970540                       # Number of data accesses
31911606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
32011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst     59130074                       # number of ReadReq hits
32111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::total        59130074                       # number of ReadReq hits
32211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::cpu.inst      59130074                       # number of demand (read+write) hits
32311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::total         59130074                       # number of demand (read+write) hits
32411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::cpu.inst     59130074                       # number of overall hits
32511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::total        59130074                       # number of overall hits
32611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst       920233                       # number of ReadReq misses
32711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::total        920233                       # number of ReadReq misses
32811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::cpu.inst       920233                       # number of demand (read+write) misses
32911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::total         920233                       # number of demand (read+write) misses
33011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::cpu.inst       920233                       # number of overall misses
33111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::total        920233                       # number of overall misses
33211336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst     60050307                       # number of ReadReq accesses(hits+misses)
33311336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total     60050307                       # number of ReadReq accesses(hits+misses)
33411336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst     60050307                       # number of demand (read+write) accesses
33511336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total     60050307                       # number of demand (read+write) accesses
33611336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst     60050307                       # number of overall (read+write) accesses
33711336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total     60050307                       # number of overall (read+write) accesses
33810585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
33910585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total     0.015324                       # miss rate for ReadReq accesses
34010585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
34110585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total     0.015324                       # miss rate for demand accesses
34210585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst     0.015324                       # miss rate for overall accesses
34310585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total     0.015324                       # miss rate for overall accesses
34410585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
34510585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
34610585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
34710585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
34810585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
34910585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
35011606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::writebacks       919606                       # number of writebacks
35111606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::total            919606                       # number of writebacks
35211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
35311336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements           992419                       # number of replacements
35411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse        65520.104765                       # Cycle average of tags in use
35511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.total_refs            4865571                       # Total number of references to valid blocks.
35611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs          1057941                       # Sample count of references to valid blocks.
35711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs             4.599095                       # Average number of references to valid blocks.
35810585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle        614754000                       # Cycle when the warmup percentage was hit.
35911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks   264.552906                       # Average occupied blocks per requestor
36011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst  4852.732213                       # Average occupied blocks per requestor
36111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819646                       # Average occupied blocks per requestor
36211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks     0.004037                       # Average percentage of cache occupancy
36311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst     0.074047                       # Average percentage of cache occupancy
36411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data     0.921674                       # Average percentage of cache occupancy
36511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total     0.999757                       # Average percentage of cache occupancy
36611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024        65522                       # Occupied blocks per task id
36711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0          168                       # Occupied blocks per task id
36811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1          606                       # Occupied blocks per task id
36911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2         3042                       # Occupied blocks per task id
37011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3         6629                       # Occupied blocks per task id
37111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4        55077                       # Occupied blocks per task id
37211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024     0.999786                       # Percentage of cache occupancy per task id
37311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tag_accesses         48449706                       # Number of tag accesses
37411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.data_accesses        48449706                       # Number of data accesses
37511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
37611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks       833476                       # number of WritebackDirty hits
37711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total       833476                       # number of WritebackDirty hits
37811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks       919354                       # number of WritebackClean hits
37911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::total       919354                       # number of WritebackClean hits
38011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data           12                       # number of UpgradeReq hits
38111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total           12                       # number of UpgradeReq hits
38211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data       187293                       # number of ReadExReq hits
38311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::total       187293                       # number of ReadExReq hits
38411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst       906926                       # number of ReadCleanReq hits
38511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total       906926                       # number of ReadCleanReq hits
38611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data       811229                       # number of ReadSharedReq hits
38711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total       811229                       # number of ReadSharedReq hits
38811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst       906926                       # number of demand (read+write) hits
38911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.data       998522                       # number of demand (read+write) hits
39011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::total         1905448                       # number of demand (read+write) hits
39111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst       906926                       # number of overall hits
39211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.data       998522                       # number of overall hits
39311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::total        1905448                       # number of overall hits
39411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data            4                       # number of UpgradeReq misses
39511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total            4                       # number of UpgradeReq misses
39611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data       117054                       # number of ReadExReq misses
39711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::total       117054                       # number of ReadExReq misses
39811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst        13289                       # number of ReadCleanReq misses
39911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total        13289                       # number of ReadCleanReq misses
40011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data       927644                       # number of ReadSharedReq misses
40111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total       927644                       # number of ReadSharedReq misses
40211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst        13289                       # number of demand (read+write) misses
40311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.data      1044698                       # number of demand (read+write) misses
40411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::total       1057987                       # number of demand (read+write) misses
40511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst        13289                       # number of overall misses
40611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.data      1044698                       # number of overall misses
40711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::total      1057987                       # number of overall misses
40811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks       833476                       # number of WritebackDirty accesses(hits+misses)
40911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total       833476                       # number of WritebackDirty accesses(hits+misses)
41011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks       919354                       # number of WritebackClean accesses(hits+misses)
41111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total       919354                       # number of WritebackClean accesses(hits+misses)
41210585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data           16                       # number of UpgradeReq accesses(hits+misses)
41310585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total           16                       # number of UpgradeReq accesses(hits+misses)
41411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data       304347                       # number of ReadExReq accesses(hits+misses)
41511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total       304347                       # number of ReadExReq accesses(hits+misses)
41611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       920215                       # number of ReadCleanReq accesses(hits+misses)
41711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total       920215                       # number of ReadCleanReq accesses(hits+misses)
41811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data      1738873                       # number of ReadSharedReq accesses(hits+misses)
41911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total      1738873                       # number of ReadSharedReq accesses(hits+misses)
42011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst       920215                       # number of demand (read+write) accesses
42111336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data      2043220                       # number of demand (read+write) accesses
42211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::total      2963435                       # number of demand (read+write) accesses
42311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst       920215                       # number of overall (read+write) accesses
42411336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data      2043220                       # number of overall (read+write) accesses
42511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::total      2963435                       # number of overall (read+write) accesses
42611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for UpgradeReq accesses
42711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total     0.250000                       # miss rate for UpgradeReq accesses
42811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.384607                       # miss rate for ReadExReq accesses
42911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total     0.384607                       # miss rate for ReadExReq accesses
43011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.014441                       # miss rate for ReadCleanReq accesses
43111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total     0.014441                       # miss rate for ReadCleanReq accesses
43211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.533474                       # miss rate for ReadSharedReq accesses
43311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total     0.533474                       # miss rate for ReadSharedReq accesses
43411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst     0.014441                       # miss rate for demand accesses
43511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data     0.511300                       # miss rate for demand accesses
43611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::total     0.357014                       # miss rate for demand accesses
43711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst     0.014441                       # miss rate for overall accesses
43811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data     0.511300                       # miss rate for overall accesses
43911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::total     0.357014                       # miss rate for overall accesses
44010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
44110585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
44210585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
44310585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
44410585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
44510585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
44611336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks        74359                       # number of writebacks
44711336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total            74359                       # number of writebacks
44811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests      5925782                       # Total number of requests made to the snoop filter.
44911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests      2962435                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
45011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests         1834                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
45111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops         1449                       # Total number of snoops made to the snoop filter.
45211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops         1449                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
45311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
45411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
45510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq           7184                       # Transaction distribution
45611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp       2666290                       # Transaction distribution
45710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq          9838                       # Transaction distribution
45810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp         9838                       # Transaction distribution
45911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty       833476                       # Transaction distribution
46011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean       919606                       # Transaction distribution
46111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict      1209231                       # Transaction distribution
46210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq           16                       # Transaction distribution
46310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp           16                       # Transaction distribution
46411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq       304347                       # Transaction distribution
46511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp       304347                       # Transaction distribution
46611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq       920233                       # Transaction distribution
46711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq      1738873                       # Transaction distribution
46811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2760072                       # Packet count per connected master and slave (bytes)
46911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      6163223                       # Packet count per connected master and slave (bytes)
47011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count::total           8923295                       # Packet count per connected master and slave (bytes)
47111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side    117749696                       # Cumulative packet size per connected master and slave (bytes)
47211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    184154670                       # Cumulative packet size per connected master and slave (bytes)
47311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size::total          301904366                       # Cumulative packet size per connected master and slave (bytes)
47411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoops                      993364                       # Total snoops (count)
47511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoopTraffic               4774656                       # Total snoop traffic (bytes)
47611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples      6936011                       # Request fanout histogram
47711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean        0.000753                       # Request fanout histogram
47811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev       0.027431                       # Request fanout histogram
47910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
48011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::0            6930788     99.92%     99.92% # Request fanout histogram
48111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::1               5223      0.08%    100.00% # Request fanout histogram
48211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
48310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
48411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
48511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
48611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::total        6936011                       # Request fanout histogram
48710585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
48810585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
48910585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
49010585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages                 298                       # Number of full page size DMA writes.
49110585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes                  2651136                       # Number of bytes transfered via DMA writes.
49210585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs                        395                       # Number of DMA write transactions.
49310585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
49410585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes                         0                       # Number of bytes transfered via DMA reads (not PRD).
49510585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs                           0                       # Number of DMA read transactions (not PRD).
49610585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
49710585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
49810585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
49911606Sandreas.sandberg@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
50010409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq                 7358                       # Transaction distribution
50110409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp                7358                       # Transaction distribution
50210409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq               51390                       # Transaction distribution
50310892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp              51390                       # Transaction distribution
50410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio         5248                       # Packet count per connected master and slave (bytes)
50511245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio         1010                       # Packet count per connected master and slave (bytes)
50610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio           10                       # Packet count per connected master and slave (bytes)
50710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio           10                       # Packet count per connected master and slave (bytes)
50810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio         1076                       # Packet count per connected master and slave (bytes)
50910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio        18012                       # Packet count per connected master and slave (bytes)
51010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio         1904                       # Packet count per connected master and slave (bytes)
51110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio         6672                       # Packet count per connected master and slave (bytes)
51210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio          102                       # Packet count per connected master and slave (bytes)
51310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total        34044                       # Packet count per connected master and slave (bytes)
51410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side        83452                       # Packet count per connected master and slave (bytes)
51510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total        83452                       # Packet count per connected master and slave (bytes)
51610409Sandreas.hansson@arm.comsystem.iobus.pkt_count::total                  117496                       # Packet count per connected master and slave (bytes)
51710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio        20992                       # Cumulative packet size per connected master and slave (bytes)
51811245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio         2733                       # Cumulative packet size per connected master and slave (bytes)
51910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio            5                       # Cumulative packet size per connected master and slave (bytes)
52010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio            5                       # Cumulative packet size per connected master and slave (bytes)
52110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio         1392                       # Cumulative packet size per connected master and slave (bytes)
52210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio         9006                       # Cumulative packet size per connected master and slave (bytes)
52310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio         7596                       # Cumulative packet size per connected master and slave (bytes)
52410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio         4193                       # Cumulative packet size per connected master and slave (bytes)
52510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio          204                       # Cumulative packet size per connected master and slave (bytes)
52610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total        46126                       # Cumulative packet size per connected master and slave (bytes)
52710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side      2661616                       # Cumulative packet size per connected master and slave (bytes)
52810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total      2661616                       # Cumulative packet size per connected master and slave (bytes)
52910409Sandreas.hansson@arm.comsystem.iobus.pkt_size::total                  2707742                       # Cumulative packet size per connected master and slave (bytes)
53011606Sandreas.sandberg@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
53110585Sandreas.hansson@arm.comsystem.iocache.tags.replacements                41686                       # number of replacements
53211336Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse                1.225569                       # Cycle average of tags in use
53310585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
53410585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs                41702                       # Sample count of references to valid blocks.
53510585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
53611606Sandreas.sandberg@arm.comsystem.iocache.tags.warmup_cycle         1685780588017                       # Cycle when the warmup percentage was hit.
53711336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide     1.225569                       # Average occupied blocks per requestor
53810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
53910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
54010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
54110585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
54210585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
54310585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses               375534                       # Number of tag accesses
54410585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses              375534                       # Number of data accesses
54511606Sandreas.sandberg@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
54610585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
54710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
54810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide        41552                       # number of WriteLineReq misses
54910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total        41552                       # number of WriteLineReq misses
55011456Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
55111456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
55211456Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
55311456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total            41726                       # number of overall misses
55410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
55510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
55610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide        41552                       # number of WriteLineReq accesses(hits+misses)
55710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total        41552                       # number of WriteLineReq accesses(hits+misses)
55811456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
55911456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
56011456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
56111456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
56210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
56310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
56410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide            1                       # miss rate for WriteLineReq accesses
56510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
56610585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
56710585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
56810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
56910585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
57010585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
57110585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
57210585Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
57310585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
57410585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
57510585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
57610585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks           41512                       # number of writebacks
57710585Sandreas.hansson@arm.comsystem.iocache.writebacks::total                41512                       # number of writebacks
57811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests       2132776                       # Total number of requests made to the snoop filter.
57911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests      1034179                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
58011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests          408                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
58111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
58211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
58311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
58411606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
58510892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq                7184                       # Transaction distribution
58611201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp             948291                       # Transaction distribution
58710585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq               9838                       # Transaction distribution
58810585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp              9838                       # Transaction distribution
58911336Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty       115871                       # Transaction distribution
59011336Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict           917188                       # Transaction distribution
59111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq              133                       # Transaction distribution
59211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeResp             133                       # Transaction distribution
59311336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq            116925                       # Transaction distribution
59411336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp           116925                       # Transaction distribution
59511201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq        941107                       # Transaction distribution
59610892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq         41552                       # Transaction distribution
59710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp        41552                       # Transaction distribution
59810585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave        34044                       # Packet count per connected master and slave (bytes)
59911606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3107355                       # Packet count per connected master and slave (bytes)
60011606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total      3141399                       # Packet count per connected master and slave (bytes)
60111336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port       125138                       # Packet count per connected master and slave (bytes)
60211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total       125138                       # Packet count per connected master and slave (bytes)
60311606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total                3266537                       # Packet count per connected master and slave (bytes)
60410585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave        46126                       # Cumulative packet size per connected master and slave (bytes)
60511336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     72461888                       # Cumulative packet size per connected master and slave (bytes)
60611336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total     72508014                       # Cumulative packet size per connected master and slave (bytes)
60710892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2667904                       # Cumulative packet size per connected master and slave (bytes)
60810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total      2667904                       # Cumulative packet size per connected master and slave (bytes)
60911336Sandreas.hansson@arm.comsystem.membus.pkt_size::total                75175918                       # Cumulative packet size per connected master and slave (bytes)
61010585Sandreas.hansson@arm.comsystem.membus.snoops                                0                       # Total snoops (count)
61111570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
61211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples           2149798                       # Request fanout histogram
61311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::mean             0.000494                       # Request fanout histogram
61411606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::stdev            0.022210                       # Request fanout histogram
61510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
61611606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0                 2148737     99.95%     99.95% # Request fanout histogram
61711606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::1                    1061      0.05%    100.00% # Request fanout histogram
61810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
61910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
62011606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value               0                       # Request fanout histogram
62110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value               1                       # Request fanout histogram
62211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total             2149798                       # Request fanout histogram
62311606Sandreas.sandberg@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
62411606Sandreas.sandberg@arm.comsystem.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
62511606Sandreas.sandberg@arm.comsystem.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
62611606Sandreas.sandberg@arm.comsystem.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
62711606Sandreas.sandberg@arm.comsystem.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
62810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
62910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
63010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
63110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
63210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
63310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi              nan                       # average number of Swi's coalesced into each post
63410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi                    0                       # total number of Swi written to ISR
63510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
63610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle           nan                       # average number of RxIdle's coalesced into each post
63710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle                 0                       # total number of RxIdle written to ISR
63810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
63910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk             nan                       # average number of RxOk's coalesced into each post
64010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk                   0                       # total number of RxOk written to ISR
64110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
64210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc           nan                       # average number of RxDesc's coalesced into each post
64310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc                 0                       # total number of RxDesc written to ISR
64410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
64510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk             nan                       # average number of TxOk's coalesced into each post
64610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk                   0                       # total number of TxOk written to ISR
64710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
64810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle           nan                       # average number of TxIdle's coalesced into each post
64910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle                 0                       # total number of TxIdle written to ISR
65010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
65110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc           nan                       # average number of TxDesc's coalesced into each post
65210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc                 0                       # total number of TxDesc written to ISR
65310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
65410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn            nan                       # average number of RxOrn's coalesced into each post
65510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn                  0                       # total number of RxOrn written to ISR
65610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
65710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
65810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
65911606Sandreas.sandberg@arm.comsystem.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66011606Sandreas.sandberg@arm.comsystem.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66111606Sandreas.sandberg@arm.comsystem.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66211606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66311606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66411606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66511606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66611606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66711606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66811606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
66911606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67011606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67111606Sandreas.sandberg@arm.comsystem.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67211606Sandreas.sandberg@arm.comsystem.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67311606Sandreas.sandberg@arm.comsystem.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67411606Sandreas.sandberg@arm.comsystem.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67511606Sandreas.sandberg@arm.comsystem.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67611606Sandreas.sandberg@arm.comsystem.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67711606Sandreas.sandberg@arm.comsystem.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67811606Sandreas.sandberg@arm.comsystem.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
67911606Sandreas.sandberg@arm.comsystem.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
68011606Sandreas.sandberg@arm.comsystem.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
68111606Sandreas.sandberg@arm.comsystem.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332003500                       # Cumulative time (in ticks) in various power states
6822968SN/A
6832968SN/A---------- End Simulation Statistics   ----------
684