stats.txt revision 11440
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.829332 # Number of seconds simulated 411336Sandreas.hansson@arm.comsim_ticks 1829331993500 # Number of ticks simulated 511336Sandreas.hansson@arm.comfinal_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711336Sandreas.hansson@arm.comhost_inst_rate 1828258 # Simulator instruction rate (inst/s) 811336Sandreas.hansson@arm.comhost_op_rate 1828257 # Simulator op (including micro ops) rate (op/s) 911336Sandreas.hansson@arm.comhost_tick_rate 55705727715 # Simulator tick rate (ticks/s) 1011336Sandreas.hansson@arm.comhost_mem_usage 331420 # Number of bytes of host memory used 1111336Sandreas.hansson@arm.comhost_seconds 32.84 # Real time elapsed on the host 1211336Sandreas.hansson@arm.comsim_insts 60038469 # Number of instructions simulated 1311336Sandreas.hansson@arm.comsim_ops 60038469 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory 1711336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1911336Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 67686528 # Number of bytes read from this memory 2011201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory 2211336Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory 2311336Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7415744 # Number of bytes written to this memory 2411201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory 2511336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory 2610352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2711336Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory 2811336Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory 2911336Sandreas.hansson@arm.comsystem.physmem.num_writes::total 115871 # Number of write requests responded to by this memory 3011201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) 3111336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 36535234 # Total read bandwidth from this memory (bytes/s) 3210352Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) 3311336Sandreas.hansson@arm.comsystem.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s) 3411201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) 3511201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) 3611336Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s) 3711336Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s) 3811336Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s) 3911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) 4011336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s) 4110585Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) 4211336Sandreas.hansson@arm.comsystem.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s) 4310036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 448721SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 458721SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 468721SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 478721SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 4811336Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9710423 # DTB read hits 498721SN/Asystem.cpu.dtb.read_misses 10329 # DTB read misses 508721SN/Asystem.cpu.dtb.read_acv 210 # DTB read access violations 518721SN/Asystem.cpu.dtb.read_accesses 728856 # DTB read accesses 5210409Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6352496 # DTB write hits 538721SN/Asystem.cpu.dtb.write_misses 1142 # DTB write misses 548721SN/Asystem.cpu.dtb.write_acv 157 # DTB write access violations 558721SN/Asystem.cpu.dtb.write_accesses 291931 # DTB write accesses 5611336Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16062919 # DTB hits 576024SN/Asystem.cpu.dtb.data_misses 11471 # DTB misses 588721SN/Asystem.cpu.dtb.data_acv 367 # DTB access violations 598721SN/Asystem.cpu.dtb.data_accesses 1020787 # DTB accesses 6011336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 4974637 # ITB hits 618721SN/Asystem.cpu.itb.fetch_misses 5006 # ITB misses 628721SN/Asystem.cpu.itb.fetch_acv 184 # ITB acv 6311336Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 4979643 # ITB accesses 648721SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 658721SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 668721SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 678721SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 688721SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 698721SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 708721SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 718721SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 726024SN/Asystem.cpu.itb.data_hits 0 # DTB hits 736024SN/Asystem.cpu.itb.data_misses 0 # DTB misses 748721SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 758721SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 7611336Sandreas.hansson@arm.comsystem.cpu.numCycles 3658670345 # number of cpu cycles simulated 778721SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 788721SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 792968SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 808721SN/Asystem.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 8111336Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed 826291SN/Asystem.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 836291SN/Asystem.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 846291SN/Asystem.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 8511336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl 8611336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl 876291SN/Asystem.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 886291SN/Asystem.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 896291SN/Asystem.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 906291SN/Asystem.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 916127SN/Asystem.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 9211336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl 936291SN/Asystem.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 946291SN/Asystem.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 9511336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl 9611336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl 976127SN/Asystem.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 986127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 996127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 10011336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl 10111336Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl 1026291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1036291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1046291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1056291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1066291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1076291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1086291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1096291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 1106291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 1116291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 1126291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 1136291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 1146291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 1156291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 1166291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 1176291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 1186291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 1196291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 1206291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 1216291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 1226291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 1236291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 1246291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 1256291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 1266291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 1276291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 1286291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 1296291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 1306291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 1316291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 1326127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 1338721SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1348721SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1358721SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1368721SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1378721SN/Asystem.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 1388721SN/Asystem.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 1398721SN/Asystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 14011336Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed 1418721SN/Asystem.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 1428721SN/Asystem.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 1438721SN/Asystem.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 1448721SN/Asystem.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 1458721SN/Asystem.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 1468721SN/Asystem.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 1478721SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1488721SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 14911336Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 192179 # number of callpals executed 1509797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 15111336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1737 # number of protection mode switches 1529797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 15311336Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1908 15411336Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1737 1558721SN/Asystem.cpu.kern.mode_good::idle 171 15611336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches 1578721SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1589797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 15911336Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches 16011336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode 16111336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode 16211336Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode 1638721SN/Asystem.cpu.kern.swap_context 4178 # number of times the context was actually changed 16411336Sandreas.hansson@arm.comsystem.cpu.committedInsts 60038469 # Number of instructions committed 16511336Sandreas.hansson@arm.comsystem.cpu.committedOps 60038469 # Number of ops (including micro ops) committed 16611336Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses 16711201Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 16811201Sandreas.hansson@arm.comsystem.cpu.num_func_calls 1484182 # number of times a function call or return occured 16911336Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls 17011336Sandreas.hansson@arm.comsystem.cpu.num_int_insts 55913692 # number of integer instructions 17111201Sandreas.hansson@arm.comsystem.cpu.num_fp_insts 324460 # number of float instructions 17211336Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 76954245 # number of times the integer registers were read 17311336Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 41740352 # number of times the integer registers were written 17411201Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 17511201Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 17611336Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 16115703 # number of memory refs 17711336Sandreas.hansson@arm.comsystem.cpu.num_load_insts 9747509 # Number of load instructions 17811201Sandreas.hansson@arm.comsystem.cpu.num_store_insts 6368194 # Number of store instructions 17911336Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles 18011336Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles 18111201Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles 18211201Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.983587 # Percentage of idle cycles 18311336Sandreas.hansson@arm.comsystem.cpu.Branches 9064428 # Number of branches fetched 18411336Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction 18511336Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction 18611201Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction 18711201Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction 18811201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction 18911201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction 19011201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction 19111201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction 19211201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction 19311201Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction 19411201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction 19511201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction 19611201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction 19711201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction 19811201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction 19911201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction 20011201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction 20111201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction 20211201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction 20311201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction 20411201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction 20511201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction 20611201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction 20711201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction 20811201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction 20911201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction 21011201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction 21111201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction 21211201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction 21311201Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction 21411336Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction 21511201Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction 21611336Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction 21711201Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 21811336Sandreas.hansson@arm.comsystem.cpu.op_class::total 60050307 # Class of executed instruction 21911336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 2042707 # number of replacements 22010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 22111336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. 22211336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. 22311336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. 22410585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 22510585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 22610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 22710585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 22810585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 22910585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 23010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 23110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 23210585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 23311336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses 23411336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses 23511336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits 23611336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits 23711336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits 23811336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits 23911336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 24011336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 24110585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 24210585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 24311336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits 24411336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits 24511336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits 24611336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 13655981 # number of overall hits 24711336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses 24811336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses 24911336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses 25011336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses 25111336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 25211336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 25311336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses 25411336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses 25511336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses 25611336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 2026074 # number of overall misses 25711336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) 25811336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) 25910585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) 26010585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) 26110585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 26210585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 26310585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 26410585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 26511336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses 26611336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses 26711336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses 26811336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses 26911336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 27011336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 27111336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 27211336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses 27311336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 27411336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses 27511336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 27611336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 27711336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 27811336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 27910585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 28010585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 28110585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 28210585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 28310585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 28410585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 28510585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 28610585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 28711336Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 833475 # number of writebacks 28811336Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 833475 # number of writebacks 28910585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 29011336Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 919603 # number of replacements 29111336Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use 29211336Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. 29311336Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. 29411336Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. 29510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. 29611336Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor 29710585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 29810585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 29910585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 30010585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 30110585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 30210585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id 30310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 30411336Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses 30511336Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 60970537 # Number of data accesses 30611336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits 30711336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits 30811336Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits 30911336Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits 31011336Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits 31111336Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 59130077 # number of overall hits 31211336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses 31311336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses 31411336Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses 31511336Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses 31611336Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses 31711336Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 920230 # number of overall misses 31811336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) 31911336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) 32011336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses 32111336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses 32211336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses 32311336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses 32410585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 32510585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 32610585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 32710585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 32810585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 32910585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 33010585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 33110585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 33210585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 33310585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 33410585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 33510585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 33610585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 33710585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 33811336Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 919603 # number of writebacks 33911336Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 919603 # number of writebacks 34010585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 34111336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 992419 # number of replacements 34211336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use 34311336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks. 34411336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 1057582 # Sample count of references to valid blocks. 34511336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 4.311847 # Average number of references to valid blocks. 34610585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 34711336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 56331.541205 # Average occupied blocks per requestor 34811336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.327000 # Average occupied blocks per requestor 34911336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 4249.506195 # Average occupied blocks per requestor 35011201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy 35111201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy 35211201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy 35310585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy 35410585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 35510585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id 35610585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id 35710585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id 35811336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 3046 # Occupied blocks per task id 35911336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 54052 # Occupied blocks per task id 36010585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 36111336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 48753652 # Number of tag accesses 36211336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 48753652 # Number of data accesses 36311336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 833475 # number of WritebackDirty hits 36411336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 833475 # number of WritebackDirty hits 36511336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 919351 # number of WritebackClean hits 36611336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 919351 # number of WritebackClean hits 36710585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 36810585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 36911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 187286 # number of ReadExReq hits 37011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 187286 # number of ReadExReq hits 37111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906923 # number of ReadCleanReq hits 37211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 906923 # number of ReadCleanReq hits 37311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits 37411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits 37511336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 906923 # number of demand (read+write) hits 37611336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 998516 # number of demand (read+write) hits 37711336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1905439 # number of demand (read+write) hits 37811336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 906923 # number of overall hits 37911336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 998516 # number of overall hits 38011336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1905439 # number of overall hits 38110585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 38210585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 38311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 117060 # number of ReadExReq misses 38411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 117060 # number of ReadExReq misses 38511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses 38611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses 38711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses 38811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses 38911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses 39011336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1044704 # number of demand (read+write) misses 39111336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1057993 # number of demand (read+write) misses 39211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses 39311336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1044704 # number of overall misses 39411336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1057993 # number of overall misses 39511336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 833475 # number of WritebackDirty accesses(hits+misses) 39611336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 833475 # number of WritebackDirty accesses(hits+misses) 39711336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 919351 # number of WritebackClean accesses(hits+misses) 39811336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 919351 # number of WritebackClean accesses(hits+misses) 39910585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 40010585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 40111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) 40211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) 40311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920212 # number of ReadCleanReq accesses(hits+misses) 40411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 920212 # number of ReadCleanReq accesses(hits+misses) 40511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses) 40611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses) 40711336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses 40811336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses 40911336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses 41011336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses 41111336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses 41211336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses 41310585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 41410585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses 41511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384628 # miss rate for ReadExReq accesses 41611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.384628 # miss rate for ReadExReq accesses 41711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses 41811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses 41911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses 42011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses 42111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses 42211336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.511303 # miss rate for demand accesses 42311336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.357016 # miss rate for demand accesses 42411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses 42511336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.511303 # miss rate for overall accesses 42611336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.357016 # miss rate for overall accesses 42710585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 42810585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 42910585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 43010585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 43110585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 43210585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 43310585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 43410585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 43511336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks 43611336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 74359 # number of writebacks 43710585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 43811336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter. 43911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data. 44011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 44111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. 44211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 44311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 44410892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution 44511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution 44610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution 44710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution 44811336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 833475 # Transaction distribution 44911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 919603 # Transaction distribution 45011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution 45110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution 45210585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution 45311336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution 45411336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution 45511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 920230 # Transaction distribution 45611336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution 45711336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760063 # Packet count per connected master and slave (bytes) 45811336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes) 45911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 8923286 # Packet count per connected master and slave (bytes) 46011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749312 # Cumulative packet size per connected master and slave (bytes) 46111336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154606 # Cumulative packet size per connected master and slave (bytes) 46211336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 301903918 # Cumulative packet size per connected master and slave (bytes) 46311336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 1075988 # Total snoops (count) 46411336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 7018629 # Request fanout histogram 46511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram 46611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram 46710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 46811336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 7013406 99.93% 99.93% # Request fanout histogram 46911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram 47011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 47110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 47211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 47311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 47411336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 7018629 # Request fanout histogram 47510585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 47610585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 47710585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 47810585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 47910585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 48010585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 48110585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 48210585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 48310585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 48410585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 48510585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 48610585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 48710409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7358 # Transaction distribution 48810409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7358 # Transaction distribution 48910409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51390 # Transaction distribution 49010892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51390 # Transaction distribution 49110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) 49211245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) 49310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 49410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 49510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 49610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) 49710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 49810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 49910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 50010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) 50110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 50210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 50310409Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) 50410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) 50511245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) 50610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 50710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 50810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 50910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) 51010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 51110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 51210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 51310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) 51410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 51510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 51610409Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) 51710585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41686 # number of replacements 51811336Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use 51910585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 52010585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 52110585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 52210585Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. 52311336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor 52410585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 52510585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 52610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 52710585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 52810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 52910585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375534 # Number of tag accesses 53010585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375534 # Number of data accesses 53110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 53210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 174 # number of ReadReq misses 53310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 53410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 53510585Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses 53610585Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 174 # number of demand (read+write) misses 53710585Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 174 # number of overall misses 53810585Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 174 # number of overall misses 53910585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 54010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 54110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 54210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 54310585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses 54410585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 174 # number of demand (read+write) accesses 54510585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses 54610585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 174 # number of overall (read+write) accesses 54710585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 54810585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 54910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 55010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 55110585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 55210585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 55310585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 55410585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 55510585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55610585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55710585Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 55810585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 55910585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 56010585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 56110585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 56210585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 56310585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 56410585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41512 # number of writebacks 56510585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 56610892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 7184 # Transaction distribution 56711201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 948291 # Transaction distribution 56810585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9838 # Transaction distribution 56910585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9838 # Transaction distribution 57011336Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 115871 # Transaction distribution 57111336Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 917188 # Transaction distribution 57211201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 147 # Transaction distribution 57311201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 147 # Transaction distribution 57411336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 116925 # Transaction distribution 57511336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 116925 # Transaction distribution 57611201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution 57710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 57810892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 57910585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) 58011336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107383 # Packet count per connected master and slave (bytes) 58111336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141427 # Packet count per connected master and slave (bytes) 58211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) 58311336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) 58411336Sandreas.hansson@arm.comsystem.membus.pkt_count::total 3266565 # Packet count per connected master and slave (bytes) 58510585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) 58611336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes) 58711336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes) 58810892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) 58910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) 59011336Sandreas.hansson@arm.comsystem.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes) 59110585Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 59211336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2149812 # Request fanout histogram 59310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 59410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 59510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 59610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 59711336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 2149812 100.00% 100.00% # Request fanout histogram 59810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 59910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 60010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 60110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 60211336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2149812 # Request fanout histogram 60310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 60410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 60510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 60610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 60710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 60810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 60910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 61010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 61110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 61210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 61310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 61410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 61510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 61610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 61710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 61810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 61910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 62010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 62110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 62210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 62310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 62410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 62510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 62610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 62710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 62810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 62910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 63010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 63110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 63210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 63310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 6342968SN/A 6352968SN/A---------- End Simulation Statistics ---------- 636