stats.txt revision 11103
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.829332 # Number of seconds simulated 410585Sandreas.hansson@arm.comsim_ticks 1829332273500 # Number of ticks simulated 510585Sandreas.hansson@arm.comfinal_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710892Sandreas.hansson@arm.comhost_inst_rate 2495393 # Simulator instruction rate (inst/s) 810892Sandreas.hansson@arm.comhost_op_rate 2495392 # Simulator op (including micro ops) rate (op/s) 910892Sandreas.hansson@arm.comhost_tick_rate 76033049021 # Simulator tick rate (ticks/s) 1010892Sandreas.hansson@arm.comhost_mem_usage 371696 # Number of bytes of host memory used 1110892Sandreas.hansson@arm.comhost_seconds 24.06 # Real time elapsed on the host 1210585Sandreas.hansson@arm.comsim_insts 60038341 # Number of instructions simulated 1310585Sandreas.hansson@arm.comsim_ops 60038341 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 856000 # Number of bytes read from this memory 1710892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 66836224 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1910892Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 67693184 # Number of bytes read from this memory 2010892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 856000 # Number of instructions bytes read from this memory 2110892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 856000 # Number of instructions bytes read from this memory 2210892Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7414144 # Number of bytes written to this memory 2310892Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7414144 # Number of bytes written to this memory 2410892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13375 # Number of read requests responded to by this memory 2510892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1044316 # Number of read requests responded to by this memory 2610352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2710892Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1057706 # Number of read requests responded to by this memory 2810892Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 115846 # Number of write requests responded to by this memory 2910892Sandreas.hansson@arm.comsystem.physmem.num_writes::total 115846 # Number of write requests responded to by this memory 3010892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 467930 # Total read bandwidth from this memory (bytes/s) 3110892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 36535858 # Total read bandwidth from this memory (bytes/s) 3210352Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) 3310892Sandreas.hansson@arm.comsystem.physmem.bw_read::total 37004313 # Total read bandwidth from this memory (bytes/s) 3410892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 467930 # Instruction read bandwidth from this memory (bytes/s) 3510892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 467930 # Instruction read bandwidth from this memory (bytes/s) 3610892Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4052924 # Write bandwidth from this memory (bytes/s) 3710892Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4052924 # Write bandwidth from this memory (bytes/s) 3810892Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4052924 # Total bandwidth to/from this memory (bytes/s) 3910892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 467930 # Total bandwidth to/from this memory (bytes/s) 4010892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 36535858 # Total bandwidth to/from this memory (bytes/s) 4110585Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) 4210892Sandreas.hansson@arm.comsystem.physmem.bw_total::total 41057237 # Total bandwidth to/from this memory (bytes/s) 4310036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 448721SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 458721SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 468721SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 478721SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 4810585Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9710422 # DTB read hits 498721SN/Asystem.cpu.dtb.read_misses 10329 # DTB read misses 508721SN/Asystem.cpu.dtb.read_acv 210 # DTB read access violations 518721SN/Asystem.cpu.dtb.read_accesses 728856 # DTB read accesses 5210409Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6352496 # DTB write hits 538721SN/Asystem.cpu.dtb.write_misses 1142 # DTB write misses 548721SN/Asystem.cpu.dtb.write_acv 157 # DTB write access violations 558721SN/Asystem.cpu.dtb.write_accesses 291931 # DTB write accesses 5610585Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16062918 # DTB hits 576024SN/Asystem.cpu.dtb.data_misses 11471 # DTB misses 588721SN/Asystem.cpu.dtb.data_acv 367 # DTB access violations 598721SN/Asystem.cpu.dtb.data_accesses 1020787 # DTB accesses 6010585Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 4974648 # ITB hits 618721SN/Asystem.cpu.itb.fetch_misses 5006 # ITB misses 628721SN/Asystem.cpu.itb.fetch_acv 184 # ITB acv 6310585Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 4979654 # ITB accesses 648721SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 658721SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 668721SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 678721SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 688721SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 698721SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 708721SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 718721SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 726024SN/Asystem.cpu.itb.data_hits 0 # DTB hits 736024SN/Asystem.cpu.itb.data_misses 0 # DTB misses 748721SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 758721SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 7610585Sandreas.hansson@arm.comsystem.cpu.numCycles 3658670905 # number of cpu cycles simulated 778721SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 788721SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 7910585Sandreas.hansson@arm.comsystem.cpu.committedInsts 60038341 # Number of instructions committed 8010585Sandreas.hansson@arm.comsystem.cpu.committedOps 60038341 # Number of ops (including micro ops) committed 8110585Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses 828721SN/Asystem.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 839797Sandreas.hansson@arm.comsystem.cpu.num_func_calls 1484182 # number of times a function call or return occured 8410585Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls 8510585Sandreas.hansson@arm.comsystem.cpu.num_int_insts 55913563 # number of integer instructions 868721SN/Asystem.cpu.num_fp_insts 324460 # number of float instructions 8710585Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 76954014 # number of times the integer registers were read 8810585Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 41740254 # number of times the integer registers were written 898721SN/Asystem.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 908721SN/Asystem.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 9110585Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 16115702 # number of memory refs 9210585Sandreas.hansson@arm.comsystem.cpu.num_load_insts 9747508 # Number of load instructions 9310409Sandreas.hansson@arm.comsystem.cpu.num_store_insts 6368194 # Number of store instructions 9410585Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles 9510585Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles 9610409Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles 9710409Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.983587 # Percentage of idle cycles 9810585Sandreas.hansson@arm.comsystem.cpu.Branches 9064400 # Number of branches fetched 9910585Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction 10010585Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction 10110409Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction 10210352Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction 10310352Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction 10410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction 10510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction 10610220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction 10710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction 10810220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction 10910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction 11010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction 11110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction 11210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction 11310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction 11410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction 11510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction 11610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction 11710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction 11810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction 11910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction 12010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction 12110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction 12210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction 12310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction 12410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction 12510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction 12610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction 12710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction 12810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction 12910585Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction 13010409Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction 13110585Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction 13210220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 13310585Sandreas.hansson@arm.comsystem.cpu.op_class::total 60050179 # Class of executed instruction 1342968SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 1358721SN/Asystem.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 13610585Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed 1376291SN/Asystem.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 1386291SN/Asystem.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 1396291SN/Asystem.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 14010585Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl 14110585Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl 1426291SN/Asystem.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 1436291SN/Asystem.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 1446291SN/Asystem.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 1456291SN/Asystem.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 1466127SN/Asystem.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 14710585Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1811929473000 99.05% 99.05% # number of cycles we spent at this ipl 1486291SN/Asystem.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 1496291SN/Asystem.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 15010585Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 17302245000 0.95% 100.00% # number of cycles we spent at this ipl 15110585Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1829332066000 # number of cycles we spent at this ipl 1526127SN/Asystem.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 1536127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1546127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 15510585Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 15610585Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl 1576291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1586291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1596291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1606291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1616291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1626291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1636291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1646291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 1656291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 1666291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 1676291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 1686291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 1696291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 1706291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 1716291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 1726291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 1736291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 1746291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 1756291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 1766291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 1776291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 1786291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 1796291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 1806291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 1816291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 1826291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 1836291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 1846291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 1856291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 1866291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 1876127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 1888721SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1898721SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1908721SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1918721SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1928721SN/Asystem.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 1938721SN/Asystem.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 1948721SN/Asystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 19510585Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed 1968721SN/Asystem.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 1978721SN/Asystem.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 1988721SN/Asystem.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 1998721SN/Asystem.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 2008721SN/Asystem.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 2018721SN/Asystem.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 2028721SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 2038721SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 20410585Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 192180 # number of callpals executed 2059797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 20610585Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1738 # number of protection mode switches 2079797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 20810585Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1909 20910585Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1738 2108721SN/Asystem.cpu.kern.mode_good::idle 171 21110585Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches 2128721SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 2139797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 21410585Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches 21510585Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # number of ticks spent at the given mode 21610585Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 21710585Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode 2188721SN/Asystem.cpu.kern.swap_context 4178 # number of times the context was actually changed 21910585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 2042728 # number of replacements 22010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 22110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks. 22210585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 2043240 # Sample count of references to valid blocks. 22310585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 6.870655 # Average number of references to valid blocks. 22410585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 22510585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 22610585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 22710585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 22810585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 22910585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 23010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 23110585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 23210585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 23310585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 66369797 # Number of tag accesses 23410585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 66369797 # Number of data accesses 23510585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7807758 # number of ReadReq hits 23610585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7807758 # number of ReadReq hits 23710585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 5848202 # number of WriteReq hits 23810585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 5848202 # number of WriteReq hits 23910585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits 24010585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits 24110585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 24210585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 24310585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 13655960 # number of demand (read+write) hits 24410585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 13655960 # number of demand (read+write) hits 24510585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 13655960 # number of overall hits 24610585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 13655960 # number of overall hits 24710585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1721724 # number of ReadReq misses 24810585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1721724 # number of ReadReq misses 24910585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses 25010585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses 25110585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 17163 # number of LoadLockedReq misses 25210585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 17163 # number of LoadLockedReq misses 25310585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2026094 # number of demand (read+write) misses 25410585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 2026094 # number of demand (read+write) misses 25510585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2026094 # number of overall misses 25610585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 2026094 # number of overall misses 25710585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9529482 # number of ReadReq accesses(hits+misses) 25810585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9529482 # number of ReadReq accesses(hits+misses) 25910585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) 26010585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) 26110585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 26210585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 26310585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 26410585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 26510585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15682054 # number of demand (read+write) accesses 26610585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15682054 # number of demand (read+write) accesses 26710585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15682054 # number of overall (read+write) accesses 26810585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15682054 # number of overall (read+write) accesses 26910585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180673 # miss rate for ReadReq accesses 27010585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.180673 # miss rate for ReadReq accesses 27110585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses 27210585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses 27310585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085685 # miss rate for LoadLockedReq accesses 27410585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.085685 # miss rate for LoadLockedReq accesses 27510585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.129198 # miss rate for demand accesses 27610585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.129198 # miss rate for demand accesses 27710585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.129198 # miss rate for overall accesses 27810585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.129198 # miss rate for overall accesses 27910585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 28010585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 28110585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 28210585Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 28310585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 28410585Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 28510585Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 28610585Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 28710892Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 833493 # number of writebacks 28810892Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 833493 # number of writebacks 28910585Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 29010585Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 919605 # number of replacements 29110585Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use 29210585Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 59129947 # Total number of references to valid blocks. 29310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. 29410585Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 64.263509 # Average number of references to valid blocks. 29510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. 29610585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.215260 # Average occupied blocks per requestor 29710585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 29810585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 29910585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 30010585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 30110585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 30210585Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id 30310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 30410585Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 60970411 # Number of tag accesses 30510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 60970411 # Number of data accesses 30610585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 59129947 # number of ReadReq hits 30710585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 59129947 # number of ReadReq hits 30810585Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 59129947 # number of demand (read+write) hits 30910585Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 59129947 # number of demand (read+write) hits 31010585Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 59129947 # number of overall hits 31110585Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 59129947 # number of overall hits 31210585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses 31310585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses 31410585Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses 31510585Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses 31610585Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses 31710585Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 920232 # number of overall misses 31810585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 60050179 # number of ReadReq accesses(hits+misses) 31910585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 60050179 # number of ReadReq accesses(hits+misses) 32010585Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 60050179 # number of demand (read+write) accesses 32110585Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 60050179 # number of demand (read+write) accesses 32210585Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 60050179 # number of overall (read+write) accesses 32310585Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 60050179 # number of overall (read+write) accesses 32410585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 32510585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 32610585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 32710585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 32810585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 32910585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 33010585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 33110585Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 33210585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 33310585Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 33410585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 33510585Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 33610585Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 33710585Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 33810585Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 33910892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 992219 # number of replacements 34010892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65424.374112 # Cycle average of tags in use 34110892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4561879 # Total number of references to valid blocks. 34210892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 1057382 # Sample count of references to valid blocks. 34310892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 4.314315 # Average number of references to valid blocks. 34410585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 34510892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 56252.896873 # Average occupied blocks per requestor 34610892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 4923.444270 # Average occupied blocks per requestor 34710892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 4248.032969 # Average occupied blocks per requestor 34810892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.858351 # Average percentage of cache occupancy 34910892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.075126 # Average percentage of cache occupancy 35010892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.064820 # Average percentage of cache occupancy 35110585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy 35210585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 35310585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id 35410585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id 35510585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id 35610892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 3053 # Occupied blocks per task id 35710892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 54045 # Occupied blocks per task id 35810585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 35910892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 48768396 # Number of tag accesses 36010892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 48768396 # Number of data accesses 36110892Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 833493 # number of Writeback hits 36210892Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 833493 # number of Writeback hits 36310585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 36410585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 36510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 187288 # number of ReadExReq hits 36610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 187288 # number of ReadExReq hits 36710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906839 # number of ReadCleanReq hits 36810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 906839 # number of ReadCleanReq hits 36910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 811246 # number of ReadSharedReq hits 37010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 811246 # number of ReadSharedReq hits 37110892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 906839 # number of demand (read+write) hits 37210892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 998534 # number of demand (read+write) hits 37310892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1905373 # number of demand (read+write) hits 37410892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 906839 # number of overall hits 37510892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 998534 # number of overall hits 37610892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1905373 # number of overall hits 37710585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 37810585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 37910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 117066 # number of ReadExReq misses 38010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 117066 # number of ReadExReq misses 38110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13375 # number of ReadCleanReq misses 38210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 13375 # number of ReadCleanReq misses 38310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 927641 # number of ReadSharedReq misses 38410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 927641 # number of ReadSharedReq misses 38510892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13375 # number of demand (read+write) misses 38610892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1044707 # number of demand (read+write) misses 38710892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1058082 # number of demand (read+write) misses 38810892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13375 # number of overall misses 38910892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1044707 # number of overall misses 39010892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1058082 # number of overall misses 39110892Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 833493 # number of Writeback accesses(hits+misses) 39210892Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 833493 # number of Writeback accesses(hits+misses) 39310585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 39410585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 39510585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) 39610585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses) 39710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920214 # number of ReadCleanReq accesses(hits+misses) 39810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 920214 # number of ReadCleanReq accesses(hits+misses) 39910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738887 # number of ReadSharedReq accesses(hits+misses) 40010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1738887 # number of ReadSharedReq accesses(hits+misses) 40110585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses 40210585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses 40310585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses 40410585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses 40510585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses 40610585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses 40710585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 40810585Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses 40910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384638 # miss rate for ReadExReq accesses 41010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.384638 # miss rate for ReadExReq accesses 41110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014535 # miss rate for ReadCleanReq accesses 41210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014535 # miss rate for ReadCleanReq accesses 41310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533468 # miss rate for ReadSharedReq accesses 41410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533468 # miss rate for ReadSharedReq accesses 41510892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014535 # miss rate for demand accesses 41610892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.511299 # miss rate for demand accesses 41710892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.357043 # miss rate for demand accesses 41810892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014535 # miss rate for overall accesses 41910892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.511299 # miss rate for overall accesses 42010892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.357043 # miss rate for overall accesses 42110585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 42210585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 42310585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 42410585Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 42510585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 42610585Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 42710585Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 42810585Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 42910892Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 74334 # number of writebacks 43010892Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 74334 # number of writebacks 43110585Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 43210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution 43310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution 43410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution 43510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution 43610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 833493 # Transaction distribution 43710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 2128840 # Transaction distribution 43810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution 43910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution 44010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution 44110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution 44210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 920232 # Transaction distribution 44310892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1738887 # Transaction distribution 44410892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760069 # Packet count per connected master and slave (bytes) 44510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163286 # Packet count per connected master and slave (bytes) 44610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 8923355 # Packet count per connected master and slave (bytes) 44710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) 44810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157102 # Cumulative packet size per connected master and slave (bytes) 44910892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 243051950 # Cumulative packet size per connected master and slave (bytes) 45010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 41883 # Total snoops (count) 45110892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 5984570 # Request fanout histogram 45210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1.006972 # Request fanout histogram 45310892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.083208 # Request fanout histogram 45410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 45610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 5942844 99.30% 99.30% # Request fanout histogram 45710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 41726 0.70% 100.00% # Request fanout histogram 45810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 45910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 46010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 46110892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 5984570 # Request fanout histogram 46210585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 46310585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 46410585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 46510585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 46610585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 46710585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 46810585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 46910585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 47010585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 47110585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 47210585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 47310585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 47410409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7358 # Transaction distribution 47510409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7358 # Transaction distribution 47610409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51390 # Transaction distribution 47710892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51390 # Transaction distribution 47810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) 47910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) 48010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 48110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 48210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 48310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) 48410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 48510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 48610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 48710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 48810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 48910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 49010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) 49110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 49210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 49310409Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) 49410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) 49510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) 49610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 49710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 49810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 49910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) 50010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 50110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 50210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 50310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 50410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 50510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 50610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) 50710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 50810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 50910409Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) 51010585Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41686 # number of replacements 51110585Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.225572 # Cycle average of tags in use 51210585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 51310585Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 51410585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 51510585Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. 51610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.225572 # Average occupied blocks per requestor 51710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 51810585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 51910585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 52010585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 52110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 52210585Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 375534 # Number of tag accesses 52310585Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 375534 # Number of data accesses 52410585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 52510585Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 174 # number of ReadReq misses 52610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 52710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 52810585Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses 52910585Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 174 # number of demand (read+write) misses 53010585Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 174 # number of overall misses 53110585Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 174 # number of overall misses 53210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 53310585Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 53410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 53510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 53610585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses 53710585Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 174 # number of demand (read+write) accesses 53810585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses 53910585Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 174 # number of overall (read+write) accesses 54010585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 54110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 54210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 54310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 54410585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 54510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 54610585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 54710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 54810585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 54910585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55010585Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 55110585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 55210585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55310585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55410585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 55510585Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 55610585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 55710585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 41512 # number of writebacks 55810585Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 55910892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 7184 # Transaction distribution 56010892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 948374 # Transaction distribution 56110585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9838 # Transaction distribution 56210585Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9838 # Transaction distribution 56310892Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 115846 # Transaction distribution 56410892Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 918371 # Transaction distribution 56510585Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 132 # Transaction distribution 56610585Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 132 # Transaction distribution 56710892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 116946 # Transaction distribution 56810892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 116946 # Transaction distribution 56910892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 941190 # Transaction distribution 57010892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 57110892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 41552 # Transaction distribution 57210585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) 57310892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3108719 # Packet count per connected master and slave (bytes) 57410892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 3142763 # Packet count per connected master and slave (bytes) 57510892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) 57610892Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) 57710892Sandreas.hansson@arm.comsystem.membus.pkt_count::total 3267901 # Packet count per connected master and slave (bytes) 57810585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) 57910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72466944 # Cumulative packet size per connected master and slave (bytes) 58010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513070 # Cumulative packet size per connected master and slave (bytes) 58110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) 58210892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) 58310892Sandreas.hansson@arm.comsystem.membus.pkt_size::total 75180974 # Cumulative packet size per connected master and slave (bytes) 58410585Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 58510892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 2151059 # Request fanout histogram 58610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 58710585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 58810585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 58910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 59010892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 2151059 100.00% 100.00% # Request fanout histogram 59110585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 59210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 59310585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 59410585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 59510892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 2151059 # Request fanout histogram 59610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 59710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 59810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 59910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 60010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 60110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 60210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 60310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 60410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 60510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 60610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 60710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 60810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 60910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 61010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 61110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 61210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 61310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 61410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 61510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 61610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 61710585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 61810585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 61910585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 62010585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 62110585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 62210585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 62310585Sandreas.hansson@arm.comsystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 62410585Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 62510585Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 62610585Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 6272968SN/A 6282968SN/A---------- End Simulation Statistics ---------- 629