stats.txt revision 10488
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.829332 # Number of seconds simulated 410409Sandreas.hansson@arm.comsim_ticks 1829331993500 # Number of ticks simulated 510409Sandreas.hansson@arm.comfinal_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710409Sandreas.hansson@arm.comhost_inst_rate 2920462 # Simulator instruction rate (inst/s) 810409Sandreas.hansson@arm.comhost_op_rate 2920460 # Simulator op (including micro ops) rate (op/s) 910409Sandreas.hansson@arm.comhost_tick_rate 88984410684 # Simulator tick rate (ticks/s) 1010409Sandreas.hansson@arm.comhost_mem_usage 366200 # Number of bytes of host memory used 1110409Sandreas.hansson@arm.comhost_seconds 20.56 # Real time elapsed on the host 1210409Sandreas.hansson@arm.comsim_insts 60038469 # Number of instructions simulated 1310409Sandreas.hansson@arm.comsim_ops 60038469 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory 1810352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 1910409Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 67714944 # Number of bytes read from this memory 209797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory 219797Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory 2210409Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory 2310352Sandreas.hansson@arm.comsystem.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 2410409Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7413184 # Number of bytes written to this memory 259797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory 2610409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory 2710352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 2810409Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory 2910409Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory 3010352Sandreas.hansson@arm.comsystem.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 3110409Sandreas.hansson@arm.comsystem.physmem.num_writes::total 115831 # Number of write requests responded to by this memory 329797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) 3310409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s) 3410352Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) 3510409Sandreas.hansson@arm.comsystem.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s) 369797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) 379797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) 3810409Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s) 3910352Sandreas.hansson@arm.comsystem.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s) 4010409Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s) 4110409Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s) 429797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) 4310409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s) 4410352Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s) 4510409Sandreas.hansson@arm.comsystem.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s) 4610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 948404 # Transaction distribution 4710409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 948404 # Transaction distribution 4810409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9838 # Transaction distribution 4910409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9838 # Transaction distribution 5010409Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 74279 # Transaction distribution 5110409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 5210409Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 5310409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 132 # Transaction distribution 5410409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 132 # Transaction distribution 5510409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 116985 # Transaction distribution 5610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 116985 # Transaction distribution 5710409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) 5810409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes) 5910409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes) 6010409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes) 6110409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes) 6210409Sandreas.hansson@arm.comsystem.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes) 6310409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) 6410409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes) 6510409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes) 6610409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes) 6710409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes) 6810409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes) 6910409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 7010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 1174168 # Request fanout histogram 7110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 7210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 7310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 7410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 7510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram 7610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 7710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 7810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 7910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 8010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 1174168 # Request fanout histogram 819885Sstever@gmail.comsystem.iocache.tags.replacements 41686 # number of replacements 8210409Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use 839885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 849885Sstever@gmail.comsystem.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 859885Sstever@gmail.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 8610409Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. 8710409Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor 889885Sstever@gmail.comsystem.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 899885Sstever@gmail.comsystem.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 9010036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 9110036SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 9210036SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 9310036SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 375534 # Number of tag accesses 9410036SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 375534 # Number of data accesses 9510352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 9610352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 978835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 988721SN/Asystem.iocache.ReadReq_misses::total 174 # number of ReadReq misses 9910352Sandreas.hansson@arm.comsystem.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses 10010352Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 174 # number of demand (read+write) misses 10110352Sandreas.hansson@arm.comsystem.iocache.overall_misses::tsunami.ide 174 # number of overall misses 10210352Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 174 # number of overall misses 1038835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 1048721SN/Asystem.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 10510352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 10610352Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 10710352Sandreas.hansson@arm.comsystem.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses 10810352Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 174 # number of demand (read+write) accesses 10910352Sandreas.hansson@arm.comsystem.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses 11010352Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 174 # number of overall (read+write) accesses 1118835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 1129055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1138835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 1149055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1158835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 1169055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1178721SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1188721SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1198721SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1208721SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 1218983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1228983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 12310352Sandreas.hansson@arm.comsystem.iocache.fast_writes 41552 # number of fast writes performed 1248721SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 1258721SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1268721SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1278721SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 1288721SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 1298721SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 1308721SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 1318721SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 1328721SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1338721SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1348721SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1358721SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 1368721SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 1378721SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 13810036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 1398721SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 1408721SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 1418721SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 1428721SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 14310409Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9710423 # DTB read hits 1448721SN/Asystem.cpu.dtb.read_misses 10329 # DTB read misses 1458721SN/Asystem.cpu.dtb.read_acv 210 # DTB read access violations 1468721SN/Asystem.cpu.dtb.read_accesses 728856 # DTB read accesses 14710409Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6352496 # DTB write hits 1488721SN/Asystem.cpu.dtb.write_misses 1142 # DTB write misses 1498721SN/Asystem.cpu.dtb.write_acv 157 # DTB write access violations 1508721SN/Asystem.cpu.dtb.write_accesses 291931 # DTB write accesses 15110409Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16062919 # DTB hits 1526024SN/Asystem.cpu.dtb.data_misses 11471 # DTB misses 1538721SN/Asystem.cpu.dtb.data_acv 367 # DTB access violations 1548721SN/Asystem.cpu.dtb.data_accesses 1020787 # DTB accesses 15510352Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 4974637 # ITB hits 1568721SN/Asystem.cpu.itb.fetch_misses 5006 # ITB misses 1578721SN/Asystem.cpu.itb.fetch_acv 184 # ITB acv 15810352Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 4979643 # ITB accesses 1598721SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 1608721SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 1618721SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 1628721SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 1638721SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 1648721SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 1658721SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 1668721SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 1676024SN/Asystem.cpu.itb.data_hits 0 # DTB hits 1686024SN/Asystem.cpu.itb.data_misses 0 # DTB misses 1698721SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 1708721SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 17110409Sandreas.hansson@arm.comsystem.cpu.numCycles 3658670345 # number of cpu cycles simulated 1728721SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1738721SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 17410409Sandreas.hansson@arm.comsystem.cpu.committedInsts 60038469 # Number of instructions committed 17510409Sandreas.hansson@arm.comsystem.cpu.committedOps 60038469 # Number of ops (including micro ops) committed 17610409Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses 1778721SN/Asystem.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 1789797Sandreas.hansson@arm.comsystem.cpu.num_func_calls 1484182 # number of times a function call or return occured 17910409Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls 18010409Sandreas.hansson@arm.comsystem.cpu.num_int_insts 55913692 # number of integer instructions 1818721SN/Asystem.cpu.num_fp_insts 324460 # number of float instructions 18210409Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 76954245 # number of times the integer registers were read 18310409Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 41740352 # number of times the integer registers were written 1848721SN/Asystem.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 1858721SN/Asystem.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 18610409Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 16115703 # number of memory refs 18710409Sandreas.hansson@arm.comsystem.cpu.num_load_insts 9747509 # Number of load instructions 18810409Sandreas.hansson@arm.comsystem.cpu.num_store_insts 6368194 # Number of store instructions 18910409Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles 19010409Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles 19110409Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles 19210409Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.983587 # Percentage of idle cycles 19310409Sandreas.hansson@arm.comsystem.cpu.Branches 9064428 # Number of branches fetched 19410409Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction 19510409Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction 19610409Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction 19710352Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction 19810352Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction 19910220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction 20010220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction 20110220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction 20210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction 20310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction 20410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction 20510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction 20610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction 20710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction 20810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction 20910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction 21010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction 21110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction 21210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction 21310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction 21410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction 21510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction 21610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction 21710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction 21810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction 21910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction 22010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction 22110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction 22210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction 22310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction 22410409Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction 22510409Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction 22610352Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction 22710220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 22810409Sandreas.hansson@arm.comsystem.cpu.op_class::total 60050307 # Class of executed instruction 2292968SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 2308721SN/Asystem.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 23110352Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed 2326291SN/Asystem.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 2336291SN/Asystem.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 2346291SN/Asystem.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 23510352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl 23610352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl 2376291SN/Asystem.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 2386291SN/Asystem.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 2396291SN/Asystem.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 2406291SN/Asystem.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 2416127SN/Asystem.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl 24210409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl 2436291SN/Asystem.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 2446291SN/Asystem.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 24510409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl 24610409Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl 2476127SN/Asystem.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 2486127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 2496127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 25010352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl 25110352Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl 2526291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 2536291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 2546291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 2556291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 2566291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 2576291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 2586291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 2596291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 2606291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 2616291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 2626291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 2636291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 2646291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 2656291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 2666291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 2676291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 2686291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 2696291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 2706291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 2716291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 2726291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 2736291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 2746291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 2756291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 2766291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 2776291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 2786291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 2796291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 2806291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 2816291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 2826127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 2838721SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 2848721SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 2858721SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 2868721SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 2878721SN/Asystem.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 2888721SN/Asystem.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 2898721SN/Asystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 29010352Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed 2918721SN/Asystem.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 2928721SN/Asystem.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 2938721SN/Asystem.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 2948721SN/Asystem.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 2958721SN/Asystem.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 2968721SN/Asystem.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 2978721SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 2988721SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 29910352Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 192179 # number of callpals executed 3009797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches 30110352Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1737 # number of protection mode switches 3029797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2097 # number of protection mode switches 30310352Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1908 30410352Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1737 3058721SN/Asystem.cpu.kern.mode_good::idle 171 30610352Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches 3078721SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 3089797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 30910352Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches 31010409Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode 31110352Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode 31210409Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode 3138721SN/Asystem.cpu.kern.swap_context 4178 # number of times the context was actually changed 3142968SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3152968SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3162968SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3172968SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3188721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3198983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 3208721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 3218721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3228983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 3238721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3248721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3258983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 3268721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3278721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3288983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 3298721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3308721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3318983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 3328721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3338721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3348983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 3358721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3368721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3378983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 3388721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3398721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3408983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 3418721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3428983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 3438721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 3442968SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 34510409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7358 # Transaction distribution 34610409Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7358 # Transaction distribution 34710409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51390 # Transaction distribution 34810409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 9838 # Transaction distribution 34910409Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 35010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) 35110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) 35210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 35310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 35410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 35510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) 35610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 35710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 35810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 35910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 36010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 36110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 36210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) 36310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 36410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 36510409Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) 36610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) 36710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) 36810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 36910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 37010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 37110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) 37210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 37310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 37410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 37510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 37610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 37710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 37810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) 37910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 38010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 38110409Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) 38210409Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 919603 # number of replacements 38310409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use 38410409Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. 38510409Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. 38610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. 38710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. 38810409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor 3899885Sstever@gmail.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 3909885Sstever@gmail.comsystem.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 39110036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 39210036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 39310036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 39410036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id 39510036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 39610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses 39710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 60970537 # Number of data accesses 39810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits 39910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits 40010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits 40110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits 40210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits 40310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 59130077 # number of overall hits 40410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses 40510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses 40610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses 40710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses 40810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses 40910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 920230 # number of overall misses 41010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) 41110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) 41210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses 41310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses 41410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses 41510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses 4168835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 4179055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 4188835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 4199055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 4208835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 4219055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 4228721SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4238721SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4248721SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 4258721SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 4268983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4278983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4288721SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 4298721SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 4308721SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 43110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 992289 # number of replacements 43210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use 43310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks. 43410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks. 43510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks. 4369885Sstever@gmail.comsystem.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 43710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor 43810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor 43910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor 44010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy 44110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy 4429797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 4439885Sstever@gmail.comsystem.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy 44410036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 44510036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id 44610036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id 44710036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id 44810352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id 44910352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id 45010036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id 45110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses 45210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses 45310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits 45410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits 45510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits 45610409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits 45710409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits 4589289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 4599289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 46010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits 46110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits 46210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits 46310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits 46410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits 46510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits 46610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits 46710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 1905281 # number of overall hits 4689797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses 4699289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 4709797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses 4719289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 4729289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 47310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses 47410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses 4759797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses 47610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses 47710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses 4789797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses 47910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses 48010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 1058151 # number of overall misses 48110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses) 48210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses) 48310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses) 48410409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses) 48510409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses) 4869289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 4879289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 48810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) 48910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) 49010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses 49110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses 49210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses 49310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses 49410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses 49510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses 49610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses 49710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses 49810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses 4999289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 5009289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses 50110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses 50210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses 50310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses 50410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses 50510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses 50610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses 50710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses 50810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses 5099289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5109289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5119289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5129289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5139289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5149289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5159289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5169289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 51710409Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks 51810409Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 74279 # number of writebacks 5199289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 52010409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 2042707 # number of replacements 5219885Sstever@gmail.comsystem.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 52210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. 52310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. 52410409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. 5259885Sstever@gmail.comsystem.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 5269885Sstever@gmail.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 5279885Sstever@gmail.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 5289885Sstever@gmail.comsystem.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 52910036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 53010036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 53110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 53210036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 53310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 53410409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses 53510409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses 53610409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits 53710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits 53810409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits 53910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits 54010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 54110409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 5429797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 5439797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 54410409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits 54510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits 54610409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits 54710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 13655981 # number of overall hits 54810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses 54910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses 55010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses 55110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses 55210409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 55310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 55410409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses 55510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses 55610409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses 55710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 2026074 # number of overall misses 55810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) 55910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) 56010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) 56110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) 5629797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 5639797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 5649797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 5659797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 56610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses 56710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses 56810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses 56910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses 57010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 57110409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 57210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 57310409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses 57410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 57510409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses 57610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 57710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 57810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 57910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 5809481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5819481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5829481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5839481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 5849481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5859481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5869481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 5879481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 58810409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 833484 # number of writebacks 58910409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 833484 # number of writebacks 5909481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 59110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution 59210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution 59310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution 59410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution 59510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution 59610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution 59710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution 59810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution 59910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution 60010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes) 60110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes) 60210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes) 60310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes) 60410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes) 60510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes) 60610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 41883 # Total snoops (count) 60710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram 60810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram 60910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram 61010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 61110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 61210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram 61310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram 61410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 61510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 61610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 61710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram 6182968SN/A 6192968SN/A---------- End Simulation Statistics ---------- 620