stats.txt revision 5520
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 4441196 # Simulator instruction rate (inst/s) 4host_mem_usage 289900 # Number of bytes of host memory used 5host_seconds 14.21 # Real time elapsed on the host 6host_tick_rate 131610473505 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 63113507 # Number of instructions simulated 9sim_seconds 1.870336 # Number of seconds simulated 10sim_ticks 1870335522500 # Number of ticks simulated 11system.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) 12system.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits 13system.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses 14system.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses 15system.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses) 16system.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits 17system.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses 18system.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses 19system.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) 20system.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits 21system.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses 22system.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses 23system.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses) 24system.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits 25system.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses 26system.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses 27system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 28system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 29system.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks. 30system.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 31system.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked 32system.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 33system.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 34system.cpu0.dcache.cache_copies 0 # number of cache copies performed 35system.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses 36system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency 37system.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 38system.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits 39system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 40system.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses 41system.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses 42system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 43system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 44system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 45system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 46system.cpu0.dcache.fast_writes 0 # number of fast writes performed 47system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 48system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 49system.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses 50system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency 51system.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 52system.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 53system.cpu0.dcache.overall_hits 12664298 # number of overall hits 54system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles 55system.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses 56system.cpu0.dcache.overall_misses 2057375 # number of overall misses 57system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 58system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 59system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 60system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses 61system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 62system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 63system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 64system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 65system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 66system.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 67system.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 68system.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 69system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 70system.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 71system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 72system.cpu0.dcache.replacements 1978967 # number of replacements 73system.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks. 74system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 75system.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use 76system.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks. 77system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 78system.cpu0.dcache.writebacks 396793 # number of writebacks 79system.cpu0.dtb.accesses 698037 # DTB accesses 80system.cpu0.dtb.acv 251 # DTB access violations 81system.cpu0.dtb.hits 15082911 # DTB hits 82system.cpu0.dtb.misses 7805 # DTB misses 83system.cpu0.dtb.read_accesses 508987 # DTB read accesses 84system.cpu0.dtb.read_acv 152 # DTB read access violations 85system.cpu0.dtb.read_hits 9148351 # DTB read hits 86system.cpu0.dtb.read_misses 7079 # DTB read misses 87system.cpu0.dtb.write_accesses 189050 # DTB write accesses 88system.cpu0.dtb.write_acv 99 # DTB write access violations 89system.cpu0.dtb.write_hits 5934560 # DTB write hits 90system.cpu0.dtb.write_misses 726 # DTB write misses 91system.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses) 92system.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits 93system.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses 94system.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses 95system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 96system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 97system.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks. 98system.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked 99system.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked 100system.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 101system.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 102system.cpu0.icache.cache_copies 0 # number of cache copies performed 103system.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses 104system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency 105system.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 106system.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits 107system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 108system.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses 109system.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses 110system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 111system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 112system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 113system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 114system.cpu0.icache.fast_writes 0 # number of fast writes performed 115system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 116system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 117system.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses 118system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency 119system.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 120system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 121system.cpu0.icache.overall_hits 56304737 # number of overall hits 122system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles 123system.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses 124system.cpu0.icache.overall_misses 884868 # number of overall misses 125system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 126system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 127system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 128system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses 129system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 130system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 131system.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 132system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 133system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 134system.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 135system.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 136system.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 137system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 138system.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 139system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 140system.cpu0.icache.replacements 884272 # number of replacements 141system.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks. 142system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 143system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use 144system.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks. 145system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 146system.cpu0.icache.writebacks 0 # number of writebacks 147system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles 148system.cpu0.itb.accesses 3858857 # ITB accesses 149system.cpu0.itb.acv 127 # ITB acv 150system.cpu0.itb.hits 3855372 # ITB hits 151system.cpu0.itb.misses 3485 # ITB misses 152system.cpu0.kern.callpal 183274 # number of callpals executed 153system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed 154system.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed 155system.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed 156system.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed 157system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed 158system.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed 159system.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed 160system.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed 161system.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed 162system.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed 163system.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed 164system.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed 165system.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed 166system.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed 167system.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed 168system.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed 169system.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed 170system.cpu0.kern.inst.arm 0 # number of arm instructions executed 171system.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed 172system.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed 173system.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl 174system.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl 175system.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl 176system.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl 177system.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl 178system.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl 179system.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl 180system.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl 181system.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 182system.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 183system.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 184system.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl 185system.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl 186system.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl 187system.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl 188system.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl 189system.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl 190system.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl 191system.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl 192system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl 193system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl 194system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl 195system.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl 196system.cpu0.kern.mode_good_kernel 1157 197system.cpu0.kern.mode_good_user 1158 198system.cpu0.kern.mode_good_idle 0 199system.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches 200system.cpu0.kern.mode_switch_user 1158 # number of protection mode switches 201system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches 202system.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches 203system.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches 204system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches 205system.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches 206system.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 207system.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode 208system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode 209system.cpu0.kern.swap_context 3762 # number of times the context was actually changed 210system.cpu0.kern.syscall 226 # number of syscalls executed 211system.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed 212system.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed 213system.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed 214system.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed 215system.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed 216system.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed 217system.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed 218system.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed 219system.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed 220system.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed 221system.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed 222system.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed 223system.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed 224system.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed 225system.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed 226system.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed 227system.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed 228system.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed 229system.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed 230system.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed 231system.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed 232system.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed 233system.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed 234system.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed 235system.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed 236system.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed 237system.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed 238system.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed 239system.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed 240system.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed 241system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles 242system.cpu0.numCycles 3740670933 # number of cpu cycles simulated 243system.cpu0.num_insts 57181549 # Number of instructions executed 244system.cpu0.num_refs 15322361 # Number of memory references 245system.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) 246system.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits 247system.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses 248system.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses 249system.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses) 250system.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits 251system.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses 252system.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses 253system.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses) 254system.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits 255system.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses 256system.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses 257system.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) 258system.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits 259system.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses 260system.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses 261system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 262system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 263system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. 264system.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 265system.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked 266system.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 267system.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 268system.cpu1.dcache.cache_copies 0 # number of cache copies performed 269system.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses 270system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency 271system.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 272system.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits 273system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 274system.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses 275system.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses 276system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 277system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 278system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 279system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 280system.cpu1.dcache.fast_writes 0 # number of fast writes performed 281system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 282system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 283system.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses 284system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency 285system.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 286system.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 287system.cpu1.dcache.overall_hits 1812118 # number of overall hits 288system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles 289system.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses 290system.cpu1.dcache.overall_misses 72152 # number of overall misses 291system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 292system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 293system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 294system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses 295system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 296system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 297system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 298system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 299system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 300system.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 301system.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 302system.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 303system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 304system.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 305system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 306system.cpu1.dcache.replacements 62338 # number of replacements 307system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. 308system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 309system.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use 310system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. 311system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. 312system.cpu1.dcache.writebacks 30848 # number of writebacks 313system.cpu1.dtb.accesses 323622 # DTB accesses 314system.cpu1.dtb.acv 116 # DTB access violations 315system.cpu1.dtb.hits 1914885 # DTB hits 316system.cpu1.dtb.misses 3692 # DTB misses 317system.cpu1.dtb.read_accesses 220342 # DTB read accesses 318system.cpu1.dtb.read_acv 58 # DTB read access violations 319system.cpu1.dtb.read_hits 1163439 # DTB read hits 320system.cpu1.dtb.read_misses 3277 # DTB read misses 321system.cpu1.dtb.write_accesses 103280 # DTB write accesses 322system.cpu1.dtb.write_acv 58 # DTB write access violations 323system.cpu1.dtb.write_hits 751446 # DTB write hits 324system.cpu1.dtb.write_misses 415 # DTB write misses 325system.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) 326system.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits 327system.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses 328system.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses 329system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 330system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 331system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. 332system.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked 333system.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked 334system.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 335system.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 336system.cpu1.icache.cache_copies 0 # number of cache copies performed 337system.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses 338system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency 339system.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 340system.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits 341system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 342system.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses 343system.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses 344system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 345system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 346system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 347system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 348system.cpu1.icache.fast_writes 0 # number of fast writes performed 349system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 350system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 351system.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses 352system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency 353system.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 354system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 355system.cpu1.icache.overall_hits 5832136 # number of overall hits 356system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles 357system.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses 358system.cpu1.icache.overall_misses 103630 # number of overall misses 359system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 360system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 361system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 362system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses 363system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 364system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 365system.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 366system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 367system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 368system.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 369system.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 370system.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 371system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 372system.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 373system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 374system.cpu1.icache.replacements 103091 # number of replacements 375system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. 376system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 377system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use 378system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. 379system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. 380system.cpu1.icache.writebacks 0 # number of writebacks 381system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 382system.cpu1.itb.accesses 1469938 # ITB accesses 383system.cpu1.itb.acv 57 # ITB acv 384system.cpu1.itb.hits 1468399 # ITB hits 385system.cpu1.itb.misses 1539 # ITB misses 386system.cpu1.kern.callpal 32131 # number of callpals executed 387system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed 388system.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed 389system.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed 390system.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed 391system.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed 392system.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed 393system.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed 394system.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed 395system.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed 396system.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed 397system.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed 398system.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed 399system.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed 400system.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed 401system.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed 402system.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed 403system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed 404system.cpu1.kern.inst.arm 0 # number of arm instructions executed 405system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 406system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 407system.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl 408system.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl 409system.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl 410system.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl 411system.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl 412system.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl 413system.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 414system.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 415system.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 416system.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 417system.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl 418system.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl 419system.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 420system.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 421system.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 422system.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl 423system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl 424system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl 425system.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl 426system.cpu1.kern.mode_good_kernel 612 427system.cpu1.kern.mode_good_user 580 428system.cpu1.kern.mode_good_idle 32 429system.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches 430system.cpu1.kern.mode_switch_user 580 # number of protection mode switches 431system.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches 432system.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches 433system.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches 434system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches 435system.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches 436system.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode 437system.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode 438system.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode 439system.cpu1.kern.swap_context 471 # number of times the context was actually changed 440system.cpu1.kern.syscall 100 # number of syscalls executed 441system.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed 442system.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed 443system.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed 444system.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed 445system.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed 446system.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed 447system.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed 448system.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed 449system.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed 450system.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed 451system.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed 452system.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed 453system.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed 454system.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed 455system.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed 456system.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed 457system.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed 458system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 459system.cpu1.numCycles 3740248881 # number of cpu cycles simulated 460system.cpu1.num_insts 5931958 # Number of instructions executed 461system.cpu1.num_refs 1926645 # Number of memory references 462system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 463system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 464system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 465system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 466system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 467system.disk0.dma_write_txs 395 # Number of DMA write transactions. 468system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 469system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 470system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 471system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 472system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 473system.disk2.dma_write_txs 1 # Number of DMA write transactions. 474system.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) 475system.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses 476system.iocache.ReadReq_misses 175 # number of ReadReq misses 477system.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) 478system.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses 479system.iocache.WriteReq_misses 41552 # number of WriteReq misses 480system.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 481system.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 482system.iocache.avg_refs 0 # Average number of references to valid blocks. 483system.iocache.blocked_no_mshrs 0 # number of cycles access was blocked 484system.iocache.blocked_no_targets 0 # number of cycles access was blocked 485system.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 486system.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked 487system.iocache.cache_copies 0 # number of cache copies performed 488system.iocache.demand_accesses 41727 # number of demand (read+write) accesses 489system.iocache.demand_avg_miss_latency 0 # average overall miss latency 490system.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 491system.iocache.demand_hits 0 # number of demand (read+write) hits 492system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 493system.iocache.demand_miss_rate 1 # miss rate for demand accesses 494system.iocache.demand_misses 41727 # number of demand (read+write) misses 495system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 496system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 497system.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 498system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 499system.iocache.fast_writes 0 # number of fast writes performed 500system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 501system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 502system.iocache.overall_accesses 41727 # number of overall (read+write) accesses 503system.iocache.overall_avg_miss_latency 0 # average overall miss latency 504system.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 505system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 506system.iocache.overall_hits 0 # number of overall hits 507system.iocache.overall_miss_latency 0 # number of overall miss cycles 508system.iocache.overall_miss_rate 1 # miss rate for overall accesses 509system.iocache.overall_misses 41727 # number of overall misses 510system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 511system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 512system.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 513system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 514system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 515system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 516system.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 517system.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 518system.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 519system.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 520system.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 521system.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 522system.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 523system.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 524system.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 525system.iocache.replacements 41695 # number of replacements 526system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. 527system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 528system.iocache.tagsinuse 0.435437 # Cycle average of tags in use 529system.iocache.total_refs 0 # Total number of references to valid blocks. 530system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 531system.iocache.writebacks 41520 # number of writebacks 532system.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses) 533system.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 534system.l2c.ReadExReq_misses 306244 # number of ReadExReq misses 535system.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses) 536system.l2c.ReadReq_hits 1759609 # number of ReadReq hits 537system.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses 538system.l2c.ReadReq_misses 964534 # number of ReadReq misses 539system.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) 540system.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 541system.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses 542system.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) 543system.l2c.Writeback_hits 427641 # number of Writeback hits 544system.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 545system.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 546system.l2c.avg_refs 1.789118 # Average number of references to valid blocks. 547system.l2c.blocked_no_mshrs 0 # number of cycles access was blocked 548system.l2c.blocked_no_targets 0 # number of cycles access was blocked 549system.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 550system.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked 551system.l2c.cache_copies 0 # number of cache copies performed 552system.l2c.demand_accesses 3030387 # number of demand (read+write) accesses 553system.l2c.demand_avg_miss_latency 0 # average overall miss latency 554system.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 555system.l2c.demand_hits 1759609 # number of demand (read+write) hits 556system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 557system.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses 558system.l2c.demand_misses 1270778 # number of demand (read+write) misses 559system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 560system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 561system.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 562system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 563system.l2c.fast_writes 0 # number of fast writes performed 564system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 565system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 566system.l2c.overall_accesses 3030387 # number of overall (read+write) accesses 567system.l2c.overall_avg_miss_latency 0 # average overall miss latency 568system.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 569system.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 570system.l2c.overall_hits 1759609 # number of overall hits 571system.l2c.overall_miss_latency 0 # number of overall miss cycles 572system.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses 573system.l2c.overall_misses 1270778 # number of overall misses 574system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 575system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 576system.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 577system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 578system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 579system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 580system.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 581system.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 582system.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 583system.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 584system.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified 585system.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued 586system.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 587system.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 588system.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 589system.l2c.replacements 1056800 # number of replacements 590system.l2c.sampled_refs 1091449 # Sample count of references to valid blocks. 591system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 592system.l2c.tagsinuse 30522.432687 # Cycle average of tags in use 593system.l2c.total_refs 1952731 # Total number of references to valid blocks. 594system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. 595system.l2c.writebacks 123878 # number of writebacks 596system.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post 597system.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post 598system.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post 599system.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post 600system.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post 601system.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post 602system.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post 603system.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post 604system.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post 605system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 606system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 607system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 608system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 609system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 610system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 611system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 612system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 613system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 614system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 615system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 616system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 617system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 618system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 619system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 620system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 621system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 622system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 623system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 624system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 625system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 626system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 627 628---------- End Simulation Statistics ---------- 629