stats.txt revision 5520
12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comhost_inst_rate 4441196 # Simulator instruction rate (inst/s) 410409Sandreas.hansson@arm.comhost_mem_usage 289900 # Number of bytes of host memory used 510409Sandreas.hansson@arm.comhost_seconds 14.21 # Real time elapsed on the host 68721SN/Ahost_tick_rate 131610473505 # Simulator tick rate (ticks/s) 710409Sandreas.hansson@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 810409Sandreas.hansson@arm.comsim_insts 63113507 # Number of instructions simulated 910409Sandreas.hansson@arm.comsim_seconds 1.870336 # Number of seconds simulated 1010409Sandreas.hansson@arm.comsim_ticks 1870335522500 # Number of ticks simulated 1110409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses 188283 # number of LoadLockedReq accesses(hits+misses) 1210409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits 172122 # number of LoadLockedReq hits 1310409Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate 0.085834 # miss rate for LoadLockedReq accesses 1410036SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_misses 16161 # number of LoadLockedReq misses 1510036SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_accesses 8975619 # number of ReadReq accesses(hits+misses) 169797Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits 7292050 # number of ReadReq hits 1710409Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate 0.187571 # miss rate for ReadReq accesses 1810352Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses 1683569 # number of ReadReq misses 1910409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses 187323 # number of StoreCondReq accesses(hits+misses) 209797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits 159821 # number of StoreCondReq hits 219797Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate 0.146816 # miss rate for StoreCondReq accesses 2210409Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses 27502 # number of StoreCondReq misses 2310352Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses 5746054 # number of WriteReq accesses(hits+misses) 2410409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits 5372248 # number of WriteReq hits 259797Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate 0.065054 # miss rate for WriteReq accesses 2610409Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses 373806 # number of WriteReq misses 2710352Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 2810409Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 2910409Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_refs 6.625587 # Average number of references to valid blocks. 3010352Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 3110409Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_no_targets 0 # number of cycles access was blocked 329797Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 3310409Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 3410352Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 3510409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses 14721673 # number of demand (read+write) accesses 369797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency 379797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 3810409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits 12664298 # number of demand (read+write) hits 3910352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 4010409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate 0.139751 # miss rate for demand accesses 4110409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses 2057375 # number of demand (read+write) misses 429797Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 4310409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 4410352Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 4510409Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 4610409Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 4710409Sandreas.hansson@arm.comsystem.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 4810409Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4910409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses 14721673 # number of overall (read+write) accesses 5010409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency 5110409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 5210409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 5310409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits 12664298 # number of overall hits 5410409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles 5510409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate 0.139751 # miss rate for overall accesses 5610409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses 2057375 # number of overall misses 5710409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits 5810409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 5910409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 6010409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses 6110409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 6210409Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 6310409Sandreas.hansson@arm.comsystem.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 6410409Sandreas.hansson@arm.comsystem.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 6510409Sandreas.hansson@arm.comsystem.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 6610409Sandreas.hansson@arm.comsystem.cpu0.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 6710409Sandreas.hansson@arm.comsystem.cpu0.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 6810409Sandreas.hansson@arm.comsystem.cpu0.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 6910409Sandreas.hansson@arm.comsystem.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 7010409Sandreas.hansson@arm.comsystem.cpu0.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 7110409Sandreas.hansson@arm.comsystem.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 7210409Sandreas.hansson@arm.comsystem.cpu0.dcache.replacements 1978967 # number of replacements 7310409Sandreas.hansson@arm.comsystem.cpu0.dcache.sampled_refs 1979479 # Sample count of references to valid blocks. 7410409Sandreas.hansson@arm.comsystem.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 7510409Sandreas.hansson@arm.comsystem.cpu0.dcache.tagsinuse 504.827685 # Cycle average of tags in use 7610409Sandreas.hansson@arm.comsystem.cpu0.dcache.total_refs 13115211 # Total number of references to valid blocks. 7710409Sandreas.hansson@arm.comsystem.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 7810409Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks 396793 # number of writebacks 7910409Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 698037 # DTB accesses 8010409Sandreas.hansson@arm.comsystem.cpu0.dtb.acv 251 # DTB access violations 819885Sstever@gmail.comsystem.cpu0.dtb.hits 15082911 # DTB hits 8210409Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7805 # DTB misses 839885Sstever@gmail.comsystem.cpu0.dtb.read_accesses 508987 # DTB read accesses 849885Sstever@gmail.comsystem.cpu0.dtb.read_acv 152 # DTB read access violations 859885Sstever@gmail.comsystem.cpu0.dtb.read_hits 9148351 # DTB read hits 8610409Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 7079 # DTB read misses 8710409Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 189050 # DTB write accesses 889885Sstever@gmail.comsystem.cpu0.dtb.write_acv 99 # DTB write access violations 899885Sstever@gmail.comsystem.cpu0.dtb.write_hits 5934560 # DTB write hits 9010036SAli.Saidi@ARM.comsystem.cpu0.dtb.write_misses 726 # DTB write misses 9110036SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_accesses 57189605 # number of ReadReq accesses(hits+misses) 9210036SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_hits 56304737 # number of ReadReq hits 9310036SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_miss_rate 0.015473 # miss rate for ReadReq accesses 9410036SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_misses 884868 # number of ReadReq misses 9510352Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 9610352Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 978835SAli.Saidi@ARM.comsystem.cpu0.icache.avg_refs 63.636703 # Average number of references to valid blocks. 988721SN/Asystem.cpu0.icache.blocked_no_mshrs 0 # number of cycles access was blocked 9910352Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_no_targets 0 # number of cycles access was blocked 10010352Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 10110352Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 10210352Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 1038835SAli.Saidi@ARM.comsystem.cpu0.icache.demand_accesses 57189605 # number of demand (read+write) accesses 1048721SN/Asystem.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency 10510352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 10610352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits 56304737 # number of demand (read+write) hits 10710352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 10810352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate 0.015473 # miss rate for demand accesses 10910352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses 884868 # number of demand (read+write) misses 11010352Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 1118835SAli.Saidi@ARM.comsystem.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 1129055Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 1138835SAli.Saidi@ARM.comsystem.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 1149055Ssaidi@eecs.umich.edusystem.cpu0.icache.fast_writes 0 # number of fast writes performed 1158835SAli.Saidi@ARM.comsystem.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated 1169055Ssaidi@eecs.umich.edusystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1178721SN/Asystem.cpu0.icache.overall_accesses 57189605 # number of overall (read+write) accesses 1188721SN/Asystem.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency 1198721SN/Asystem.cpu0.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 1208721SN/Asystem.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 1218983Snate@binkert.orgsystem.cpu0.icache.overall_hits 56304737 # number of overall hits 1228983Snate@binkert.orgsystem.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles 12310352Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate 0.015473 # miss rate for overall accesses 1248721SN/Asystem.cpu0.icache.overall_misses 884868 # number of overall misses 1258721SN/Asystem.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits 1268721SN/Asystem.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 1278721SN/Asystem.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 1288721SN/Asystem.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses 1298721SN/Asystem.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 1308721SN/Asystem.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1318721SN/Asystem.cpu0.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 1328721SN/Asystem.cpu0.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 1338721SN/Asystem.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 1348721SN/Asystem.cpu0.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 1358721SN/Asystem.cpu0.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 1368721SN/Asystem.cpu0.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 1378721SN/Asystem.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 13810036SAli.Saidi@ARM.comsystem.cpu0.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 1398721SN/Asystem.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 1408721SN/Asystem.cpu0.icache.replacements 884272 # number of replacements 1418721SN/Asystem.cpu0.icache.sampled_refs 884784 # Sample count of references to valid blocks. 1428721SN/Asystem.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 14310409Sandreas.hansson@arm.comsystem.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use 1448721SN/Asystem.cpu0.icache.total_refs 56304737 # Total number of references to valid blocks. 1458721SN/Asystem.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. 1468721SN/Asystem.cpu0.icache.writebacks 0 # number of writebacks 14710409Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.984710 # Percentage of idle cycles 1488721SN/Asystem.cpu0.itb.accesses 3858857 # ITB accesses 1498721SN/Asystem.cpu0.itb.acv 127 # ITB acv 1508721SN/Asystem.cpu0.itb.hits 3855372 # ITB hits 15110409Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3485 # ITB misses 1526024SN/Asystem.cpu0.kern.callpal 183274 # number of callpals executed 1538721SN/Asystem.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed 1548721SN/Asystem.cpu0.kern.callpal_wripir 110 0.06% 0.06% # number of callpals executed 15510352Sandreas.hansson@arm.comsystem.cpu0.kern.callpal_wrmces 1 0.00% 0.06% # number of callpals executed 1568721SN/Asystem.cpu0.kern.callpal_wrfen 1 0.00% 0.06% # number of callpals executed 1578721SN/Asystem.cpu0.kern.callpal_wrvptptr 1 0.00% 0.06% # number of callpals executed 15810352Sandreas.hansson@arm.comsystem.cpu0.kern.callpal_swpctx 3761 2.05% 2.11% # number of callpals executed 1598721SN/Asystem.cpu0.kern.callpal_tbi 38 0.02% 2.14% # number of callpals executed 1608721SN/Asystem.cpu0.kern.callpal_wrent 7 0.00% 2.14% # number of callpals executed 1618721SN/Asystem.cpu0.kern.callpal_swpipl 168019 91.68% 93.82% # number of callpals executed 1628721SN/Asystem.cpu0.kern.callpal_rdps 6150 3.36% 97.17% # number of callpals executed 1638721SN/Asystem.cpu0.kern.callpal_wrkgp 1 0.00% 97.17% # number of callpals executed 1648721SN/Asystem.cpu0.kern.callpal_wrusp 3 0.00% 97.17% # number of callpals executed 1658721SN/Asystem.cpu0.kern.callpal_rdusp 7 0.00% 97.18% # number of callpals executed 1668721SN/Asystem.cpu0.kern.callpal_whami 2 0.00% 97.18% # number of callpals executed 1676024SN/Asystem.cpu0.kern.callpal_rti 4673 2.55% 99.73% # number of callpals executed 1686024SN/Asystem.cpu0.kern.callpal_callsys 357 0.19% 99.92% # number of callpals executed 1698721SN/Asystem.cpu0.kern.callpal_imb 142 0.08% 100.00% # number of callpals executed 1708721SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 17110409Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 197103 # number of hwrei instructions executed 1728721SN/Asystem.cpu0.kern.inst.quiesce 6167 # number of quiesce instructions executed 1738721SN/Asystem.cpu0.kern.ipl_count 174852 # number of times we switched to this ipl 17410409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count_0 70996 40.60% 40.60% # number of times we switched to this ipl 17510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count_21 243 0.14% 40.74% # number of times we switched to this ipl 17610409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count_22 1908 1.09% 41.83% # number of times we switched to this ipl 1778721SN/Asystem.cpu0.kern.ipl_count_30 8 0.00% 41.84% # number of times we switched to this ipl 1789797Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count_31 101697 58.16% 100.00% # number of times we switched to this ipl 17910409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good 141409 # number of times we switched to this ipl from a different ipl 18010409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good_0 69629 49.24% 49.24% # number of times we switched to this ipl from a different ipl 1818721SN/Asystem.cpu0.kern.ipl_good_21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl 18210409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good_22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl 18310409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good_30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl 1848721SN/Asystem.cpu0.kern.ipl_good_31 69621 49.23% 100.00% # number of times we switched to this ipl from a different ipl 1858721SN/Asystem.cpu0.kern.ipl_ticks 1870335315000 # number of cycles we spent at this ipl 18610409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks_0 1853125830000 99.08% 99.08% # number of cycles we spent at this ipl 18710409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks_21 20110000 0.00% 99.08% # number of cycles we spent at this ipl 18810409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks_22 82044000 0.00% 99.09% # number of cycles we spent at this ipl 18910409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks_30 949500 0.00% 99.09% # number of cycles we spent at this ipl 19010409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks_31 17106381500 0.91% 100.00% # number of cycles we spent at this ipl 19110409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used_0 0.980745 # fraction of swpipl calls that actually changed the ipl 19210409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl 19310409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl 19410409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl 19510409Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used_31 0.684592 # fraction of swpipl calls that actually changed the ipl 19610409Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good_kernel 1157 19710352Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good_user 1158 19810352Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good_idle 0 19910220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_kernel 7090 # number of protection mode switches 20010220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_user 1158 # number of protection mode switches 20110220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_idle 0 # number of protection mode switches 20210220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good <err: div-0> # fraction of useful protection mode switches 20310220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good_kernel 0.163188 # fraction of useful protection mode switches 20410220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches 20510220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good_idle <err: div-0> # fraction of useful protection mode switches 20610220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks_kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode 20710220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks_user 957009000 0.05% 100.00% # number of ticks spent at the given mode 20810220Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode 20910220Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3762 # number of times the context was actually changed 21010220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall 226 # number of syscalls executed 21110220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_2 6 2.65% 2.65% # number of syscalls executed 21210220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_3 19 8.41% 11.06% # number of syscalls executed 21310220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_4 2 0.88% 11.95% # number of syscalls executed 21410220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_6 32 14.16% 26.11% # number of syscalls executed 21510220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_12 1 0.44% 26.55% # number of syscalls executed 21610220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_15 1 0.44% 26.99% # number of syscalls executed 21710220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_17 9 3.98% 30.97% # number of syscalls executed 21810220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_19 8 3.54% 34.51% # number of syscalls executed 21910220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_20 6 2.65% 37.17% # number of syscalls executed 22010220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_23 2 0.88% 38.05% # number of syscalls executed 22110220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_24 4 1.77% 39.82% # number of syscalls executed 22210220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_33 7 3.10% 42.92% # number of syscalls executed 22310220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_41 2 0.88% 43.81% # number of syscalls executed 22410409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_45 37 16.37% 60.18% # number of syscalls executed 22510409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_47 4 1.77% 61.95% # number of syscalls executed 22610352Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_48 8 3.54% 65.49% # number of syscalls executed 22710220Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_54 10 4.42% 69.91% # number of syscalls executed 22810409Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_58 1 0.44% 70.35% # number of syscalls executed 2292968SN/Asystem.cpu0.kern.syscall_59 4 1.77% 72.12% # number of syscalls executed 2308721SN/Asystem.cpu0.kern.syscall_71 30 13.27% 85.40% # number of syscalls executed 23110352Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_73 3 1.33% 86.73% # number of syscalls executed 2326291SN/Asystem.cpu0.kern.syscall_74 8 3.54% 90.27% # number of syscalls executed 2336291SN/Asystem.cpu0.kern.syscall_87 1 0.44% 90.71% # number of syscalls executed 2346291SN/Asystem.cpu0.kern.syscall_90 2 0.88% 91.59% # number of syscalls executed 23510352Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_92 9 3.98% 95.58% # number of syscalls executed 23610352Sandreas.hansson@arm.comsystem.cpu0.kern.syscall_97 2 0.88% 96.46% # number of syscalls executed 2376291SN/Asystem.cpu0.kern.syscall_98 2 0.88% 97.35% # number of syscalls executed 2386291SN/Asystem.cpu0.kern.syscall_132 2 0.88% 98.23% # number of syscalls executed 2396291SN/Asystem.cpu0.kern.syscall_144 2 0.88% 99.12% # number of syscalls executed 2406291SN/Asystem.cpu0.kern.syscall_147 2 0.88% 100.00% # number of syscalls executed 2416127SN/Asystem.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles 24210409Sandreas.hansson@arm.comsystem.cpu0.numCycles 3740670933 # number of cpu cycles simulated 2436291SN/Asystem.cpu0.num_insts 57181549 # Number of instructions executed 2446291SN/Asystem.cpu0.num_refs 15322361 # Number of memory references 24510409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses 16418 # number of LoadLockedReq accesses(hits+misses) 24610409Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits 15129 # number of LoadLockedReq hits 2476127SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate 0.078511 # miss rate for LoadLockedReq accesses 2486127SN/Asystem.cpu1.dcache.LoadLockedReq_misses 1289 # number of LoadLockedReq misses 2496127SN/Asystem.cpu1.dcache.ReadReq_accesses 1150965 # number of ReadReq accesses(hits+misses) 25010352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits 1109315 # number of ReadReq hits 25110352Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate 0.036187 # miss rate for ReadReq accesses 2526291SN/Asystem.cpu1.dcache.ReadReq_misses 41650 # number of ReadReq misses 2536291SN/Asystem.cpu1.dcache.StoreCondReq_accesses 16345 # number of StoreCondReq accesses(hits+misses) 2546291SN/Asystem.cpu1.dcache.StoreCondReq_hits 13438 # number of StoreCondReq hits 2556291SN/Asystem.cpu1.dcache.StoreCondReq_miss_rate 0.177853 # miss rate for StoreCondReq accesses 2566291SN/Asystem.cpu1.dcache.StoreCondReq_misses 2907 # number of StoreCondReq misses 2576291SN/Asystem.cpu1.dcache.WriteReq_accesses 733305 # number of WriteReq accesses(hits+misses) 2586291SN/Asystem.cpu1.dcache.WriteReq_hits 702803 # number of WriteReq hits 2596291SN/Asystem.cpu1.dcache.WriteReq_miss_rate 0.041595 # miss rate for WriteReq accesses 2606291SN/Asystem.cpu1.dcache.WriteReq_misses 30502 # number of WriteReq misses 2616291SN/Asystem.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 2626291SN/Asystem.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 2636291SN/Asystem.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. 2646291SN/Asystem.cpu1.dcache.blocked_no_mshrs 0 # number of cycles access was blocked 2656291SN/Asystem.cpu1.dcache.blocked_no_targets 0 # number of cycles access was blocked 2666291SN/Asystem.cpu1.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 2676291SN/Asystem.cpu1.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked 2686291SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 2696291SN/Asystem.cpu1.dcache.demand_accesses 1884270 # number of demand (read+write) accesses 2706291SN/Asystem.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency 2716291SN/Asystem.cpu1.dcache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 2726291SN/Asystem.cpu1.dcache.demand_hits 1812118 # number of demand (read+write) hits 2736291SN/Asystem.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 2746291SN/Asystem.cpu1.dcache.demand_miss_rate 0.038292 # miss rate for demand accesses 2756291SN/Asystem.cpu1.dcache.demand_misses 72152 # number of demand (read+write) misses 2766291SN/Asystem.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 2776291SN/Asystem.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 2786291SN/Asystem.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 2796291SN/Asystem.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 2806291SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 2816291SN/Asystem.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 2826127SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2838721SN/Asystem.cpu1.dcache.overall_accesses 1884270 # number of overall (read+write) accesses 2848721SN/Asystem.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency 2858721SN/Asystem.cpu1.dcache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 2868721SN/Asystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 2878721SN/Asystem.cpu1.dcache.overall_hits 1812118 # number of overall hits 2888721SN/Asystem.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles 2898721SN/Asystem.cpu1.dcache.overall_miss_rate 0.038292 # miss rate for overall accesses 29010352Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses 72152 # number of overall misses 2918721SN/Asystem.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits 2928721SN/Asystem.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 2938721SN/Asystem.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 2948721SN/Asystem.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses 2958721SN/Asystem.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 2968721SN/Asystem.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 2978721SN/Asystem.cpu1.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 2988721SN/Asystem.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 29910352Sandreas.hansson@arm.comsystem.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 3009797Sandreas.hansson@arm.comsystem.cpu1.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 30110352Sandreas.hansson@arm.comsystem.cpu1.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 3029797Sandreas.hansson@arm.comsystem.cpu1.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 30310352Sandreas.hansson@arm.comsystem.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 30410352Sandreas.hansson@arm.comsystem.cpu1.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 3058721SN/Asystem.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 30610352Sandreas.hansson@arm.comsystem.cpu1.dcache.replacements 62338 # number of replacements 3078721SN/Asystem.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. 3089797Sandreas.hansson@arm.comsystem.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 30910352Sandreas.hansson@arm.comsystem.cpu1.dcache.tagsinuse 391.950049 # Cycle average of tags in use 31010409Sandreas.hansson@arm.comsystem.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks. 31110352Sandreas.hansson@arm.comsystem.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. 31210409Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks 30848 # number of writebacks 3138721SN/Asystem.cpu1.dtb.accesses 323622 # DTB accesses 3142968SN/Asystem.cpu1.dtb.acv 116 # DTB access violations 3152968SN/Asystem.cpu1.dtb.hits 1914885 # DTB hits 3162968SN/Asystem.cpu1.dtb.misses 3692 # DTB misses 3172968SN/Asystem.cpu1.dtb.read_accesses 220342 # DTB read accesses 3188721SN/Asystem.cpu1.dtb.read_acv 58 # DTB read access violations 3198983Snate@binkert.orgsystem.cpu1.dtb.read_hits 1163439 # DTB read hits 3208721SN/Asystem.cpu1.dtb.read_misses 3277 # DTB read misses 3218721SN/Asystem.cpu1.dtb.write_accesses 103280 # DTB write accesses 3228983Snate@binkert.orgsystem.cpu1.dtb.write_acv 58 # DTB write access violations 3238721SN/Asystem.cpu1.dtb.write_hits 751446 # DTB write hits 3248721SN/Asystem.cpu1.dtb.write_misses 415 # DTB write misses 3258983Snate@binkert.orgsystem.cpu1.icache.ReadReq_accesses 5935766 # number of ReadReq accesses(hits+misses) 3268721SN/Asystem.cpu1.icache.ReadReq_hits 5832136 # number of ReadReq hits 3278721SN/Asystem.cpu1.icache.ReadReq_miss_rate 0.017459 # miss rate for ReadReq accesses 3288983Snate@binkert.orgsystem.cpu1.icache.ReadReq_misses 103630 # number of ReadReq misses 3298721SN/Asystem.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 3308721SN/Asystem.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 3318983Snate@binkert.orgsystem.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. 3328721SN/Asystem.cpu1.icache.blocked_no_mshrs 0 # number of cycles access was blocked 3338721SN/Asystem.cpu1.icache.blocked_no_targets 0 # number of cycles access was blocked 3348983Snate@binkert.orgsystem.cpu1.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 3358721SN/Asystem.cpu1.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked 3368721SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 3378983Snate@binkert.orgsystem.cpu1.icache.demand_accesses 5935766 # number of demand (read+write) accesses 3388721SN/Asystem.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency 3398721SN/Asystem.cpu1.icache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 3408983Snate@binkert.orgsystem.cpu1.icache.demand_hits 5832136 # number of demand (read+write) hits 3418721SN/Asystem.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 3428983Snate@binkert.orgsystem.cpu1.icache.demand_miss_rate 0.017459 # miss rate for demand accesses 3438721SN/Asystem.cpu1.icache.demand_misses 103630 # number of demand (read+write) misses 3442968SN/Asystem.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 34510409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 34610409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 34710409Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 34810409Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 34910409Sandreas.hansson@arm.comsystem.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated 35010409Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 35110409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses 5935766 # number of overall (read+write) accesses 35210409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency 35310409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 35410409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 35510409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits 5832136 # number of overall hits 35610409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles 35710409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate 0.017459 # miss rate for overall accesses 35810409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses 103630 # number of overall misses 35910409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits 36010409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 36110409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 36210409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses 36310409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 36410409Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 36510409Sandreas.hansson@arm.comsystem.cpu1.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 36610409Sandreas.hansson@arm.comsystem.cpu1.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 36710409Sandreas.hansson@arm.comsystem.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 36810409Sandreas.hansson@arm.comsystem.cpu1.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 36910409Sandreas.hansson@arm.comsystem.cpu1.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 37010409Sandreas.hansson@arm.comsystem.cpu1.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 37110409Sandreas.hansson@arm.comsystem.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 37210409Sandreas.hansson@arm.comsystem.cpu1.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 37310409Sandreas.hansson@arm.comsystem.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 37410409Sandreas.hansson@arm.comsystem.cpu1.icache.replacements 103091 # number of replacements 37510409Sandreas.hansson@arm.comsystem.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. 37610409Sandreas.hansson@arm.comsystem.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 37710409Sandreas.hansson@arm.comsystem.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use 37810409Sandreas.hansson@arm.comsystem.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks. 37910409Sandreas.hansson@arm.comsystem.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. 38010409Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks 0 # number of writebacks 38110409Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.998413 # Percentage of idle cycles 38210409Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 1469938 # ITB accesses 38310409Sandreas.hansson@arm.comsystem.cpu1.itb.acv 57 # ITB acv 38410409Sandreas.hansson@arm.comsystem.cpu1.itb.hits 1468399 # ITB hits 38510409Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1539 # ITB misses 38610409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal 32131 # number of callpals executed 38710409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed 38810409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_wripir 8 0.02% 0.03% # number of callpals executed 3899885Sstever@gmail.comsystem.cpu1.kern.callpal_wrmces 1 0.00% 0.03% # number of callpals executed 3909885Sstever@gmail.comsystem.cpu1.kern.callpal_wrfen 1 0.00% 0.03% # number of callpals executed 39110036SAli.Saidi@ARM.comsystem.cpu1.kern.callpal_swpctx 470 1.46% 1.50% # number of callpals executed 39210036SAli.Saidi@ARM.comsystem.cpu1.kern.callpal_tbi 15 0.05% 1.54% # number of callpals executed 39310036SAli.Saidi@ARM.comsystem.cpu1.kern.callpal_wrent 7 0.02% 1.57% # number of callpals executed 39410036SAli.Saidi@ARM.comsystem.cpu1.kern.callpal_swpipl 26238 81.66% 83.22% # number of callpals executed 39510036SAli.Saidi@ARM.comsystem.cpu1.kern.callpal_rdps 2576 8.02% 91.24% # number of callpals executed 39610409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_wrkgp 1 0.00% 91.25% # number of callpals executed 39710409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_wrusp 4 0.01% 91.26% # number of callpals executed 39810409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_rdusp 2 0.01% 91.26% # number of callpals executed 39910409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_whami 3 0.01% 91.27% # number of callpals executed 40010409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_rti 2607 8.11% 99.39% # number of callpals executed 40110409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_callsys 158 0.49% 99.88% # number of callpals executed 40210409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_imb 38 0.12% 100.00% # number of callpals executed 40310409Sandreas.hansson@arm.comsystem.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed 40410409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 40510409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed 40610409Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed 40710409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count 30863 # number of times we switched to this ipl 40810409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count_0 10328 33.46% 33.46% # number of times we switched to this ipl 40910409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count_22 1907 6.18% 39.64% # number of times we switched to this ipl 41010409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count_30 110 0.36% 40.00% # number of times we switched to this ipl 41110409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count_31 18518 60.00% 100.00% # number of times we switched to this ipl 41210409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good 22543 # number of times we switched to this ipl from a different ipl 41310409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good_0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl 41410409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good_22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl 41510409Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good_30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl 4168835SAli.Saidi@ARM.comsystem.cpu1.kern.ipl_good_31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl 4179055Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_ticks 1870124427000 # number of cycles we spent at this ipl 4188835SAli.Saidi@ARM.comsystem.cpu1.kern.ipl_ticks_0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl 4199055Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_ticks_22 82001000 0.00% 99.42% # number of cycles we spent at this ipl 4208835SAli.Saidi@ARM.comsystem.cpu1.kern.ipl_ticks_30 14064500 0.00% 99.42% # number of cycles we spent at this ipl 4219055Ssaidi@eecs.umich.edusystem.cpu1.kern.ipl_ticks_31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl 4228721SN/Asystem.cpu1.kern.ipl_used_0 0.999032 # fraction of swpipl calls that actually changed the ipl 4238721SN/Asystem.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl 4248721SN/Asystem.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl 4258721SN/Asystem.cpu1.kern.ipl_used_31 0.551247 # fraction of swpipl calls that actually changed the ipl 4268983Snate@binkert.orgsystem.cpu1.kern.mode_good_kernel 612 4278983Snate@binkert.orgsystem.cpu1.kern.mode_good_user 580 4288721SN/Asystem.cpu1.kern.mode_good_idle 32 4298721SN/Asystem.cpu1.kern.mode_switch_kernel 1033 # number of protection mode switches 4308721SN/Asystem.cpu1.kern.mode_switch_user 580 # number of protection mode switches 43110409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_idle 2046 # number of protection mode switches 43210409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good 1.608089 # fraction of useful protection mode switches 43310409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good_kernel 0.592449 # fraction of useful protection mode switches 43410409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches 43510409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good_idle 0.015640 # fraction of useful protection mode switches 4369885Sstever@gmail.comsystem.cpu1.kern.mode_ticks_kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode 43710409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks_user 508289000 0.03% 0.10% # number of ticks spent at the given mode 43810409Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks_idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode 43910409Sandreas.hansson@arm.comsystem.cpu1.kern.swap_context 471 # number of times the context was actually changed 44010409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall 100 # number of syscalls executed 44110409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_2 2 2.00% 2.00% # number of syscalls executed 4429797Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_3 11 11.00% 13.00% # number of syscalls executed 4439885Sstever@gmail.comsystem.cpu1.kern.syscall_4 2 2.00% 15.00% # number of syscalls executed 44410036SAli.Saidi@ARM.comsystem.cpu1.kern.syscall_6 10 10.00% 25.00% # number of syscalls executed 44510036SAli.Saidi@ARM.comsystem.cpu1.kern.syscall_17 6 6.00% 31.00% # number of syscalls executed 44610036SAli.Saidi@ARM.comsystem.cpu1.kern.syscall_19 2 2.00% 33.00% # number of syscalls executed 44710036SAli.Saidi@ARM.comsystem.cpu1.kern.syscall_23 2 2.00% 35.00% # number of syscalls executed 44810352Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_24 2 2.00% 37.00% # number of syscalls executed 44910352Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_33 4 4.00% 41.00% # number of syscalls executed 45010036SAli.Saidi@ARM.comsystem.cpu1.kern.syscall_45 17 17.00% 58.00% # number of syscalls executed 45110409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_47 2 2.00% 60.00% # number of syscalls executed 45210409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_48 2 2.00% 62.00% # number of syscalls executed 45310409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_59 3 3.00% 65.00% # number of syscalls executed 45410409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_71 24 24.00% 89.00% # number of syscalls executed 45510409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_74 8 8.00% 97.00% # number of syscalls executed 45610409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_90 1 1.00% 98.00% # number of syscalls executed 45710409Sandreas.hansson@arm.comsystem.cpu1.kern.syscall_132 2 2.00% 100.00% # number of syscalls executed 4589289Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles 4599289Sandreas.hansson@arm.comsystem.cpu1.numCycles 3740248881 # number of cpu cycles simulated 46010409Sandreas.hansson@arm.comsystem.cpu1.num_insts 5931958 # Number of instructions executed 46110409Sandreas.hansson@arm.comsystem.cpu1.num_refs 1926645 # Number of memory references 46210409Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 46310409Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 46410409Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 46510409Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 46610409Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 46710409Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 4689797Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 4699289Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4709797Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 4719289Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 4729289Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 47310409Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 47410409Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses 175 # number of ReadReq accesses(hits+misses) 4759797Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses 47610409Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses 175 # number of ReadReq misses 47710409Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses 41552 # number of WriteReq accesses(hits+misses) 4789797Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate 1 # miss rate for WriteReq accesses 47910409Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses 41552 # number of WriteReq misses 48010409Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 48110409Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 48210409Sandreas.hansson@arm.comsystem.iocache.avg_refs 0 # Average number of references to valid blocks. 48310409Sandreas.hansson@arm.comsystem.iocache.blocked_no_mshrs 0 # number of cycles access was blocked 48410409Sandreas.hansson@arm.comsystem.iocache.blocked_no_targets 0 # number of cycles access was blocked 48510409Sandreas.hansson@arm.comsystem.iocache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 4869289Sandreas.hansson@arm.comsystem.iocache.blocked_cycles_no_targets 0 # number of cycles access was blocked 4879289Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 48810409Sandreas.hansson@arm.comsystem.iocache.demand_accesses 41727 # number of demand (read+write) accesses 48910409Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency 0 # average overall miss latency 49010409Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 49110409Sandreas.hansson@arm.comsystem.iocache.demand_hits 0 # number of demand (read+write) hits 49210409Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 49310409Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate 1 # miss rate for demand accesses 49410409Sandreas.hansson@arm.comsystem.iocache.demand_misses 41727 # number of demand (read+write) misses 49510409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 49610409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 49710409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 49810409Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 4999289Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 5009289Sandreas.hansson@arm.comsystem.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 50110409Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 50210409Sandreas.hansson@arm.comsystem.iocache.overall_accesses 41727 # number of overall (read+write) accesses 50310409Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency 0 # average overall miss latency 50410409Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 50510409Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 50610409Sandreas.hansson@arm.comsystem.iocache.overall_hits 0 # number of overall hits 50710409Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency 0 # number of overall miss cycles 50810409Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate 1 # miss rate for overall accesses 5099289Sandreas.hansson@arm.comsystem.iocache.overall_misses 41727 # number of overall misses 5109289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_hits 0 # number of overall MSHR hits 5119289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 5129289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 5139289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses 0 # number of overall MSHR misses 5149289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 5159289Sandreas.hansson@arm.comsystem.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 5169289Sandreas.hansson@arm.comsystem.iocache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 51710409Sandreas.hansson@arm.comsystem.iocache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 51810409Sandreas.hansson@arm.comsystem.iocache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 5199289Sandreas.hansson@arm.comsystem.iocache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 52010409Sandreas.hansson@arm.comsystem.iocache.prefetcher.num_hwpf_identified 0 # number of hwpf identified 5219885Sstever@gmail.comsystem.iocache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 52210409Sandreas.hansson@arm.comsystem.iocache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 52310409Sandreas.hansson@arm.comsystem.iocache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 52410409Sandreas.hansson@arm.comsystem.iocache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 5259885Sstever@gmail.comsystem.iocache.replacements 41695 # number of replacements 5269885Sstever@gmail.comsystem.iocache.sampled_refs 41711 # Sample count of references to valid blocks. 5279885Sstever@gmail.comsystem.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 5289885Sstever@gmail.comsystem.iocache.tagsinuse 0.435437 # Cycle average of tags in use 52910036SAli.Saidi@ARM.comsystem.iocache.total_refs 0 # Total number of references to valid blocks. 53010036SAli.Saidi@ARM.comsystem.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. 53110036SAli.Saidi@ARM.comsystem.iocache.writebacks 41520 # number of writebacks 53210036SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses 306244 # number of ReadExReq accesses(hits+misses) 53310036SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 53410409Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses 306244 # number of ReadExReq misses 53510409Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses 2724143 # number of ReadReq accesses(hits+misses) 53610409Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits 1759609 # number of ReadReq hits 53710409Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate 0.354069 # miss rate for ReadReq accesses 53810409Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses 964534 # number of ReadReq misses 53910409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses 125010 # number of UpgradeReq accesses(hits+misses) 54010409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses 54110409Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses 125010 # number of UpgradeReq misses 5429797Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses 427641 # number of Writeback accesses(hits+misses) 5439797Sandreas.hansson@arm.comsystem.l2c.Writeback_hits 427641 # number of Writeback hits 54410409Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked 54510409Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked 54610409Sandreas.hansson@arm.comsystem.l2c.avg_refs 1.789118 # Average number of references to valid blocks. 54710409Sandreas.hansson@arm.comsystem.l2c.blocked_no_mshrs 0 # number of cycles access was blocked 54810409Sandreas.hansson@arm.comsystem.l2c.blocked_no_targets 0 # number of cycles access was blocked 54910409Sandreas.hansson@arm.comsystem.l2c.blocked_cycles_no_mshrs 0 # number of cycles access was blocked 55010409Sandreas.hansson@arm.comsystem.l2c.blocked_cycles_no_targets 0 # number of cycles access was blocked 55110409Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 55210409Sandreas.hansson@arm.comsystem.l2c.demand_accesses 3030387 # number of demand (read+write) accesses 55310409Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency 0 # average overall miss latency 55410409Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 55510409Sandreas.hansson@arm.comsystem.l2c.demand_hits 1759609 # number of demand (read+write) hits 55610409Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 55710409Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate 0.419345 # miss rate for demand accesses 55810409Sandreas.hansson@arm.comsystem.l2c.demand_misses 1270778 # number of demand (read+write) misses 55910409Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 56010409Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 56110409Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses 5629797Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 5639797Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 5649797Sandreas.hansson@arm.comsystem.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 5659797Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 56610409Sandreas.hansson@arm.comsystem.l2c.overall_accesses 3030387 # number of overall (read+write) accesses 56710409Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency 0 # average overall miss latency 56810409Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency <err: div-0> # average overall mshr miss latency 56910409Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency 57010409Sandreas.hansson@arm.comsystem.l2c.overall_hits 1759609 # number of overall hits 57110409Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency 0 # number of overall miss cycles 57210409Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate 0.419345 # miss rate for overall accesses 57310409Sandreas.hansson@arm.comsystem.l2c.overall_misses 1270778 # number of overall misses 57410409Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits 0 # number of overall MSHR hits 57510409Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 57610409Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses 57710409Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses 0 # number of overall MSHR misses 57810409Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 57910409Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 5809481Snilay@cs.wisc.edusystem.l2c.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache 5819481Snilay@cs.wisc.edusystem.l2c.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr 5829481Snilay@cs.wisc.edusystem.l2c.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue 5839481Snilay@cs.wisc.edusystem.l2c.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 5849481Snilay@cs.wisc.edusystem.l2c.prefetcher.num_hwpf_identified 0 # number of hwpf identified 5859481Snilay@cs.wisc.edusystem.l2c.prefetcher.num_hwpf_issued 0 # number of hwpf issued 5869481Snilay@cs.wisc.edusystem.l2c.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated 5879481Snilay@cs.wisc.edusystem.l2c.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page 58810409Sandreas.hansson@arm.comsystem.l2c.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 58910409Sandreas.hansson@arm.comsystem.l2c.replacements 1056800 # number of replacements 5909481Snilay@cs.wisc.edusystem.l2c.sampled_refs 1091449 # Sample count of references to valid blocks. 59110409Sandreas.hansson@arm.comsystem.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 59210409Sandreas.hansson@arm.comsystem.l2c.tagsinuse 30522.432687 # Cycle average of tags in use 59310409Sandreas.hansson@arm.comsystem.l2c.total_refs 1952731 # Total number of references to valid blocks. 59410409Sandreas.hansson@arm.comsystem.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. 59510409Sandreas.hansson@arm.comsystem.l2c.writebacks 123878 # number of writebacks 59610409Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxDesc <err: div-0> # average number of RxDesc's coalesced into each post 59710409Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxIdle <err: div-0> # average number of RxIdle's coalesced into each post 59810409Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOk <err: div-0> # average number of RxOk's coalesced into each post 59910409Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedRxOrn <err: div-0> # average number of RxOrn's coalesced into each post 60010409Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedSwi <err: div-0> # average number of Swi's coalesced into each post 60110409Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTotal <err: div-0> # average number of interrupts coalesced into each post 60210409Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxDesc <err: div-0> # average number of TxDesc's coalesced into each post 60310409Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxIdle <err: div-0> # average number of TxIdle's coalesced into each post 60410409Sandreas.hansson@arm.comsystem.tsunami.ethernet.coalescedTxOk <err: div-0> # average number of TxOk's coalesced into each post 60510409Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 60610409Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 60710409Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 60810409Sandreas.hansson@arm.comsystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 60910409Sandreas.hansson@arm.comsystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 61010409Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 61110409Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 61210409Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 61310409Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 61410409Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 61510409Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 61610409Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 61710409Sandreas.hansson@arm.comsystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 6182968SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 6192968SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 620system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 621system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 622system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 623system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 624system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 625system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 626system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 627 628---------- End Simulation Statistics ---------- 629