config.ini revision 8893
17860SN/A[root]
27860SN/Atype=Root
37860SN/Achildren=system
48825Snilay@cs.wisc.edufull_system=false
57935SN/Atime_sync_enable=false
67935SN/Atime_sync_period=100000000000
77935SN/Atime_sync_spin_threshold=100000000
87860SN/A
97860SN/A[system]
107860SN/Atype=System
117860SN/Achildren=cpu membus physmem
128825Snilay@cs.wisc.eduboot_osflags=a
138825Snilay@cs.wisc.eduinit_param=0
148825Snilay@cs.wisc.edukernel=
158825Snilay@cs.wisc.eduload_addr_mask=1099511627775
167860SN/Amem_mode=atomic
178464SN/Amemories=system.physmem
188721SN/Anum_work_ids=16
197860SN/Aphysmem=system.physmem
208825Snilay@cs.wisc.edureadfile=
218825Snilay@cs.wisc.edusymbolfile=
227935SN/Awork_begin_ckpt_count=0
237935SN/Awork_begin_cpu_id_exit=-1
247935SN/Awork_begin_exit_count=0
257935SN/Awork_cpus_ckpt_count=0
267935SN/Awork_end_ckpt_count=0
277935SN/Awork_end_exit_count=0
287935SN/Awork_item_id=-1
298893Ssaidi@eecs.umich.edusystem_port=system.membus.slave[0]
307860SN/A
317860SN/A[system.cpu]
327860SN/Atype=DerivO3CPU
338825Snilay@cs.wisc.educhildren=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
347860SN/ABTBEntries=4096
357860SN/ABTBTagSize=16
367860SN/ALFSTSize=1024
377860SN/ALQEntries=32
388210SN/ALSQCheckLoads=true
398210SN/ALSQDepCheckShift=4
407860SN/ARASSize=16
417860SN/ASQEntries=32
427860SN/ASSITSize=1024
437860SN/Aactivity=0
447860SN/AbackComSize=5
457860SN/AcachePorts=200
467860SN/Achecker=Null
477860SN/AchoiceCtrBits=2
487860SN/AchoicePredictorSize=8192
497860SN/Aclock=500
507860SN/AcommitToDecodeDelay=1
517860SN/AcommitToFetchDelay=1
527860SN/AcommitToIEWDelay=1
537860SN/AcommitToRenameDelay=1
547860SN/AcommitWidth=8
557860SN/Acpu_id=0
567860SN/AdecodeToFetchDelay=1
577860SN/AdecodeToRenameDelay=1
587860SN/AdecodeWidth=8
597860SN/Adefer_registration=false
607860SN/AdispatchWidth=8
617860SN/Ado_checkpoint_insts=true
628825Snilay@cs.wisc.edudo_quiesce=true
637860SN/Ado_statistics_insts=true
647860SN/Adtb=system.cpu.dtb
657860SN/AfetchToDecodeDelay=1
667860SN/AfetchTrapLatency=1
677860SN/AfetchWidth=8
687860SN/AforwardComSize=5
697860SN/AfuPool=system.cpu.fuPool
707860SN/Afunction_trace=false
717860SN/Afunction_trace_start=0
727860SN/AglobalCtrBits=2
737860SN/AglobalHistoryBits=13
747860SN/AglobalPredictorSize=8192
757860SN/AiewToCommitDelay=1
767860SN/AiewToDecodeDelay=1
777860SN/AiewToFetchDelay=1
787860SN/AiewToRenameDelay=1
797860SN/AinstShiftAmt=2
808825Snilay@cs.wisc.eduinterrupts=system.cpu.interrupts
817860SN/AissueToExecuteDelay=1
827860SN/AissueWidth=8
837860SN/Aitb=system.cpu.itb
847860SN/AlocalCtrBits=2
857860SN/AlocalHistoryBits=11
867860SN/AlocalHistoryTableSize=2048
877860SN/AlocalPredictorSize=2048
887860SN/Amax_insts_all_threads=0
897860SN/Amax_insts_any_thread=0
907860SN/Amax_loads_all_threads=0
917860SN/Amax_loads_any_thread=0
928825Snilay@cs.wisc.eduneedsTSO=false
937860SN/AnumIQEntries=64
947860SN/AnumPhysFloatRegs=256
957860SN/AnumPhysIntRegs=256
967860SN/AnumROBEntries=192
977860SN/AnumRobs=1
987860SN/AnumThreads=1
997860SN/Aphase=0
1007860SN/ApredType=tournament
1018825Snilay@cs.wisc.eduprofile=0
1027860SN/Aprogress_interval=0
1037860SN/ArenameToDecodeDelay=1
1047860SN/ArenameToFetchDelay=1
1057860SN/ArenameToIEWDelay=2
1067860SN/ArenameToROBDelay=1
1077860SN/ArenameWidth=8
1087860SN/AsmtCommitPolicy=RoundRobin
1097860SN/AsmtFetchPolicy=SingleThread
1107860SN/AsmtIQPolicy=Partitioned
1117860SN/AsmtIQThreshold=100
1127860SN/AsmtLSQPolicy=Partitioned
1137860SN/AsmtLSQThreshold=100
1147860SN/AsmtNumFetchingThreads=1
1157860SN/AsmtROBPolicy=Partitioned
1167860SN/AsmtROBThreshold=100
1177860SN/AsquashWidth=8
1188521SN/Astore_set_clear_period=250000
1197860SN/Asystem=system
1207860SN/Atracer=system.cpu.tracer
1217860SN/AtrapLatency=13
1227860SN/AwbDepth=1
1237860SN/AwbWidth=8
1247860SN/Aworkload=system.cpu.workload
1257860SN/Adcache_port=system.cpu.dcache.cpu_side
1267860SN/Aicache_port=system.cpu.icache.cpu_side
1277860SN/A
1287860SN/A[system.cpu.dcache]
1297860SN/Atype=BaseCache
1308893Ssaidi@eecs.umich.eduaddr_ranges=0:18446744073709551615
1317860SN/Aassoc=2
1327860SN/Ablock_size=64
1337860SN/Aforward_snoops=true
1347860SN/Ahash_delay=1
1358150SN/Ais_top_level=true
1367860SN/Alatency=1000
1377860SN/Amax_miss_count=0
1387860SN/Amshrs=10
1397860SN/Aprefetch_on_access=false
1408835SAli.Saidi@ARM.comprefetcher=Null
1417860SN/AprioritizeRequests=false
1427860SN/Arepl=Null
1437860SN/Asize=262144
1447860SN/Asubblock_size=0
1458835SAli.Saidi@ARM.comsystem=system
1467860SN/Atgts_per_mshr=20
1477860SN/Atrace_addr=0
1487860SN/Atwo_queue=false
1497860SN/Awrite_buffers=8
1507860SN/Acpu_side=system.cpu.dcache_port
1518893Ssaidi@eecs.umich.edumem_side=system.cpu.toL2Bus.slave[1]
1527860SN/A
1537860SN/A[system.cpu.dtb]
1547860SN/Atype=ArmTLB
1558825Snilay@cs.wisc.educhildren=walker
1567860SN/Asize=64
1578825Snilay@cs.wisc.eduwalker=system.cpu.dtb.walker
1588825Snilay@cs.wisc.edu
1598825Snilay@cs.wisc.edu[system.cpu.dtb.walker]
1608825Snilay@cs.wisc.edutype=ArmTableWalker
1618825Snilay@cs.wisc.edumax_backoff=100000
1628825Snilay@cs.wisc.edumin_backoff=0
1638825Snilay@cs.wisc.edusys=system
1648893Ssaidi@eecs.umich.eduport=system.cpu.toL2Bus.slave[3]
1657860SN/A
1667860SN/A[system.cpu.fuPool]
1677860SN/Atype=FUPool
1687860SN/Achildren=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
1697860SN/AFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
1707860SN/A
1717860SN/A[system.cpu.fuPool.FUList0]
1727860SN/Atype=FUDesc
1737860SN/Achildren=opList
1747860SN/Acount=6
1757860SN/AopList=system.cpu.fuPool.FUList0.opList
1767860SN/A
1777860SN/A[system.cpu.fuPool.FUList0.opList]
1787860SN/Atype=OpDesc
1797860SN/AissueLat=1
1807860SN/AopClass=IntAlu
1817860SN/AopLat=1
1827860SN/A
1837860SN/A[system.cpu.fuPool.FUList1]
1847860SN/Atype=FUDesc
1857860SN/Achildren=opList0 opList1
1867860SN/Acount=2
1877860SN/AopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
1887860SN/A
1897860SN/A[system.cpu.fuPool.FUList1.opList0]
1907860SN/Atype=OpDesc
1917860SN/AissueLat=1
1927860SN/AopClass=IntMult
1937860SN/AopLat=3
1947860SN/A
1957860SN/A[system.cpu.fuPool.FUList1.opList1]
1967860SN/Atype=OpDesc
1977860SN/AissueLat=19
1987860SN/AopClass=IntDiv
1997860SN/AopLat=20
2007860SN/A
2017860SN/A[system.cpu.fuPool.FUList2]
2027860SN/Atype=FUDesc
2037860SN/Achildren=opList0 opList1 opList2
2047860SN/Acount=4
2057860SN/AopList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
2067860SN/A
2077860SN/A[system.cpu.fuPool.FUList2.opList0]
2087860SN/Atype=OpDesc
2097860SN/AissueLat=1
2107860SN/AopClass=FloatAdd
2117860SN/AopLat=2
2127860SN/A
2137860SN/A[system.cpu.fuPool.FUList2.opList1]
2147860SN/Atype=OpDesc
2157860SN/AissueLat=1
2167860SN/AopClass=FloatCmp
2177860SN/AopLat=2
2187860SN/A
2197860SN/A[system.cpu.fuPool.FUList2.opList2]
2207860SN/Atype=OpDesc
2217860SN/AissueLat=1
2227860SN/AopClass=FloatCvt
2237860SN/AopLat=2
2247860SN/A
2257860SN/A[system.cpu.fuPool.FUList3]
2267860SN/Atype=FUDesc
2277860SN/Achildren=opList0 opList1 opList2
2287860SN/Acount=2
2297860SN/AopList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
2307860SN/A
2317860SN/A[system.cpu.fuPool.FUList3.opList0]
2327860SN/Atype=OpDesc
2337860SN/AissueLat=1
2347860SN/AopClass=FloatMult
2357860SN/AopLat=4
2367860SN/A
2377860SN/A[system.cpu.fuPool.FUList3.opList1]
2387860SN/Atype=OpDesc
2397860SN/AissueLat=12
2407860SN/AopClass=FloatDiv
2417860SN/AopLat=12
2427860SN/A
2437860SN/A[system.cpu.fuPool.FUList3.opList2]
2447860SN/Atype=OpDesc
2457860SN/AissueLat=24
2467860SN/AopClass=FloatSqrt
2477860SN/AopLat=24
2487860SN/A
2497860SN/A[system.cpu.fuPool.FUList4]
2507860SN/Atype=FUDesc
2517860SN/Achildren=opList
2527860SN/Acount=0
2537860SN/AopList=system.cpu.fuPool.FUList4.opList
2547860SN/A
2557860SN/A[system.cpu.fuPool.FUList4.opList]
2567860SN/Atype=OpDesc
2577860SN/AissueLat=1
2587860SN/AopClass=MemRead
2597860SN/AopLat=1
2607860SN/A
2617860SN/A[system.cpu.fuPool.FUList5]
2627860SN/Atype=FUDesc
2637860SN/Achildren=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
2647860SN/Acount=4
2657860SN/AopList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
2667860SN/A
2677860SN/A[system.cpu.fuPool.FUList5.opList00]
2687860SN/Atype=OpDesc
2697860SN/AissueLat=1
2707860SN/AopClass=SimdAdd
2717860SN/AopLat=1
2727860SN/A
2737860SN/A[system.cpu.fuPool.FUList5.opList01]
2747860SN/Atype=OpDesc
2757860SN/AissueLat=1
2767860SN/AopClass=SimdAddAcc
2777860SN/AopLat=1
2787860SN/A
2797860SN/A[system.cpu.fuPool.FUList5.opList02]
2807860SN/Atype=OpDesc
2817860SN/AissueLat=1
2827860SN/AopClass=SimdAlu
2837860SN/AopLat=1
2847860SN/A
2857860SN/A[system.cpu.fuPool.FUList5.opList03]
2867860SN/Atype=OpDesc
2877860SN/AissueLat=1
2887860SN/AopClass=SimdCmp
2897860SN/AopLat=1
2907860SN/A
2917860SN/A[system.cpu.fuPool.FUList5.opList04]
2927860SN/Atype=OpDesc
2937860SN/AissueLat=1
2947860SN/AopClass=SimdCvt
2957860SN/AopLat=1
2967860SN/A
2977860SN/A[system.cpu.fuPool.FUList5.opList05]
2987860SN/Atype=OpDesc
2997860SN/AissueLat=1
3007860SN/AopClass=SimdMisc
3017860SN/AopLat=1
3027860SN/A
3037860SN/A[system.cpu.fuPool.FUList5.opList06]
3047860SN/Atype=OpDesc
3057860SN/AissueLat=1
3067860SN/AopClass=SimdMult
3077860SN/AopLat=1
3087860SN/A
3097860SN/A[system.cpu.fuPool.FUList5.opList07]
3107860SN/Atype=OpDesc
3117860SN/AissueLat=1
3127860SN/AopClass=SimdMultAcc
3137860SN/AopLat=1
3147860SN/A
3157860SN/A[system.cpu.fuPool.FUList5.opList08]
3167860SN/Atype=OpDesc
3177860SN/AissueLat=1
3187860SN/AopClass=SimdShift
3197860SN/AopLat=1
3207860SN/A
3217860SN/A[system.cpu.fuPool.FUList5.opList09]
3227860SN/Atype=OpDesc
3237860SN/AissueLat=1
3247860SN/AopClass=SimdShiftAcc
3257860SN/AopLat=1
3267860SN/A
3277860SN/A[system.cpu.fuPool.FUList5.opList10]
3287860SN/Atype=OpDesc
3297860SN/AissueLat=1
3307860SN/AopClass=SimdSqrt
3317860SN/AopLat=1
3327860SN/A
3337860SN/A[system.cpu.fuPool.FUList5.opList11]
3347860SN/Atype=OpDesc
3357860SN/AissueLat=1
3367860SN/AopClass=SimdFloatAdd
3377860SN/AopLat=1
3387860SN/A
3397860SN/A[system.cpu.fuPool.FUList5.opList12]
3407860SN/Atype=OpDesc
3417860SN/AissueLat=1
3427860SN/AopClass=SimdFloatAlu
3437860SN/AopLat=1
3447860SN/A
3457860SN/A[system.cpu.fuPool.FUList5.opList13]
3467860SN/Atype=OpDesc
3477860SN/AissueLat=1
3487860SN/AopClass=SimdFloatCmp
3497860SN/AopLat=1
3507860SN/A
3517860SN/A[system.cpu.fuPool.FUList5.opList14]
3527860SN/Atype=OpDesc
3537860SN/AissueLat=1
3547860SN/AopClass=SimdFloatCvt
3557860SN/AopLat=1
3567860SN/A
3577860SN/A[system.cpu.fuPool.FUList5.opList15]
3587860SN/Atype=OpDesc
3597860SN/AissueLat=1
3607860SN/AopClass=SimdFloatDiv
3617860SN/AopLat=1
3627860SN/A
3637860SN/A[system.cpu.fuPool.FUList5.opList16]
3647860SN/Atype=OpDesc
3657860SN/AissueLat=1
3667860SN/AopClass=SimdFloatMisc
3677860SN/AopLat=1
3687860SN/A
3697860SN/A[system.cpu.fuPool.FUList5.opList17]
3707860SN/Atype=OpDesc
3717860SN/AissueLat=1
3727860SN/AopClass=SimdFloatMult
3737860SN/AopLat=1
3747860SN/A
3757860SN/A[system.cpu.fuPool.FUList5.opList18]
3767860SN/Atype=OpDesc
3777860SN/AissueLat=1
3787860SN/AopClass=SimdFloatMultAcc
3797860SN/AopLat=1
3807860SN/A
3817860SN/A[system.cpu.fuPool.FUList5.opList19]
3827860SN/Atype=OpDesc
3837860SN/AissueLat=1
3847860SN/AopClass=SimdFloatSqrt
3857860SN/AopLat=1
3867860SN/A
3877860SN/A[system.cpu.fuPool.FUList6]
3887860SN/Atype=FUDesc
3897860SN/Achildren=opList
3907860SN/Acount=0
3917860SN/AopList=system.cpu.fuPool.FUList6.opList
3927860SN/A
3937860SN/A[system.cpu.fuPool.FUList6.opList]
3947860SN/Atype=OpDesc
3957860SN/AissueLat=1
3967860SN/AopClass=MemWrite
3977860SN/AopLat=1
3987860SN/A
3997860SN/A[system.cpu.fuPool.FUList7]
4007860SN/Atype=FUDesc
4017860SN/Achildren=opList0 opList1
4027860SN/Acount=4
4037860SN/AopList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
4047860SN/A
4057860SN/A[system.cpu.fuPool.FUList7.opList0]
4067860SN/Atype=OpDesc
4077860SN/AissueLat=1
4087860SN/AopClass=MemRead
4097860SN/AopLat=1
4107860SN/A
4117860SN/A[system.cpu.fuPool.FUList7.opList1]
4127860SN/Atype=OpDesc
4137860SN/AissueLat=1
4147860SN/AopClass=MemWrite
4157860SN/AopLat=1
4167860SN/A
4177860SN/A[system.cpu.fuPool.FUList8]
4187860SN/Atype=FUDesc
4197860SN/Achildren=opList
4207860SN/Acount=1
4217860SN/AopList=system.cpu.fuPool.FUList8.opList
4227860SN/A
4237860SN/A[system.cpu.fuPool.FUList8.opList]
4247860SN/Atype=OpDesc
4257860SN/AissueLat=3
4267860SN/AopClass=IprAccess
4277860SN/AopLat=3
4287860SN/A
4297860SN/A[system.cpu.icache]
4307860SN/Atype=BaseCache
4318893Ssaidi@eecs.umich.eduaddr_ranges=0:18446744073709551615
4327860SN/Aassoc=2
4337860SN/Ablock_size=64
4347860SN/Aforward_snoops=true
4357860SN/Ahash_delay=1
4368150SN/Ais_top_level=true
4377860SN/Alatency=1000
4387860SN/Amax_miss_count=0
4397860SN/Amshrs=10
4407860SN/Aprefetch_on_access=false
4418835SAli.Saidi@ARM.comprefetcher=Null
4427860SN/AprioritizeRequests=false
4437860SN/Arepl=Null
4447860SN/Asize=131072
4457860SN/Asubblock_size=0
4468835SAli.Saidi@ARM.comsystem=system
4477860SN/Atgts_per_mshr=20
4487860SN/Atrace_addr=0
4497860SN/Atwo_queue=false
4507860SN/Awrite_buffers=8
4517860SN/Acpu_side=system.cpu.icache_port
4528893Ssaidi@eecs.umich.edumem_side=system.cpu.toL2Bus.slave[0]
4537860SN/A
4548825Snilay@cs.wisc.edu[system.cpu.interrupts]
4558825Snilay@cs.wisc.edutype=ArmInterrupts
4568825Snilay@cs.wisc.edu
4577860SN/A[system.cpu.itb]
4587860SN/Atype=ArmTLB
4598825Snilay@cs.wisc.educhildren=walker
4607860SN/Asize=64
4618825Snilay@cs.wisc.eduwalker=system.cpu.itb.walker
4628825Snilay@cs.wisc.edu
4638825Snilay@cs.wisc.edu[system.cpu.itb.walker]
4648825Snilay@cs.wisc.edutype=ArmTableWalker
4658825Snilay@cs.wisc.edumax_backoff=100000
4668825Snilay@cs.wisc.edumin_backoff=0
4678825Snilay@cs.wisc.edusys=system
4688893Ssaidi@eecs.umich.eduport=system.cpu.toL2Bus.slave[2]
4697860SN/A
4707860SN/A[system.cpu.l2cache]
4717860SN/Atype=BaseCache
4728893Ssaidi@eecs.umich.eduaddr_ranges=0:18446744073709551615
4737860SN/Aassoc=2
4747860SN/Ablock_size=64
4757860SN/Aforward_snoops=true
4767860SN/Ahash_delay=1
4778150SN/Ais_top_level=false
4787860SN/Alatency=1000
4797860SN/Amax_miss_count=0
4807860SN/Amshrs=10
4817860SN/Aprefetch_on_access=false
4828835SAli.Saidi@ARM.comprefetcher=Null
4837860SN/AprioritizeRequests=false
4847860SN/Arepl=Null
4857860SN/Asize=2097152
4867860SN/Asubblock_size=0
4878835SAli.Saidi@ARM.comsystem=system
4887860SN/Atgts_per_mshr=5
4897860SN/Atrace_addr=0
4907860SN/Atwo_queue=false
4917860SN/Awrite_buffers=8
4928893Ssaidi@eecs.umich.educpu_side=system.cpu.toL2Bus.master[0]
4938893Ssaidi@eecs.umich.edumem_side=system.membus.slave[1]
4947860SN/A
4957860SN/A[system.cpu.toL2Bus]
4967860SN/Atype=Bus
4977860SN/Ablock_size=64
4987860SN/Abus_id=0
4997860SN/Aclock=1000
5007860SN/Aheader_cycles=1
5017860SN/Ause_default_range=false
5027860SN/Awidth=64
5038893Ssaidi@eecs.umich.edumaster=system.cpu.l2cache.cpu_side
5048893Ssaidi@eecs.umich.eduslave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
5057860SN/A
5067860SN/A[system.cpu.tracer]
5077860SN/Atype=ExeTracer
5087860SN/A
5097860SN/A[system.cpu.workload]
5107860SN/Atype=LiveProcess
5117860SN/Acmd=twolf smred
5128835SAli.Saidi@ARM.comcwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
5137860SN/Aegid=100
5147860SN/Aenv=
5157860SN/Aerrout=cerr
5167860SN/Aeuid=100
5178835SAli.Saidi@ARM.comexecutable=/dist/m5/cpu2000/binaries/arm/linux/twolf
5187860SN/Agid=100
5197860SN/Ainput=cin
5207860SN/Amax_stack_size=67108864
5217860SN/Aoutput=cout
5227860SN/Apid=100
5237860SN/Appid=99
5247860SN/Asimpoint=0
5257860SN/Asystem=system
5267860SN/Auid=100
5277860SN/A
5287860SN/A[system.membus]
5297860SN/Atype=Bus
5307860SN/Ablock_size=64
5317860SN/Abus_id=0
5327860SN/Aclock=1000
5337860SN/Aheader_cycles=1
5347860SN/Ause_default_range=false
5357860SN/Awidth=64
5368893Ssaidi@eecs.umich.edumaster=system.physmem.port[0]
5378893Ssaidi@eecs.umich.eduslave=system.system_port system.cpu.l2cache.mem_side
5387860SN/A
5397860SN/A[system.physmem]
5407860SN/Atype=PhysicalMemory
5417860SN/Afile=
5427860SN/Alatency=30000
5437860SN/Alatency_var=0
5447860SN/Anull=false
5457860SN/Arange=0:134217727
5467860SN/Azero=false
5478893Ssaidi@eecs.umich.eduport=system.membus.master[0]
5487860SN/A
549