1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 59LFSTSize=1024 60LQEntries=16 61LSQCheckLoads=true 62LSQDepCheckShift=0 63SQEntries=16 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cacheStorePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=2 79decodeWidth=3 80default_p_state=UNDEFINED 81dispatchWidth=6 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dstage2_mmu=system.cpu.dstage2_mmu 86dtb=system.cpu.dtb 87eventq_index=0 88fetchBufferSize=16 89fetchQueueSize=32 90fetchToDecodeDelay=3 91fetchTrapLatency=1 92fetchWidth=3 93forwardComSize=5 94fuPool=system.cpu.fuPool 95function_trace=false 96function_trace_start=0 97iewToCommitDelay=1 98iewToDecodeDelay=1 99iewToFetchDelay=1 100iewToRenameDelay=1 101interrupts=system.cpu.interrupts 102isa=system.cpu.isa 103issueToExecuteDelay=1 104issueWidth=8 105istage2_mmu=system.cpu.istage2_mmu 106itb=system.cpu.itb 107max_insts_all_threads=0 108max_insts_any_thread=0 109max_loads_all_threads=0 110max_loads_any_thread=0 111needsTSO=false 112numIQEntries=32 113numPhysCCRegs=640 114numPhysFloatRegs=192 115numPhysIntRegs=128 116numROBEntries=40 117numRobs=1 118numThreads=1 119p_state_clk_gate_bins=20 120p_state_clk_gate_max=1000000000000 121p_state_clk_gate_min=1000 122power_model=Null 123profile=0 124progress_interval=0 125renameToDecodeDelay=1 126renameToFetchDelay=1 127renameToIEWDelay=1 128renameToROBDelay=1 129renameWidth=3 130simpoint_start_insts= 131smtCommitPolicy=RoundRobin 132smtFetchPolicy=SingleThread 133smtIQPolicy=Partitioned 134smtIQThreshold=100 135smtLSQPolicy=Partitioned 136smtLSQThreshold=100 137smtNumFetchingThreads=1 138smtROBPolicy=Partitioned 139smtROBThreshold=100 140socket_id=0 141squashWidth=8 142store_set_clear_period=250000 143switched_out=false 144syscallRetryLatency=10000 145system=system 146tracer=system.cpu.tracer 147trapLatency=13 148wbWidth=8 149workload=system.cpu.workload 150dcache_port=system.cpu.dcache.cpu_side 151icache_port=system.cpu.icache.cpu_side 152 153[system.cpu.branchPred] 154type=BiModeBP 155BTBEntries=2048 156BTBTagSize=18 157RASSize=16 158choiceCtrBits=2 159choicePredictorSize=8192 160eventq_index=0 161globalCtrBits=2 162globalPredictorSize=8192 163indirectHashGHR=true 164indirectHashTargets=true 165indirectPathLength=3 166indirectSets=256 167indirectTagSize=16 168indirectWays=2 169instShiftAmt=2 170numThreads=1 171useIndirect=true 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl 180data_latency=2 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 184is_read_only=false 185max_miss_count=0 186mshrs=6 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=32768 196system=system 197tag_latency=2 198tags=system.cpu.dcache.tags 199tgts_per_mshr=8 200write_buffers=16 201writeback_clean=true 202cpu_side=system.cpu.dcache_port 203mem_side=system.cpu.toL2Bus.slave[1] 204 205[system.cpu.dcache.tags] 206type=LRU 207assoc=2 208block_size=64 209clk_domain=system.cpu_clk_domain 210data_latency=2 211default_p_state=UNDEFINED 212eventq_index=0 213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=32768 219tag_latency=2 220 221[system.cpu.dstage2_mmu] 222type=ArmStage2MMU 223children=stage2_tlb 224eventq_index=0 225stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 226sys=system 227tlb=system.cpu.dtb 228 229[system.cpu.dstage2_mmu.stage2_tlb] 230type=ArmTLB 231children=walker 232eventq_index=0 233is_stage2=true 234size=32 235walker=system.cpu.dstage2_mmu.stage2_tlb.walker 236 237[system.cpu.dstage2_mmu.stage2_tlb.walker] 238type=ArmTableWalker 239clk_domain=system.cpu_clk_domain 240default_p_state=UNDEFINED 241eventq_index=0 242is_stage2=true 243num_squash_per_cycle=2 244p_state_clk_gate_bins=20 245p_state_clk_gate_max=1000000000000 246p_state_clk_gate_min=1000 247power_model=Null 248sys=system 249 250[system.cpu.dtb] 251type=ArmTLB 252children=walker 253eventq_index=0 254is_stage2=false 255size=64 256walker=system.cpu.dtb.walker 257 258[system.cpu.dtb.walker] 259type=ArmTableWalker 260clk_domain=system.cpu_clk_domain 261default_p_state=UNDEFINED 262eventq_index=0 263is_stage2=false 264num_squash_per_cycle=2 265p_state_clk_gate_bins=20 266p_state_clk_gate_max=1000000000000 267p_state_clk_gate_min=1000 268power_model=Null 269sys=system 270port=system.cpu.toL2Bus.slave[3] 271 272[system.cpu.fuPool] 273type=FUPool 274children=FUList0 FUList1 FUList2 FUList3 FUList4 275FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 276eventq_index=0 277 278[system.cpu.fuPool.FUList0] 279type=FUDesc 280children=opList 281count=2 282eventq_index=0 283opList=system.cpu.fuPool.FUList0.opList 284 285[system.cpu.fuPool.FUList0.opList] 286type=OpDesc 287eventq_index=0 288opClass=IntAlu 289opLat=1 290pipelined=true 291 292[system.cpu.fuPool.FUList1] 293type=FUDesc 294children=opList0 opList1 opList2 295count=1 296eventq_index=0 297opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 298 299[system.cpu.fuPool.FUList1.opList0] 300type=OpDesc 301eventq_index=0 302opClass=IntMult 303opLat=3 304pipelined=true 305 306[system.cpu.fuPool.FUList1.opList1] 307type=OpDesc 308eventq_index=0 309opClass=IntDiv 310opLat=12 311pipelined=false 312 313[system.cpu.fuPool.FUList1.opList2] 314type=OpDesc 315eventq_index=0 316opClass=IprAccess 317opLat=3 318pipelined=true 319 320[system.cpu.fuPool.FUList2] 321type=FUDesc 322children=opList0 opList1 323count=1 324eventq_index=0 325opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 326 327[system.cpu.fuPool.FUList2.opList0] 328type=OpDesc 329eventq_index=0 330opClass=MemRead 331opLat=2 332pipelined=true 333 334[system.cpu.fuPool.FUList2.opList1] 335type=OpDesc 336eventq_index=0 337opClass=FloatMemRead 338opLat=2 339pipelined=true 340 341[system.cpu.fuPool.FUList3] 342type=FUDesc 343children=opList0 opList1 344count=1 345eventq_index=0 346opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 347 348[system.cpu.fuPool.FUList3.opList0] 349type=OpDesc 350eventq_index=0 351opClass=MemWrite 352opLat=2 353pipelined=true 354 355[system.cpu.fuPool.FUList3.opList1] 356type=OpDesc 357eventq_index=0 358opClass=FloatMemWrite 359opLat=2 360pipelined=true 361 362[system.cpu.fuPool.FUList4] 363type=FUDesc 364children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 365count=2 366eventq_index=0 367opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 368 369[system.cpu.fuPool.FUList4.opList00] 370type=OpDesc 371eventq_index=0 372opClass=SimdAdd 373opLat=4 374pipelined=true 375 376[system.cpu.fuPool.FUList4.opList01] 377type=OpDesc 378eventq_index=0 379opClass=SimdAddAcc 380opLat=4 381pipelined=true 382 383[system.cpu.fuPool.FUList4.opList02] 384type=OpDesc 385eventq_index=0 386opClass=SimdAlu 387opLat=4 388pipelined=true 389 390[system.cpu.fuPool.FUList4.opList03] 391type=OpDesc 392eventq_index=0 393opClass=SimdCmp 394opLat=4 395pipelined=true 396 397[system.cpu.fuPool.FUList4.opList04] 398type=OpDesc 399eventq_index=0 400opClass=SimdCvt 401opLat=3 402pipelined=true 403 404[system.cpu.fuPool.FUList4.opList05] 405type=OpDesc 406eventq_index=0 407opClass=SimdMisc 408opLat=3 409pipelined=true 410 411[system.cpu.fuPool.FUList4.opList06] 412type=OpDesc 413eventq_index=0 414opClass=SimdMult 415opLat=5 416pipelined=true 417 418[system.cpu.fuPool.FUList4.opList07] 419type=OpDesc 420eventq_index=0 421opClass=SimdMultAcc 422opLat=5 423pipelined=true 424 425[system.cpu.fuPool.FUList4.opList08] 426type=OpDesc 427eventq_index=0 428opClass=SimdShift 429opLat=3 430pipelined=true 431 432[system.cpu.fuPool.FUList4.opList09] 433type=OpDesc 434eventq_index=0 435opClass=SimdShiftAcc 436opLat=3 437pipelined=true 438 439[system.cpu.fuPool.FUList4.opList10] 440type=OpDesc 441eventq_index=0 442opClass=SimdSqrt 443opLat=9 444pipelined=true 445 446[system.cpu.fuPool.FUList4.opList11] 447type=OpDesc 448eventq_index=0 449opClass=SimdFloatAdd 450opLat=5 451pipelined=true 452 453[system.cpu.fuPool.FUList4.opList12] 454type=OpDesc 455eventq_index=0 456opClass=SimdFloatAlu 457opLat=5 458pipelined=true 459 460[system.cpu.fuPool.FUList4.opList13] 461type=OpDesc 462eventq_index=0 463opClass=SimdFloatCmp 464opLat=3 465pipelined=true 466 467[system.cpu.fuPool.FUList4.opList14] 468type=OpDesc 469eventq_index=0 470opClass=SimdFloatCvt 471opLat=3 472pipelined=true 473 474[system.cpu.fuPool.FUList4.opList15] 475type=OpDesc 476eventq_index=0 477opClass=SimdFloatDiv 478opLat=3 479pipelined=true 480 481[system.cpu.fuPool.FUList4.opList16] 482type=OpDesc 483eventq_index=0 484opClass=SimdFloatMisc 485opLat=3 486pipelined=true 487 488[system.cpu.fuPool.FUList4.opList17] 489type=OpDesc 490eventq_index=0 491opClass=SimdFloatMult 492opLat=3 493pipelined=true 494 495[system.cpu.fuPool.FUList4.opList18] 496type=OpDesc 497eventq_index=0 498opClass=SimdFloatMultAcc 499opLat=5 500pipelined=true 501 502[system.cpu.fuPool.FUList4.opList19] 503type=OpDesc 504eventq_index=0 505opClass=SimdFloatSqrt 506opLat=9 507pipelined=true 508 509[system.cpu.fuPool.FUList4.opList20] 510type=OpDesc 511eventq_index=0 512opClass=FloatAdd 513opLat=5 514pipelined=true 515 516[system.cpu.fuPool.FUList4.opList21] 517type=OpDesc 518eventq_index=0 519opClass=FloatCmp 520opLat=5 521pipelined=true 522 523[system.cpu.fuPool.FUList4.opList22] 524type=OpDesc 525eventq_index=0 526opClass=FloatCvt 527opLat=5 528pipelined=true 529 530[system.cpu.fuPool.FUList4.opList23] 531type=OpDesc 532eventq_index=0 533opClass=FloatDiv 534opLat=9 535pipelined=false 536 537[system.cpu.fuPool.FUList4.opList24] 538type=OpDesc 539eventq_index=0 540opClass=FloatSqrt 541opLat=33 542pipelined=false 543 544[system.cpu.fuPool.FUList4.opList25] 545type=OpDesc 546eventq_index=0 547opClass=FloatMult 548opLat=4 549pipelined=true 550 551[system.cpu.fuPool.FUList4.opList26] 552type=OpDesc 553eventq_index=0 554opClass=FloatMultAcc 555opLat=5 556pipelined=true 557 558[system.cpu.fuPool.FUList4.opList27] 559type=OpDesc 560eventq_index=0 561opClass=FloatMisc 562opLat=3 563pipelined=true 564 565[system.cpu.icache] 566type=Cache 567children=tags 568addr_ranges=0:18446744073709551615:0:0:0:0 569assoc=2 570clk_domain=system.cpu_clk_domain 571clusivity=mostly_incl 572data_latency=1 573default_p_state=UNDEFINED 574demand_mshr_reserve=1 575eventq_index=0 576is_read_only=true 577max_miss_count=0 578mshrs=2 579p_state_clk_gate_bins=20 580p_state_clk_gate_max=1000000000000 581p_state_clk_gate_min=1000 582power_model=Null 583prefetch_on_access=false 584prefetcher=Null 585response_latency=1 586sequential_access=false 587size=32768 588system=system 589tag_latency=1 590tags=system.cpu.icache.tags 591tgts_per_mshr=8 592write_buffers=8 593writeback_clean=true 594cpu_side=system.cpu.icache_port 595mem_side=system.cpu.toL2Bus.slave[0] 596 597[system.cpu.icache.tags] 598type=LRU 599assoc=2 600block_size=64 601clk_domain=system.cpu_clk_domain 602data_latency=1 603default_p_state=UNDEFINED 604eventq_index=0 605p_state_clk_gate_bins=20 606p_state_clk_gate_max=1000000000000 607p_state_clk_gate_min=1000 608power_model=Null 609sequential_access=false 610size=32768 611tag_latency=1 612 613[system.cpu.interrupts] 614type=ArmInterrupts 615eventq_index=0 616 617[system.cpu.isa] 618type=ArmISA 619decoderFlavour=Generic 620eventq_index=0 621fpsid=1090793632 622id_aa64afr0_el1=0 623id_aa64afr1_el1=0 624id_aa64dfr0_el1=1052678 625id_aa64dfr1_el1=0 626id_aa64isar0_el1=0 627id_aa64isar1_el1=0 628id_aa64mmfr0_el1=15728642 629id_aa64mmfr1_el1=0 630id_isar0=34607377 631id_isar1=34677009 632id_isar2=555950401 633id_isar3=17899825 634id_isar4=268501314 635id_isar5=0 636id_mmfr0=270536963 637id_mmfr1=0 638id_mmfr2=19070976 639id_mmfr3=34611729 640midr=1091551472 641pmu=Null 642system=system 643 644[system.cpu.istage2_mmu] 645type=ArmStage2MMU 646children=stage2_tlb 647eventq_index=0 648stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 649sys=system 650tlb=system.cpu.itb 651 652[system.cpu.istage2_mmu.stage2_tlb] 653type=ArmTLB 654children=walker 655eventq_index=0 656is_stage2=true 657size=32 658walker=system.cpu.istage2_mmu.stage2_tlb.walker 659 660[system.cpu.istage2_mmu.stage2_tlb.walker] 661type=ArmTableWalker 662clk_domain=system.cpu_clk_domain 663default_p_state=UNDEFINED 664eventq_index=0 665is_stage2=true 666num_squash_per_cycle=2 667p_state_clk_gate_bins=20 668p_state_clk_gate_max=1000000000000 669p_state_clk_gate_min=1000 670power_model=Null 671sys=system 672 673[system.cpu.itb] 674type=ArmTLB 675children=walker 676eventq_index=0 677is_stage2=false 678size=64 679walker=system.cpu.itb.walker 680 681[system.cpu.itb.walker] 682type=ArmTableWalker 683clk_domain=system.cpu_clk_domain 684default_p_state=UNDEFINED 685eventq_index=0 686is_stage2=false 687num_squash_per_cycle=2 688p_state_clk_gate_bins=20 689p_state_clk_gate_max=1000000000000 690p_state_clk_gate_min=1000 691power_model=Null 692sys=system 693port=system.cpu.toL2Bus.slave[2] 694 695[system.cpu.l2cache] 696type=Cache 697children=prefetcher tags 698addr_ranges=0:18446744073709551615:0:0:0:0 699assoc=16 700clk_domain=system.cpu_clk_domain 701clusivity=mostly_excl 702data_latency=12 703default_p_state=UNDEFINED 704demand_mshr_reserve=1 705eventq_index=0 706is_read_only=false 707max_miss_count=0 708mshrs=16 709p_state_clk_gate_bins=20 710p_state_clk_gate_max=1000000000000 711p_state_clk_gate_min=1000 712power_model=Null 713prefetch_on_access=true 714prefetcher=system.cpu.l2cache.prefetcher 715response_latency=12 716sequential_access=false 717size=1048576 718system=system 719tag_latency=12 720tags=system.cpu.l2cache.tags 721tgts_per_mshr=8 722write_buffers=8 723writeback_clean=false 724cpu_side=system.cpu.toL2Bus.master[0] 725mem_side=system.membus.slave[1] 726 727[system.cpu.l2cache.prefetcher] 728type=StridePrefetcher 729cache_snoop=false 730clk_domain=system.cpu_clk_domain 731default_p_state=UNDEFINED 732degree=8 733eventq_index=0 734latency=1 735max_conf=7 736min_conf=0 737on_data=true 738on_inst=true 739on_miss=false 740on_read=true 741on_write=true 742p_state_clk_gate_bins=20 743p_state_clk_gate_max=1000000000000 744p_state_clk_gate_min=1000 745power_model=Null 746queue_filter=true 747queue_size=32 748queue_squash=true 749start_conf=4 750sys=system 751table_assoc=4 752table_sets=16 753tag_prefetch=true 754thresh_conf=4 755use_master_id=true 756 757[system.cpu.l2cache.tags] 758type=RandomRepl 759assoc=16 760block_size=64 761clk_domain=system.cpu_clk_domain 762data_latency=12 763default_p_state=UNDEFINED 764eventq_index=0 765p_state_clk_gate_bins=20 766p_state_clk_gate_max=1000000000000 767p_state_clk_gate_min=1000 768power_model=Null 769sequential_access=false 770size=1048576 771tag_latency=12 772 773[system.cpu.toL2Bus] 774type=CoherentXBar 775children=snoop_filter 776clk_domain=system.cpu_clk_domain 777default_p_state=UNDEFINED 778eventq_index=0 779forward_latency=0 780frontend_latency=1 781p_state_clk_gate_bins=20 782p_state_clk_gate_max=1000000000000 783p_state_clk_gate_min=1000 784point_of_coherency=false 785power_model=Null 786response_latency=1 787snoop_filter=system.cpu.toL2Bus.snoop_filter 788snoop_response_latency=1 789system=system 790use_default_range=false 791width=32 792master=system.cpu.l2cache.cpu_side 793slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 794 795[system.cpu.toL2Bus.snoop_filter] 796type=SnoopFilter 797eventq_index=0 798lookup_latency=0 799max_capacity=8388608 800system=system 801 802[system.cpu.tracer] 803type=ExeTracer 804eventq_index=0 805 806[system.cpu.workload] 807type=Process 808cmd=twolf smred 809cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing 810drivers= 811egid=100 812env= 813errout=cerr 814euid=100 815eventq_index=0 816executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf 817gid=100 818input=cin 819kvmInSE=false 820maxStackSize=67108864 821output=cout 822pgid=100 823pid=100 824ppid=0 825simpoint=0 826system=system 827uid=100 828useArchPT=false 829 830[system.cpu_clk_domain] 831type=SrcClockDomain 832clock=500 833domain_id=-1 834eventq_index=0 835init_perf_level=0 836voltage_domain=system.voltage_domain 837 838[system.dvfs_handler] 839type=DVFSHandler 840domains= 841enable=false 842eventq_index=0 843sys_clk_domain=system.clk_domain 844transition_latency=100000000 845 846[system.membus] 847type=CoherentXBar 848children=snoop_filter 849clk_domain=system.clk_domain 850default_p_state=UNDEFINED 851eventq_index=0 852forward_latency=4 853frontend_latency=3 854p_state_clk_gate_bins=20 855p_state_clk_gate_max=1000000000000 856p_state_clk_gate_min=1000 857point_of_coherency=true 858power_model=Null 859response_latency=2 860snoop_filter=system.membus.snoop_filter 861snoop_response_latency=4 862system=system 863use_default_range=false 864width=16 865master=system.physmem.port 866slave=system.system_port system.cpu.l2cache.mem_side 867 868[system.membus.snoop_filter] 869type=SnoopFilter 870eventq_index=0 871lookup_latency=1 872max_capacity=8388608 873system=system 874 875[system.physmem] 876type=DRAMCtrl 877IDD0=0.055000 878IDD02=0.000000 879IDD2N=0.032000 880IDD2N2=0.000000 881IDD2P0=0.000000 882IDD2P02=0.000000 883IDD2P1=0.032000 884IDD2P12=0.000000 885IDD3N=0.038000 886IDD3N2=0.000000 887IDD3P0=0.000000 888IDD3P02=0.000000 889IDD3P1=0.038000 890IDD3P12=0.000000 891IDD4R=0.157000 892IDD4R2=0.000000 893IDD4W=0.125000 894IDD4W2=0.000000 895IDD5=0.235000 896IDD52=0.000000 897IDD6=0.020000 898IDD62=0.000000 899VDD=1.500000 900VDD2=0.000000 901activation_limit=4 902addr_mapping=RoRaBaCoCh 903bank_groups_per_rank=0 904banks_per_rank=8 905burst_length=8 906channels=1 907clk_domain=system.clk_domain 908conf_table_reported=true 909default_p_state=UNDEFINED 910device_bus_width=8 911device_rowbuffer_size=1024 912device_size=536870912 913devices_per_rank=8 914dll=true 915eventq_index=0 916in_addr_map=true 917kvm_map=true 918max_accesses_per_row=16 919mem_sched_policy=frfcfs 920min_writes_per_switch=16 921null=false 922p_state_clk_gate_bins=20 923p_state_clk_gate_max=1000000000000 924p_state_clk_gate_min=1000 925page_policy=open_adaptive 926power_model=Null 927range=0:134217727:0:0:0:0 928ranks_per_channel=2 929read_buffer_size=32 930static_backend_latency=10000 931static_frontend_latency=10000 932tBURST=5000 933tCCD_L=0 934tCK=1250 935tCL=13750 936tCS=2500 937tRAS=35000 938tRCD=13750 939tREFI=7800000 940tRFC=260000 941tRP=13750 942tRRD=6000 943tRRD_L=0 944tRTP=7500 945tRTW=2500 946tWR=15000 947tWTR=7500 948tXAW=30000 949tXP=6000 950tXPDLL=0 951tXS=270000 952tXSDLL=0 953write_buffer_size=64 954write_high_thresh_perc=85 955write_low_thresh_perc=50 956port=system.membus.master[0] 957 958[system.voltage_domain] 959type=VoltageDomain 960eventq_index=0 961voltage=1.000000 962 963