config.ini revision 10798
12SN/A[root] 22188SN/Atype=Root 32SN/Achildren=system 42SN/Aeventq_index=0 52SN/Afull_system=false 62SN/Asim_quantum=0 72SN/Atime_sync_enable=false 82SN/Atime_sync_period=100000000000 92SN/Atime_sync_spin_threshold=100000000 102SN/A 112SN/A[system] 122SN/Atype=System 132SN/Achildren=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 142SN/Aboot_osflags=a 152SN/Acache_line_size=64 162SN/Aclk_domain=system.clk_domain 172SN/Aeventq_index=0 182SN/Ainit_param=0 192SN/Akernel= 202SN/Akernel_addr_check=true 212SN/Aload_addr_mask=1099511627775 222SN/Aload_offset=0 232SN/Amem_mode=timing 242SN/Amem_ranges= 252SN/Amemories=system.physmem 262SN/Ammap_using_noreserve=false 272665SN/Anum_work_ids=16 282665SN/Areadfile= 292665SN/Asymbolfile= 302665SN/Awork_begin_ckpt_count=0 312665SN/Awork_begin_cpu_id_exit=-1 322SN/Awork_begin_exit_count=0 332SN/Awork_cpus_ckpt_count=0 342SN/Awork_end_ckpt_count=0 352SN/Awork_end_exit_count=0 362465SN/Awork_item_id=-1 377680Sgblack@eecs.umich.edusystem_port=system.membus.slave[0] 386658Snate@binkert.org 391717SN/A[system.clk_domain] 402683Sktlim@umich.edutype=SrcClockDomain 412680SN/Aclock=1000 428761Sgblack@eecs.umich.edudomain_id=-1 435529Snate@binkert.orgeventq_index=0 442SN/Ainit_perf_level=0 451858SN/Avoltage_domain=system.voltage_domain 463565Sgblack@eecs.umich.edu 475529Snate@binkert.org[system.cpu] 481917SN/Atype=DerivO3CPU 491070SN/Achildren=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 501917SN/ALFSTSize=1024 512188SN/ALQEntries=16 521917SN/ALSQCheckLoads=true 532290SN/ALSQDepCheckShift=0 541070SN/ASQEntries=16 551917SN/ASSITSize=1024 562SN/Aactivity=0 575529Snate@binkert.orgbackComSize=5 58360SN/AbranchPred=system.cpu.branchPred 592519SN/AcachePorts=200 602SN/Achecker=Null 612SN/Aclk_domain=system.cpu_clk_domain 622SN/AcommitToDecodeDelay=1 632SN/AcommitToFetchDelay=1 642SN/AcommitToIEWDelay=1 651858SN/AcommitToRenameDelay=1 662683Sktlim@umich.educommitWidth=8 676022Sgblack@eecs.umich.educpu_id=0 682683Sktlim@umich.edudecodeToFetchDelay=1 696324Sgblack@eecs.umich.edudecodeToRenameDelay=2 706324Sgblack@eecs.umich.edudecodeWidth=3 712521SN/AdispatchWidth=6 722SN/Ado_checkpoint_insts=true 732683Sktlim@umich.edudo_quiesce=true 742190SN/Ado_statistics_insts=true 752680SN/Adstage2_mmu=system.cpu.dstage2_mmu 762290SN/Adtb=system.cpu.dtb 776316Sgblack@eecs.umich.edueventq_index=0 781917SN/AfetchBufferSize=16 795529Snate@binkert.orgfetchQueueSize=32 801982SN/AfetchToDecodeDelay=3 811917SN/AfetchTrapLatency=1 822683Sktlim@umich.edufetchWidth=3 832683Sktlim@umich.eduforwardComSize=5 841917SN/AfuPool=system.cpu.fuPool 851917SN/Afunction_trace=false 861917SN/Afunction_trace_start=0 871917SN/AiewToCommitDelay=1 881917SN/AiewToDecodeDelay=1 891917SN/AiewToFetchDelay=1 901917SN/AiewToRenameDelay=1 911917SN/Ainterrupts=system.cpu.interrupts 922521SN/Aisa=system.cpu.isa 935482Snate@binkert.orgissueToExecuteDelay=1 943548Sgblack@eecs.umich.eduissueWidth=8 952SN/Aistage2_mmu=system.cpu.istage2_mmu 962SN/Aitb=system.cpu.itb 974997Sgblack@eecs.umich.edumax_insts_all_threads=0 986331Sgblack@eecs.umich.edumax_insts_any_thread=0 996331Sgblack@eecs.umich.edumax_loads_all_threads=0 1004997Sgblack@eecs.umich.edumax_loads_any_thread=0 1012SN/AneedsTSO=false 1026316Sgblack@eecs.umich.edunumIQEntries=32 1032683Sktlim@umich.edunumPhysCCRegs=640 1042SN/AnumPhysFloatRegs=192 1052190SN/AnumPhysIntRegs=128 1062862Sktlim@umich.edunumROBEntries=40 1072862Sktlim@umich.edunumRobs=1 1082864Sktlim@umich.edunumThreads=1 1092862Sktlim@umich.eduprofile=0 1105712Shsul@eecs.umich.eduprogress_interval=0 1112862Sktlim@umich.edurenameToDecodeDelay=1 1126331Sgblack@eecs.umich.edurenameToFetchDelay=1 1132862Sktlim@umich.edurenameToIEWDelay=1 1142190SN/ArenameToROBDelay=1 1152683Sktlim@umich.edurenameWidth=3 1162190SN/Asimpoint_start_insts= 1172190SN/AsmtCommitPolicy=RoundRobin 1182683Sktlim@umich.edusmtFetchPolicy=SingleThread 1191070SN/AsmtIQPolicy=Partitioned 1208754Sgblack@eecs.umich.edusmtIQThreshold=100 1213486Sktlim@umich.edusmtLSQPolicy=Partitioned 1222680SN/AsmtLSQThreshold=100 1231070SN/AsmtNumFetchingThreads=1 1241070SN/AsmtROBPolicy=Partitioned 1251917SN/AsmtROBThreshold=100 1262683Sktlim@umich.edusocket_id=0 127180SN/AsquashWidth=8 128180SN/Astore_set_clear_period=250000 1291858SN/Aswitched_out=false 1302235SN/Asystem=system 131180SN/Atracer=system.cpu.tracer 1322235SN/AtrapLatency=13 133180SN/AwbWidth=8 134180SN/Aworkload=system.cpu.workload 1352862Sktlim@umich.edudcache_port=system.cpu.dcache.cpu_side 1362862Sktlim@umich.eduicache_port=system.cpu.icache.cpu_side 1372313SN/A 1382313SN/A[system.cpu.branchPred] 1392680SN/Atype=BiModeBP 1402313SN/ABTBEntries=2048 1412680SN/ABTBTagSize=18 1422313SN/ARASSize=16 1432313SN/AchoiceCtrBits=2 1442680SN/AchoicePredictorSize=8192 1452313SN/Aeventq_index=0 1462361SN/AglobalCtrBits=2 1473548Sgblack@eecs.umich.eduglobalPredictorSize=8192 1482361SN/AinstShiftAmt=2 1492361SN/AnumThreads=1 1502361SN/A 1512235SN/A[system.cpu.dcache] 152180SN/Atype=BaseCache 153180SN/Achildren=tags 154180SN/Aaddr_ranges=0:18446744073709551615 1556029Ssteve.reinhardt@amd.comassoc=2 156180SN/Aclk_domain=system.cpu_clk_domain 157180SN/Ademand_mshr_reserve=1 1582SN/Aeventq_index=0 1592864Sktlim@umich.eduforward_snoops=true 1602864Sktlim@umich.eduhit_latency=2 1612864Sktlim@umich.eduis_top_level=true 1622864Sktlim@umich.edumax_miss_count=0 1632864Sktlim@umich.edumshrs=6 1642864Sktlim@umich.eduprefetch_on_access=false 1652864Sktlim@umich.eduprefetcher=Null 1662864Sktlim@umich.eduresponse_latency=2 1672864Sktlim@umich.edusequential_access=false 1683548Sgblack@eecs.umich.edusize=32768 1692864Sktlim@umich.edusystem=system 1702864Sktlim@umich.edutags=system.cpu.dcache.tags 1712864Sktlim@umich.edutgts_per_mshr=8 1722864Sktlim@umich.edutwo_queue=false 1732864Sktlim@umich.eduwrite_buffers=16 1742864Sktlim@umich.educpu_side=system.cpu.dcache_port 1752864Sktlim@umich.edumem_side=system.cpu.toL2Bus.slave[1] 1762862Sktlim@umich.edu 1772862Sktlim@umich.edu[system.cpu.dcache.tags] 1782862Sktlim@umich.edutype=LRU 1792862Sktlim@umich.eduassoc=2 1802862Sktlim@umich.edublock_size=64 1812862Sktlim@umich.educlk_domain=system.cpu_clk_domain 1822862Sktlim@umich.edueventq_index=0 1832862Sktlim@umich.eduhit_latency=2 1845714Shsul@eecs.umich.edusequential_access=false 1855715Shsul@eecs.umich.edusize=32768 1865714Shsul@eecs.umich.edu 1872862Sktlim@umich.edu[system.cpu.dstage2_mmu] 1882862Sktlim@umich.edutype=ArmStage2MMU 1892862Sktlim@umich.educhildren=stage2_tlb 1902683Sktlim@umich.edueventq_index=0 191217SN/Astage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 1922862Sktlim@umich.edusys=system 1936315Sgblack@eecs.umich.edutlb=system.cpu.dtb 1946316Sgblack@eecs.umich.edu 1957720Sgblack@eecs.umich.edu[system.cpu.dstage2_mmu.stage2_tlb] 196223SN/Atype=ArmTLB 1976677SBrad.Beckmann@amd.comchildren=walker 1986677SBrad.Beckmann@amd.comeventq_index=0 1996677SBrad.Beckmann@amd.comis_stage2=true 2006677SBrad.Beckmann@amd.comsize=32 2016678Sgblack@eecs.umich.eduwalker=system.cpu.dstage2_mmu.stage2_tlb.walker 202217SN/A 203217SN/A[system.cpu.dstage2_mmu.stage2_tlb.walker] 204217SN/Atype=ArmTableWalker 205217SN/Aclk_domain=system.cpu_clk_domain 2062683Sktlim@umich.edueventq_index=0 207217SN/Ais_stage2=true 2082862Sktlim@umich.edunum_squash_per_cycle=2 2096315Sgblack@eecs.umich.edusys=system 2106316Sgblack@eecs.umich.edu 2117720Sgblack@eecs.umich.edu[system.cpu.dtb] 212223SN/Atype=ArmTLB 2136677SBrad.Beckmann@amd.comchildren=walker 2146677SBrad.Beckmann@amd.comeventq_index=0 2156677SBrad.Beckmann@amd.comis_stage2=false 2166677SBrad.Beckmann@amd.comsize=64 2176678Sgblack@eecs.umich.eduwalker=system.cpu.dtb.walker 218217SN/A 219217SN/A[system.cpu.dtb.walker] 2202683Sktlim@umich.edutype=ArmTableWalker 2212683Sktlim@umich.educlk_domain=system.cpu_clk_domain 2222683Sktlim@umich.edueventq_index=0 2232683Sktlim@umich.eduis_stage2=false 2242683Sktlim@umich.edunum_squash_per_cycle=2 2252683Sktlim@umich.edusys=system 2262683Sktlim@umich.eduport=system.cpu.toL2Bus.slave[3] 2272683Sktlim@umich.edu 228217SN/A[system.cpu.fuPool] 229217SN/Atype=FUPool 2302683Sktlim@umich.educhildren=FUList0 FUList1 FUList2 FUList3 FUList4 2312SN/AFUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 2322680SN/Aeventq_index=0 2332SN/A 2342SN/A[system.cpu.fuPool.FUList0] 2357823Ssteve.reinhardt@amd.comtype=FUDesc 2362188SN/Achildren=opList 2374400Srdreslin@umich.educount=2 2385715Shsul@eecs.umich.edueventq_index=0 2395543Ssaidi@eecs.umich.eduopList=system.cpu.fuPool.FUList0.opList 2404400Srdreslin@umich.edu 2412290SN/A[system.cpu.fuPool.FUList0.opList] 2422680SN/Atype=OpDesc 2432290SN/Aeventq_index=0 2442290SN/AissueLat=1 2455715Shsul@eecs.umich.eduopClass=IntAlu 246393SN/AopLat=1 247393SN/A 248393SN/A[system.cpu.fuPool.FUList1] 2492683Sktlim@umich.edutype=FUDesc 250393SN/Achildren=opList0 opList1 opList2 2512680SN/Acount=1 252393SN/Aeventq_index=0 253393SN/AopList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 2547823Ssteve.reinhardt@amd.com 2557823Ssteve.reinhardt@amd.com[system.cpu.fuPool.FUList1.opList0] 2562188SN/Atype=OpDesc 2571858SN/Aeventq_index=0 2582SN/AissueLat=1 2595704Snate@binkert.orgopClass=IntMult 2602680SN/AopLat=3 2612SN/A 2622SN/A[system.cpu.fuPool.FUList1.opList1] 2632SN/Atype=OpDesc 2642188SN/Aeventq_index=0 2652680SN/AissueLat=12 2665715Shsul@eecs.umich.eduopClass=IntDiv 2672SN/AopLat=12 2682SN/A 269393SN/A[system.cpu.fuPool.FUList1.opList2] 270393SN/Atype=OpDesc 2712683Sktlim@umich.edueventq_index=0 272393SN/AissueLat=1 2732680SN/AopClass=IprAccess 274393SN/AopLat=3 275393SN/A 2762680SN/A[system.cpu.fuPool.FUList2] 2775715Shsul@eecs.umich.edutype=FUDesc 278393SN/Achildren=opList 279393SN/Acount=1 280393SN/Aeventq_index=0 281393SN/AopList=system.cpu.fuPool.FUList2.opList 2822683Sktlim@umich.edu 2832SN/A[system.cpu.fuPool.FUList2.opList] 2842330SN/Atype=OpDesc 2852341SN/Aeventq_index=0 2862341SN/AissueLat=1 2872330SN/AopClass=MemRead 2882SN/AopLat=2 289716SN/A 290716SN/A[system.cpu.fuPool.FUList3] 2912683Sktlim@umich.edutype=FUDesc 2922190SN/Achildren=opList 2932680SN/Acount=1 2942190SN/Aeventq_index=0 2952190SN/AopList=system.cpu.fuPool.FUList3.opList 296 297[system.cpu.fuPool.FUList3.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=MemWrite 302opLat=2 303 304[system.cpu.fuPool.FUList4] 305type=FUDesc 306children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 307count=2 308eventq_index=0 309opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 310 311[system.cpu.fuPool.FUList4.opList00] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=SimdAdd 316opLat=4 317 318[system.cpu.fuPool.FUList4.opList01] 319type=OpDesc 320eventq_index=0 321issueLat=1 322opClass=SimdAddAcc 323opLat=4 324 325[system.cpu.fuPool.FUList4.opList02] 326type=OpDesc 327eventq_index=0 328issueLat=1 329opClass=SimdAlu 330opLat=4 331 332[system.cpu.fuPool.FUList4.opList03] 333type=OpDesc 334eventq_index=0 335issueLat=1 336opClass=SimdCmp 337opLat=4 338 339[system.cpu.fuPool.FUList4.opList04] 340type=OpDesc 341eventq_index=0 342issueLat=1 343opClass=SimdCvt 344opLat=3 345 346[system.cpu.fuPool.FUList4.opList05] 347type=OpDesc 348eventq_index=0 349issueLat=1 350opClass=SimdMisc 351opLat=3 352 353[system.cpu.fuPool.FUList4.opList06] 354type=OpDesc 355eventq_index=0 356issueLat=1 357opClass=SimdMult 358opLat=5 359 360[system.cpu.fuPool.FUList4.opList07] 361type=OpDesc 362eventq_index=0 363issueLat=1 364opClass=SimdMultAcc 365opLat=5 366 367[system.cpu.fuPool.FUList4.opList08] 368type=OpDesc 369eventq_index=0 370issueLat=1 371opClass=SimdShift 372opLat=3 373 374[system.cpu.fuPool.FUList4.opList09] 375type=OpDesc 376eventq_index=0 377issueLat=1 378opClass=SimdShiftAcc 379opLat=3 380 381[system.cpu.fuPool.FUList4.opList10] 382type=OpDesc 383eventq_index=0 384issueLat=1 385opClass=SimdSqrt 386opLat=9 387 388[system.cpu.fuPool.FUList4.opList11] 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=SimdFloatAdd 393opLat=5 394 395[system.cpu.fuPool.FUList4.opList12] 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=SimdFloatAlu 400opLat=5 401 402[system.cpu.fuPool.FUList4.opList13] 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=SimdFloatCmp 407opLat=3 408 409[system.cpu.fuPool.FUList4.opList14] 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdFloatCvt 414opLat=3 415 416[system.cpu.fuPool.FUList4.opList15] 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdFloatDiv 421opLat=3 422 423[system.cpu.fuPool.FUList4.opList16] 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdFloatMisc 428opLat=3 429 430[system.cpu.fuPool.FUList4.opList17] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdFloatMult 435opLat=3 436 437[system.cpu.fuPool.FUList4.opList18] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdFloatMultAcc 442opLat=1 443 444[system.cpu.fuPool.FUList4.opList19] 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdFloatSqrt 449opLat=9 450 451[system.cpu.fuPool.FUList4.opList20] 452type=OpDesc 453eventq_index=0 454issueLat=1 455opClass=FloatAdd 456opLat=5 457 458[system.cpu.fuPool.FUList4.opList21] 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=FloatCmp 463opLat=5 464 465[system.cpu.fuPool.FUList4.opList22] 466type=OpDesc 467eventq_index=0 468issueLat=1 469opClass=FloatCvt 470opLat=5 471 472[system.cpu.fuPool.FUList4.opList23] 473type=OpDesc 474eventq_index=0 475issueLat=9 476opClass=FloatDiv 477opLat=9 478 479[system.cpu.fuPool.FUList4.opList24] 480type=OpDesc 481eventq_index=0 482issueLat=33 483opClass=FloatSqrt 484opLat=33 485 486[system.cpu.fuPool.FUList4.opList25] 487type=OpDesc 488eventq_index=0 489issueLat=1 490opClass=FloatMult 491opLat=4 492 493[system.cpu.icache] 494type=BaseCache 495children=tags 496addr_ranges=0:18446744073709551615 497assoc=2 498clk_domain=system.cpu_clk_domain 499demand_mshr_reserve=1 500eventq_index=0 501forward_snoops=false 502hit_latency=1 503is_top_level=true 504max_miss_count=0 505mshrs=2 506prefetch_on_access=false 507prefetcher=Null 508response_latency=1 509sequential_access=false 510size=32768 511system=system 512tags=system.cpu.icache.tags 513tgts_per_mshr=8 514two_queue=false 515write_buffers=8 516cpu_side=system.cpu.icache_port 517mem_side=system.cpu.toL2Bus.slave[0] 518 519[system.cpu.icache.tags] 520type=LRU 521assoc=2 522block_size=64 523clk_domain=system.cpu_clk_domain 524eventq_index=0 525hit_latency=1 526sequential_access=false 527size=32768 528 529[system.cpu.interrupts] 530type=ArmInterrupts 531eventq_index=0 532 533[system.cpu.isa] 534type=ArmISA 535eventq_index=0 536fpsid=1090793632 537id_aa64afr0_el1=0 538id_aa64afr1_el1=0 539id_aa64dfr0_el1=1052678 540id_aa64dfr1_el1=0 541id_aa64isar0_el1=0 542id_aa64isar1_el1=0 543id_aa64mmfr0_el1=15728642 544id_aa64mmfr1_el1=0 545id_aa64pfr0_el1=17 546id_aa64pfr1_el1=0 547id_isar0=34607377 548id_isar1=34677009 549id_isar2=555950401 550id_isar3=17899825 551id_isar4=268501314 552id_isar5=0 553id_mmfr0=270536963 554id_mmfr1=0 555id_mmfr2=19070976 556id_mmfr3=34611729 557id_pfr0=49 558id_pfr1=4113 559midr=1091551472 560pmu=Null 561system=system 562 563[system.cpu.istage2_mmu] 564type=ArmStage2MMU 565children=stage2_tlb 566eventq_index=0 567stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 568sys=system 569tlb=system.cpu.itb 570 571[system.cpu.istage2_mmu.stage2_tlb] 572type=ArmTLB 573children=walker 574eventq_index=0 575is_stage2=true 576size=32 577walker=system.cpu.istage2_mmu.stage2_tlb.walker 578 579[system.cpu.istage2_mmu.stage2_tlb.walker] 580type=ArmTableWalker 581clk_domain=system.cpu_clk_domain 582eventq_index=0 583is_stage2=true 584num_squash_per_cycle=2 585sys=system 586 587[system.cpu.itb] 588type=ArmTLB 589children=walker 590eventq_index=0 591is_stage2=false 592size=64 593walker=system.cpu.itb.walker 594 595[system.cpu.itb.walker] 596type=ArmTableWalker 597clk_domain=system.cpu_clk_domain 598eventq_index=0 599is_stage2=false 600num_squash_per_cycle=2 601sys=system 602port=system.cpu.toL2Bus.slave[2] 603 604[system.cpu.l2cache] 605type=BaseCache 606children=prefetcher tags 607addr_ranges=0:18446744073709551615 608assoc=16 609clk_domain=system.cpu_clk_domain 610demand_mshr_reserve=1 611eventq_index=0 612forward_snoops=true 613hit_latency=12 614is_top_level=false 615max_miss_count=0 616mshrs=16 617prefetch_on_access=true 618prefetcher=system.cpu.l2cache.prefetcher 619response_latency=12 620sequential_access=false 621size=1048576 622system=system 623tags=system.cpu.l2cache.tags 624tgts_per_mshr=8 625two_queue=false 626write_buffers=8 627cpu_side=system.cpu.toL2Bus.master[0] 628mem_side=system.membus.slave[1] 629 630[system.cpu.l2cache.prefetcher] 631type=StridePrefetcher 632cache_snoop=false 633clk_domain=system.cpu_clk_domain 634degree=8 635eventq_index=0 636latency=1 637max_conf=7 638min_conf=0 639on_data=true 640on_inst=true 641on_miss=false 642on_read=true 643on_write=true 644queue_filter=true 645queue_size=32 646queue_squash=true 647start_conf=4 648sys=system 649table_assoc=4 650table_sets=16 651tag_prefetch=true 652thresh_conf=4 653use_master_id=true 654 655[system.cpu.l2cache.tags] 656type=RandomRepl 657assoc=16 658block_size=64 659clk_domain=system.cpu_clk_domain 660eventq_index=0 661hit_latency=12 662sequential_access=false 663size=1048576 664 665[system.cpu.toL2Bus] 666type=CoherentXBar 667clk_domain=system.cpu_clk_domain 668eventq_index=0 669forward_latency=0 670frontend_latency=1 671response_latency=1 672snoop_filter=Null 673snoop_response_latency=1 674system=system 675use_default_range=false 676width=32 677master=system.cpu.l2cache.cpu_side 678slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 679 680[system.cpu.tracer] 681type=ExeTracer 682eventq_index=0 683 684[system.cpu.workload] 685type=LiveProcess 686cmd=twolf smred 687cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing 688drivers= 689egid=100 690env= 691errout=cerr 692euid=100 693eventq_index=0 694executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/twolf 695gid=100 696input=cin 697kvmInSE=false 698max_stack_size=67108864 699output=cout 700pid=100 701ppid=99 702simpoint=0 703system=system 704uid=100 705useArchPT=false 706 707[system.cpu_clk_domain] 708type=SrcClockDomain 709clock=500 710domain_id=-1 711eventq_index=0 712init_perf_level=0 713voltage_domain=system.voltage_domain 714 715[system.dvfs_handler] 716type=DVFSHandler 717domains= 718enable=false 719eventq_index=0 720sys_clk_domain=system.clk_domain 721transition_latency=100000000 722 723[system.membus] 724type=CoherentXBar 725clk_domain=system.clk_domain 726eventq_index=0 727forward_latency=4 728frontend_latency=3 729response_latency=2 730snoop_filter=Null 731snoop_response_latency=4 732system=system 733use_default_range=false 734width=16 735master=system.physmem.port 736slave=system.system_port system.cpu.l2cache.mem_side 737 738[system.physmem] 739type=DRAMCtrl 740IDD0=0.075000 741IDD02=0.000000 742IDD2N=0.050000 743IDD2N2=0.000000 744IDD2P0=0.000000 745IDD2P02=0.000000 746IDD2P1=0.000000 747IDD2P12=0.000000 748IDD3N=0.057000 749IDD3N2=0.000000 750IDD3P0=0.000000 751IDD3P02=0.000000 752IDD3P1=0.000000 753IDD3P12=0.000000 754IDD4R=0.187000 755IDD4R2=0.000000 756IDD4W=0.165000 757IDD4W2=0.000000 758IDD5=0.220000 759IDD52=0.000000 760IDD6=0.000000 761IDD62=0.000000 762VDD=1.500000 763VDD2=0.000000 764activation_limit=4 765addr_mapping=RoRaBaCoCh 766bank_groups_per_rank=0 767banks_per_rank=8 768burst_length=8 769channels=1 770clk_domain=system.clk_domain 771conf_table_reported=true 772device_bus_width=8 773device_rowbuffer_size=1024 774device_size=536870912 775devices_per_rank=8 776dll=true 777eventq_index=0 778in_addr_map=true 779max_accesses_per_row=16 780mem_sched_policy=frfcfs 781min_writes_per_switch=16 782null=false 783page_policy=open_adaptive 784range=0:134217727 785ranks_per_channel=2 786read_buffer_size=32 787static_backend_latency=10000 788static_frontend_latency=10000 789tBURST=5000 790tCCD_L=0 791tCK=1250 792tCL=13750 793tCS=2500 794tRAS=35000 795tRCD=13750 796tREFI=7800000 797tRFC=260000 798tRP=13750 799tRRD=6000 800tRRD_L=0 801tRTP=7500 802tRTW=2500 803tWR=15000 804tWTR=7500 805tXAW=30000 806tXP=0 807tXPDLL=0 808tXS=0 809tXSDLL=0 810write_buffer_size=64 811write_high_thresh_perc=85 812write_low_thresh_perc=50 813port=system.membus.master[0] 814 815[system.voltage_domain] 816type=VoltageDomain 817eventq_index=0 818voltage=1.000000 819 820