stats.txt revision 11507
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.033525 # Number of seconds simulated 4sim_ticks 33524756000 # Number of ticks simulated 5final_tick 33524756000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 102958 # Simulator instruction rate (inst/s) 8host_op_rate 131671 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48677985 # Simulator tick rate (ticks/s) 10host_mem_usage 277880 # Number of bytes of host memory used 11host_seconds 688.70 # Real time elapsed on the host 12sim_insts 70907652 # Number of instructions simulated 13sim_ops 90682607 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 697984 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2927552 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 6172096 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9797632 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 697984 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 697984 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6216960 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6216960 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 10906 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 45743 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 96439 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 153088 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 97140 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 97140 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 20819958 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 87325080 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 184105620 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 292250658 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 20819958 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 20819958 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 185443855 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 185443855 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 185443855 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 20819958 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 87325080 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 184105620 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 477694513 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 153089 # Number of read requests accepted 44system.physmem.writeReqs 97140 # Number of write requests accepted 45system.physmem.readBursts 153089 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 97140 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 9788224 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue 49system.physmem.bytesWritten 6215872 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 9797696 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 6216960 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 9103 # Per bank write bursts 56system.physmem.perBankRdBursts::1 9407 # Per bank write bursts 57system.physmem.perBankRdBursts::2 9452 # Per bank write bursts 58system.physmem.perBankRdBursts::3 11458 # Per bank write bursts 59system.physmem.perBankRdBursts::4 10748 # Per bank write bursts 60system.physmem.perBankRdBursts::5 11390 # Per bank write bursts 61system.physmem.perBankRdBursts::6 10031 # Per bank write bursts 62system.physmem.perBankRdBursts::7 8920 # Per bank write bursts 63system.physmem.perBankRdBursts::8 9321 # Per bank write bursts 64system.physmem.perBankRdBursts::9 9437 # Per bank write bursts 65system.physmem.perBankRdBursts::10 9070 # Per bank write bursts 66system.physmem.perBankRdBursts::11 9080 # Per bank write bursts 67system.physmem.perBankRdBursts::12 8731 # Per bank write bursts 68system.physmem.perBankRdBursts::13 8724 # Per bank write bursts 69system.physmem.perBankRdBursts::14 9025 # Per bank write bursts 70system.physmem.perBankRdBursts::15 9044 # Per bank write bursts 71system.physmem.perBankWrBursts::0 5968 # Per bank write bursts 72system.physmem.perBankWrBursts::1 6230 # Per bank write bursts 73system.physmem.perBankWrBursts::2 6083 # Per bank write bursts 74system.physmem.perBankWrBursts::3 6155 # Per bank write bursts 75system.physmem.perBankWrBursts::4 6058 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6286 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6021 # Per bank write bursts 78system.physmem.perBankWrBursts::7 5958 # Per bank write bursts 79system.physmem.perBankWrBursts::8 5969 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6064 # Per bank write bursts 81system.physmem.perBankWrBursts::10 6185 # Per bank write bursts 82system.physmem.perBankWrBursts::11 5907 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6058 # Per bank write bursts 84system.physmem.perBankWrBursts::13 6089 # Per bank write bursts 85system.physmem.perBankWrBursts::14 6121 # Per bank write bursts 86system.physmem.perBankWrBursts::15 5971 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 33524744500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 153089 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 97140 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 50282 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 54410 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 13705 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 10264 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6125 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 5282 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 4726 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4368 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3666 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 71 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 33 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 7 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1229 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1284 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1769 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 2313 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 2958 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 3844 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 4769 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5371 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5945 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6375 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6905 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 7468 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8082 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8760 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 9125 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 7620 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6645 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6222 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 195 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 85 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 63 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 40 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 4 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 96335 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 166.118316 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 104.810468 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 234.858667 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 60546 62.85% 62.85% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 22368 23.22% 86.07% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 3987 4.14% 90.21% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1542 1.60% 91.81% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 931 0.97% 92.77% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 863 0.90% 93.67% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 636 0.66% 94.33% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 773 0.80% 95.13% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 4689 4.87% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 96335 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5845 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 26.165269 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 198.412430 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-511 5844 99.98% 99.98% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::14848-15359 1 0.02% 100.00% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::total 5845 # Reads before turning the bus around for writes 220system.physmem.wrPerTurnAround::samples 5845 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::mean 16.616424 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::gmean 16.570046 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::stdev 1.313075 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::16 4545 77.76% 77.76% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::17 48 0.82% 78.58% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::18 753 12.88% 91.46% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::19 215 3.68% 95.14% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::20 127 2.17% 97.31% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::21 88 1.51% 98.82% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::22 42 0.72% 99.54% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::23 17 0.29% 99.83% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::24 5 0.09% 99.91% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::25 5 0.09% 100.00% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::total 5845 # Writes before turning the bus around for reads 235system.physmem.totQLat 6714977565 # Total ticks spent queuing 236system.physmem.totMemAccLat 9582621315 # Total ticks spent from burst creation until serviced by the DRAM 237system.physmem.totBusLat 764705000 # Total ticks spent in databus transfers 238system.physmem.avgQLat 43905.67 # Average queueing delay per DRAM burst 239system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 240system.physmem.avgMemAccLat 62655.67 # Average memory access latency per DRAM burst 241system.physmem.avgRdBW 291.97 # Average DRAM read bandwidth in MiByte/s 242system.physmem.avgWrBW 185.41 # Average achieved write bandwidth in MiByte/s 243system.physmem.avgRdBWSys 292.25 # Average system read bandwidth in MiByte/s 244system.physmem.avgWrBWSys 185.44 # Average system write bandwidth in MiByte/s 245system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 246system.physmem.busUtil 3.73 # Data bus utilization in percentage 247system.physmem.busUtilRead 2.28 # Data bus utilization in percentage for reads 248system.physmem.busUtilWrite 1.45 # Data bus utilization in percentage for writes 249system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing 250system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing 251system.physmem.readRowHits 120882 # Number of row buffer hits during reads 252system.physmem.writeRowHits 32837 # Number of row buffer hits during writes 253system.physmem.readRowHitRate 79.04 # Row buffer hit rate for reads 254system.physmem.writeRowHitRate 33.80 # Row buffer hit rate for writes 255system.physmem.avgGap 133976.26 # Average gap between requests 256system.physmem.pageHitRate 61.47 # Row buffer hit rate, read and write combined 257system.physmem_0.actEnergy 378438480 # Energy for activate commands per rank (pJ) 258system.physmem_0.preEnergy 206489250 # Energy for precharge commands per rank (pJ) 259system.physmem_0.readEnergy 627572400 # Energy for read commands per rank (pJ) 260system.physmem_0.writeEnergy 315854640 # Energy for write commands per rank (pJ) 261system.physmem_0.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) 262system.physmem_0.actBackEnergy 15155251200 # Energy for active background per rank (pJ) 263system.physmem_0.preBackEnergy 6817959750 # Energy for precharge background per rank (pJ) 264system.physmem_0.totalEnergy 25690916520 # Total energy per rank (pJ) 265system.physmem_0.averagePower 766.433942 # Core power per rank (mW) 266system.physmem_0.memoryStateTime::IDLE 11238384768 # Time in different power states 267system.physmem_0.memoryStateTime::REF 1119300000 # Time in different power states 268system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 269system.physmem_0.memoryStateTime::ACT 21162395232 # Time in different power states 270system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 271system.physmem_1.actEnergy 349513920 # Energy for activate commands per rank (pJ) 272system.physmem_1.preEnergy 190707000 # Energy for precharge commands per rank (pJ) 273system.physmem_1.readEnergy 564751200 # Energy for read commands per rank (pJ) 274system.physmem_1.writeEnergy 313295040 # Energy for write commands per rank (pJ) 275system.physmem_1.refreshEnergy 2189350800 # Energy for refresh commands per rank (pJ) 276system.physmem_1.actBackEnergy 13737724470 # Energy for active background per rank (pJ) 277system.physmem_1.preBackEnergy 8061404250 # Energy for precharge background per rank (pJ) 278system.physmem_1.totalEnergy 25406746680 # Total energy per rank (pJ) 279system.physmem_1.averagePower 757.956338 # Core power per rank (mW) 280system.physmem_1.memoryStateTime::IDLE 13314860915 # Time in different power states 281system.physmem_1.memoryStateTime::REF 1119300000 # Time in different power states 282system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 283system.physmem_1.memoryStateTime::ACT 19085999585 # Time in different power states 284system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 285system.cpu.branchPred.lookups 17055826 # Number of BP lookups 286system.cpu.branchPred.condPredicted 11447804 # Number of conditional branches predicted 287system.cpu.branchPred.condIncorrect 598855 # Number of conditional branches incorrect 288system.cpu.branchPred.BTBLookups 9258903 # Number of BTB lookups 289system.cpu.branchPred.BTBHits 7371283 # Number of BTB hits 290system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 291system.cpu.branchPred.BTBHitPct 79.612920 # BTB Hit Percentage 292system.cpu.branchPred.usedRAS 1853216 # Number of times the RAS was used to get a target. 293system.cpu.branchPred.RASInCorrect 101575 # Number of incorrect RAS predictions. 294system.cpu.branchPred.indirectLookups 232758 # Number of indirect predictor lookups. 295system.cpu.branchPred.indirectHits 195217 # Number of indirect target hits. 296system.cpu.branchPred.indirectMisses 37541 # Number of indirect misses. 297system.cpu.branchPredindirectMispredicted 22230 # Number of mispredicted indirect branches. 298system.cpu_clk_domain.clock 500 # Clock period in ticks 299system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 308system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 309system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 310system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 311system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 312system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 314system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 315system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 316system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 317system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 318system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 319system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 320system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 321system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 322system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 323system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 324system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 325system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 326system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 327system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 328system.cpu.dtb.walker.walks 0 # Table walker walks requested 329system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.inst_hits 0 # ITB inst hits 337system.cpu.dtb.inst_misses 0 # ITB inst misses 338system.cpu.dtb.read_hits 0 # DTB read hits 339system.cpu.dtb.read_misses 0 # DTB read misses 340system.cpu.dtb.write_hits 0 # DTB write hits 341system.cpu.dtb.write_misses 0 # DTB write misses 342system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 343system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 344system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 345system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 346system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 347system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 348system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 349system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 350system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 351system.cpu.dtb.read_accesses 0 # DTB read accesses 352system.cpu.dtb.write_accesses 0 # DTB write accesses 353system.cpu.dtb.inst_accesses 0 # ITB inst accesses 354system.cpu.dtb.hits 0 # DTB hits 355system.cpu.dtb.misses 0 # DTB misses 356system.cpu.dtb.accesses 0 # DTB accesses 357system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 366system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 367system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 368system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 369system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 370system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 372system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 373system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 374system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 375system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 376system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 377system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 378system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 386system.cpu.itb.walker.walks 0 # Table walker walks requested 387system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.inst_hits 0 # ITB inst hits 395system.cpu.itb.inst_misses 0 # ITB inst misses 396system.cpu.itb.read_hits 0 # DTB read hits 397system.cpu.itb.read_misses 0 # DTB read misses 398system.cpu.itb.write_hits 0 # DTB write hits 399system.cpu.itb.write_misses 0 # DTB write misses 400system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 401system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 402system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 403system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 404system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 405system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 406system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 407system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 408system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 409system.cpu.itb.read_accesses 0 # DTB read accesses 410system.cpu.itb.write_accesses 0 # DTB write accesses 411system.cpu.itb.inst_accesses 0 # ITB inst accesses 412system.cpu.itb.hits 0 # DTB hits 413system.cpu.itb.misses 0 # DTB misses 414system.cpu.itb.accesses 0 # DTB accesses 415system.cpu.workload.num_syscalls 1946 # Number of system calls 416system.cpu.numCycles 67049513 # number of cpu cycles simulated 417system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 418system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 419system.cpu.fetch.icacheStallCycles 5112037 # Number of cycles fetch is stalled on an Icache miss 420system.cpu.fetch.Insts 87027076 # Number of instructions fetch has processed 421system.cpu.fetch.Branches 17055826 # Number of branches that fetch encountered 422system.cpu.fetch.predictedBranches 9419716 # Number of branches that fetch has predicted taken 423system.cpu.fetch.Cycles 60300614 # Number of cycles fetch has run and was not squashing or blocked 424system.cpu.fetch.SquashCycles 1224115 # Number of cycles fetch has spent squashing 425system.cpu.fetch.MiscStallCycles 5977 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 426system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps 427system.cpu.fetch.IcacheWaitRetryStallCycles 12656 # Number of stall cycles due to full MSHR 428system.cpu.fetch.CacheLines 22418203 # Number of cache lines fetched 429system.cpu.fetch.IcacheSquashes 68072 # Number of outstanding Icache misses that were squashed 430system.cpu.fetch.rateDist::samples 66043378 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::mean 1.665685 # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::stdev 1.303820 # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::0 20904696 31.65% 31.65% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::1 8151419 12.34% 44.00% # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::2 9105743 13.79% 57.78% # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::3 27881520 42.22% 100.00% # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::total 66043378 # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.branchRate 0.254377 # Number of branch fetches per cycle 443system.cpu.fetch.rate 1.297952 # Number of inst fetches per cycle 444system.cpu.decode.IdleCycles 8568047 # Number of cycles decode is idle 445system.cpu.decode.BlockedCycles 20331818 # Number of cycles decode is blocked 446system.cpu.decode.RunCycles 31035970 # Number of cycles decode is running 447system.cpu.decode.UnblockCycles 5662045 # Number of cycles decode is unblocking 448system.cpu.decode.SquashCycles 445498 # Number of cycles decode is squashing 449system.cpu.decode.BranchResolved 3138719 # Number of times decode resolved a branch 450system.cpu.decode.BranchMispred 168392 # Number of times decode detected a branch misprediction 451system.cpu.decode.DecodedInsts 100377883 # Number of instructions handled by decode 452system.cpu.decode.SquashedInsts 2807284 # Number of squashed instructions handled by decode 453system.cpu.rename.SquashCycles 445498 # Number of cycles rename is squashing 454system.cpu.rename.IdleCycles 13201972 # Number of cycles rename is idle 455system.cpu.rename.BlockCycles 6021135 # Number of cycles rename is blocking 456system.cpu.rename.serializeStallCycles 843957 # count of cycles rename stalled for serializing inst 457system.cpu.rename.RunCycles 31848304 # Number of cycles rename is running 458system.cpu.rename.UnblockCycles 13682512 # Number of cycles rename is unblocking 459system.cpu.rename.RenamedInsts 98401933 # Number of instructions processed by rename 460system.cpu.rename.SquashedInsts 864722 # Number of squashed instructions processed by rename 461system.cpu.rename.ROBFullEvents 3910657 # Number of times rename has blocked due to ROB full 462system.cpu.rename.IQFullEvents 69359 # Number of times rename has blocked due to IQ full 463system.cpu.rename.LQFullEvents 4461482 # Number of times rename has blocked due to LQ full 464system.cpu.rename.SQFullEvents 5194138 # Number of times rename has blocked due to SQ full 465system.cpu.rename.RenamedOperands 103316551 # Number of destination operands rename has renamed 466system.cpu.rename.RenameLookups 453881397 # Number of register rename lookups that rename has made 467system.cpu.rename.int_rename_lookups 114363596 # Number of integer rename lookups 468system.cpu.rename.fp_rename_lookups 706 # Number of floating rename lookups 469system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed 470system.cpu.rename.UndoneMaps 9687182 # Number of HB maps that are undone due to squashing 471system.cpu.rename.serializingInsts 18952 # count of serializing insts renamed 472system.cpu.rename.tempSerializingInsts 18977 # count of temporary serializing insts renamed 473system.cpu.rename.skidInsts 12759909 # count of insts added to the skid buffer 474system.cpu.memDep0.insertedLoads 24172969 # Number of loads inserted to the mem dependence unit. 475system.cpu.memDep0.insertedStores 21779154 # Number of stores inserted to the mem dependence unit. 476system.cpu.memDep0.conflictingLoads 1438398 # Number of conflicting loads. 477system.cpu.memDep0.conflictingStores 2287665 # Number of conflicting stores. 478system.cpu.iq.iqInstsAdded 97467378 # Number of instructions added to the IQ (excludes non-spec) 479system.cpu.iq.iqNonSpecInstsAdded 34812 # Number of non-speculative instructions added to the IQ 480system.cpu.iq.iqInstsIssued 94518121 # Number of instructions issued 481system.cpu.iq.iqSquashedInstsIssued 609879 # Number of squashed instructions issued 482system.cpu.iq.iqSquashedInstsExamined 6819583 # Number of squashed instructions iterated over during squash; mainly for profiling 483system.cpu.iq.iqSquashedOperandsExamined 18149075 # Number of squashed operands that are examined and possibly removed from graph 484system.cpu.iq.iqSquashedNonSpecRemoved 1026 # Number of squashed non-spec instructions that were removed 485system.cpu.iq.issued_per_cycle::samples 66043378 # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::mean 1.431152 # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::stdev 1.152558 # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::0 17971444 27.21% 27.21% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::1 17366377 26.30% 53.51% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::2 17018277 25.77% 79.28% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::3 11635318 17.62% 96.89% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::4 2050574 3.10% 100.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::5 1388 0.00% 100.00% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::total 66043378 # Number of insts issued each cycle 502system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::IntAlu 6745698 22.64% 22.64% # attempts to use FU when none available 504system.cpu.iq.fu_full::IntMult 37 0.00% 22.64% # attempts to use FU when none available 505system.cpu.iq.fu_full::IntDiv 0 0.00% 22.64% # attempts to use FU when none available 506system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.64% # attempts to use FU when none available 507system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.64% # attempts to use FU when none available 508system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.64% # attempts to use FU when none available 509system.cpu.iq.fu_full::FloatMult 0 0.00% 22.64% # attempts to use FU when none available 510system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.64% # attempts to use FU when none available 511system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.64% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.64% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.64% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.64% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.64% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.64% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.64% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdMult 0 0.00% 22.64% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.64% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdShift 0 0.00% 22.64% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.64% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.64% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.64% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.64% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.64% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.64% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.64% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.64% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.64% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.64% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.64% # attempts to use FU when none available 532system.cpu.iq.fu_full::MemRead 11091756 37.22% 59.86% # attempts to use FU when none available 533system.cpu.iq.fu_full::MemWrite 11960162 40.14% 100.00% # attempts to use FU when none available 534system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 535system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 536system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 537system.cpu.iq.FU_type_0::IntAlu 49324075 52.18% 52.18% # Type of FU issued 538system.cpu.iq.FU_type_0::IntMult 86626 0.09% 52.28% # Type of FU issued 539system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued 542system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued 543system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued 544system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued 545system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.28% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.28% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.28% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.28% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.28% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.28% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.28% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.28% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatCmp 6 0.00% 52.28% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatMisc 12 0.00% 52.28% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued 566system.cpu.iq.FU_type_0::MemRead 23968009 25.36% 77.63% # Type of FU issued 567system.cpu.iq.FU_type_0::MemWrite 21139361 22.37% 100.00% # Type of FU issued 568system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 569system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 570system.cpu.iq.FU_type_0::total 94518121 # Type of FU issued 571system.cpu.iq.rate 1.409676 # Inst issue rate 572system.cpu.iq.fu_busy_cnt 29797653 # FU busy when requested 573system.cpu.iq.fu_busy_rate 0.315259 # FU busy rate (busy events/executed inst) 574system.cpu.iq.int_inst_queue_reads 285486823 # Number of integer instruction queue reads 575system.cpu.iq.int_inst_queue_writes 104332871 # Number of integer instruction queue writes 576system.cpu.iq.int_inst_queue_wakeup_accesses 93229184 # Number of integer instruction queue wakeup accesses 577system.cpu.iq.fp_inst_queue_reads 329 # Number of floating instruction queue reads 578system.cpu.iq.fp_inst_queue_writes 574 # Number of floating instruction queue writes 579system.cpu.iq.fp_inst_queue_wakeup_accesses 84 # Number of floating instruction queue wakeup accesses 580system.cpu.iq.int_alu_accesses 124315586 # Number of integer alu accesses 581system.cpu.iq.fp_alu_accesses 188 # Number of floating point alu accesses 582system.cpu.iew.lsq.thread0.forwLoads 1381077 # Number of loads that had data forwarded from stores 583system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 584system.cpu.iew.lsq.thread0.squashedLoads 1306707 # Number of loads squashed 585system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed 586system.cpu.iew.lsq.thread0.memOrderViolation 11900 # Number of memory ordering violations 587system.cpu.iew.lsq.thread0.squashedStores 1223416 # Number of stores squashed 588system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 589system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 590system.cpu.iew.lsq.thread0.rescheduledLoads 147221 # Number of loads that were rescheduled 591system.cpu.iew.lsq.thread0.cacheBlocked 186554 # Number of times an access to memory failed due to the cache being blocked 592system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 593system.cpu.iew.iewSquashCycles 445498 # Number of cycles IEW is squashing 594system.cpu.iew.iewBlockCycles 578203 # Number of cycles IEW is blocking 595system.cpu.iew.iewUnblockCycles 566637 # Number of cycles IEW is unblocking 596system.cpu.iew.iewDispatchedInsts 97517928 # Number of instructions dispatched to IQ 597system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 598system.cpu.iew.iewDispLoadInsts 24172969 # Number of dispatched load instructions 599system.cpu.iew.iewDispStoreInsts 21779154 # Number of dispatched store instructions 600system.cpu.iew.iewDispNonSpecInsts 18892 # Number of dispatched non-speculative instructions 601system.cpu.iew.iewIQFullEvents 1555 # Number of times the IQ has become full, causing a stall 602system.cpu.iew.iewLSQFullEvents 562180 # Number of times the LSQ has become full, causing a stall 603system.cpu.iew.memOrderViolationEvents 11900 # Number of memory order violations 604system.cpu.iew.predictedTakenIncorrect 250835 # Number of branches that were predicted taken incorrectly 605system.cpu.iew.predictedNotTakenIncorrect 223196 # Number of branches that were predicted not taken incorrectly 606system.cpu.iew.branchMispredicts 474031 # Number of branch mispredicts detected at execute 607system.cpu.iew.iewExecutedInsts 93719339 # Number of executed instructions 608system.cpu.iew.iewExecLoadInsts 23701905 # Number of load instructions executed 609system.cpu.iew.iewExecSquashedInsts 798782 # Number of squashed instructions skipped in execute 610system.cpu.iew.exec_swp 0 # number of swp insts executed 611system.cpu.iew.exec_nop 15738 # number of nop insts executed 612system.cpu.iew.exec_refs 44631646 # number of memory reference insts executed 613system.cpu.iew.exec_branches 14212084 # Number of branches executed 614system.cpu.iew.exec_stores 20929741 # Number of stores executed 615system.cpu.iew.exec_rate 1.397763 # Inst execution rate 616system.cpu.iew.wb_sent 93338125 # cumulative count of insts sent to commit 617system.cpu.iew.wb_count 93229268 # cumulative count of insts written-back 618system.cpu.iew.wb_producers 44994314 # num instructions producing a value 619system.cpu.iew.wb_consumers 76693481 # num instructions consuming a value 620system.cpu.iew.wb_rate 1.390454 # insts written-back per cycle 621system.cpu.iew.wb_fanout 0.586677 # average fanout of values written-back 622system.cpu.commit.commitSquashedInsts 5957514 # The number of squashed insts skipped by commit 623system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 624system.cpu.commit.branchMispredicts 432296 # The number of times a branch was mispredicted 625system.cpu.commit.committed_per_cycle::samples 65078464 # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::mean 1.393520 # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::stdev 2.163869 # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::0 31565690 48.50% 48.50% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::1 16713735 25.68% 74.19% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::2 4316875 6.63% 80.82% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::3 4188712 6.44% 87.26% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::4 1942227 2.98% 90.24% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::5 1235606 1.90% 92.14% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::6 754913 1.16% 93.30% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::7 587526 0.90% 94.20% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::8 3773180 5.80% 100.00% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::total 65078464 # Number of insts commited each cycle 642system.cpu.commit.committedInsts 70913204 # Number of instructions committed 643system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed 644system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 645system.cpu.commit.refs 43422000 # Number of memory references committed 646system.cpu.commit.loads 22866262 # Number of loads committed 647system.cpu.commit.membars 15920 # Number of memory barriers committed 648system.cpu.commit.branches 13741468 # Number of branches committed 649system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 650system.cpu.commit.int_insts 81528527 # Number of committed integer instructions. 651system.cpu.commit.function_calls 1679850 # Number of function calls committed. 652system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 653system.cpu.commit.op_class_0::IntAlu 47186033 52.03% 52.03% # Class of committed instruction 654system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 655system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 656system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 657system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 658system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 659system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction 660system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction 661system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 682system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 683system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 684system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction 687system.cpu.commit.bw_lim_events 3773180 # number cycles where commit BW limit reached 688system.cpu.rob.rob_reads 157925658 # The number of ROB reads 689system.cpu.rob.rob_writes 194257744 # The number of ROB writes 690system.cpu.timesIdled 27177 # Number of times that the entire CPU went into an idle state and unscheduled itself 691system.cpu.idleCycles 1006135 # Total number of cycles that the CPU has spent unscheduled due to idling 692system.cpu.committedInsts 70907652 # Number of Instructions Simulated 693system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated 694system.cpu.cpi 0.945589 # CPI: Cycles Per Instruction 695system.cpu.cpi_total 0.945589 # CPI: Total CPI of All Threads 696system.cpu.ipc 1.057542 # IPC: Instructions Per Cycle 697system.cpu.ipc_total 1.057542 # IPC: Total IPC of All Threads 698system.cpu.int_regfile_reads 102008139 # number of integer regfile reads 699system.cpu.int_regfile_writes 56630693 # number of integer regfile writes 700system.cpu.fp_regfile_reads 48 # number of floating regfile reads 701system.cpu.fp_regfile_writes 42 # number of floating regfile writes 702system.cpu.cc_regfile_reads 345209533 # number of cc regfile reads 703system.cpu.cc_regfile_writes 38766867 # number of cc regfile writes 704system.cpu.misc_regfile_reads 44112758 # number of misc regfile reads 705system.cpu.misc_regfile_writes 31840 # number of misc regfile writes 706system.cpu.dcache.tags.replacements 486293 # number of replacements 707system.cpu.dcache.tags.tagsinuse 510.756058 # Cycle average of tags in use 708system.cpu.dcache.tags.total_refs 40330532 # Total number of references to valid blocks. 709system.cpu.dcache.tags.sampled_refs 486805 # Sample count of references to valid blocks. 710system.cpu.dcache.tags.avg_refs 82.847407 # Average number of references to valid blocks. 711system.cpu.dcache.tags.warmup_cycle 150823500 # Cycle when the warmup percentage was hit. 712system.cpu.dcache.tags.occ_blocks::cpu.data 510.756058 # Average occupied blocks per requestor 713system.cpu.dcache.tags.occ_percent::cpu.data 0.997570 # Average percentage of cache occupancy 714system.cpu.dcache.tags.occ_percent::total 0.997570 # Average percentage of cache occupancy 715system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 716system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 717system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id 718system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 719system.cpu.dcache.tags.tag_accesses 84456645 # Number of tag accesses 720system.cpu.dcache.tags.data_accesses 84456645 # Number of data accesses 721system.cpu.dcache.ReadReq_hits::cpu.data 21406566 # number of ReadReq hits 722system.cpu.dcache.ReadReq_hits::total 21406566 # number of ReadReq hits 723system.cpu.dcache.WriteReq_hits::cpu.data 18832689 # number of WriteReq hits 724system.cpu.dcache.WriteReq_hits::total 18832689 # number of WriteReq hits 725system.cpu.dcache.SoftPFReq_hits::cpu.data 59994 # number of SoftPFReq hits 726system.cpu.dcache.SoftPFReq_hits::total 59994 # number of SoftPFReq hits 727system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits 728system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits 729system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 730system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 731system.cpu.dcache.demand_hits::cpu.data 40239255 # number of demand (read+write) hits 732system.cpu.dcache.demand_hits::total 40239255 # number of demand (read+write) hits 733system.cpu.dcache.overall_hits::cpu.data 40299249 # number of overall hits 734system.cpu.dcache.overall_hits::total 40299249 # number of overall hits 735system.cpu.dcache.ReadReq_misses::cpu.data 567937 # number of ReadReq misses 736system.cpu.dcache.ReadReq_misses::total 567937 # number of ReadReq misses 737system.cpu.dcache.WriteReq_misses::cpu.data 1017212 # number of WriteReq misses 738system.cpu.dcache.WriteReq_misses::total 1017212 # number of WriteReq misses 739system.cpu.dcache.SoftPFReq_misses::cpu.data 68679 # number of SoftPFReq misses 740system.cpu.dcache.SoftPFReq_misses::total 68679 # number of SoftPFReq misses 741system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses 742system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses 743system.cpu.dcache.demand_misses::cpu.data 1585149 # number of demand (read+write) misses 744system.cpu.dcache.demand_misses::total 1585149 # number of demand (read+write) misses 745system.cpu.dcache.overall_misses::cpu.data 1653828 # number of overall misses 746system.cpu.dcache.overall_misses::total 1653828 # number of overall misses 747system.cpu.dcache.ReadReq_miss_latency::cpu.data 9485185000 # number of ReadReq miss cycles 748system.cpu.dcache.ReadReq_miss_latency::total 9485185000 # number of ReadReq miss cycles 749system.cpu.dcache.WriteReq_miss_latency::cpu.data 14264451930 # number of WriteReq miss cycles 750system.cpu.dcache.WriteReq_miss_latency::total 14264451930 # number of WriteReq miss cycles 751system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5633500 # number of LoadLockedReq miss cycles 752system.cpu.dcache.LoadLockedReq_miss_latency::total 5633500 # number of LoadLockedReq miss cycles 753system.cpu.dcache.demand_miss_latency::cpu.data 23749636930 # number of demand (read+write) miss cycles 754system.cpu.dcache.demand_miss_latency::total 23749636930 # number of demand (read+write) miss cycles 755system.cpu.dcache.overall_miss_latency::cpu.data 23749636930 # number of overall miss cycles 756system.cpu.dcache.overall_miss_latency::total 23749636930 # number of overall miss cycles 757system.cpu.dcache.ReadReq_accesses::cpu.data 21974503 # number of ReadReq accesses(hits+misses) 758system.cpu.dcache.ReadReq_accesses::total 21974503 # number of ReadReq accesses(hits+misses) 759system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 760system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 761system.cpu.dcache.SoftPFReq_accesses::cpu.data 128673 # number of SoftPFReq accesses(hits+misses) 762system.cpu.dcache.SoftPFReq_accesses::total 128673 # number of SoftPFReq accesses(hits+misses) 763system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15924 # number of LoadLockedReq accesses(hits+misses) 764system.cpu.dcache.LoadLockedReq_accesses::total 15924 # number of LoadLockedReq accesses(hits+misses) 765system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 766system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 767system.cpu.dcache.demand_accesses::cpu.data 41824404 # number of demand (read+write) accesses 768system.cpu.dcache.demand_accesses::total 41824404 # number of demand (read+write) accesses 769system.cpu.dcache.overall_accesses::cpu.data 41953077 # number of overall (read+write) accesses 770system.cpu.dcache.overall_accesses::total 41953077 # number of overall (read+write) accesses 771system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025845 # miss rate for ReadReq accesses 772system.cpu.dcache.ReadReq_miss_rate::total 0.025845 # miss rate for ReadReq accesses 773system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051245 # miss rate for WriteReq accesses 774system.cpu.dcache.WriteReq_miss_rate::total 0.051245 # miss rate for WriteReq accesses 775system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.533748 # miss rate for SoftPFReq accesses 776system.cpu.dcache.SoftPFReq_miss_rate::total 0.533748 # miss rate for SoftPFReq accesses 777system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038809 # miss rate for LoadLockedReq accesses 778system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038809 # miss rate for LoadLockedReq accesses 779system.cpu.dcache.demand_miss_rate::cpu.data 0.037900 # miss rate for demand accesses 780system.cpu.dcache.demand_miss_rate::total 0.037900 # miss rate for demand accesses 781system.cpu.dcache.overall_miss_rate::cpu.data 0.039421 # miss rate for overall accesses 782system.cpu.dcache.overall_miss_rate::total 0.039421 # miss rate for overall accesses 783system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16701.121779 # average ReadReq miss latency 784system.cpu.dcache.ReadReq_avg_miss_latency::total 16701.121779 # average ReadReq miss latency 785system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14023.086564 # average WriteReq miss latency 786system.cpu.dcache.WriteReq_avg_miss_latency::total 14023.086564 # average WriteReq miss latency 787system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9115.695793 # average LoadLockedReq miss latency 788system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9115.695793 # average LoadLockedReq miss latency 789system.cpu.dcache.demand_avg_miss_latency::cpu.data 14982.589605 # average overall miss latency 790system.cpu.dcache.demand_avg_miss_latency::total 14982.589605 # average overall miss latency 791system.cpu.dcache.overall_avg_miss_latency::cpu.data 14360.403216 # average overall miss latency 792system.cpu.dcache.overall_avg_miss_latency::total 14360.403216 # average overall miss latency 793system.cpu.dcache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked 794system.cpu.dcache.blocked_cycles::no_targets 2907482 # number of cycles access was blocked 795system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 796system.cpu.dcache.blocked::no_targets 131418 # number of cycles access was blocked 797system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked 798system.cpu.dcache.avg_blocked_cycles::no_targets 22.123925 # average number of cycles each access was blocked 799system.cpu.dcache.writebacks::writebacks 486293 # number of writebacks 800system.cpu.dcache.writebacks::total 486293 # number of writebacks 801system.cpu.dcache.ReadReq_mshr_hits::cpu.data 267392 # number of ReadReq MSHR hits 802system.cpu.dcache.ReadReq_mshr_hits::total 267392 # number of ReadReq MSHR hits 803system.cpu.dcache.WriteReq_mshr_hits::cpu.data 868636 # number of WriteReq MSHR hits 804system.cpu.dcache.WriteReq_mshr_hits::total 868636 # number of WriteReq MSHR hits 805system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits 806system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits 807system.cpu.dcache.demand_mshr_hits::cpu.data 1136028 # number of demand (read+write) MSHR hits 808system.cpu.dcache.demand_mshr_hits::total 1136028 # number of demand (read+write) MSHR hits 809system.cpu.dcache.overall_mshr_hits::cpu.data 1136028 # number of overall MSHR hits 810system.cpu.dcache.overall_mshr_hits::total 1136028 # number of overall MSHR hits 811system.cpu.dcache.ReadReq_mshr_misses::cpu.data 300545 # number of ReadReq MSHR misses 812system.cpu.dcache.ReadReq_mshr_misses::total 300545 # number of ReadReq MSHR misses 813system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148576 # number of WriteReq MSHR misses 814system.cpu.dcache.WriteReq_mshr_misses::total 148576 # number of WriteReq MSHR misses 815system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37700 # number of SoftPFReq MSHR misses 816system.cpu.dcache.SoftPFReq_mshr_misses::total 37700 # number of SoftPFReq MSHR misses 817system.cpu.dcache.demand_mshr_misses::cpu.data 449121 # number of demand (read+write) MSHR misses 818system.cpu.dcache.demand_mshr_misses::total 449121 # number of demand (read+write) MSHR misses 819system.cpu.dcache.overall_mshr_misses::cpu.data 486821 # number of overall MSHR misses 820system.cpu.dcache.overall_mshr_misses::total 486821 # number of overall MSHR misses 821system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3693304500 # number of ReadReq MSHR miss cycles 822system.cpu.dcache.ReadReq_mshr_miss_latency::total 3693304500 # number of ReadReq MSHR miss cycles 823system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2308719470 # number of WriteReq MSHR miss cycles 824system.cpu.dcache.WriteReq_mshr_miss_latency::total 2308719470 # number of WriteReq MSHR miss cycles 825system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1888982500 # number of SoftPFReq MSHR miss cycles 826system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1888982500 # number of SoftPFReq MSHR miss cycles 827system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6002023970 # number of demand (read+write) MSHR miss cycles 828system.cpu.dcache.demand_mshr_miss_latency::total 6002023970 # number of demand (read+write) MSHR miss cycles 829system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7891006470 # number of overall MSHR miss cycles 830system.cpu.dcache.overall_mshr_miss_latency::total 7891006470 # number of overall MSHR miss cycles 831system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013677 # mshr miss rate for ReadReq accesses 832system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013677 # mshr miss rate for ReadReq accesses 833system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses 834system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses 835system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292991 # mshr miss rate for SoftPFReq accesses 836system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292991 # mshr miss rate for SoftPFReq accesses 837system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010738 # mshr miss rate for demand accesses 838system.cpu.dcache.demand_mshr_miss_rate::total 0.010738 # mshr miss rate for demand accesses 839system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011604 # mshr miss rate for overall accesses 840system.cpu.dcache.overall_mshr_miss_rate::total 0.011604 # mshr miss rate for overall accesses 841system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12288.690546 # average ReadReq mshr miss latency 842system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12288.690546 # average ReadReq mshr miss latency 843system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15538.979849 # average WriteReq mshr miss latency 844system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15538.979849 # average WriteReq mshr miss latency 845system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50105.636605 # average SoftPFReq mshr miss latency 846system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50105.636605 # average SoftPFReq mshr miss latency 847system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13363.935265 # average overall mshr miss latency 848system.cpu.dcache.demand_avg_mshr_miss_latency::total 13363.935265 # average overall mshr miss latency 849system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16209.256523 # average overall mshr miss latency 850system.cpu.dcache.overall_avg_mshr_miss_latency::total 16209.256523 # average overall mshr miss latency 851system.cpu.icache.tags.replacements 325000 # number of replacements 852system.cpu.icache.tags.tagsinuse 510.229072 # Cycle average of tags in use 853system.cpu.icache.tags.total_refs 22083387 # Total number of references to valid blocks. 854system.cpu.icache.tags.sampled_refs 325512 # Sample count of references to valid blocks. 855system.cpu.icache.tags.avg_refs 67.842006 # Average number of references to valid blocks. 856system.cpu.icache.tags.warmup_cycle 1115028500 # Cycle when the warmup percentage was hit. 857system.cpu.icache.tags.occ_blocks::cpu.inst 510.229072 # Average occupied blocks per requestor 858system.cpu.icache.tags.occ_percent::cpu.inst 0.996541 # Average percentage of cache occupancy 859system.cpu.icache.tags.occ_percent::total 0.996541 # Average percentage of cache occupancy 860system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 861system.cpu.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 862system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 863system.cpu.icache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id 864system.cpu.icache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id 865system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 866system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 867system.cpu.icache.tags.tag_accesses 45161716 # Number of tag accesses 868system.cpu.icache.tags.data_accesses 45161716 # Number of data accesses 869system.cpu.icache.ReadReq_hits::cpu.inst 22083387 # number of ReadReq hits 870system.cpu.icache.ReadReq_hits::total 22083387 # number of ReadReq hits 871system.cpu.icache.demand_hits::cpu.inst 22083387 # number of demand (read+write) hits 872system.cpu.icache.demand_hits::total 22083387 # number of demand (read+write) hits 873system.cpu.icache.overall_hits::cpu.inst 22083387 # number of overall hits 874system.cpu.icache.overall_hits::total 22083387 # number of overall hits 875system.cpu.icache.ReadReq_misses::cpu.inst 334707 # number of ReadReq misses 876system.cpu.icache.ReadReq_misses::total 334707 # number of ReadReq misses 877system.cpu.icache.demand_misses::cpu.inst 334707 # number of demand (read+write) misses 878system.cpu.icache.demand_misses::total 334707 # number of demand (read+write) misses 879system.cpu.icache.overall_misses::cpu.inst 334707 # number of overall misses 880system.cpu.icache.overall_misses::total 334707 # number of overall misses 881system.cpu.icache.ReadReq_miss_latency::cpu.inst 3526570179 # number of ReadReq miss cycles 882system.cpu.icache.ReadReq_miss_latency::total 3526570179 # number of ReadReq miss cycles 883system.cpu.icache.demand_miss_latency::cpu.inst 3526570179 # number of demand (read+write) miss cycles 884system.cpu.icache.demand_miss_latency::total 3526570179 # number of demand (read+write) miss cycles 885system.cpu.icache.overall_miss_latency::cpu.inst 3526570179 # number of overall miss cycles 886system.cpu.icache.overall_miss_latency::total 3526570179 # number of overall miss cycles 887system.cpu.icache.ReadReq_accesses::cpu.inst 22418094 # number of ReadReq accesses(hits+misses) 888system.cpu.icache.ReadReq_accesses::total 22418094 # number of ReadReq accesses(hits+misses) 889system.cpu.icache.demand_accesses::cpu.inst 22418094 # number of demand (read+write) accesses 890system.cpu.icache.demand_accesses::total 22418094 # number of demand (read+write) accesses 891system.cpu.icache.overall_accesses::cpu.inst 22418094 # number of overall (read+write) accesses 892system.cpu.icache.overall_accesses::total 22418094 # number of overall (read+write) accesses 893system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014930 # miss rate for ReadReq accesses 894system.cpu.icache.ReadReq_miss_rate::total 0.014930 # miss rate for ReadReq accesses 895system.cpu.icache.demand_miss_rate::cpu.inst 0.014930 # miss rate for demand accesses 896system.cpu.icache.demand_miss_rate::total 0.014930 # miss rate for demand accesses 897system.cpu.icache.overall_miss_rate::cpu.inst 0.014930 # miss rate for overall accesses 898system.cpu.icache.overall_miss_rate::total 0.014930 # miss rate for overall accesses 899system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10536.290484 # average ReadReq miss latency 900system.cpu.icache.ReadReq_avg_miss_latency::total 10536.290484 # average ReadReq miss latency 901system.cpu.icache.demand_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency 902system.cpu.icache.demand_avg_miss_latency::total 10536.290484 # average overall miss latency 903system.cpu.icache.overall_avg_miss_latency::cpu.inst 10536.290484 # average overall miss latency 904system.cpu.icache.overall_avg_miss_latency::total 10536.290484 # average overall miss latency 905system.cpu.icache.blocked_cycles::no_mshrs 264177 # number of cycles access was blocked 906system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked 907system.cpu.icache.blocked::no_mshrs 16495 # number of cycles access was blocked 908system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 909system.cpu.icache.avg_blocked_cycles::no_mshrs 16.015580 # average number of cycles each access was blocked 910system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked 911system.cpu.icache.writebacks::writebacks 325000 # number of writebacks 912system.cpu.icache.writebacks::total 325000 # number of writebacks 913system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9178 # number of ReadReq MSHR hits 914system.cpu.icache.ReadReq_mshr_hits::total 9178 # number of ReadReq MSHR hits 915system.cpu.icache.demand_mshr_hits::cpu.inst 9178 # number of demand (read+write) MSHR hits 916system.cpu.icache.demand_mshr_hits::total 9178 # number of demand (read+write) MSHR hits 917system.cpu.icache.overall_mshr_hits::cpu.inst 9178 # number of overall MSHR hits 918system.cpu.icache.overall_mshr_hits::total 9178 # number of overall MSHR hits 919system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325529 # number of ReadReq MSHR misses 920system.cpu.icache.ReadReq_mshr_misses::total 325529 # number of ReadReq MSHR misses 921system.cpu.icache.demand_mshr_misses::cpu.inst 325529 # number of demand (read+write) MSHR misses 922system.cpu.icache.demand_mshr_misses::total 325529 # number of demand (read+write) MSHR misses 923system.cpu.icache.overall_mshr_misses::cpu.inst 325529 # number of overall MSHR misses 924system.cpu.icache.overall_mshr_misses::total 325529 # number of overall MSHR misses 925system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 3259633220 # number of ReadReq MSHR miss cycles 926system.cpu.icache.ReadReq_mshr_miss_latency::total 3259633220 # number of ReadReq MSHR miss cycles 927system.cpu.icache.demand_mshr_miss_latency::cpu.inst 3259633220 # number of demand (read+write) MSHR miss cycles 928system.cpu.icache.demand_mshr_miss_latency::total 3259633220 # number of demand (read+write) MSHR miss cycles 929system.cpu.icache.overall_mshr_miss_latency::cpu.inst 3259633220 # number of overall MSHR miss cycles 930system.cpu.icache.overall_mshr_miss_latency::total 3259633220 # number of overall MSHR miss cycles 931system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for ReadReq accesses 932system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses 933system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for demand accesses 934system.cpu.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses 935system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014521 # mshr miss rate for overall accesses 936system.cpu.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses 937system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10013.342037 # average ReadReq mshr miss latency 938system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10013.342037 # average ReadReq mshr miss latency 939system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency 940system.cpu.icache.demand_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency 941system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10013.342037 # average overall mshr miss latency 942system.cpu.icache.overall_avg_mshr_miss_latency::total 10013.342037 # average overall mshr miss latency 943system.cpu.l2cache.prefetcher.num_hwpf_issued 822902 # number of hwpf issued 944system.cpu.l2cache.prefetcher.pfIdentified 826054 # number of prefetch candidates identified 945system.cpu.l2cache.prefetcher.pfBufferHit 2760 # number of redundant prefetches already in prefetch queue 946system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 947system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 948system.cpu.l2cache.prefetcher.pfSpanPage 78906 # number of prefetches not generated due to page crossing 949system.cpu.l2cache.tags.replacements 128177 # number of replacements 950system.cpu.l2cache.tags.tagsinuse 15989.063291 # Cycle average of tags in use 951system.cpu.l2cache.tags.total_refs 1184574 # Total number of references to valid blocks. 952system.cpu.l2cache.tags.sampled_refs 144531 # Sample count of references to valid blocks. 953system.cpu.l2cache.tags.avg_refs 8.195986 # Average number of references to valid blocks. 954system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 955system.cpu.l2cache.tags.occ_blocks::writebacks 15883.544788 # Average occupied blocks per requestor 956system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 105.518503 # Average occupied blocks per requestor 957system.cpu.l2cache.tags.occ_percent::writebacks 0.969455 # Average percentage of cache occupancy 958system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006440 # Average percentage of cache occupancy 959system.cpu.l2cache.tags.occ_percent::total 0.975895 # Average percentage of cache occupancy 960system.cpu.l2cache.tags.occ_task_id_blocks::1022 30 # Occupied blocks per task id 961system.cpu.l2cache.tags.occ_task_id_blocks::1024 16324 # Occupied blocks per task id 962system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id 963system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id 964system.cpu.l2cache.tags.age_task_id_blocks_1022::3 14 # Occupied blocks per task id 965system.cpu.l2cache.tags.age_task_id_blocks_1022::4 6 # Occupied blocks per task id 966system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 967system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2742 # Occupied blocks per task id 968system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12115 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1024::3 553 # Occupied blocks per task id 970system.cpu.l2cache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id 971system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001831 # Percentage of cache occupancy per task id 972system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996338 # Percentage of cache occupancy per task id 973system.cpu.l2cache.tags.tag_accesses 25089114 # Number of tag accesses 974system.cpu.l2cache.tags.data_accesses 25089114 # Number of data accesses 975system.cpu.l2cache.WritebackDirty_hits::writebacks 260314 # number of WritebackDirty hits 976system.cpu.l2cache.WritebackDirty_hits::total 260314 # number of WritebackDirty hits 977system.cpu.l2cache.WritebackClean_hits::writebacks 470737 # number of WritebackClean hits 978system.cpu.l2cache.WritebackClean_hits::total 470737 # number of WritebackClean hits 979system.cpu.l2cache.ReadExReq_hits::cpu.data 137093 # number of ReadExReq hits 980system.cpu.l2cache.ReadExReq_hits::total 137093 # number of ReadExReq hits 981system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 314576 # number of ReadCleanReq hits 982system.cpu.l2cache.ReadCleanReq_hits::total 314576 # number of ReadCleanReq hits 983system.cpu.l2cache.ReadSharedReq_hits::cpu.data 300687 # number of ReadSharedReq hits 984system.cpu.l2cache.ReadSharedReq_hits::total 300687 # number of ReadSharedReq hits 985system.cpu.l2cache.demand_hits::cpu.inst 314576 # number of demand (read+write) hits 986system.cpu.l2cache.demand_hits::cpu.data 437780 # number of demand (read+write) hits 987system.cpu.l2cache.demand_hits::total 752356 # number of demand (read+write) hits 988system.cpu.l2cache.overall_hits::cpu.inst 314576 # number of overall hits 989system.cpu.l2cache.overall_hits::cpu.data 437780 # number of overall hits 990system.cpu.l2cache.overall_hits::total 752356 # number of overall hits 991system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses 992system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses 993system.cpu.l2cache.ReadExReq_misses::cpu.data 11519 # number of ReadExReq misses 994system.cpu.l2cache.ReadExReq_misses::total 11519 # number of ReadExReq misses 995system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 10935 # number of ReadCleanReq misses 996system.cpu.l2cache.ReadCleanReq_misses::total 10935 # number of ReadCleanReq misses 997system.cpu.l2cache.ReadSharedReq_misses::cpu.data 37506 # number of ReadSharedReq misses 998system.cpu.l2cache.ReadSharedReq_misses::total 37506 # number of ReadSharedReq misses 999system.cpu.l2cache.demand_misses::cpu.inst 10935 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::cpu.data 49025 # number of demand (read+write) misses 1001system.cpu.l2cache.demand_misses::total 59960 # number of demand (read+write) misses 1002system.cpu.l2cache.overall_misses::cpu.inst 10935 # number of overall misses 1003system.cpu.l2cache.overall_misses::cpu.data 49025 # number of overall misses 1004system.cpu.l2cache.overall_misses::total 59960 # number of overall misses 1005system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1190791000 # number of ReadExReq miss cycles 1006system.cpu.l2cache.ReadExReq_miss_latency::total 1190791000 # number of ReadExReq miss cycles 1007system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 838826500 # number of ReadCleanReq miss cycles 1008system.cpu.l2cache.ReadCleanReq_miss_latency::total 838826500 # number of ReadCleanReq miss cycles 1009system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3069049000 # number of ReadSharedReq miss cycles 1010system.cpu.l2cache.ReadSharedReq_miss_latency::total 3069049000 # number of ReadSharedReq miss cycles 1011system.cpu.l2cache.demand_miss_latency::cpu.inst 838826500 # number of demand (read+write) miss cycles 1012system.cpu.l2cache.demand_miss_latency::cpu.data 4259840000 # number of demand (read+write) miss cycles 1013system.cpu.l2cache.demand_miss_latency::total 5098666500 # number of demand (read+write) miss cycles 1014system.cpu.l2cache.overall_miss_latency::cpu.inst 838826500 # number of overall miss cycles 1015system.cpu.l2cache.overall_miss_latency::cpu.data 4259840000 # number of overall miss cycles 1016system.cpu.l2cache.overall_miss_latency::total 5098666500 # number of overall miss cycles 1017system.cpu.l2cache.WritebackDirty_accesses::writebacks 260314 # number of WritebackDirty accesses(hits+misses) 1018system.cpu.l2cache.WritebackDirty_accesses::total 260314 # number of WritebackDirty accesses(hits+misses) 1019system.cpu.l2cache.WritebackClean_accesses::writebacks 470737 # number of WritebackClean accesses(hits+misses) 1020system.cpu.l2cache.WritebackClean_accesses::total 470737 # number of WritebackClean accesses(hits+misses) 1021system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 1022system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) 1023system.cpu.l2cache.ReadExReq_accesses::cpu.data 148612 # number of ReadExReq accesses(hits+misses) 1024system.cpu.l2cache.ReadExReq_accesses::total 148612 # number of ReadExReq accesses(hits+misses) 1025system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 325511 # number of ReadCleanReq accesses(hits+misses) 1026system.cpu.l2cache.ReadCleanReq_accesses::total 325511 # number of ReadCleanReq accesses(hits+misses) 1027system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 338193 # number of ReadSharedReq accesses(hits+misses) 1028system.cpu.l2cache.ReadSharedReq_accesses::total 338193 # number of ReadSharedReq accesses(hits+misses) 1029system.cpu.l2cache.demand_accesses::cpu.inst 325511 # number of demand (read+write) accesses 1030system.cpu.l2cache.demand_accesses::cpu.data 486805 # number of demand (read+write) accesses 1031system.cpu.l2cache.demand_accesses::total 812316 # number of demand (read+write) accesses 1032system.cpu.l2cache.overall_accesses::cpu.inst 325511 # number of overall (read+write) accesses 1033system.cpu.l2cache.overall_accesses::cpu.data 486805 # number of overall (read+write) accesses 1034system.cpu.l2cache.overall_accesses::total 812316 # number of overall (read+write) accesses 1035system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1036system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1037system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.077511 # miss rate for ReadExReq accesses 1038system.cpu.l2cache.ReadExReq_miss_rate::total 0.077511 # miss rate for ReadExReq accesses 1039system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.033593 # miss rate for ReadCleanReq accesses 1040system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.033593 # miss rate for ReadCleanReq accesses 1041system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.110901 # miss rate for ReadSharedReq accesses 1042system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.110901 # miss rate for ReadSharedReq accesses 1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.033593 # miss rate for demand accesses 1044system.cpu.l2cache.demand_miss_rate::cpu.data 0.100708 # miss rate for demand accesses 1045system.cpu.l2cache.demand_miss_rate::total 0.073814 # miss rate for demand accesses 1046system.cpu.l2cache.overall_miss_rate::cpu.inst 0.033593 # miss rate for overall accesses 1047system.cpu.l2cache.overall_miss_rate::cpu.data 0.100708 # miss rate for overall accesses 1048system.cpu.l2cache.overall_miss_rate::total 0.073814 # miss rate for overall accesses 1049system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 103376.247938 # average ReadExReq miss latency 1050system.cpu.l2cache.ReadExReq_avg_miss_latency::total 103376.247938 # average ReadExReq miss latency 1051system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76710.242341 # average ReadCleanReq miss latency 1052system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76710.242341 # average ReadCleanReq miss latency 1053system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81828.214152 # average ReadSharedReq miss latency 1054system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81828.214152 # average ReadSharedReq miss latency 1055system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76710.242341 # average overall miss latency 1056system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency 1057system.cpu.l2cache.demand_avg_miss_latency::total 85034.464643 # average overall miss latency 1058system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76710.242341 # average overall miss latency 1059system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86891.177970 # average overall miss latency 1060system.cpu.l2cache.overall_avg_miss_latency::total 85034.464643 # average overall miss latency 1061system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1062system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1063system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1064system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1065system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1066system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1067system.cpu.l2cache.unused_prefetches 424 # number of HardPF blocks evicted w/o reference 1068system.cpu.l2cache.writebacks::writebacks 97140 # number of writebacks 1069system.cpu.l2cache.writebacks::total 97140 # number of writebacks 1070system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3182 # number of ReadExReq MSHR hits 1071system.cpu.l2cache.ReadExReq_mshr_hits::total 3182 # number of ReadExReq MSHR hits 1072system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 28 # number of ReadCleanReq MSHR hits 1073system.cpu.l2cache.ReadCleanReq_mshr_hits::total 28 # number of ReadCleanReq MSHR hits 1074system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 100 # number of ReadSharedReq MSHR hits 1075system.cpu.l2cache.ReadSharedReq_mshr_hits::total 100 # number of ReadSharedReq MSHR hits 1076system.cpu.l2cache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits 1077system.cpu.l2cache.demand_mshr_hits::cpu.data 3282 # number of demand (read+write) MSHR hits 1078system.cpu.l2cache.demand_mshr_hits::total 3310 # number of demand (read+write) MSHR hits 1079system.cpu.l2cache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits 1080system.cpu.l2cache.overall_mshr_hits::cpu.data 3282 # number of overall MSHR hits 1081system.cpu.l2cache.overall_mshr_hits::total 3310 # number of overall MSHR hits 1082system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112662 # number of HardPFReq MSHR misses 1083system.cpu.l2cache.HardPFReq_mshr_misses::total 112662 # number of HardPFReq MSHR misses 1084system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses 1085system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses 1086system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8337 # number of ReadExReq MSHR misses 1087system.cpu.l2cache.ReadExReq_mshr_misses::total 8337 # number of ReadExReq MSHR misses 1088system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10907 # number of ReadCleanReq MSHR misses 1089system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10907 # number of ReadCleanReq MSHR misses 1090system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 37406 # number of ReadSharedReq MSHR misses 1091system.cpu.l2cache.ReadSharedReq_mshr_misses::total 37406 # number of ReadSharedReq MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 10907 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.demand_mshr_misses::cpu.data 45743 # number of demand (read+write) MSHR misses 1094system.cpu.l2cache.demand_mshr_misses::total 56650 # number of demand (read+write) MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 10907 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.data 45743 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112662 # number of overall MSHR misses 1098system.cpu.l2cache.overall_mshr_misses::total 169312 # number of overall MSHR misses 1099system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10325101509 # number of HardPFReq MSHR miss cycles 1100system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10325101509 # number of HardPFReq MSHR miss cycles 1101system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 232500 # number of UpgradeReq MSHR miss cycles 1102system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 232500 # number of UpgradeReq MSHR miss cycles 1103system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 662233000 # number of ReadExReq MSHR miss cycles 1104system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 662233000 # number of ReadExReq MSHR miss cycles 1105system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 771578500 # number of ReadCleanReq MSHR miss cycles 1106system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 771578500 # number of ReadCleanReq MSHR miss cycles 1107system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2838075000 # number of ReadSharedReq MSHR miss cycles 1108system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2838075000 # number of ReadSharedReq MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 771578500 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3500308000 # number of demand (read+write) MSHR miss cycles 1111system.cpu.l2cache.demand_mshr_miss_latency::total 4271886500 # number of demand (read+write) MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 771578500 # number of overall MSHR miss cycles 1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3500308000 # number of overall MSHR miss cycles 1114system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10325101509 # number of overall MSHR miss cycles 1115system.cpu.l2cache.overall_mshr_miss_latency::total 14596988009 # number of overall MSHR miss cycles 1116system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1117system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1118system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1119system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1120system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056099 # mshr miss rate for ReadExReq accesses 1121system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056099 # mshr miss rate for ReadExReq accesses 1122system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for ReadCleanReq accesses 1123system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033507 # mshr miss rate for ReadCleanReq accesses 1124system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.110605 # mshr miss rate for ReadSharedReq accesses 1125system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.110605 # mshr miss rate for ReadSharedReq accesses 1126system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for demand accesses 1127system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for demand accesses 1128system.cpu.l2cache.demand_mshr_miss_rate::total 0.069739 # mshr miss rate for demand accesses 1129system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.033507 # mshr miss rate for overall accesses 1130system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.093966 # mshr miss rate for overall accesses 1131system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1132system.cpu.l2cache.overall_mshr_miss_rate::total 0.208431 # mshr miss rate for overall accesses 1133system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average HardPFReq mshr miss latency 1134system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91646.708819 # average HardPFReq mshr miss latency 1135system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14531.250000 # average UpgradeReq mshr miss latency 1136system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14531.250000 # average UpgradeReq mshr miss latency 1137system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79433.009476 # average ReadExReq mshr miss latency 1138system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79433.009476 # average ReadExReq mshr miss latency 1139system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70741.587971 # average ReadCleanReq mshr miss latency 1140system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70741.587971 # average ReadCleanReq mshr miss latency 1141system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75872.186280 # average ReadSharedReq mshr miss latency 1142system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75872.186280 # average ReadSharedReq mshr miss latency 1143system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency 1144system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency 1145system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75408.411297 # average overall mshr miss latency 1146system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70741.587971 # average overall mshr miss latency 1147system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76521.172638 # average overall mshr miss latency 1148system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91646.708819 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::total 86213.546642 # average overall mshr miss latency 1150system.cpu.toL2Bus.snoop_filter.tot_requests 1623643 # Total number of requests made to the snoop filter. 1151system.cpu.toL2Bus.snoop_filter.hit_single_requests 811337 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1152system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1153system.cpu.toL2Bus.snoop_filter.tot_snoops 67456 # Total number of snoops made to the snoop filter. 1154system.cpu.toL2Bus.snoop_filter.hit_single_snoops 56671 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1155system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 10785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1156system.cpu.toL2Bus.trans_dist::ReadResp 663721 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::WritebackDirty 357454 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::WritebackClean 550979 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::CleanEvict 79349 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::HardPFReq 142185 # Transaction distribution 1161system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution 1162system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution 1163system.cpu.toL2Bus.trans_dist::ReadExReq 148612 # Transaction distribution 1164system.cpu.toL2Bus.trans_dist::ReadExResp 148612 # Transaction distribution 1165system.cpu.toL2Bus.trans_dist::ReadCleanReq 325529 # Transaction distribution 1166system.cpu.toL2Bus.trans_dist::ReadSharedReq 338193 # Transaction distribution 1167system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976039 # Packet count per connected master and slave (bytes) 1168system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1459935 # Packet count per connected master and slave (bytes) 1169system.cpu.toL2Bus.pkt_count::total 2435974 # Packet count per connected master and slave (bytes) 1170system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41632640 # Cumulative packet size per connected master and slave (bytes) 1171system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62278272 # Cumulative packet size per connected master and slave (bytes) 1172system.cpu.toL2Bus.pkt_size::total 103910912 # Cumulative packet size per connected master and slave (bytes) 1173system.cpu.toL2Bus.snoops 318692 # Total snoops (count) 1174system.cpu.toL2Bus.snoop_fanout::samples 1131024 # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::mean 0.140178 # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::stdev 0.373630 # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::0 983264 86.94% 86.94% # Request fanout histogram 1179system.cpu.toL2Bus.snoop_fanout::1 136975 12.11% 99.05% # Request fanout histogram 1180system.cpu.toL2Bus.snoop_fanout::2 10785 0.95% 100.00% # Request fanout histogram 1181system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1182system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1183system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1184system.cpu.toL2Bus.snoop_fanout::total 1131024 # Request fanout histogram 1185system.cpu.toL2Bus.reqLayer0.occupancy 1623114500 # Layer occupancy (ticks) 1186system.cpu.toL2Bus.reqLayer0.utilization 4.8 # Layer utilization (%) 1187system.cpu.toL2Bus.respLayer0.occupancy 488687208 # Layer occupancy (ticks) 1188system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 1189system.cpu.toL2Bus.respLayer1.occupancy 730433064 # Layer occupancy (ticks) 1190system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) 1191system.membus.trans_dist::ReadResp 144751 # Transaction distribution 1192system.membus.trans_dist::WritebackDirty 97140 # Transaction distribution 1193system.membus.trans_dist::CleanEvict 28117 # Transaction distribution 1194system.membus.trans_dist::UpgradeReq 16 # Transaction distribution 1195system.membus.trans_dist::ReadExReq 8337 # Transaction distribution 1196system.membus.trans_dist::ReadExResp 8337 # Transaction distribution 1197system.membus.trans_dist::ReadSharedReq 144752 # Transaction distribution 1198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 431450 # Packet count per connected master and slave (bytes) 1199system.membus.pkt_count::total 431450 # Packet count per connected master and slave (bytes) 1200system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16014592 # Cumulative packet size per connected master and slave (bytes) 1201system.membus.pkt_size::total 16014592 # Cumulative packet size per connected master and slave (bytes) 1202system.membus.snoops 0 # Total snoops (count) 1203system.membus.snoop_fanout::samples 278362 # Request fanout histogram 1204system.membus.snoop_fanout::mean 0 # Request fanout histogram 1205system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1206system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1207system.membus.snoop_fanout::0 278362 100.00% 100.00% # Request fanout histogram 1208system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1209system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1210system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1211system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1212system.membus.snoop_fanout::total 278362 # Request fanout histogram 1213system.membus.reqLayer0.occupancy 747889943 # Layer occupancy (ticks) 1214system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) 1215system.membus.respLayer1.occupancy 799798093 # Layer occupancy (ticks) 1216system.membus.respLayer1.utilization 2.4 # Layer utilization (%) 1217 1218---------- End Simulation Statistics ---------- 1219