stats.txt revision 10636
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.033020 # Number of seconds simulated 4sim_ticks 33019504000 # Number of ticks simulated 5final_tick 33019504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 123822 # Simulator instruction rate (inst/s) 8host_op_rate 158353 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57659893 # Simulator tick rate (ticks/s) 10host_mem_usage 322352 # Number of bytes of host memory used 11host_seconds 572.66 # Real time elapsed on the host 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 90682584 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 588736 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2517376 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 6201600 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9307712 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 588736 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 588736 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6262016 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6262016 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 9199 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 39334 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 96900 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 145433 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 97844 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 97844 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 17829947 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 76239062 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 187816268 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 281885276 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 17829947 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 17829947 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 189645974 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 189645974 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 189645974 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 17829947 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 76239062 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 187816268 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 471531250 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 145433 # Number of read requests accepted 44system.physmem.writeReqs 97844 # Number of write requests accepted 45system.physmem.readBursts 145433 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 97844 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 9300480 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue 49system.physmem.bytesWritten 6260352 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 9307712 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 6262016 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 9146 # Per bank write bursts 56system.physmem.perBankRdBursts::1 9381 # Per bank write bursts 57system.physmem.perBankRdBursts::2 9349 # Per bank write bursts 58system.physmem.perBankRdBursts::3 9489 # Per bank write bursts 59system.physmem.perBankRdBursts::4 9691 # Per bank write bursts 60system.physmem.perBankRdBursts::5 9742 # Per bank write bursts 61system.physmem.perBankRdBursts::6 9065 # Per bank write bursts 62system.physmem.perBankRdBursts::7 9033 # Per bank write bursts 63system.physmem.perBankRdBursts::8 9160 # Per bank write bursts 64system.physmem.perBankRdBursts::9 8585 # Per bank write bursts 65system.physmem.perBankRdBursts::10 8818 # Per bank write bursts 66system.physmem.perBankRdBursts::11 8754 # Per bank write bursts 67system.physmem.perBankRdBursts::12 8666 # Per bank write bursts 68system.physmem.perBankRdBursts::13 8713 # Per bank write bursts 69system.physmem.perBankRdBursts::14 8726 # Per bank write bursts 70system.physmem.perBankRdBursts::15 9002 # Per bank write bursts 71system.physmem.perBankWrBursts::0 5993 # Per bank write bursts 72system.physmem.perBankWrBursts::1 6194 # Per bank write bursts 73system.physmem.perBankWrBursts::2 6159 # Per bank write bursts 74system.physmem.perBankWrBursts::3 6198 # Per bank write bursts 75system.physmem.perBankWrBursts::4 6133 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6325 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6074 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6046 # Per bank write bursts 79system.physmem.perBankWrBursts::8 6012 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6139 # Per bank write bursts 81system.physmem.perBankWrBursts::10 6243 # Per bank write bursts 82system.physmem.perBankWrBursts::11 5934 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6049 # Per bank write bursts 84system.physmem.perBankWrBursts::13 6103 # Per bank write bursts 85system.physmem.perBankWrBursts::14 6164 # Per bank write bursts 86system.physmem.perBankWrBursts::15 6052 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 33019298500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 145433 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 97844 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 47136 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 46826 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 17078 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 9801 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 6398 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 5373 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 4750 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4278 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3551 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1117 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1152 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1935 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 2597 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 3403 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4356 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5168 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5608 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5930 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6190 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6581 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 7181 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 7838 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 8277 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 7722 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 7174 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6437 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 72 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 88783 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 175.237151 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 110.501041 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 239.251674 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 52191 58.78% 58.78% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 22671 25.54% 84.32% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4463 5.03% 89.35% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1678 1.89% 91.24% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 979 1.10% 92.34% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 876 0.99% 93.33% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 737 0.83% 94.16% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 796 0.90% 95.05% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 4392 4.95% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 88783 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5909 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 24.589101 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 21.077809 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 187.247746 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 5908 99.98% 99.98% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 5909 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 5909 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 16.554070 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 16.510446 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.278697 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 4738 80.18% 80.18% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::17 25 0.42% 80.61% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18 725 12.27% 92.88% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::19 165 2.79% 95.67% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::20 107 1.81% 97.48% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::21 76 1.29% 98.76% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::22 36 0.61% 99.37% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::23 24 0.41% 99.78% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::24 8 0.14% 99.92% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::total 5909 # Writes before turning the bus around for reads 237system.physmem.totQLat 7598607995 # Total ticks spent queuing 238system.physmem.totMemAccLat 10323357995 # Total ticks spent from burst creation until serviced by the DRAM 239system.physmem.totBusLat 726600000 # Total ticks spent in databus transfers 240system.physmem.avgQLat 52288.80 # Average queueing delay per DRAM burst 241system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 242system.physmem.avgMemAccLat 71038.80 # Average memory access latency per DRAM burst 243system.physmem.avgRdBW 281.67 # Average DRAM read bandwidth in MiByte/s 244system.physmem.avgWrBW 189.60 # Average achieved write bandwidth in MiByte/s 245system.physmem.avgRdBWSys 281.89 # Average system read bandwidth in MiByte/s 246system.physmem.avgWrBWSys 189.65 # Average system write bandwidth in MiByte/s 247system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 248system.physmem.busUtil 3.68 # Data bus utilization in percentage 249system.physmem.busUtilRead 2.20 # Data bus utilization in percentage for reads 250system.physmem.busUtilWrite 1.48 # Data bus utilization in percentage for writes 251system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing 252system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing 253system.physmem.readRowHits 118226 # Number of row buffer hits during reads 254system.physmem.writeRowHits 36119 # Number of row buffer hits during writes 255system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads 256system.physmem.writeRowHitRate 36.91 # Row buffer hit rate for writes 257system.physmem.avgGap 135727.17 # Average gap between requests 258system.physmem.pageHitRate 63.47 # Row buffer hit rate, read and write combined 259system.physmem_0.actEnergy 342362160 # Energy for activate commands per rank (pJ) 260system.physmem_0.preEnergy 186804750 # Energy for precharge commands per rank (pJ) 261system.physmem_0.readEnergy 583720800 # Energy for read commands per rank (pJ) 262system.physmem_0.writeEnergy 318193920 # Energy for write commands per rank (pJ) 263system.physmem_0.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) 264system.physmem_0.actBackEnergy 11787255720 # Energy for active background per rank (pJ) 265system.physmem_0.preBackEnergy 9468687000 # Energy for precharge background per rank (pJ) 266system.physmem_0.totalEnergy 24843318750 # Total energy per rank (pJ) 267system.physmem_0.averagePower 752.509165 # Core power per rank (mW) 268system.physmem_0.memoryStateTime::IDLE 15653624306 # Time in different power states 269system.physmem_0.memoryStateTime::REF 1102400000 # Time in different power states 270system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 271system.physmem_0.memoryStateTime::ACT 16257963444 # Time in different power states 272system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 273system.physmem_1.actEnergy 328376160 # Energy for activate commands per rank (pJ) 274system.physmem_1.preEnergy 179173500 # Energy for precharge commands per rank (pJ) 275system.physmem_1.readEnergy 549010800 # Energy for read commands per rank (pJ) 276system.physmem_1.writeEnergy 315414000 # Energy for write commands per rank (pJ) 277system.physmem_1.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) 278system.physmem_1.actBackEnergy 11313288180 # Energy for active background per rank (pJ) 279system.physmem_1.preBackEnergy 9884473500 # Energy for precharge background per rank (pJ) 280system.physmem_1.totalEnergy 24726030540 # Total energy per rank (pJ) 281system.physmem_1.averagePower 748.955517 # Core power per rank (mW) 282system.physmem_1.memoryStateTime::IDLE 16351310453 # Time in different power states 283system.physmem_1.memoryStateTime::REF 1102400000 # Time in different power states 284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_1.memoryStateTime::ACT 15560341797 # Time in different power states 286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.cpu.branchPred.lookups 17204705 # Number of BP lookups 288system.cpu.branchPred.condPredicted 11516912 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 648025 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 9345879 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 7673903 # Number of BTB hits 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 82.110019 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 1872530 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 101564 # Number of incorrect RAS predictions. 296system.cpu_clk_domain.clock 500 # Clock period in ticks 297system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 306system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 307system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 308system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 309system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 310system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 314system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 315system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 316system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 317system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 318system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 319system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 320system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 321system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 322system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 323system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 324system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 325system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 326system.cpu.dtb.walker.walks 0 # Table walker walks requested 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.inst_hits 0 # ITB inst hits 335system.cpu.dtb.inst_misses 0 # ITB inst misses 336system.cpu.dtb.read_hits 0 # DTB read hits 337system.cpu.dtb.read_misses 0 # DTB read misses 338system.cpu.dtb.write_hits 0 # DTB write hits 339system.cpu.dtb.write_misses 0 # DTB write misses 340system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 341system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 342system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 343system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 344system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 345system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 346system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 347system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 348system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 349system.cpu.dtb.read_accesses 0 # DTB read accesses 350system.cpu.dtb.write_accesses 0 # DTB write accesses 351system.cpu.dtb.inst_accesses 0 # ITB inst accesses 352system.cpu.dtb.hits 0 # DTB hits 353system.cpu.dtb.misses 0 # DTB misses 354system.cpu.dtb.accesses 0 # DTB accesses 355system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 364system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 365system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 366system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 367system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 368system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 372system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 373system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 374system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 375system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 376system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 384system.cpu.itb.walker.walks 0 # Table walker walks requested 385system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.inst_hits 0 # ITB inst hits 393system.cpu.itb.inst_misses 0 # ITB inst misses 394system.cpu.itb.read_hits 0 # DTB read hits 395system.cpu.itb.read_misses 0 # DTB read misses 396system.cpu.itb.write_hits 0 # DTB write hits 397system.cpu.itb.write_misses 0 # DTB write misses 398system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 399system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 400system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 401system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 402system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 403system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 404system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 405system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 406system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 407system.cpu.itb.read_accesses 0 # DTB read accesses 408system.cpu.itb.write_accesses 0 # DTB write accesses 409system.cpu.itb.inst_accesses 0 # ITB inst accesses 410system.cpu.itb.hits 0 # DTB hits 411system.cpu.itb.misses 0 # DTB misses 412system.cpu.itb.accesses 0 # DTB accesses 413system.cpu.workload.num_syscalls 1946 # Number of system calls 414system.cpu.numCycles 66039009 # number of cpu cycles simulated 415system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 416system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 417system.cpu.fetch.icacheStallCycles 4981802 # Number of cycles fetch is stalled on an Icache miss 418system.cpu.fetch.Insts 88178088 # Number of instructions fetch has processed 419system.cpu.fetch.Branches 17204705 # Number of branches that fetch encountered 420system.cpu.fetch.predictedBranches 9546433 # Number of branches that fetch has predicted taken 421system.cpu.fetch.Cycles 59635234 # Number of cycles fetch has run and was not squashing or blocked 422system.cpu.fetch.SquashCycles 1322107 # Number of cycles fetch has spent squashing 423system.cpu.fetch.MiscStallCycles 4931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 424system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps 425system.cpu.fetch.IcacheWaitRetryStallCycles 10977 # Number of stall cycles due to full MSHR 426system.cpu.fetch.CacheLines 22758925 # Number of cache lines fetched 427system.cpu.fetch.IcacheSquashes 68935 # Number of outstanding Icache misses that were squashed 428system.cpu.fetch.rateDist::samples 65294039 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::mean 1.709071 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::stdev 1.292735 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::0 19515211 29.89% 29.89% # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::1 8274054 12.67% 42.56% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::2 9196195 14.08% 56.64% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::3 28308579 43.36% 100.00% # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::total 65294039 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.branchRate 0.260523 # Number of branch fetches per cycle 441system.cpu.fetch.rate 1.335242 # Number of inst fetches per cycle 442system.cpu.decode.IdleCycles 8590503 # Number of cycles decode is idle 443system.cpu.decode.BlockedCycles 19016582 # Number of cycles decode is blocked 444system.cpu.decode.RunCycles 31530881 # Number of cycles decode is running 445system.cpu.decode.UnblockCycles 5663983 # Number of cycles decode is unblocking 446system.cpu.decode.SquashCycles 492090 # Number of cycles decode is squashing 447system.cpu.decode.BranchResolved 3178633 # Number of times decode resolved a branch 448system.cpu.decode.BranchMispred 170869 # Number of times decode detected a branch misprediction 449system.cpu.decode.DecodedInsts 101389113 # Number of instructions handled by decode 450system.cpu.decode.SquashedInsts 3042046 # Number of squashed instructions handled by decode 451system.cpu.rename.SquashCycles 492090 # Number of cycles rename is squashing 452system.cpu.rename.IdleCycles 13367671 # Number of cycles rename is idle 453system.cpu.rename.BlockCycles 5222790 # Number of cycles rename is blocking 454system.cpu.rename.serializeStallCycles 763292 # count of cycles rename stalled for serializing inst 455system.cpu.rename.RunCycles 32193949 # Number of cycles rename is running 456system.cpu.rename.UnblockCycles 13254247 # Number of cycles rename is unblocking 457system.cpu.rename.RenamedInsts 99181436 # Number of instructions processed by rename 458system.cpu.rename.SquashedInsts 981589 # Number of squashed instructions processed by rename 459system.cpu.rename.ROBFullEvents 3720885 # Number of times rename has blocked due to ROB full 460system.cpu.rename.IQFullEvents 53337 # Number of times rename has blocked due to IQ full 461system.cpu.rename.LQFullEvents 4029509 # Number of times rename has blocked due to LQ full 462system.cpu.rename.SQFullEvents 5185175 # Number of times rename has blocked due to SQ full 463system.cpu.rename.RenamedOperands 103906436 # Number of destination operands rename has renamed 464system.cpu.rename.RenameLookups 457606733 # Number of register rename lookups that rename has made 465system.cpu.rename.int_rename_lookups 115387380 # Number of integer rename lookups 466system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups 467system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed 468system.cpu.rename.UndoneMaps 10277210 # Number of HB maps that are undone due to squashing 469system.cpu.rename.serializingInsts 18665 # count of serializing insts renamed 470system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed 471system.cpu.rename.skidInsts 12765420 # count of insts added to the skid buffer 472system.cpu.memDep0.insertedLoads 24319642 # Number of loads inserted to the mem dependence unit. 473system.cpu.memDep0.insertedStores 21987038 # Number of stores inserted to the mem dependence unit. 474system.cpu.memDep0.conflictingLoads 1312197 # Number of conflicting loads. 475system.cpu.memDep0.conflictingStores 2209009 # Number of conflicting stores. 476system.cpu.iq.iqInstsAdded 98145273 # Number of instructions added to the IQ (excludes non-spec) 477system.cpu.iq.iqNonSpecInstsAdded 34526 # Number of non-speculative instructions added to the IQ 478system.cpu.iq.iqInstsIssued 94858951 # Number of instructions issued 479system.cpu.iq.iqSquashedInstsIssued 691771 # Number of squashed instructions issued 480system.cpu.iq.iqSquashedInstsExamined 7393055 # Number of squashed instructions iterated over during squash; mainly for profiling 481system.cpu.iq.iqSquashedOperandsExamined 20168064 # Number of squashed operands that are examined and possibly removed from graph 482system.cpu.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed 483system.cpu.iq.issued_per_cycle::samples 65294039 # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::mean 1.452796 # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::stdev 1.148580 # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::0 17159256 26.28% 26.28% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::1 17193875 26.33% 52.61% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::2 17194261 26.33% 78.95% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::3 11711028 17.94% 96.88% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::4 2034625 3.12% 100.00% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::5 994 0.00% 100.00% # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::total 65294039 # Number of insts issued each cycle 500system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 501system.cpu.iq.fu_full::IntAlu 6670808 22.11% 22.11% # attempts to use FU when none available 502system.cpu.iq.fu_full::IntMult 41 0.00% 22.11% # attempts to use FU when none available 503system.cpu.iq.fu_full::IntDiv 0 0.00% 22.11% # attempts to use FU when none available 504system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.11% # attempts to use FU when none available 505system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.11% # attempts to use FU when none available 506system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.11% # attempts to use FU when none available 507system.cpu.iq.fu_full::FloatMult 0 0.00% 22.11% # attempts to use FU when none available 508system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.11% # attempts to use FU when none available 509system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.11% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.11% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.11% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.11% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.11% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.11% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.11% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdMult 0 0.00% 22.11% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.11% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdShift 0 0.00% 22.11% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.11% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.11% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.11% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.11% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.11% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.11% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.11% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.11% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.11% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.11% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.11% # attempts to use FU when none available 530system.cpu.iq.fu_full::MemRead 11293243 37.42% 59.53% # attempts to use FU when none available 531system.cpu.iq.fu_full::MemWrite 12213472 40.47% 100.00% # attempts to use FU when none available 532system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 533system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 534system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 535system.cpu.iq.FU_type_0::IntAlu 49494148 52.18% 52.18% # Type of FU issued 536system.cpu.iq.FU_type_0::IntMult 89879 0.09% 52.27% # Type of FU issued 537system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.27% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued 541system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued 542system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued 543system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued 564system.cpu.iq.FU_type_0::MemRead 24035201 25.34% 77.61% # Type of FU issued 565system.cpu.iq.FU_type_0::MemWrite 21239685 22.39% 100.00% # Type of FU issued 566system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 567system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 568system.cpu.iq.FU_type_0::total 94858951 # Type of FU issued 569system.cpu.iq.rate 1.436408 # Inst issue rate 570system.cpu.iq.fu_busy_cnt 30177564 # FU busy when requested 571system.cpu.iq.fu_busy_rate 0.318131 # FU busy rate (busy events/executed inst) 572system.cpu.iq.int_inst_queue_reads 285881069 # Number of integer instruction queue reads 573system.cpu.iq.int_inst_queue_writes 105584154 # Number of integer instruction queue writes 574system.cpu.iq.int_inst_queue_wakeup_accesses 93463006 # Number of integer instruction queue wakeup accesses 575system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads 576system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes 577system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses 578system.cpu.iq.int_alu_accesses 125036397 # Number of integer alu accesses 579system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses 580system.cpu.iew.lsq.thread0.forwLoads 1353483 # Number of loads that had data forwarded from stores 581system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 582system.cpu.iew.lsq.thread0.squashedLoads 1453380 # Number of loads squashed 583system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed 584system.cpu.iew.lsq.thread0.memOrderViolation 11797 # Number of memory ordering violations 585system.cpu.iew.lsq.thread0.squashedStores 1431300 # Number of stores squashed 586system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 587system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 588system.cpu.iew.lsq.thread0.rescheduledLoads 120407 # Number of loads that were rescheduled 589system.cpu.iew.lsq.thread0.cacheBlocked 169543 # Number of times an access to memory failed due to the cache being blocked 590system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 591system.cpu.iew.iewSquashCycles 492090 # Number of cycles IEW is squashing 592system.cpu.iew.iewBlockCycles 617243 # Number of cycles IEW is blocking 593system.cpu.iew.iewUnblockCycles 370435 # Number of cycles IEW is unblocking 594system.cpu.iew.iewDispatchedInsts 98189662 # Number of instructions dispatched to IQ 595system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 596system.cpu.iew.iewDispLoadInsts 24319642 # Number of dispatched load instructions 597system.cpu.iew.iewDispStoreInsts 21987038 # Number of dispatched store instructions 598system.cpu.iew.iewDispNonSpecInsts 18606 # Number of dispatched non-speculative instructions 599system.cpu.iew.iewIQFullEvents 1603 # Number of times the IQ has become full, causing a stall 600system.cpu.iew.iewLSQFullEvents 365951 # Number of times the LSQ has become full, causing a stall 601system.cpu.iew.memOrderViolationEvents 11797 # Number of memory order violations 602system.cpu.iew.predictedTakenIncorrect 302833 # Number of branches that were predicted taken incorrectly 603system.cpu.iew.predictedNotTakenIncorrect 221503 # Number of branches that were predicted not taken incorrectly 604system.cpu.iew.branchMispredicts 524336 # Number of branch mispredicts detected at execute 605system.cpu.iew.iewExecutedInsts 93942350 # Number of executed instructions 606system.cpu.iew.iewExecLoadInsts 23727911 # Number of load instructions executed 607system.cpu.iew.iewExecSquashedInsts 916601 # Number of squashed instructions skipped in execute 608system.cpu.iew.exec_swp 0 # number of swp insts executed 609system.cpu.iew.exec_nop 9863 # number of nop insts executed 610system.cpu.iew.exec_refs 44710370 # number of memory reference insts executed 611system.cpu.iew.exec_branches 14251746 # Number of branches executed 612system.cpu.iew.exec_stores 20982459 # Number of stores executed 613system.cpu.iew.exec_rate 1.422528 # Inst execution rate 614system.cpu.iew.wb_sent 93584307 # cumulative count of insts sent to commit 615system.cpu.iew.wb_count 93463063 # cumulative count of insts written-back 616system.cpu.iew.wb_producers 44927637 # num instructions producing a value 617system.cpu.iew.wb_consumers 76497349 # num instructions consuming a value 618system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 619system.cpu.iew.wb_rate 1.415271 # insts written-back per cycle 620system.cpu.iew.wb_fanout 0.587310 # average fanout of values written-back 621system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 622system.cpu.commit.commitSquashedInsts 6519180 # The number of squashed insts skipped by commit 623system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 624system.cpu.commit.branchMispredicts 479062 # The number of times a branch was mispredicted 625system.cpu.commit.committed_per_cycle::samples 64238392 # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::mean 1.411744 # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::stdev 2.175817 # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::0 30786432 47.93% 47.93% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::1 16709618 26.01% 73.94% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::2 4274980 6.65% 80.59% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::3 4124415 6.42% 87.01% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::4 1949899 3.04% 90.05% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::5 1296449 2.02% 92.07% # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::6 706597 1.10% 93.17% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::7 586126 0.91% 94.08% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::8 3803876 5.92% 100.00% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::total 64238392 # Number of insts commited each cycle 642system.cpu.commit.committedInsts 70913181 # Number of instructions committed 643system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed 644system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 645system.cpu.commit.refs 43422000 # Number of memory references committed 646system.cpu.commit.loads 22866262 # Number of loads committed 647system.cpu.commit.membars 15920 # Number of memory barriers committed 648system.cpu.commit.branches 13741485 # Number of branches committed 649system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 650system.cpu.commit.int_insts 81528487 # Number of committed integer instructions. 651system.cpu.commit.function_calls 1679850 # Number of function calls committed. 652system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 653system.cpu.commit.op_class_0::IntAlu 47186010 52.03% 52.03% # Class of committed instruction 654system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 655system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 656system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 657system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 658system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 659system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction 660system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction 661system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 682system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 683system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 684system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction 687system.cpu.commit.bw_lim_events 3803876 # number cycles where commit BW limit reached 688system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 689system.cpu.rob.rob_reads 157616533 # The number of ROB reads 690system.cpu.rob.rob_writes 195472136 # The number of ROB writes 691system.cpu.timesIdled 23660 # Number of times that the entire CPU went into an idle state and unscheduled itself 692system.cpu.idleCycles 744970 # Total number of cycles that the CPU has spent unscheduled due to idling 693system.cpu.committedInsts 70907629 # Number of Instructions Simulated 694system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated 695system.cpu.cpi 0.931339 # CPI: Cycles Per Instruction 696system.cpu.cpi_total 0.931339 # CPI: Total CPI of All Threads 697system.cpu.ipc 1.073723 # IPC: Instructions Per Cycle 698system.cpu.ipc_total 1.073723 # IPC: Total IPC of All Threads 699system.cpu.int_regfile_reads 102238235 # number of integer regfile reads 700system.cpu.int_regfile_writes 56792997 # number of integer regfile writes 701system.cpu.fp_regfile_reads 36 # number of floating regfile reads 702system.cpu.fp_regfile_writes 21 # number of floating regfile writes 703system.cpu.cc_regfile_reads 345997909 # number of cc regfile reads 704system.cpu.cc_regfile_writes 38804494 # number of cc regfile writes 705system.cpu.misc_regfile_reads 44208348 # number of misc regfile reads 706system.cpu.misc_regfile_writes 31840 # number of misc regfile writes 707system.cpu.dcache.tags.replacements 485280 # number of replacements 708system.cpu.dcache.tags.tagsinuse 510.769602 # Cycle average of tags in use 709system.cpu.dcache.tags.total_refs 40441610 # Total number of references to valid blocks. 710system.cpu.dcache.tags.sampled_refs 485792 # Sample count of references to valid blocks. 711system.cpu.dcache.tags.avg_refs 83.248818 # Average number of references to valid blocks. 712system.cpu.dcache.tags.warmup_cycle 148406000 # Cycle when the warmup percentage was hit. 713system.cpu.dcache.tags.occ_blocks::cpu.data 510.769602 # Average occupied blocks per requestor 714system.cpu.dcache.tags.occ_percent::cpu.data 0.997597 # Average percentage of cache occupancy 715system.cpu.dcache.tags.occ_percent::total 0.997597 # Average percentage of cache occupancy 716system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 717system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 718system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id 719system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 720system.cpu.dcache.tags.tag_accesses 84635072 # Number of tag accesses 721system.cpu.dcache.tags.data_accesses 84635072 # Number of data accesses 722system.cpu.dcache.ReadReq_hits::cpu.data 21513403 # number of ReadReq hits 723system.cpu.dcache.ReadReq_hits::total 21513403 # number of ReadReq hits 724system.cpu.dcache.WriteReq_hits::cpu.data 18834640 # number of WriteReq hits 725system.cpu.dcache.WriteReq_hits::total 18834640 # number of WriteReq hits 726system.cpu.dcache.SoftPFReq_hits::cpu.data 62245 # number of SoftPFReq hits 727system.cpu.dcache.SoftPFReq_hits::total 62245 # number of SoftPFReq hits 728system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits 729system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits 730system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 731system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 732system.cpu.dcache.demand_hits::cpu.data 40348043 # number of demand (read+write) hits 733system.cpu.dcache.demand_hits::total 40348043 # number of demand (read+write) hits 734system.cpu.dcache.overall_hits::cpu.data 40410288 # number of overall hits 735system.cpu.dcache.overall_hits::total 40410288 # number of overall hits 736system.cpu.dcache.ReadReq_misses::cpu.data 550665 # number of ReadReq misses 737system.cpu.dcache.ReadReq_misses::total 550665 # number of ReadReq misses 738system.cpu.dcache.WriteReq_misses::cpu.data 1015261 # number of WriteReq misses 739system.cpu.dcache.WriteReq_misses::total 1015261 # number of WriteReq misses 740system.cpu.dcache.SoftPFReq_misses::cpu.data 66581 # number of SoftPFReq misses 741system.cpu.dcache.SoftPFReq_misses::total 66581 # number of SoftPFReq misses 742system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses 743system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses 744system.cpu.dcache.demand_misses::cpu.data 1565926 # number of demand (read+write) misses 745system.cpu.dcache.demand_misses::total 1565926 # number of demand (read+write) misses 746system.cpu.dcache.overall_misses::cpu.data 1632507 # number of overall misses 747system.cpu.dcache.overall_misses::total 1632507 # number of overall misses 748system.cpu.dcache.ReadReq_miss_latency::cpu.data 8659099753 # number of ReadReq miss cycles 749system.cpu.dcache.ReadReq_miss_latency::total 8659099753 # number of ReadReq miss cycles 750system.cpu.dcache.WriteReq_miss_latency::cpu.data 14372727937 # number of WriteReq miss cycles 751system.cpu.dcache.WriteReq_miss_latency::total 14372727937 # number of WriteReq miss cycles 752system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4891750 # number of LoadLockedReq miss cycles 753system.cpu.dcache.LoadLockedReq_miss_latency::total 4891750 # number of LoadLockedReq miss cycles 754system.cpu.dcache.demand_miss_latency::cpu.data 23031827690 # number of demand (read+write) miss cycles 755system.cpu.dcache.demand_miss_latency::total 23031827690 # number of demand (read+write) miss cycles 756system.cpu.dcache.overall_miss_latency::cpu.data 23031827690 # number of overall miss cycles 757system.cpu.dcache.overall_miss_latency::total 23031827690 # number of overall miss cycles 758system.cpu.dcache.ReadReq_accesses::cpu.data 22064068 # number of ReadReq accesses(hits+misses) 759system.cpu.dcache.ReadReq_accesses::total 22064068 # number of ReadReq accesses(hits+misses) 760system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 761system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 762system.cpu.dcache.SoftPFReq_accesses::cpu.data 128826 # number of SoftPFReq accesses(hits+misses) 763system.cpu.dcache.SoftPFReq_accesses::total 128826 # number of SoftPFReq accesses(hits+misses) 764system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) 765system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) 766system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 767system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 768system.cpu.dcache.demand_accesses::cpu.data 41913969 # number of demand (read+write) accesses 769system.cpu.dcache.demand_accesses::total 41913969 # number of demand (read+write) accesses 770system.cpu.dcache.overall_accesses::cpu.data 42042795 # number of overall (read+write) accesses 771system.cpu.dcache.overall_accesses::total 42042795 # number of overall (read+write) accesses 772system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024958 # miss rate for ReadReq accesses 773system.cpu.dcache.ReadReq_miss_rate::total 0.024958 # miss rate for ReadReq accesses 774system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051147 # miss rate for WriteReq accesses 775system.cpu.dcache.WriteReq_miss_rate::total 0.051147 # miss rate for WriteReq accesses 776system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516829 # miss rate for SoftPFReq accesses 777system.cpu.dcache.SoftPFReq_miss_rate::total 0.516829 # miss rate for SoftPFReq accesses 778system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses 779system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses 780system.cpu.dcache.demand_miss_rate::cpu.data 0.037360 # miss rate for demand accesses 781system.cpu.dcache.demand_miss_rate::total 0.037360 # miss rate for demand accesses 782system.cpu.dcache.overall_miss_rate::cpu.data 0.038830 # miss rate for overall accesses 783system.cpu.dcache.overall_miss_rate::total 0.038830 # miss rate for overall accesses 784system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15724.805014 # average ReadReq miss latency 785system.cpu.dcache.ReadReq_avg_miss_latency::total 15724.805014 # average ReadReq miss latency 786system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14156.682801 # average WriteReq miss latency 787system.cpu.dcache.WriteReq_avg_miss_latency::total 14156.682801 # average WriteReq miss latency 788system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8942.870201 # average LoadLockedReq miss latency 789system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8942.870201 # average LoadLockedReq miss latency 790system.cpu.dcache.demand_avg_miss_latency::cpu.data 14708.120109 # average overall miss latency 791system.cpu.dcache.demand_avg_miss_latency::total 14708.120109 # average overall miss latency 792system.cpu.dcache.overall_avg_miss_latency::cpu.data 14108.256620 # average overall miss latency 793system.cpu.dcache.overall_avg_miss_latency::total 14108.256620 # average overall miss latency 794system.cpu.dcache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked 795system.cpu.dcache.blocked_cycles::no_targets 2883834 # number of cycles access was blocked 796system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 797system.cpu.dcache.blocked::no_targets 127457 # number of cycles access was blocked 798system.cpu.dcache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked 799system.cpu.dcache.avg_blocked_cycles::no_targets 22.625937 # average number of cycles each access was blocked 800system.cpu.dcache.fast_writes 0 # number of fast writes performed 801system.cpu.dcache.cache_copies 0 # number of cache copies performed 802system.cpu.dcache.writebacks::writebacks 264417 # number of writebacks 803system.cpu.dcache.writebacks::total 264417 # number of writebacks 804system.cpu.dcache.ReadReq_mshr_hits::cpu.data 250985 # number of ReadReq MSHR hits 805system.cpu.dcache.ReadReq_mshr_hits::total 250985 # number of ReadReq MSHR hits 806system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866735 # number of WriteReq MSHR hits 807system.cpu.dcache.WriteReq_mshr_hits::total 866735 # number of WriteReq MSHR hits 808system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # number of LoadLockedReq MSHR hits 809system.cpu.dcache.LoadLockedReq_mshr_hits::total 547 # number of LoadLockedReq MSHR hits 810system.cpu.dcache.demand_mshr_hits::cpu.data 1117720 # number of demand (read+write) MSHR hits 811system.cpu.dcache.demand_mshr_hits::total 1117720 # number of demand (read+write) MSHR hits 812system.cpu.dcache.overall_mshr_hits::cpu.data 1117720 # number of overall MSHR hits 813system.cpu.dcache.overall_mshr_hits::total 1117720 # number of overall MSHR hits 814system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299680 # number of ReadReq MSHR misses 815system.cpu.dcache.ReadReq_mshr_misses::total 299680 # number of ReadReq MSHR misses 816system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148526 # number of WriteReq MSHR misses 817system.cpu.dcache.WriteReq_mshr_misses::total 148526 # number of WriteReq MSHR misses 818system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses 819system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses 820system.cpu.dcache.demand_mshr_misses::cpu.data 448206 # number of demand (read+write) MSHR misses 821system.cpu.dcache.demand_mshr_misses::total 448206 # number of demand (read+write) MSHR misses 822system.cpu.dcache.overall_mshr_misses::cpu.data 485803 # number of overall MSHR misses 823system.cpu.dcache.overall_mshr_misses::total 485803 # number of overall MSHR misses 824system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2833367604 # number of ReadReq MSHR miss cycles 825system.cpu.dcache.ReadReq_mshr_miss_latency::total 2833367604 # number of ReadReq MSHR miss cycles 826system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2154211948 # number of WriteReq MSHR miss cycles 827system.cpu.dcache.WriteReq_mshr_miss_latency::total 2154211948 # number of WriteReq MSHR miss cycles 828system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1934780357 # number of SoftPFReq MSHR miss cycles 829system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1934780357 # number of SoftPFReq MSHR miss cycles 830system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4987579552 # number of demand (read+write) MSHR miss cycles 831system.cpu.dcache.demand_mshr_miss_latency::total 4987579552 # number of demand (read+write) MSHR miss cycles 832system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6922359909 # number of overall MSHR miss cycles 833system.cpu.dcache.overall_mshr_miss_latency::total 6922359909 # number of overall MSHR miss cycles 834system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013582 # mshr miss rate for ReadReq accesses 835system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013582 # mshr miss rate for ReadReq accesses 836system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses 837system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses 838system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291843 # mshr miss rate for SoftPFReq accesses 839system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291843 # mshr miss rate for SoftPFReq accesses 840system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010693 # mshr miss rate for demand accesses 841system.cpu.dcache.demand_mshr_miss_rate::total 0.010693 # mshr miss rate for demand accesses 842system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses 843system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses 844system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9454.643633 # average ReadReq mshr miss latency 845system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9454.643633 # average ReadReq mshr miss latency 846system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14503.938354 # average WriteReq mshr miss latency 847system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14503.938354 # average WriteReq mshr miss latency 848system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51461.030322 # average SoftPFReq mshr miss latency 849system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51461.030322 # average SoftPFReq mshr miss latency 850system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11127.873237 # average overall mshr miss latency 851system.cpu.dcache.demand_avg_mshr_miss_latency::total 11127.873237 # average overall mshr miss latency 852system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14249.314864 # average overall mshr miss latency 853system.cpu.dcache.overall_avg_mshr_miss_latency::total 14249.314864 # average overall mshr miss latency 854system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 855system.cpu.icache.tags.replacements 322868 # number of replacements 856system.cpu.icache.tags.tagsinuse 510.284584 # Cycle average of tags in use 857system.cpu.icache.tags.total_refs 22426703 # Total number of references to valid blocks. 858system.cpu.icache.tags.sampled_refs 323380 # Sample count of references to valid blocks. 859system.cpu.icache.tags.avg_refs 69.350928 # Average number of references to valid blocks. 860system.cpu.icache.tags.warmup_cycle 1086653000 # Cycle when the warmup percentage was hit. 861system.cpu.icache.tags.occ_blocks::cpu.inst 510.284584 # Average occupied blocks per requestor 862system.cpu.icache.tags.occ_percent::cpu.inst 0.996650 # Average percentage of cache occupancy 863system.cpu.icache.tags.occ_percent::total 0.996650 # Average percentage of cache occupancy 864system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 865system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 866system.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id 867system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 868system.cpu.icache.tags.age_task_id_blocks_1024::3 351 # Occupied blocks per task id 869system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 870system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 871system.cpu.icache.tags.tag_accesses 45841045 # Number of tag accesses 872system.cpu.icache.tags.data_accesses 45841045 # Number of data accesses 873system.cpu.icache.ReadReq_hits::cpu.inst 22426703 # number of ReadReq hits 874system.cpu.icache.ReadReq_hits::total 22426703 # number of ReadReq hits 875system.cpu.icache.demand_hits::cpu.inst 22426703 # number of demand (read+write) hits 876system.cpu.icache.demand_hits::total 22426703 # number of demand (read+write) hits 877system.cpu.icache.overall_hits::cpu.inst 22426703 # number of overall hits 878system.cpu.icache.overall_hits::total 22426703 # number of overall hits 879system.cpu.icache.ReadReq_misses::cpu.inst 332124 # number of ReadReq misses 880system.cpu.icache.ReadReq_misses::total 332124 # number of ReadReq misses 881system.cpu.icache.demand_misses::cpu.inst 332124 # number of demand (read+write) misses 882system.cpu.icache.demand_misses::total 332124 # number of demand (read+write) misses 883system.cpu.icache.overall_misses::cpu.inst 332124 # number of overall misses 884system.cpu.icache.overall_misses::total 332124 # number of overall misses 885system.cpu.icache.ReadReq_miss_latency::cpu.inst 3299467842 # number of ReadReq miss cycles 886system.cpu.icache.ReadReq_miss_latency::total 3299467842 # number of ReadReq miss cycles 887system.cpu.icache.demand_miss_latency::cpu.inst 3299467842 # number of demand (read+write) miss cycles 888system.cpu.icache.demand_miss_latency::total 3299467842 # number of demand (read+write) miss cycles 889system.cpu.icache.overall_miss_latency::cpu.inst 3299467842 # number of overall miss cycles 890system.cpu.icache.overall_miss_latency::total 3299467842 # number of overall miss cycles 891system.cpu.icache.ReadReq_accesses::cpu.inst 22758827 # number of ReadReq accesses(hits+misses) 892system.cpu.icache.ReadReq_accesses::total 22758827 # number of ReadReq accesses(hits+misses) 893system.cpu.icache.demand_accesses::cpu.inst 22758827 # number of demand (read+write) accesses 894system.cpu.icache.demand_accesses::total 22758827 # number of demand (read+write) accesses 895system.cpu.icache.overall_accesses::cpu.inst 22758827 # number of overall (read+write) accesses 896system.cpu.icache.overall_accesses::total 22758827 # number of overall (read+write) accesses 897system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014593 # miss rate for ReadReq accesses 898system.cpu.icache.ReadReq_miss_rate::total 0.014593 # miss rate for ReadReq accesses 899system.cpu.icache.demand_miss_rate::cpu.inst 0.014593 # miss rate for demand accesses 900system.cpu.icache.demand_miss_rate::total 0.014593 # miss rate for demand accesses 901system.cpu.icache.overall_miss_rate::cpu.inst 0.014593 # miss rate for overall accesses 902system.cpu.icache.overall_miss_rate::total 0.014593 # miss rate for overall accesses 903system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9934.445695 # average ReadReq miss latency 904system.cpu.icache.ReadReq_avg_miss_latency::total 9934.445695 # average ReadReq miss latency 905system.cpu.icache.demand_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency 906system.cpu.icache.demand_avg_miss_latency::total 9934.445695 # average overall miss latency 907system.cpu.icache.overall_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency 908system.cpu.icache.overall_avg_miss_latency::total 9934.445695 # average overall miss latency 909system.cpu.icache.blocked_cycles::no_mshrs 226617 # number of cycles access was blocked 910system.cpu.icache.blocked_cycles::no_targets 46 # number of cycles access was blocked 911system.cpu.icache.blocked::no_mshrs 14091 # number of cycles access was blocked 912system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 913system.cpu.icache.avg_blocked_cycles::no_mshrs 16.082393 # average number of cycles each access was blocked 914system.cpu.icache.avg_blocked_cycles::no_targets 23 # average number of cycles each access was blocked 915system.cpu.icache.fast_writes 0 # number of fast writes performed 916system.cpu.icache.cache_copies 0 # number of cache copies performed 917system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8733 # number of ReadReq MSHR hits 918system.cpu.icache.ReadReq_mshr_hits::total 8733 # number of ReadReq MSHR hits 919system.cpu.icache.demand_mshr_hits::cpu.inst 8733 # number of demand (read+write) MSHR hits 920system.cpu.icache.demand_mshr_hits::total 8733 # number of demand (read+write) MSHR hits 921system.cpu.icache.overall_mshr_hits::cpu.inst 8733 # number of overall MSHR hits 922system.cpu.icache.overall_mshr_hits::total 8733 # number of overall MSHR hits 923system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323391 # number of ReadReq MSHR misses 924system.cpu.icache.ReadReq_mshr_misses::total 323391 # number of ReadReq MSHR misses 925system.cpu.icache.demand_mshr_misses::cpu.inst 323391 # number of demand (read+write) MSHR misses 926system.cpu.icache.demand_mshr_misses::total 323391 # number of demand (read+write) MSHR misses 927system.cpu.icache.overall_mshr_misses::cpu.inst 323391 # number of overall MSHR misses 928system.cpu.icache.overall_mshr_misses::total 323391 # number of overall MSHR misses 929system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2699093031 # number of ReadReq MSHR miss cycles 930system.cpu.icache.ReadReq_mshr_miss_latency::total 2699093031 # number of ReadReq MSHR miss cycles 931system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2699093031 # number of demand (read+write) MSHR miss cycles 932system.cpu.icache.demand_mshr_miss_latency::total 2699093031 # number of demand (read+write) MSHR miss cycles 933system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2699093031 # number of overall MSHR miss cycles 934system.cpu.icache.overall_mshr_miss_latency::total 2699093031 # number of overall MSHR miss cycles 935system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for ReadReq accesses 936system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014209 # mshr miss rate for ReadReq accesses 937system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for demand accesses 938system.cpu.icache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses 939system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for overall accesses 940system.cpu.icache.overall_mshr_miss_rate::total 0.014209 # mshr miss rate for overall accesses 941system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8346.221852 # average ReadReq mshr miss latency 942system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8346.221852 # average ReadReq mshr miss latency 943system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency 944system.cpu.icache.demand_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency 945system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency 946system.cpu.icache.overall_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency 947system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 948system.cpu.l2cache.prefetcher.num_hwpf_issued 812320 # number of hwpf issued 949system.cpu.l2cache.prefetcher.pfIdentified 826786 # number of prefetch candidates identified 950system.cpu.l2cache.prefetcher.pfBufferHit 12696 # number of redundant prefetches already in prefetch queue 951system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 952system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 953system.cpu.l2cache.prefetcher.pfSpanPage 79190 # number of prefetches not generated due to page crossing 954system.cpu.l2cache.tags.replacements 129572 # number of replacements 955system.cpu.l2cache.tags.tagsinuse 16081.031642 # Cycle average of tags in use 956system.cpu.l2cache.tags.total_refs 872493 # Total number of references to valid blocks. 957system.cpu.l2cache.tags.sampled_refs 145853 # Sample count of references to valid blocks. 958system.cpu.l2cache.tags.avg_refs 5.982002 # Average number of references to valid blocks. 959system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 960system.cpu.l2cache.tags.occ_blocks::writebacks 12593.782282 # Average occupied blocks per requestor 961system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.951130 # Average occupied blocks per requestor 962system.cpu.l2cache.tags.occ_blocks::cpu.data 1938.685438 # Average occupied blocks per requestor 963system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 114.612791 # Average occupied blocks per requestor 964system.cpu.l2cache.tags.occ_percent::writebacks 0.768663 # Average percentage of cache occupancy 965system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087521 # Average percentage of cache occupancy 966system.cpu.l2cache.tags.occ_percent::cpu.data 0.118328 # Average percentage of cache occupancy 967system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006995 # Average percentage of cache occupancy 968system.cpu.l2cache.tags.occ_percent::total 0.981508 # Average percentage of cache occupancy 969system.cpu.l2cache.tags.occ_task_id_blocks::1022 28 # Occupied blocks per task id 970system.cpu.l2cache.tags.occ_task_id_blocks::1024 16253 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id 973system.cpu.l2cache.tags.age_task_id_blocks_1022::3 15 # Occupied blocks per task id 974system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2807 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11875 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1024::3 526 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1024::4 887 # Occupied blocks per task id 980system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001709 # Percentage of cache occupancy per task id 981system.cpu.l2cache.tags.occ_task_id_percent::1024 0.992004 # Percentage of cache occupancy per task id 982system.cpu.l2cache.tags.tag_accesses 17471961 # Number of tag accesses 983system.cpu.l2cache.tags.data_accesses 17471961 # Number of data accesses 984system.cpu.l2cache.ReadReq_hits::cpu.inst 314144 # number of ReadReq hits 985system.cpu.l2cache.ReadReq_hits::cpu.data 305991 # number of ReadReq hits 986system.cpu.l2cache.ReadReq_hits::total 620135 # number of ReadReq hits 987system.cpu.l2cache.Writeback_hits::writebacks 264417 # number of Writeback hits 988system.cpu.l2cache.Writeback_hits::total 264417 # number of Writeback hits 989system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 990system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 991system.cpu.l2cache.ReadExReq_hits::cpu.data 137166 # number of ReadExReq hits 992system.cpu.l2cache.ReadExReq_hits::total 137166 # number of ReadExReq hits 993system.cpu.l2cache.demand_hits::cpu.inst 314144 # number of demand (read+write) hits 994system.cpu.l2cache.demand_hits::cpu.data 443157 # number of demand (read+write) hits 995system.cpu.l2cache.demand_hits::total 757301 # number of demand (read+write) hits 996system.cpu.l2cache.overall_hits::cpu.inst 314144 # number of overall hits 997system.cpu.l2cache.overall_hits::cpu.data 443157 # number of overall hits 998system.cpu.l2cache.overall_hits::total 757301 # number of overall hits 999system.cpu.l2cache.ReadReq_misses::cpu.inst 9232 # number of ReadReq misses 1000system.cpu.l2cache.ReadReq_misses::cpu.data 31234 # number of ReadReq misses 1001system.cpu.l2cache.ReadReq_misses::total 40466 # number of ReadReq misses 1002system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 1003system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 1004system.cpu.l2cache.ReadExReq_misses::cpu.data 11401 # number of ReadExReq misses 1005system.cpu.l2cache.ReadExReq_misses::total 11401 # number of ReadExReq misses 1006system.cpu.l2cache.demand_misses::cpu.inst 9232 # number of demand (read+write) misses 1007system.cpu.l2cache.demand_misses::cpu.data 42635 # number of demand (read+write) misses 1008system.cpu.l2cache.demand_misses::total 51867 # number of demand (read+write) misses 1009system.cpu.l2cache.overall_misses::cpu.inst 9232 # number of overall misses 1010system.cpu.l2cache.overall_misses::cpu.data 42635 # number of overall misses 1011system.cpu.l2cache.overall_misses::total 51867 # number of overall misses 1012system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 649699988 # number of ReadReq miss cycles 1013system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2574698315 # number of ReadReq miss cycles 1014system.cpu.l2cache.ReadReq_miss_latency::total 3224398303 # number of ReadReq miss cycles 1015system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1168450243 # number of ReadExReq miss cycles 1016system.cpu.l2cache.ReadExReq_miss_latency::total 1168450243 # number of ReadExReq miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.inst 649699988 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::cpu.data 3743148558 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.demand_miss_latency::total 4392848546 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.overall_miss_latency::cpu.inst 649699988 # number of overall miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.data 3743148558 # number of overall miss cycles 1022system.cpu.l2cache.overall_miss_latency::total 4392848546 # number of overall miss cycles 1023system.cpu.l2cache.ReadReq_accesses::cpu.inst 323376 # number of ReadReq accesses(hits+misses) 1024system.cpu.l2cache.ReadReq_accesses::cpu.data 337225 # number of ReadReq accesses(hits+misses) 1025system.cpu.l2cache.ReadReq_accesses::total 660601 # number of ReadReq accesses(hits+misses) 1026system.cpu.l2cache.Writeback_accesses::writebacks 264417 # number of Writeback accesses(hits+misses) 1027system.cpu.l2cache.Writeback_accesses::total 264417 # number of Writeback accesses(hits+misses) 1028system.cpu.l2cache.UpgradeReq_accesses::cpu.data 11 # number of UpgradeReq accesses(hits+misses) 1029system.cpu.l2cache.UpgradeReq_accesses::total 11 # number of UpgradeReq accesses(hits+misses) 1030system.cpu.l2cache.ReadExReq_accesses::cpu.data 148567 # number of ReadExReq accesses(hits+misses) 1031system.cpu.l2cache.ReadExReq_accesses::total 148567 # number of ReadExReq accesses(hits+misses) 1032system.cpu.l2cache.demand_accesses::cpu.inst 323376 # number of demand (read+write) accesses 1033system.cpu.l2cache.demand_accesses::cpu.data 485792 # number of demand (read+write) accesses 1034system.cpu.l2cache.demand_accesses::total 809168 # number of demand (read+write) accesses 1035system.cpu.l2cache.overall_accesses::cpu.inst 323376 # number of overall (read+write) accesses 1036system.cpu.l2cache.overall_accesses::cpu.data 485792 # number of overall (read+write) accesses 1037system.cpu.l2cache.overall_accesses::total 809168 # number of overall (read+write) accesses 1038system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.028549 # miss rate for ReadReq accesses 1039system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.092621 # miss rate for ReadReq accesses 1040system.cpu.l2cache.ReadReq_miss_rate::total 0.061256 # miss rate for ReadReq accesses 1041system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.545455 # miss rate for UpgradeReq accesses 1042system.cpu.l2cache.UpgradeReq_miss_rate::total 0.545455 # miss rate for UpgradeReq accesses 1043system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076740 # miss rate for ReadExReq accesses 1044system.cpu.l2cache.ReadExReq_miss_rate::total 0.076740 # miss rate for ReadExReq accesses 1045system.cpu.l2cache.demand_miss_rate::cpu.inst 0.028549 # miss rate for demand accesses 1046system.cpu.l2cache.demand_miss_rate::cpu.data 0.087764 # miss rate for demand accesses 1047system.cpu.l2cache.demand_miss_rate::total 0.064099 # miss rate for demand accesses 1048system.cpu.l2cache.overall_miss_rate::cpu.inst 0.028549 # miss rate for overall accesses 1049system.cpu.l2cache.overall_miss_rate::cpu.data 0.087764 # miss rate for overall accesses 1050system.cpu.l2cache.overall_miss_rate::total 0.064099 # miss rate for overall accesses 1051system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70374.782062 # average ReadReq miss latency 1052system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82432.551546 # average ReadReq miss latency 1053system.cpu.l2cache.ReadReq_avg_miss_latency::total 79681.666164 # average ReadReq miss latency 1054system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102486.645294 # average ReadExReq miss latency 1055system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102486.645294 # average ReadExReq miss latency 1056system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70374.782062 # average overall miss latency 1057system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87795.204832 # average overall miss latency 1058system.cpu.l2cache.demand_avg_miss_latency::total 84694.479071 # average overall miss latency 1059system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70374.782062 # average overall miss latency 1060system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87795.204832 # average overall miss latency 1061system.cpu.l2cache.overall_avg_miss_latency::total 84694.479071 # average overall miss latency 1062system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1063system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1064system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1065system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1066system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1067system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1068system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1069system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1070system.cpu.l2cache.writebacks::writebacks 97844 # number of writebacks 1071system.cpu.l2cache.writebacks::total 97844 # number of writebacks 1072system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 33 # number of ReadReq MSHR hits 1073system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 152 # number of ReadReq MSHR hits 1074system.cpu.l2cache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits 1075system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3161 # number of ReadExReq MSHR hits 1076system.cpu.l2cache.ReadExReq_mshr_hits::total 3161 # number of ReadExReq MSHR hits 1077system.cpu.l2cache.demand_mshr_hits::cpu.inst 33 # number of demand (read+write) MSHR hits 1078system.cpu.l2cache.demand_mshr_hits::cpu.data 3313 # number of demand (read+write) MSHR hits 1079system.cpu.l2cache.demand_mshr_hits::total 3346 # number of demand (read+write) MSHR hits 1080system.cpu.l2cache.overall_mshr_hits::cpu.inst 33 # number of overall MSHR hits 1081system.cpu.l2cache.overall_mshr_hits::cpu.data 3313 # number of overall MSHR hits 1082system.cpu.l2cache.overall_mshr_hits::total 3346 # number of overall MSHR hits 1083system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9199 # number of ReadReq MSHR misses 1084system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31082 # number of ReadReq MSHR misses 1085system.cpu.l2cache.ReadReq_mshr_misses::total 40281 # number of ReadReq MSHR misses 1086system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112599 # number of HardPFReq MSHR misses 1087system.cpu.l2cache.HardPFReq_mshr_misses::total 112599 # number of HardPFReq MSHR misses 1088system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 1089system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 1090system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8240 # number of ReadExReq MSHR misses 1091system.cpu.l2cache.ReadExReq_mshr_misses::total 8240 # number of ReadExReq MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 9199 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.demand_mshr_misses::cpu.data 39322 # number of demand (read+write) MSHR misses 1094system.cpu.l2cache.demand_mshr_misses::total 48521 # number of demand (read+write) MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 9199 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.data 39322 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112599 # number of overall MSHR misses 1098system.cpu.l2cache.overall_mshr_misses::total 161120 # number of overall MSHR misses 1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 569300762 # number of ReadReq MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2303617903 # number of ReadReq MSHR miss cycles 1101system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872918665 # number of ReadReq MSHR miss cycles 1102system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of HardPFReq MSHR miss cycles 1103system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 11396158527 # number of HardPFReq MSHR miss cycles 1104system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39006 # number of UpgradeReq MSHR miss cycles 1105system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39006 # number of UpgradeReq MSHR miss cycles 1106system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 539005297 # number of ReadExReq MSHR miss cycles 1107system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 539005297 # number of ReadExReq MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 569300762 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2842623200 # number of demand (read+write) MSHR miss cycles 1110system.cpu.l2cache.demand_mshr_miss_latency::total 3411923962 # number of demand (read+write) MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 569300762 # number of overall MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2842623200 # number of overall MSHR miss cycles 1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of overall MSHR miss cycles 1114system.cpu.l2cache.overall_mshr_miss_latency::total 14808082489 # number of overall MSHR miss cycles 1115system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for ReadReq accesses 1116system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092170 # mshr miss rate for ReadReq accesses 1117system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.060976 # mshr miss rate for ReadReq accesses 1118system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1119system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1120system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses 1121system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses 1122system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055463 # mshr miss rate for ReadExReq accesses 1123system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055463 # mshr miss rate for ReadExReq accesses 1124system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for demand accesses 1125system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for demand accesses 1126system.cpu.l2cache.demand_mshr_miss_rate::total 0.059964 # mshr miss rate for demand accesses 1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for overall accesses 1128system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for overall accesses 1129system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1130system.cpu.l2cache.overall_mshr_miss_rate::total 0.199118 # mshr miss rate for overall accesses 1131system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61887.244483 # average ReadReq mshr miss latency 1132system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74114.210894 # average ReadReq mshr miss latency 1133system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71321.930066 # average ReadReq mshr miss latency 1134system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average HardPFReq mshr miss latency 1135system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 101210.121999 # average HardPFReq mshr miss latency 1136system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6501 # average UpgradeReq mshr miss latency 1137system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6501 # average UpgradeReq mshr miss latency 1138system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65413.264199 # average ReadExReq mshr miss latency 1139system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65413.264199 # average ReadExReq mshr miss latency 1140system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency 1141system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency 1142system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70318.500484 # average overall mshr miss latency 1143system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency 1144system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency 1145system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average overall mshr miss latency 1146system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91907.165398 # average overall mshr miss latency 1147system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1148system.cpu.toL2Bus.trans_dist::ReadReq 660616 # Transaction distribution 1149system.cpu.toL2Bus.trans_dist::ReadResp 660616 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::Writeback 264417 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::HardPFReq 169278 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution 1156system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646767 # Packet count per connected master and slave (bytes) 1157system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1236023 # Packet count per connected master and slave (bytes) 1158system.cpu.toL2Bus.pkt_count::total 1882790 # Packet count per connected master and slave (bytes) 1159system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20696064 # Cumulative packet size per connected master and slave (bytes) 1160system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48013376 # Cumulative packet size per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_size::total 68709440 # Cumulative packet size per connected master and slave (bytes) 1162system.cpu.toL2Bus.snoops 169293 # Total snoops (count) 1163system.cpu.toL2Bus.snoop_fanout::samples 1242889 # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::mean 5.136197 # Request fanout histogram 1165system.cpu.toL2Bus.snoop_fanout::stdev 0.342998 # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1167system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1168system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::5 1073611 86.38% 86.38% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::6 169278 13.62% 100.00% # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::total 1242889 # Request fanout histogram 1178system.cpu.toL2Bus.reqLayer0.occupancy 801222500 # Layer occupancy (ticks) 1179system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) 1180system.cpu.toL2Bus.respLayer0.occupancy 486660171 # Layer occupancy (ticks) 1181system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 1182system.cpu.toL2Bus.respLayer1.occupancy 734282302 # Layer occupancy (ticks) 1183system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) 1184system.membus.trans_dist::ReadReq 137181 # Transaction distribution 1185system.membus.trans_dist::ReadResp 137181 # Transaction distribution 1186system.membus.trans_dist::Writeback 97844 # Transaction distribution 1187system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1188system.membus.trans_dist::UpgradeResp 6 # Transaction distribution 1189system.membus.trans_dist::ReadExReq 8252 # Transaction distribution 1190system.membus.trans_dist::ReadExResp 8252 # Transaction distribution 1191system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388722 # Packet count per connected master and slave (bytes) 1192system.membus.pkt_count::total 388722 # Packet count per connected master and slave (bytes) 1193system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15569728 # Cumulative packet size per connected master and slave (bytes) 1194system.membus.pkt_size::total 15569728 # Cumulative packet size per connected master and slave (bytes) 1195system.membus.snoops 0 # Total snoops (count) 1196system.membus.snoop_fanout::samples 243283 # Request fanout histogram 1197system.membus.snoop_fanout::mean 0 # Request fanout histogram 1198system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1199system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1200system.membus.snoop_fanout::0 243283 100.00% 100.00% # Request fanout histogram 1201system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1202system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1203system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1204system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1205system.membus.snoop_fanout::total 243283 # Request fanout histogram 1206system.membus.reqLayer0.occupancy 1077095188 # Layer occupancy (ticks) 1207system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) 1208system.membus.respLayer1.occupancy 1335208239 # Layer occupancy (ticks) 1209system.membus.respLayer1.utilization 4.0 # Layer utilization (%) 1210 1211---------- End Simulation Statistics ---------- 1212