stats.txt revision 10515
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.032615 # Number of seconds simulated 4sim_ticks 32615215000 # Number of ticks simulated 5final_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 125661 # Simulator instruction rate (inst/s) 8host_op_rate 160706 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 57800178 # Simulator tick rate (ticks/s) 10host_mem_usage 335740 # Number of bytes of host memory used 11host_seconds 564.28 # Real time elapsed on the host 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 90682584 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 133120 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 2337984 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 7506432 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9977536 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 133120 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 133120 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6303424 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6303424 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2080 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 36531 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 117288 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 155899 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 98491 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 98491 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 4081531 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 71683844 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 230151235 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 305916610 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 4081531 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 4081531 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 193266364 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 193266364 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 193266364 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 4081531 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 71683844 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 230151235 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 499182973 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 155899 # Number of read requests accepted 44system.physmem.writeReqs 98491 # Number of write requests accepted 45system.physmem.readBursts 155899 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 98491 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 9968640 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue 49system.physmem.bytesWritten 6301696 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 9977536 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 6303424 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 10106 # Per bank write bursts 56system.physmem.perBankRdBursts::1 10077 # Per bank write bursts 57system.physmem.perBankRdBursts::2 9750 # Per bank write bursts 58system.physmem.perBankRdBursts::3 10345 # Per bank write bursts 59system.physmem.perBankRdBursts::4 10619 # Per bank write bursts 60system.physmem.perBankRdBursts::5 10733 # Per bank write bursts 61system.physmem.perBankRdBursts::6 9548 # Per bank write bursts 62system.physmem.perBankRdBursts::7 9567 # Per bank write bursts 63system.physmem.perBankRdBursts::8 9971 # Per bank write bursts 64system.physmem.perBankRdBursts::9 9445 # Per bank write bursts 65system.physmem.perBankRdBursts::10 9639 # Per bank write bursts 66system.physmem.perBankRdBursts::11 9476 # Per bank write bursts 67system.physmem.perBankRdBursts::12 8930 # Per bank write bursts 68system.physmem.perBankRdBursts::13 9084 # Per bank write bursts 69system.physmem.perBankRdBursts::14 9062 # Per bank write bursts 70system.physmem.perBankRdBursts::15 9408 # Per bank write bursts 71system.physmem.perBankWrBursts::0 6017 # Per bank write bursts 72system.physmem.perBankWrBursts::1 6275 # Per bank write bursts 73system.physmem.perBankWrBursts::2 6171 # Per bank write bursts 74system.physmem.perBankWrBursts::3 6231 # Per bank write bursts 75system.physmem.perBankWrBursts::4 6142 # Per bank write bursts 76system.physmem.perBankWrBursts::5 6389 # Per bank write bursts 77system.physmem.perBankWrBursts::6 6054 # Per bank write bursts 78system.physmem.perBankWrBursts::7 6025 # Per bank write bursts 79system.physmem.perBankWrBursts::8 6057 # Per bank write bursts 80system.physmem.perBankWrBursts::9 6227 # Per bank write bursts 81system.physmem.perBankWrBursts::10 6350 # Per bank write bursts 82system.physmem.perBankWrBursts::11 5949 # Per bank write bursts 83system.physmem.perBankWrBursts::12 6129 # Per bank write bursts 84system.physmem.perBankWrBursts::13 6148 # Per bank write bursts 85system.physmem.perBankWrBursts::14 6212 # Per bank write bursts 86system.physmem.perBankWrBursts::15 6088 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 32615126500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 155899 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 98491 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 46242 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 51007 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 19397 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 10907 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 7160 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 6108 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 5351 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4799 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 4082 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 329 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 161 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 51 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 22 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 12 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 1248 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 1291 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 1960 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 2723 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 3606 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 4588 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 5698 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 5990 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 6308 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 6755 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 7385 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8090 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8877 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 7957 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 7389 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 6799 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 6302 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 59 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 91367 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 178.055709 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 111.660605 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 241.201750 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 53557 58.62% 58.62% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 22743 24.89% 83.51% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 4730 5.18% 88.69% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 1990 2.18% 90.86% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 1303 1.43% 92.29% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 874 0.96% 93.25% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 818 0.90% 94.14% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 792 0.87% 95.01% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 4560 4.99% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 91367 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 5918 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 26.315816 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 22.639360 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 186.500180 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 5917 99.98% 99.98% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 5918 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 5918 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 16.638053 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 16.588323 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.367969 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 4586 77.49% 77.49% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::17 35 0.59% 78.08% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18 770 13.01% 91.09% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::19 230 3.89% 94.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::20 141 2.38% 97.36% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::21 69 1.17% 98.53% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::22 46 0.78% 99.31% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::23 20 0.34% 99.65% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::24 12 0.20% 99.85% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::25 3 0.05% 99.90% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::26 5 0.08% 99.98% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 5918 # Writes before turning the bus around for reads 238system.physmem.totQLat 7435933847 # Total ticks spent queuing 239system.physmem.totMemAccLat 10356433847 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 778800000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 47739.69 # Average queueing delay per DRAM burst 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 243system.physmem.avgMemAccLat 66489.69 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 305.64 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 193.21 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 305.92 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 193.27 # Average system write bandwidth in MiByte/s 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 3.90 # Data bus utilization in percentage 250system.physmem.busUtilRead 2.39 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 1.51 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing 254system.physmem.readRowHits 126861 # Number of row buffer hits during reads 255system.physmem.writeRowHits 35985 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 36.54 # Row buffer hit rate for writes 258system.physmem.avgGap 128209.15 # Average gap between requests 259system.physmem.pageHitRate 64.05 # Row buffer hit rate, read and write combined 260system.physmem.memoryStateTime::IDLE 11335868113 # Time in different power states 261system.physmem.memoryStateTime::REF 1088880000 # Time in different power states 262system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 263system.physmem.memoryStateTime::ACT 20184340637 # Time in different power states 264system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 265system.physmem.actEnergy::0 352167480 # Energy for activate commands per rank (pJ) 266system.physmem.actEnergy::1 337674960 # Energy for activate commands per rank (pJ) 267system.physmem.preEnergy::0 192154875 # Energy for precharge commands per rank (pJ) 268system.physmem.preEnergy::1 184247250 # Energy for precharge commands per rank (pJ) 269system.physmem.readEnergy::0 628633200 # Energy for read commands per rank (pJ) 270system.physmem.readEnergy::1 584321400 # Energy for read commands per rank (pJ) 271system.physmem.writeEnergy::0 319101120 # Energy for write commands per rank (pJ) 272system.physmem.writeEnergy::1 318206880 # Energy for write commands per rank (pJ) 273system.physmem.refreshEnergy::0 2129849280 # Energy for refresh commands per rank (pJ) 274system.physmem.refreshEnergy::1 2129849280 # Energy for refresh commands per rank (pJ) 275system.physmem.actBackEnergy::0 12060126405 # Energy for active background per rank (pJ) 276system.physmem.actBackEnergy::1 11622718665 # Energy for active background per rank (pJ) 277system.physmem.preBackEnergy::0 8986386750 # Energy for precharge background per rank (pJ) 278system.physmem.preBackEnergy::1 9370077750 # Energy for precharge background per rank (pJ) 279system.physmem.totalEnergy::0 24668419110 # Total energy per rank (pJ) 280system.physmem.totalEnergy::1 24547096185 # Total energy per rank (pJ) 281system.physmem.averagePower::0 756.489386 # Core power per rank (mW) 282system.physmem.averagePower::1 752.768859 # Core power per rank (mW) 283system.membus.trans_dist::ReadReq 149976 # Transaction distribution 284system.membus.trans_dist::ReadResp 149976 # Transaction distribution 285system.membus.trans_dist::Writeback 98491 # Transaction distribution 286system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 287system.membus.trans_dist::UpgradeResp 6 # Transaction distribution 288system.membus.trans_dist::ReadExReq 5923 # Transaction distribution 289system.membus.trans_dist::ReadExResp 5923 # Transaction distribution 290system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 410301 # Packet count per connected master and slave (bytes) 291system.membus.pkt_count::total 410301 # Packet count per connected master and slave (bytes) 292system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16280960 # Cumulative packet size per connected master and slave (bytes) 293system.membus.pkt_size::total 16280960 # Cumulative packet size per connected master and slave (bytes) 294system.membus.snoops 0 # Total snoops (count) 295system.membus.snoop_fanout::samples 254396 # Request fanout histogram 296system.membus.snoop_fanout::mean 0 # Request fanout histogram 297system.membus.snoop_fanout::stdev 0 # Request fanout histogram 298system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 299system.membus.snoop_fanout::0 254396 100.00% 100.00% # Request fanout histogram 300system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 301system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 302system.membus.snoop_fanout::min_value 0 # Request fanout histogram 303system.membus.snoop_fanout::max_value 0 # Request fanout histogram 304system.membus.snoop_fanout::total 254396 # Request fanout histogram 305system.membus.reqLayer0.occupancy 1082237025 # Layer occupancy (ticks) 306system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) 307system.membus.respLayer1.occupancy 1431940683 # Layer occupancy (ticks) 308system.membus.respLayer1.utilization 4.4 # Layer utilization (%) 309system.cpu_clk_domain.clock 500 # Clock period in ticks 310system.cpu.branchPred.lookups 17209876 # Number of BP lookups 311system.cpu.branchPred.condPredicted 11519021 # Number of conditional branches predicted 312system.cpu.branchPred.condIncorrect 648079 # Number of conditional branches incorrect 313system.cpu.branchPred.BTBLookups 9339439 # Number of BTB lookups 314system.cpu.branchPred.BTBHits 7675638 # Number of BTB hits 315system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 316system.cpu.branchPred.BTBHitPct 82.185215 # BTB Hit Percentage 317system.cpu.branchPred.usedRAS 1872557 # Number of times the RAS was used to get a target. 318system.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. 319system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 320system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 321system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 322system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 323system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 324system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 325system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 327system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 328system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 329system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 330system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 331system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 332system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 333system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 334system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 335system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 336system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 337system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 338system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 339system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 340system.cpu.dtb.inst_hits 0 # ITB inst hits 341system.cpu.dtb.inst_misses 0 # ITB inst misses 342system.cpu.dtb.read_hits 0 # DTB read hits 343system.cpu.dtb.read_misses 0 # DTB read misses 344system.cpu.dtb.write_hits 0 # DTB write hits 345system.cpu.dtb.write_misses 0 # DTB write misses 346system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 347system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 348system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 349system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 350system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 351system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 352system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.dtb.read_accesses 0 # DTB read accesses 356system.cpu.dtb.write_accesses 0 # DTB write accesses 357system.cpu.dtb.inst_accesses 0 # ITB inst accesses 358system.cpu.dtb.hits 0 # DTB hits 359system.cpu.dtb.misses 0 # DTB misses 360system.cpu.dtb.accesses 0 # DTB accesses 361system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 362system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 363system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 364system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 365system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 366system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 367system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 368system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 371system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 372system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 373system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 374system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 375system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 376system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 377system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 378system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 379system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 380system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 381system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 382system.cpu.itb.inst_hits 0 # ITB inst hits 383system.cpu.itb.inst_misses 0 # ITB inst misses 384system.cpu.itb.read_hits 0 # DTB read hits 385system.cpu.itb.read_misses 0 # DTB read misses 386system.cpu.itb.write_hits 0 # DTB write hits 387system.cpu.itb.write_misses 0 # DTB write misses 388system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 389system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 390system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 391system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 392system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 393system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 394system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 395system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 396system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.itb.read_accesses 0 # DTB read accesses 398system.cpu.itb.write_accesses 0 # DTB write accesses 399system.cpu.itb.inst_accesses 0 # ITB inst accesses 400system.cpu.itb.hits 0 # DTB hits 401system.cpu.itb.misses 0 # DTB misses 402system.cpu.itb.accesses 0 # DTB accesses 403system.cpu.workload.num_syscalls 1946 # Number of system calls 404system.cpu.numCycles 65230431 # number of cpu cycles simulated 405system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 406system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 407system.cpu.fetch.icacheStallCycles 4923591 # Number of cycles fetch is stalled on an Icache miss 408system.cpu.fetch.Insts 88199449 # Number of instructions fetch has processed 409system.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered 410system.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken 411system.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked 412system.cpu.fetch.SquashCycles 1322461 # Number of cycles fetch has spent squashing 413system.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 414system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps 415system.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR 416system.cpu.fetch.CacheLines 22763618 # Number of cache lines fetched 417system.cpu.fetch.IcacheSquashes 68177 # Number of outstanding Icache misses that were squashed 418system.cpu.fetch.rateDist::samples 64885124 # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::mean 1.720232 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::stdev 1.289546 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::0 19096390 29.43% 29.43% # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::1 8276176 12.76% 42.19% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::2 9196383 14.17% 56.36% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::3 28316175 43.64% 100.00% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::total 64885124 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.branchRate 0.263832 # Number of branch fetches per cycle 431system.cpu.fetch.rate 1.352121 # Number of inst fetches per cycle 432system.cpu.decode.IdleCycles 8536355 # Number of cycles decode is idle 433system.cpu.decode.BlockedCycles 18658081 # Number of cycles decode is blocked 434system.cpu.decode.RunCycles 31532227 # Number of cycles decode is running 435system.cpu.decode.UnblockCycles 5666329 # Number of cycles decode is unblocking 436system.cpu.decode.SquashCycles 492132 # Number of cycles decode is squashing 437system.cpu.decode.BranchResolved 3179364 # Number of times decode resolved a branch 438system.cpu.decode.BranchMispred 171028 # Number of times decode detected a branch misprediction 439system.cpu.decode.DecodedInsts 101394580 # Number of instructions handled by decode 440system.cpu.decode.SquashedInsts 3046745 # Number of squashed instructions handled by decode 441system.cpu.rename.SquashCycles 492132 # Number of cycles rename is squashing 442system.cpu.rename.IdleCycles 13317145 # Number of cycles rename is idle 443system.cpu.rename.BlockCycles 5269714 # Number of cycles rename is blocking 444system.cpu.rename.serializeStallCycles 677558 # count of cycles rename stalled for serializing inst 445system.cpu.rename.RunCycles 32193664 # Number of cycles rename is running 446system.cpu.rename.UnblockCycles 12934911 # Number of cycles rename is unblocking 447system.cpu.rename.RenamedInsts 99186097 # Number of instructions processed by rename 448system.cpu.rename.SquashedInsts 982635 # Number of squashed instructions processed by rename 449system.cpu.rename.ROBFullEvents 3696460 # Number of times rename has blocked due to ROB full 450system.cpu.rename.IQFullEvents 54484 # Number of times rename has blocked due to IQ full 451system.cpu.rename.LQFullEvents 4041872 # Number of times rename has blocked due to LQ full 452system.cpu.rename.SQFullEvents 4848974 # Number of times rename has blocked due to SQ full 453system.cpu.rename.RenamedOperands 103911408 # Number of destination operands rename has renamed 454system.cpu.rename.RenameLookups 457625717 # Number of register rename lookups that rename has made 455system.cpu.rename.int_rename_lookups 115391737 # Number of integer rename lookups 456system.cpu.rename.fp_rename_lookups 582 # Number of floating rename lookups 457system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed 458system.cpu.rename.UndoneMaps 10282182 # Number of HB maps that are undone due to squashing 459system.cpu.rename.serializingInsts 18671 # count of serializing insts renamed 460system.cpu.rename.tempSerializingInsts 18658 # count of temporary serializing insts renamed 461system.cpu.rename.skidInsts 12776141 # count of insts added to the skid buffer 462system.cpu.memDep0.insertedLoads 24320792 # Number of loads inserted to the mem dependence unit. 463system.cpu.memDep0.insertedStores 21987717 # Number of stores inserted to the mem dependence unit. 464system.cpu.memDep0.conflictingLoads 1318624 # Number of conflicting loads. 465system.cpu.memDep0.conflictingStores 2218270 # Number of conflicting stores. 466system.cpu.iq.iqInstsAdded 98150566 # Number of instructions added to the IQ (excludes non-spec) 467system.cpu.iq.iqNonSpecInstsAdded 34524 # Number of non-speculative instructions added to the IQ 468system.cpu.iq.iqInstsIssued 94860274 # Number of instructions issued 469system.cpu.iq.iqSquashedInstsIssued 691673 # Number of squashed instructions issued 470system.cpu.iq.iqSquashedInstsExamined 7398751 # Number of squashed instructions iterated over during squash; mainly for profiling 471system.cpu.iq.iqSquashedOperandsExamined 20189182 # Number of squashed operands that are examined and possibly removed from graph 472system.cpu.iq.iqSquashedNonSpecRemoved 738 # Number of squashed non-spec instructions that were removed 473system.cpu.iq.issued_per_cycle::samples 64885124 # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::mean 1.461973 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::stdev 1.146315 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::0 16747153 25.81% 25.81% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::1 17200007 26.51% 52.32% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::2 17188207 26.49% 78.81% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::3 11716155 18.06% 96.87% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::4 2032622 3.13% 100.00% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::5 980 0.00% 100.00% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::total 64885124 # Number of insts issued each cycle 490system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 491system.cpu.iq.fu_full::IntAlu 6675057 22.12% 22.12% # attempts to use FU when none available 492system.cpu.iq.fu_full::IntMult 43 0.00% 22.12% # attempts to use FU when none available 493system.cpu.iq.fu_full::IntDiv 0 0.00% 22.12% # attempts to use FU when none available 494system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.12% # attempts to use FU when none available 495system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.12% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.12% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatMult 0 0.00% 22.12% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.12% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.12% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.12% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.12% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.12% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.12% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.12% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.12% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdMult 0 0.00% 22.12% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.12% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdShift 0 0.00% 22.12% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.12% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.12% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.12% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.12% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.12% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.12% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.12% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.12% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.12% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.12% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.12% # attempts to use FU when none available 520system.cpu.iq.fu_full::MemRead 11293925 37.43% 59.55% # attempts to use FU when none available 521system.cpu.iq.fu_full::MemWrite 12204027 40.45% 100.00% # attempts to use FU when none available 522system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 523system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 524system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 525system.cpu.iq.FU_type_0::IntAlu 49495845 52.18% 52.18% # Type of FU issued 526system.cpu.iq.FU_type_0::IntMult 89880 0.09% 52.27% # Type of FU issued 527system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued 528system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.27% # Type of FU issued 529system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued 554system.cpu.iq.FU_type_0::MemRead 24035217 25.34% 77.61% # Type of FU issued 555system.cpu.iq.FU_type_0::MemWrite 21239293 22.39% 100.00% # Type of FU issued 556system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 557system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 558system.cpu.iq.FU_type_0::total 94860274 # Type of FU issued 559system.cpu.iq.rate 1.454233 # Inst issue rate 560system.cpu.iq.fu_busy_cnt 30173052 # FU busy when requested 561system.cpu.iq.fu_busy_rate 0.318079 # FU busy rate (busy events/executed inst) 562system.cpu.iq.int_inst_queue_reads 285470188 # Number of integer instruction queue reads 563system.cpu.iq.int_inst_queue_writes 105595239 # Number of integer instruction queue writes 564system.cpu.iq.int_inst_queue_wakeup_accesses 93464369 # Number of integer instruction queue wakeup accesses 565system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads 566system.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes 567system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses 568system.cpu.iq.int_alu_accesses 125033207 # Number of integer alu accesses 569system.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses 570system.cpu.iew.lsq.thread0.forwLoads 1351291 # Number of loads that had data forwarded from stores 571system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 572system.cpu.iew.lsq.thread0.squashedLoads 1454530 # Number of loads squashed 573system.cpu.iew.lsq.thread0.ignoredResponses 2099 # Number of memory responses ignored because the instruction is squashed 574system.cpu.iew.lsq.thread0.memOrderViolation 11910 # Number of memory ordering violations 575system.cpu.iew.lsq.thread0.squashedStores 1431979 # Number of stores squashed 576system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 577system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 578system.cpu.iew.lsq.thread0.rescheduledLoads 120662 # Number of loads that were rescheduled 579system.cpu.iew.lsq.thread0.cacheBlocked 168795 # Number of times an access to memory failed due to the cache being blocked 580system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 581system.cpu.iew.iewSquashCycles 492132 # Number of cycles IEW is squashing 582system.cpu.iew.iewBlockCycles 622391 # Number of cycles IEW is blocking 583system.cpu.iew.iewUnblockCycles 354812 # Number of cycles IEW is unblocking 584system.cpu.iew.iewDispatchedInsts 98194956 # Number of instructions dispatched to IQ 585system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 586system.cpu.iew.iewDispLoadInsts 24320792 # Number of dispatched load instructions 587system.cpu.iew.iewDispStoreInsts 21987717 # Number of dispatched store instructions 588system.cpu.iew.iewDispNonSpecInsts 18604 # Number of dispatched non-speculative instructions 589system.cpu.iew.iewIQFullEvents 1618 # Number of times the IQ has become full, causing a stall 590system.cpu.iew.iewLSQFullEvents 350368 # Number of times the LSQ has become full, causing a stall 591system.cpu.iew.memOrderViolationEvents 11910 # Number of memory order violations 592system.cpu.iew.predictedTakenIncorrect 302846 # Number of branches that were predicted taken incorrectly 593system.cpu.iew.predictedNotTakenIncorrect 221657 # Number of branches that were predicted not taken incorrectly 594system.cpu.iew.branchMispredicts 524503 # Number of branch mispredicts detected at execute 595system.cpu.iew.iewExecutedInsts 93943274 # Number of executed instructions 596system.cpu.iew.iewExecLoadInsts 23727789 # Number of load instructions executed 597system.cpu.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute 598system.cpu.iew.exec_swp 0 # number of swp insts executed 599system.cpu.iew.exec_nop 9866 # number of nop insts executed 600system.cpu.iew.exec_refs 44709300 # number of memory reference insts executed 601system.cpu.iew.exec_branches 14252629 # Number of branches executed 602system.cpu.iew.exec_stores 20981511 # Number of stores executed 603system.cpu.iew.exec_rate 1.440176 # Inst execution rate 604system.cpu.iew.wb_sent 93586002 # cumulative count of insts sent to commit 605system.cpu.iew.wb_count 93464426 # cumulative count of insts written-back 606system.cpu.iew.wb_producers 44933898 # num instructions producing a value 607system.cpu.iew.wb_consumers 76510027 # num instructions consuming a value 608system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 609system.cpu.iew.wb_rate 1.432835 # insts written-back per cycle 610system.cpu.iew.wb_fanout 0.587294 # average fanout of values written-back 611system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 612system.cpu.commit.commitSquashedInsts 6524705 # The number of squashed insts skipped by commit 613system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 614system.cpu.commit.branchMispredicts 478981 # The number of times a branch was mispredicted 615system.cpu.commit.committed_per_cycle::samples 63829281 # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::mean 1.420792 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::stdev 2.179767 # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::0 30376493 47.59% 47.59% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::1 16710378 26.18% 73.77% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::2 4273265 6.69% 80.46% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::3 4126779 6.47% 86.93% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::4 1950134 3.06% 89.99% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::5 1295842 2.03% 92.02% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::6 707155 1.11% 93.12% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::7 585665 0.92% 94.04% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::8 3803570 5.96% 100.00% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::total 63829281 # Number of insts commited each cycle 632system.cpu.commit.committedInsts 70913181 # Number of instructions committed 633system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed 634system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 635system.cpu.commit.refs 43422000 # Number of memory references committed 636system.cpu.commit.loads 22866262 # Number of loads committed 637system.cpu.commit.membars 15920 # Number of memory barriers committed 638system.cpu.commit.branches 13741485 # Number of branches committed 639system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 640system.cpu.commit.int_insts 81528487 # Number of committed integer instructions. 641system.cpu.commit.function_calls 1679850 # Number of function calls committed. 642system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 643system.cpu.commit.op_class_0::IntAlu 47186010 52.03% 52.03% # Class of committed instruction 644system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 645system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 646system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 647system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 648system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 649system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction 650system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction 651system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 672system.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 673system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 674system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 675system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction 677system.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached 678system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 679system.cpu.rob.rob_reads 157213253 # The number of ROB reads 680system.cpu.rob.rob_writes 195483388 # The number of ROB writes 681system.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself 682system.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling 683system.cpu.committedInsts 70907629 # Number of Instructions Simulated 684system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated 685system.cpu.cpi 0.919935 # CPI: Cycles Per Instruction 686system.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads 687system.cpu.ipc 1.087033 # IPC: Instructions Per Cycle 688system.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads 689system.cpu.int_regfile_reads 102236524 # number of integer regfile reads 690system.cpu.int_regfile_writes 56794814 # number of integer regfile writes 691system.cpu.fp_regfile_reads 36 # number of floating regfile reads 692system.cpu.fp_regfile_writes 21 # number of floating regfile writes 693system.cpu.cc_regfile_reads 346002142 # number of cc regfile reads 694system.cpu.cc_regfile_writes 38804540 # number of cc regfile writes 695system.cpu.misc_regfile_reads 44207937 # number of misc regfile reads 696system.cpu.misc_regfile_writes 31840 # number of misc regfile writes 697system.cpu.toL2Bus.trans_dist::ReadReq 661258 # Transaction distribution 698system.cpu.toL2Bus.trans_dist::ReadResp 661257 # Transaction distribution 699system.cpu.toL2Bus.trans_dist::Writeback 256573 # Transaction distribution 700system.cpu.toL2Bus.trans_dist::HardPFReq 261175 # Transaction distribution 701system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution 702system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution 703system.cpu.toL2Bus.trans_dist::ReadExReq 148561 # Transaction distribution 704system.cpu.toL2Bus.trans_dist::ReadExResp 148561 # Transaction distribution 705system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647966 # Packet count per connected master and slave (bytes) 706system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1228253 # Packet count per connected master and slave (bytes) 707system.cpu.toL2Bus.pkt_count::total 1876219 # Packet count per connected master and slave (bytes) 708system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20734528 # Cumulative packet size per connected master and slave (bytes) 709system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47513792 # Cumulative packet size per connected master and slave (bytes) 710system.cpu.toL2Bus.pkt_size::total 68248320 # Cumulative packet size per connected master and slave (bytes) 711system.cpu.toL2Bus.snoops 261186 # Total snoops (count) 712system.cpu.toL2Bus.snoop_fanout::samples 1327591 # Request fanout histogram 713system.cpu.toL2Bus.snoop_fanout::mean 5.196729 # Request fanout histogram 714system.cpu.toL2Bus.snoop_fanout::stdev 0.397525 # Request fanout histogram 715system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 716system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 717system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 718system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 719system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 720system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 721system.cpu.toL2Bus.snoop_fanout::5 1066416 80.33% 80.33% # Request fanout histogram 722system.cpu.toL2Bus.snoop_fanout::6 261175 19.67% 100.00% # Request fanout histogram 723system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 724system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 725system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 726system.cpu.toL2Bus.snoop_fanout::total 1327591 # Request fanout histogram 727system.cpu.toL2Bus.reqLayer0.occupancy 789786488 # Layer occupancy (ticks) 728system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) 729system.cpu.toL2Bus.respLayer0.occupancy 486428945 # Layer occupancy (ticks) 730system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 731system.cpu.toL2Bus.respLayer1.occupancy 733917689 # Layer occupancy (ticks) 732system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 733system.cpu.icache.tags.replacements 323466 # number of replacements 734system.cpu.icache.tags.tagsinuse 510.438944 # Cycle average of tags in use 735system.cpu.icache.tags.total_refs 22431935 # Total number of references to valid blocks. 736system.cpu.icache.tags.sampled_refs 323978 # Sample count of references to valid blocks. 737system.cpu.icache.tags.avg_refs 69.239069 # Average number of references to valid blocks. 738system.cpu.icache.tags.warmup_cycle 1054590000 # Cycle when the warmup percentage was hit. 739system.cpu.icache.tags.occ_blocks::cpu.inst 510.438944 # Average occupied blocks per requestor 740system.cpu.icache.tags.occ_percent::cpu.inst 0.996951 # Average percentage of cache occupancy 741system.cpu.icache.tags.occ_percent::total 0.996951 # Average percentage of cache occupancy 742system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 743system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 744system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id 745system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id 746system.cpu.icache.tags.age_task_id_blocks_1024::3 267 # Occupied blocks per task id 747system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 748system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 749system.cpu.icache.tags.tag_accesses 45851126 # Number of tag accesses 750system.cpu.icache.tags.data_accesses 45851126 # Number of data accesses 751system.cpu.icache.ReadReq_hits::cpu.inst 22431935 # number of ReadReq hits 752system.cpu.icache.ReadReq_hits::total 22431935 # number of ReadReq hits 753system.cpu.icache.demand_hits::cpu.inst 22431935 # number of demand (read+write) hits 754system.cpu.icache.demand_hits::total 22431935 # number of demand (read+write) hits 755system.cpu.icache.overall_hits::cpu.inst 22431935 # number of overall hits 756system.cpu.icache.overall_hits::total 22431935 # number of overall hits 757system.cpu.icache.ReadReq_misses::cpu.inst 331634 # number of ReadReq misses 758system.cpu.icache.ReadReq_misses::total 331634 # number of ReadReq misses 759system.cpu.icache.demand_misses::cpu.inst 331634 # number of demand (read+write) misses 760system.cpu.icache.demand_misses::total 331634 # number of demand (read+write) misses 761system.cpu.icache.overall_misses::cpu.inst 331634 # number of overall misses 762system.cpu.icache.overall_misses::total 331634 # number of overall misses 763system.cpu.icache.ReadReq_miss_latency::cpu.inst 2861760504 # number of ReadReq miss cycles 764system.cpu.icache.ReadReq_miss_latency::total 2861760504 # number of ReadReq miss cycles 765system.cpu.icache.demand_miss_latency::cpu.inst 2861760504 # number of demand (read+write) miss cycles 766system.cpu.icache.demand_miss_latency::total 2861760504 # number of demand (read+write) miss cycles 767system.cpu.icache.overall_miss_latency::cpu.inst 2861760504 # number of overall miss cycles 768system.cpu.icache.overall_miss_latency::total 2861760504 # number of overall miss cycles 769system.cpu.icache.ReadReq_accesses::cpu.inst 22763569 # number of ReadReq accesses(hits+misses) 770system.cpu.icache.ReadReq_accesses::total 22763569 # number of ReadReq accesses(hits+misses) 771system.cpu.icache.demand_accesses::cpu.inst 22763569 # number of demand (read+write) accesses 772system.cpu.icache.demand_accesses::total 22763569 # number of demand (read+write) accesses 773system.cpu.icache.overall_accesses::cpu.inst 22763569 # number of overall (read+write) accesses 774system.cpu.icache.overall_accesses::total 22763569 # number of overall (read+write) accesses 775system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses 776system.cpu.icache.ReadReq_miss_rate::total 0.014569 # miss rate for ReadReq accesses 777system.cpu.icache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses 778system.cpu.icache.demand_miss_rate::total 0.014569 # miss rate for demand accesses 779system.cpu.icache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses 780system.cpu.icache.overall_miss_rate::total 0.014569 # miss rate for overall accesses 781system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8629.273549 # average ReadReq miss latency 782system.cpu.icache.ReadReq_avg_miss_latency::total 8629.273549 # average ReadReq miss latency 783system.cpu.icache.demand_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency 784system.cpu.icache.demand_avg_miss_latency::total 8629.273549 # average overall miss latency 785system.cpu.icache.overall_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency 786system.cpu.icache.overall_avg_miss_latency::total 8629.273549 # average overall miss latency 787system.cpu.icache.blocked_cycles::no_mshrs 97738 # number of cycles access was blocked 788system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 789system.cpu.icache.blocked::no_mshrs 12080 # number of cycles access was blocked 790system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 791system.cpu.icache.avg_blocked_cycles::no_mshrs 8.090894 # average number of cycles each access was blocked 792system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 793system.cpu.icache.fast_writes 0 # number of fast writes performed 794system.cpu.icache.cache_copies 0 # number of cache copies performed 795system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7645 # number of ReadReq MSHR hits 796system.cpu.icache.ReadReq_mshr_hits::total 7645 # number of ReadReq MSHR hits 797system.cpu.icache.demand_mshr_hits::cpu.inst 7645 # number of demand (read+write) MSHR hits 798system.cpu.icache.demand_mshr_hits::total 7645 # number of demand (read+write) MSHR hits 799system.cpu.icache.overall_mshr_hits::cpu.inst 7645 # number of overall MSHR hits 800system.cpu.icache.overall_mshr_hits::total 7645 # number of overall MSHR hits 801system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323989 # number of ReadReq MSHR misses 802system.cpu.icache.ReadReq_mshr_misses::total 323989 # number of ReadReq MSHR misses 803system.cpu.icache.demand_mshr_misses::cpu.inst 323989 # number of demand (read+write) MSHR misses 804system.cpu.icache.demand_mshr_misses::total 323989 # number of demand (read+write) MSHR misses 805system.cpu.icache.overall_mshr_misses::cpu.inst 323989 # number of overall MSHR misses 806system.cpu.icache.overall_mshr_misses::total 323989 # number of overall MSHR misses 807system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325660123 # number of ReadReq MSHR miss cycles 808system.cpu.icache.ReadReq_mshr_miss_latency::total 2325660123 # number of ReadReq MSHR miss cycles 809system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325660123 # number of demand (read+write) MSHR miss cycles 810system.cpu.icache.demand_mshr_miss_latency::total 2325660123 # number of demand (read+write) MSHR miss cycles 811system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325660123 # number of overall MSHR miss cycles 812system.cpu.icache.overall_mshr_miss_latency::total 2325660123 # number of overall MSHR miss cycles 813system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for ReadReq accesses 814system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014233 # mshr miss rate for ReadReq accesses 815system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for demand accesses 816system.cpu.icache.demand_mshr_miss_rate::total 0.014233 # mshr miss rate for demand accesses 817system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for overall accesses 818system.cpu.icache.overall_mshr_miss_rate::total 0.014233 # mshr miss rate for overall accesses 819system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7178.207047 # average ReadReq mshr miss latency 820system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7178.207047 # average ReadReq mshr miss latency 821system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency 822system.cpu.icache.demand_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency 823system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency 824system.cpu.icache.overall_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency 825system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 826system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 3266027 # number of hwpf identified 827system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 304781 # number of hwpf that were already in mshr 828system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2719229 # number of hwpf that were already in the cache 829system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 25673 # number of hwpf that were already in the prefetch queue 830system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 831system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 17215 # number of hwpf removed because MSHR allocated 832system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 199121 # number of hwpf issued 833system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 314405 # number of hwpf spanning a virtual page 834system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 835system.cpu.l2cache.tags.replacements 140078 # number of replacements 836system.cpu.l2cache.tags.tagsinuse 16107.104250 # Cycle average of tags in use 837system.cpu.l2cache.tags.total_refs 874451 # Total number of references to valid blocks. 838system.cpu.l2cache.tags.sampled_refs 156393 # Sample count of references to valid blocks. 839system.cpu.l2cache.tags.avg_refs 5.591369 # Average number of references to valid blocks. 840system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 841system.cpu.l2cache.tags.occ_blocks::writebacks 11482.142430 # Average occupied blocks per requestor 842system.cpu.l2cache.tags.occ_blocks::cpu.inst 301.953059 # Average occupied blocks per requestor 843system.cpu.l2cache.tags.occ_blocks::cpu.data 1690.013125 # Average occupied blocks per requestor 844system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2632.995635 # Average occupied blocks per requestor 845system.cpu.l2cache.tags.occ_percent::writebacks 0.700814 # Average percentage of cache occupancy 846system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018430 # Average percentage of cache occupancy 847system.cpu.l2cache.tags.occ_percent::cpu.data 0.103150 # Average percentage of cache occupancy 848system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.160705 # Average percentage of cache occupancy 849system.cpu.l2cache.tags.occ_percent::total 0.983100 # Average percentage of cache occupancy 850system.cpu.l2cache.tags.occ_task_id_blocks::1022 869 # Occupied blocks per task id 851system.cpu.l2cache.tags.occ_task_id_blocks::1024 15446 # Occupied blocks per task id 852system.cpu.l2cache.tags.age_task_id_blocks_1022::0 223 # Occupied blocks per task id 853system.cpu.l2cache.tags.age_task_id_blocks_1022::1 244 # Occupied blocks per task id 854system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id 855system.cpu.l2cache.tags.age_task_id_blocks_1022::3 234 # Occupied blocks per task id 856system.cpu.l2cache.tags.age_task_id_blocks_1022::4 156 # Occupied blocks per task id 857system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 858system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2751 # Occupied blocks per task id 859system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11585 # Occupied blocks per task id 860system.cpu.l2cache.tags.age_task_id_blocks_1024::3 388 # Occupied blocks per task id 861system.cpu.l2cache.tags.age_task_id_blocks_1024::4 623 # Occupied blocks per task id 862system.cpu.l2cache.tags.occ_task_id_percent::1022 0.053040 # Percentage of cache occupancy per task id 863system.cpu.l2cache.tags.occ_task_id_percent::1024 0.942749 # Percentage of cache occupancy per task id 864system.cpu.l2cache.tags.tag_accesses 17367214 # Number of tag accesses 865system.cpu.l2cache.tags.data_accesses 17367214 # Number of data accesses 866system.cpu.l2cache.ReadReq_hits::cpu.inst 320997 # number of ReadReq hits 867system.cpu.l2cache.ReadReq_hits::cpu.data 306363 # number of ReadReq hits 868system.cpu.l2cache.ReadReq_hits::total 627360 # number of ReadReq hits 869system.cpu.l2cache.Writeback_hits::writebacks 256573 # number of Writeback hits 870system.cpu.l2cache.Writeback_hits::total 256573 # number of Writeback hits 871system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 872system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 873system.cpu.l2cache.ReadExReq_hits::cpu.data 139690 # number of ReadExReq hits 874system.cpu.l2cache.ReadExReq_hits::total 139690 # number of ReadExReq hits 875system.cpu.l2cache.demand_hits::cpu.inst 320997 # number of demand (read+write) hits 876system.cpu.l2cache.demand_hits::cpu.data 446053 # number of demand (read+write) hits 877system.cpu.l2cache.demand_hits::total 767050 # number of demand (read+write) hits 878system.cpu.l2cache.overall_hits::cpu.inst 320997 # number of overall hits 879system.cpu.l2cache.overall_hits::cpu.data 446053 # number of overall hits 880system.cpu.l2cache.overall_hits::total 767050 # number of overall hits 881system.cpu.l2cache.ReadReq_misses::cpu.inst 2981 # number of ReadReq misses 882system.cpu.l2cache.ReadReq_misses::cpu.data 30906 # number of ReadReq misses 883system.cpu.l2cache.ReadReq_misses::total 33887 # number of ReadReq misses 884system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 885system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 886system.cpu.l2cache.ReadExReq_misses::cpu.data 8871 # number of ReadExReq misses 887system.cpu.l2cache.ReadExReq_misses::total 8871 # number of ReadExReq misses 888system.cpu.l2cache.demand_misses::cpu.inst 2981 # number of demand (read+write) misses 889system.cpu.l2cache.demand_misses::cpu.data 39777 # number of demand (read+write) misses 890system.cpu.l2cache.demand_misses::total 42758 # number of demand (read+write) misses 891system.cpu.l2cache.overall_misses::cpu.inst 2981 # number of overall misses 892system.cpu.l2cache.overall_misses::cpu.data 39777 # number of overall misses 893system.cpu.l2cache.overall_misses::total 42758 # number of overall misses 894system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232061970 # number of ReadReq miss cycles 895system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2519217993 # number of ReadReq miss cycles 896system.cpu.l2cache.ReadReq_miss_latency::total 2751279963 # number of ReadReq miss cycles 897system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950040000 # number of ReadExReq miss cycles 898system.cpu.l2cache.ReadExReq_miss_latency::total 950040000 # number of ReadExReq miss cycles 899system.cpu.l2cache.demand_miss_latency::cpu.inst 232061970 # number of demand (read+write) miss cycles 900system.cpu.l2cache.demand_miss_latency::cpu.data 3469257993 # number of demand (read+write) miss cycles 901system.cpu.l2cache.demand_miss_latency::total 3701319963 # number of demand (read+write) miss cycles 902system.cpu.l2cache.overall_miss_latency::cpu.inst 232061970 # number of overall miss cycles 903system.cpu.l2cache.overall_miss_latency::cpu.data 3469257993 # number of overall miss cycles 904system.cpu.l2cache.overall_miss_latency::total 3701319963 # number of overall miss cycles 905system.cpu.l2cache.ReadReq_accesses::cpu.inst 323978 # number of ReadReq accesses(hits+misses) 906system.cpu.l2cache.ReadReq_accesses::cpu.data 337269 # number of ReadReq accesses(hits+misses) 907system.cpu.l2cache.ReadReq_accesses::total 661247 # number of ReadReq accesses(hits+misses) 908system.cpu.l2cache.Writeback_accesses::writebacks 256573 # number of Writeback accesses(hits+misses) 909system.cpu.l2cache.Writeback_accesses::total 256573 # number of Writeback accesses(hits+misses) 910system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) 911system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) 912system.cpu.l2cache.ReadExReq_accesses::cpu.data 148561 # number of ReadExReq accesses(hits+misses) 913system.cpu.l2cache.ReadExReq_accesses::total 148561 # number of ReadExReq accesses(hits+misses) 914system.cpu.l2cache.demand_accesses::cpu.inst 323978 # number of demand (read+write) accesses 915system.cpu.l2cache.demand_accesses::cpu.data 485830 # number of demand (read+write) accesses 916system.cpu.l2cache.demand_accesses::total 809808 # number of demand (read+write) accesses 917system.cpu.l2cache.overall_accesses::cpu.inst 323978 # number of overall (read+write) accesses 918system.cpu.l2cache.overall_accesses::cpu.data 485830 # number of overall (read+write) accesses 919system.cpu.l2cache.overall_accesses::total 809808 # number of overall (read+write) accesses 920system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.009201 # miss rate for ReadReq accesses 921system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.091636 # miss rate for ReadReq accesses 922system.cpu.l2cache.ReadReq_miss_rate::total 0.051247 # miss rate for ReadReq accesses 923system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses 924system.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses 925system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.059713 # miss rate for ReadExReq accesses 926system.cpu.l2cache.ReadExReq_miss_rate::total 0.059713 # miss rate for ReadExReq accesses 927system.cpu.l2cache.demand_miss_rate::cpu.inst 0.009201 # miss rate for demand accesses 928system.cpu.l2cache.demand_miss_rate::cpu.data 0.081874 # miss rate for demand accesses 929system.cpu.l2cache.demand_miss_rate::total 0.052800 # miss rate for demand accesses 930system.cpu.l2cache.overall_miss_rate::cpu.inst 0.009201 # miss rate for overall accesses 931system.cpu.l2cache.overall_miss_rate::cpu.data 0.081874 # miss rate for overall accesses 932system.cpu.l2cache.overall_miss_rate::total 0.052800 # miss rate for overall accesses 933system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77847.021134 # average ReadReq miss latency 934system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81512.262765 # average ReadReq miss latency 935system.cpu.l2cache.ReadReq_avg_miss_latency::total 81189.835719 # average ReadReq miss latency 936system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107095.028745 # average ReadExReq miss latency 937system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107095.028745 # average ReadExReq miss latency 938system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77847.021134 # average overall miss latency 939system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87217.688438 # average overall miss latency 940system.cpu.l2cache.demand_avg_miss_latency::total 86564.384747 # average overall miss latency 941system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77847.021134 # average overall miss latency 942system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87217.688438 # average overall miss latency 943system.cpu.l2cache.overall_avg_miss_latency::total 86564.384747 # average overall miss latency 944system.cpu.l2cache.blocked_cycles::no_mshrs 3458 # number of cycles access was blocked 945system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 946system.cpu.l2cache.blocked::no_mshrs 119 # number of cycles access was blocked 947system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 948system.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.058824 # average number of cycles each access was blocked 949system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 950system.cpu.l2cache.fast_writes 0 # number of fast writes performed 951system.cpu.l2cache.cache_copies 0 # number of cache copies performed 952system.cpu.l2cache.writebacks::writebacks 98491 # number of writebacks 953system.cpu.l2cache.writebacks::total 98491 # number of writebacks 954system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 910 # number of ReadReq MSHR hits 955system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 298 # number of ReadReq MSHR hits 956system.cpu.l2cache.ReadReq_mshr_hits::total 1208 # number of ReadReq MSHR hits 957system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2953 # number of ReadExReq MSHR hits 958system.cpu.l2cache.ReadExReq_mshr_hits::total 2953 # number of ReadExReq MSHR hits 959system.cpu.l2cache.demand_mshr_hits::cpu.inst 910 # number of demand (read+write) MSHR hits 960system.cpu.l2cache.demand_mshr_hits::cpu.data 3251 # number of demand (read+write) MSHR hits 961system.cpu.l2cache.demand_mshr_hits::total 4161 # number of demand (read+write) MSHR hits 962system.cpu.l2cache.overall_mshr_hits::cpu.inst 910 # number of overall MSHR hits 963system.cpu.l2cache.overall_mshr_hits::cpu.data 3251 # number of overall MSHR hits 964system.cpu.l2cache.overall_mshr_hits::total 4161 # number of overall MSHR hits 965system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2071 # number of ReadReq MSHR misses 966system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30608 # number of ReadReq MSHR misses 967system.cpu.l2cache.ReadReq_mshr_misses::total 32679 # number of ReadReq MSHR misses 968system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 199121 # number of HardPFReq MSHR misses 969system.cpu.l2cache.HardPFReq_mshr_misses::total 199121 # number of HardPFReq MSHR misses 970system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 971system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 972system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 5918 # number of ReadExReq MSHR misses 973system.cpu.l2cache.ReadExReq_mshr_misses::total 5918 # number of ReadExReq MSHR misses 974system.cpu.l2cache.demand_mshr_misses::cpu.inst 2071 # number of demand (read+write) MSHR misses 975system.cpu.l2cache.demand_mshr_misses::cpu.data 36526 # number of demand (read+write) MSHR misses 976system.cpu.l2cache.demand_mshr_misses::total 38597 # number of demand (read+write) MSHR misses 977system.cpu.l2cache.overall_mshr_misses::cpu.inst 2071 # number of overall MSHR misses 978system.cpu.l2cache.overall_mshr_misses::cpu.data 36526 # number of overall MSHR misses 979system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 199121 # number of overall MSHR misses 980system.cpu.l2cache.overall_mshr_misses::total 237718 # number of overall MSHR misses 981system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159067500 # number of ReadReq MSHR miss cycles 982system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2245450503 # number of ReadReq MSHR miss cycles 983system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2404518003 # number of ReadReq MSHR miss cycles 984system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of HardPFReq MSHR miss cycles 985system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 12215795775 # number of HardPFReq MSHR miss cycles 986system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 36006 # number of UpgradeReq MSHR miss cycles 987system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 36006 # number of UpgradeReq MSHR miss cycles 988system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 395713000 # number of ReadExReq MSHR miss cycles 989system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 395713000 # number of ReadExReq MSHR miss cycles 990system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159067500 # number of demand (read+write) MSHR miss cycles 991system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2641163503 # number of demand (read+write) MSHR miss cycles 992system.cpu.l2cache.demand_mshr_miss_latency::total 2800231003 # number of demand (read+write) MSHR miss cycles 993system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159067500 # number of overall MSHR miss cycles 994system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2641163503 # number of overall MSHR miss cycles 995system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of overall MSHR miss cycles 996system.cpu.l2cache.overall_mshr_miss_latency::total 15016026778 # number of overall MSHR miss cycles 997system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for ReadReq accesses 998system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.090752 # mshr miss rate for ReadReq accesses 999system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.049420 # mshr miss rate for ReadReq accesses 1000system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1001system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1002system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses 1003system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses 1004system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.039835 # mshr miss rate for ReadExReq accesses 1005system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.039835 # mshr miss rate for ReadExReq accesses 1006system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for demand accesses 1007system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for demand accesses 1008system.cpu.l2cache.demand_mshr_miss_rate::total 0.047662 # mshr miss rate for demand accesses 1009system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for overall accesses 1010system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for overall accesses 1011system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1012system.cpu.l2cache.overall_mshr_miss_rate::total 0.293549 # mshr miss rate for overall accesses 1013system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 76807.098020 # average ReadReq mshr miss latency 1014system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73361.555900 # average ReadReq mshr miss latency 1015system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73579.913798 # average ReadReq mshr miss latency 1016system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average HardPFReq mshr miss latency 1017system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61348.605998 # average HardPFReq mshr miss latency 1018system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 1019system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 1020system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66866.002028 # average ReadExReq mshr miss latency 1021system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66866.002028 # average ReadExReq mshr miss latency 1022system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency 1023system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency 1024system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72550.483276 # average overall mshr miss latency 1025system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency 1026system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency 1027system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average overall mshr miss latency 1028system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63167.394888 # average overall mshr miss latency 1029system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1030system.cpu.dcache.tags.replacements 485318 # number of replacements 1031system.cpu.dcache.tags.tagsinuse 510.841997 # Cycle average of tags in use 1032system.cpu.dcache.tags.total_refs 40443714 # Total number of references to valid blocks. 1033system.cpu.dcache.tags.sampled_refs 485830 # Sample count of references to valid blocks. 1034system.cpu.dcache.tags.avg_refs 83.246638 # Average number of references to valid blocks. 1035system.cpu.dcache.tags.warmup_cycle 139928000 # Cycle when the warmup percentage was hit. 1036system.cpu.dcache.tags.occ_blocks::cpu.data 510.841997 # Average occupied blocks per requestor 1037system.cpu.dcache.tags.occ_percent::cpu.data 0.997738 # Average percentage of cache occupancy 1038system.cpu.dcache.tags.occ_percent::total 0.997738 # Average percentage of cache occupancy 1039system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1040system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 1041system.cpu.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id 1042system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1043system.cpu.dcache.tags.tag_accesses 84640426 # Number of tag accesses 1044system.cpu.dcache.tags.data_accesses 84640426 # Number of data accesses 1045system.cpu.dcache.ReadReq_hits::cpu.data 21515343 # number of ReadReq hits 1046system.cpu.dcache.ReadReq_hits::total 21515343 # number of ReadReq hits 1047system.cpu.dcache.WriteReq_hits::cpu.data 18834765 # number of WriteReq hits 1048system.cpu.dcache.WriteReq_hits::total 18834765 # number of WriteReq hits 1049system.cpu.dcache.SoftPFReq_hits::cpu.data 62288 # number of SoftPFReq hits 1050system.cpu.dcache.SoftPFReq_hits::total 62288 # number of SoftPFReq hits 1051system.cpu.dcache.LoadLockedReq_hits::cpu.data 15377 # number of LoadLockedReq hits 1052system.cpu.dcache.LoadLockedReq_hits::total 15377 # number of LoadLockedReq hits 1053system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 1054system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 1055system.cpu.dcache.demand_hits::cpu.data 40350108 # number of demand (read+write) hits 1056system.cpu.dcache.demand_hits::total 40350108 # number of demand (read+write) hits 1057system.cpu.dcache.overall_hits::cpu.data 40412396 # number of overall hits 1058system.cpu.dcache.overall_hits::total 40412396 # number of overall hits 1059system.cpu.dcache.ReadReq_misses::cpu.data 551365 # number of ReadReq misses 1060system.cpu.dcache.ReadReq_misses::total 551365 # number of ReadReq misses 1061system.cpu.dcache.WriteReq_misses::cpu.data 1015136 # number of WriteReq misses 1062system.cpu.dcache.WriteReq_misses::total 1015136 # number of WriteReq misses 1063system.cpu.dcache.SoftPFReq_misses::cpu.data 66556 # number of SoftPFReq misses 1064system.cpu.dcache.SoftPFReq_misses::total 66556 # number of SoftPFReq misses 1065system.cpu.dcache.LoadLockedReq_misses::cpu.data 549 # number of LoadLockedReq misses 1066system.cpu.dcache.LoadLockedReq_misses::total 549 # number of LoadLockedReq misses 1067system.cpu.dcache.demand_misses::cpu.data 1566501 # number of demand (read+write) misses 1068system.cpu.dcache.demand_misses::total 1566501 # number of demand (read+write) misses 1069system.cpu.dcache.overall_misses::cpu.data 1633057 # number of overall misses 1070system.cpu.dcache.overall_misses::total 1633057 # number of overall misses 1071system.cpu.dcache.ReadReq_miss_latency::cpu.data 8548612161 # number of ReadReq miss cycles 1072system.cpu.dcache.ReadReq_miss_latency::total 8548612161 # number of ReadReq miss cycles 1073system.cpu.dcache.WriteReq_miss_latency::cpu.data 13150540915 # number of WriteReq miss cycles 1074system.cpu.dcache.WriteReq_miss_latency::total 13150540915 # number of WriteReq miss cycles 1075system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5021750 # number of LoadLockedReq miss cycles 1076system.cpu.dcache.LoadLockedReq_miss_latency::total 5021750 # number of LoadLockedReq miss cycles 1077system.cpu.dcache.demand_miss_latency::cpu.data 21699153076 # number of demand (read+write) miss cycles 1078system.cpu.dcache.demand_miss_latency::total 21699153076 # number of demand (read+write) miss cycles 1079system.cpu.dcache.overall_miss_latency::cpu.data 21699153076 # number of overall miss cycles 1080system.cpu.dcache.overall_miss_latency::total 21699153076 # number of overall miss cycles 1081system.cpu.dcache.ReadReq_accesses::cpu.data 22066708 # number of ReadReq accesses(hits+misses) 1082system.cpu.dcache.ReadReq_accesses::total 22066708 # number of ReadReq accesses(hits+misses) 1083system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 1084system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 1085system.cpu.dcache.SoftPFReq_accesses::cpu.data 128844 # number of SoftPFReq accesses(hits+misses) 1086system.cpu.dcache.SoftPFReq_accesses::total 128844 # number of SoftPFReq accesses(hits+misses) 1087system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) 1088system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) 1089system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 1090system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 1091system.cpu.dcache.demand_accesses::cpu.data 41916609 # number of demand (read+write) accesses 1092system.cpu.dcache.demand_accesses::total 41916609 # number of demand (read+write) accesses 1093system.cpu.dcache.overall_accesses::cpu.data 42045453 # number of overall (read+write) accesses 1094system.cpu.dcache.overall_accesses::total 42045453 # number of overall (read+write) accesses 1095system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024986 # miss rate for ReadReq accesses 1096system.cpu.dcache.ReadReq_miss_rate::total 0.024986 # miss rate for ReadReq accesses 1097system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051141 # miss rate for WriteReq accesses 1098system.cpu.dcache.WriteReq_miss_rate::total 0.051141 # miss rate for WriteReq accesses 1099system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516563 # miss rate for SoftPFReq accesses 1100system.cpu.dcache.SoftPFReq_miss_rate::total 0.516563 # miss rate for SoftPFReq accesses 1101system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034472 # miss rate for LoadLockedReq accesses 1102system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034472 # miss rate for LoadLockedReq accesses 1103system.cpu.dcache.demand_miss_rate::cpu.data 0.037372 # miss rate for demand accesses 1104system.cpu.dcache.demand_miss_rate::total 0.037372 # miss rate for demand accesses 1105system.cpu.dcache.overall_miss_rate::cpu.data 0.038840 # miss rate for overall accesses 1106system.cpu.dcache.overall_miss_rate::total 0.038840 # miss rate for overall accesses 1107system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15504.451971 # average ReadReq miss latency 1108system.cpu.dcache.ReadReq_avg_miss_latency::total 15504.451971 # average ReadReq miss latency 1109system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12954.462176 # average WriteReq miss latency 1110system.cpu.dcache.WriteReq_avg_miss_latency::total 12954.462176 # average WriteReq miss latency 1111system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9147.085610 # average LoadLockedReq miss latency 1112system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9147.085610 # average LoadLockedReq miss latency 1113system.cpu.dcache.demand_avg_miss_latency::cpu.data 13851.988014 # average overall miss latency 1114system.cpu.dcache.demand_avg_miss_latency::total 13851.988014 # average overall miss latency 1115system.cpu.dcache.overall_avg_miss_latency::cpu.data 13287.443779 # average overall miss latency 1116system.cpu.dcache.overall_avg_miss_latency::total 13287.443779 # average overall miss latency 1117system.cpu.dcache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked 1118system.cpu.dcache.blocked_cycles::no_targets 2567726 # number of cycles access was blocked 1119system.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 1120system.cpu.dcache.blocked::no_targets 127351 # number of cycles access was blocked 1121system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.214286 # average number of cycles each access was blocked 1122system.cpu.dcache.avg_blocked_cycles::no_targets 20.162590 # average number of cycles each access was blocked 1123system.cpu.dcache.fast_writes 0 # number of fast writes performed 1124system.cpu.dcache.cache_copies 0 # number of cache copies performed 1125system.cpu.dcache.writebacks::writebacks 256573 # number of writebacks 1126system.cpu.dcache.writebacks::total 256573 # number of writebacks 1127system.cpu.dcache.ReadReq_mshr_hits::cpu.data 251643 # number of ReadReq MSHR hits 1128system.cpu.dcache.ReadReq_mshr_hits::total 251643 # number of ReadReq MSHR hits 1129system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866615 # number of WriteReq MSHR hits 1130system.cpu.dcache.WriteReq_mshr_hits::total 866615 # number of WriteReq MSHR hits 1131system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 549 # number of LoadLockedReq MSHR hits 1132system.cpu.dcache.LoadLockedReq_mshr_hits::total 549 # number of LoadLockedReq MSHR hits 1133system.cpu.dcache.demand_mshr_hits::cpu.data 1118258 # number of demand (read+write) MSHR hits 1134system.cpu.dcache.demand_mshr_hits::total 1118258 # number of demand (read+write) MSHR hits 1135system.cpu.dcache.overall_mshr_hits::cpu.data 1118258 # number of overall MSHR hits 1136system.cpu.dcache.overall_mshr_hits::total 1118258 # number of overall MSHR hits 1137system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299722 # number of ReadReq MSHR misses 1138system.cpu.dcache.ReadReq_mshr_misses::total 299722 # number of ReadReq MSHR misses 1139system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148521 # number of WriteReq MSHR misses 1140system.cpu.dcache.WriteReq_mshr_misses::total 148521 # number of WriteReq MSHR misses 1141system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses 1142system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses 1143system.cpu.dcache.demand_mshr_misses::cpu.data 448243 # number of demand (read+write) MSHR misses 1144system.cpu.dcache.demand_mshr_misses::total 448243 # number of demand (read+write) MSHR misses 1145system.cpu.dcache.overall_mshr_misses::cpu.data 485840 # number of overall MSHR misses 1146system.cpu.dcache.overall_mshr_misses::total 485840 # number of overall MSHR misses 1147system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2813681816 # number of ReadReq MSHR miss cycles 1148system.cpu.dcache.ReadReq_mshr_miss_latency::total 2813681816 # number of ReadReq MSHR miss cycles 1149system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1950344957 # number of WriteReq MSHR miss cycles 1150system.cpu.dcache.WriteReq_mshr_miss_latency::total 1950344957 # number of WriteReq MSHR miss cycles 1151system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1901549750 # number of SoftPFReq MSHR miss cycles 1152system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1901549750 # number of SoftPFReq MSHR miss cycles 1153system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4764026773 # number of demand (read+write) MSHR miss cycles 1154system.cpu.dcache.demand_mshr_miss_latency::total 4764026773 # number of demand (read+write) MSHR miss cycles 1155system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6665576523 # number of overall MSHR miss cycles 1156system.cpu.dcache.overall_mshr_miss_latency::total 6665576523 # number of overall MSHR miss cycles 1157system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013583 # mshr miss rate for ReadReq accesses 1158system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013583 # mshr miss rate for ReadReq accesses 1159system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses 1160system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses 1161system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291802 # mshr miss rate for SoftPFReq accesses 1162system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291802 # mshr miss rate for SoftPFReq accesses 1163system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010694 # mshr miss rate for demand accesses 1164system.cpu.dcache.demand_mshr_miss_rate::total 0.010694 # mshr miss rate for demand accesses 1165system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses 1166system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses 1167system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9387.638598 # average ReadReq mshr miss latency 1168system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9387.638598 # average ReadReq mshr miss latency 1169system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13131.779055 # average WriteReq mshr miss latency 1170system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13131.779055 # average WriteReq mshr miss latency 1171system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50577.167061 # average SoftPFReq mshr miss latency 1172system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50577.167061 # average SoftPFReq mshr miss latency 1173system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10628.223470 # average overall mshr miss latency 1174system.cpu.dcache.demand_avg_mshr_miss_latency::total 10628.223470 # average overall mshr miss latency 1175system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13719.694803 # average overall mshr miss latency 1176system.cpu.dcache.overall_avg_mshr_miss_latency::total 13719.694803 # average overall mshr miss latency 1177system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1178 1179---------- End Simulation Statistics ---------- 1180