stats.txt revision 9481
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 39459Ssaidi@eecs.umich.edusim_seconds 0.026275 # Number of seconds simulated 49459Ssaidi@eecs.umich.edusim_ticks 26275145500 # Number of ticks simulated 59459Ssaidi@eecs.umich.edufinal_tick 26275145500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79481Snilay@cs.wisc.eduhost_inst_rate 87619 # Simulator instruction rate (inst/s) 89481Snilay@cs.wisc.eduhost_op_rate 124343 # Simulator op (including micro ops) rate (op/s) 99481Snilay@cs.wisc.eduhost_tick_rate 32467681 # Simulator tick rate (ticks/s) 109481Snilay@cs.wisc.eduhost_mem_usage 316828 # Number of bytes of host memory used 119481Snilay@cs.wisc.eduhost_seconds 809.27 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 70907629 # Number of instructions simulated 139459Ssaidi@eecs.umich.edusim_ops 100626876 # Number of ops (including micro ops) simulated 149459Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory 159459Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory 169459Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 8240576 # Number of bytes read from this memory 179459Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 298112 # Number of instructions bytes read from this memory 189459Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 298112 # Number of instructions bytes read from this memory 199459Ssaidi@eecs.umich.edusystem.physmem.bytes_written::writebacks 5372608 # Number of bytes written to this memory 209459Ssaidi@eecs.umich.edusystem.physmem.bytes_written::total 5372608 # Number of bytes written to this memory 219459Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 4658 # Number of read requests responded to by this memory 229459Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory 239459Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 128759 # Number of read requests responded to by this memory 249459Ssaidi@eecs.umich.edusystem.physmem.num_writes::writebacks 83947 # Number of write requests responded to by this memory 259459Ssaidi@eecs.umich.edusystem.physmem.num_writes::total 83947 # Number of write requests responded to by this memory 269459Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.inst 11345779 # Total read bandwidth from this memory (bytes/s) 279459Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.data 302280495 # Total read bandwidth from this memory (bytes/s) 289459Ssaidi@eecs.umich.edusystem.physmem.bw_read::total 313626275 # Total read bandwidth from this memory (bytes/s) 299459Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu.inst 11345779 # Instruction read bandwidth from this memory (bytes/s) 309459Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 11345779 # Instruction read bandwidth from this memory (bytes/s) 319459Ssaidi@eecs.umich.edusystem.physmem.bw_write::writebacks 204474910 # Write bandwidth from this memory (bytes/s) 329459Ssaidi@eecs.umich.edusystem.physmem.bw_write::total 204474910 # Write bandwidth from this memory (bytes/s) 339459Ssaidi@eecs.umich.edusystem.physmem.bw_total::writebacks 204474910 # Total bandwidth to/from this memory (bytes/s) 349459Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.inst 11345779 # Total bandwidth to/from this memory (bytes/s) 359459Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.data 302280495 # Total bandwidth to/from this memory (bytes/s) 369459Ssaidi@eecs.umich.edusystem.physmem.bw_total::total 518101184 # Total bandwidth to/from this memory (bytes/s) 379459Ssaidi@eecs.umich.edusystem.physmem.readReqs 128759 # Total number of read requests seen 389459Ssaidi@eecs.umich.edusystem.physmem.writeReqs 83947 # Total number of write requests seen 399459Ssaidi@eecs.umich.edusystem.physmem.cpureqs 213029 # Reqs generatd by CPU via cache - shady 409459Ssaidi@eecs.umich.edusystem.physmem.bytesRead 8240576 # Total number of bytes read from memory 419459Ssaidi@eecs.umich.edusystem.physmem.bytesWritten 5372608 # Total number of bytes written to memory 429459Ssaidi@eecs.umich.edusystem.physmem.bytesConsumedRd 8240576 # bytesRead derated as per pkt->getSize() 439459Ssaidi@eecs.umich.edusystem.physmem.bytesConsumedWr 5372608 # bytesWritten derated as per pkt->getSize() 449459Ssaidi@eecs.umich.edusystem.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q 459459Ssaidi@eecs.umich.edusystem.physmem.neitherReadNorWrite 323 # Reqs where no action is needed 469459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::0 8173 # Track reads on a per bank basis 479459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::1 8031 # Track reads on a per bank basis 489459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::2 8094 # Track reads on a per bank basis 499459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::3 7897 # Track reads on a per bank basis 509459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::4 7925 # Track reads on a per bank basis 519459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::5 8110 # Track reads on a per bank basis 529459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::6 8031 # Track reads on a per bank basis 539459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::7 7954 # Track reads on a per bank basis 549459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::8 7989 # Track reads on a per bank basis 559459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::9 8189 # Track reads on a per bank basis 569459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::10 8178 # Track reads on a per bank basis 579459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::11 8151 # Track reads on a per bank basis 589459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::12 8058 # Track reads on a per bank basis 599459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::13 8009 # Track reads on a per bank basis 609459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::14 7986 # Track reads on a per bank basis 619459Ssaidi@eecs.umich.edusystem.physmem.perBankRdReqs::15 7982 # Track reads on a per bank basis 629459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::0 5173 # Track writes on a per bank basis 639322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis 649459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::2 5232 # Track writes on a per bank basis 659459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::3 5235 # Track writes on a per bank basis 669459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::4 5165 # Track writes on a per bank basis 679322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis 689459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::6 5168 # Track writes on a per bank basis 699322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis 709459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::8 5231 # Track writes on a per bank basis 719322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis 729322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis 739322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis 749459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::12 5371 # Track writes on a per bank basis 759348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis 769348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis 779459Ssaidi@eecs.umich.edusystem.physmem.perBankWrReqs::15 5150 # Track writes on a per bank basis 789312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 799312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 809459Ssaidi@eecs.umich.edusystem.physmem.totGap 26275013500 # Total gap between requests 819312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 829312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 839312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 849312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 859312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 879459Ssaidi@eecs.umich.edusystem.physmem.readPktSize::6 128759 # Categorize read packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 969459Ssaidi@eecs.umich.edusystem.physmem.writePktSize::6 83947 # categorize write packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 1019312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 1029312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 1039312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 1049312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 1059459Ssaidi@eecs.umich.edusystem.physmem.neitherpktsize::6 323 # categorize neither packet sizes 1069312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1079312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1089459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::0 70960 # What read queue length does an incoming req see 1099459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::1 55313 # What read queue length does an incoming req see 1109459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::2 2400 # What read queue length does an incoming req see 1119459Ssaidi@eecs.umich.edusystem.physmem.rdQLenPdf::3 72 # What read queue length does an incoming req see 1129348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see 1139322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1149322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1419459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::0 3605 # What write queue length does an incoming req see 1429459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see 1439348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see 1449459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::3 3650 # What write queue length does an incoming req see 1459459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see 1469322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see 1479322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see 1489322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see 1499322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see 1509322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see 1519322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see 1529322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see 1539322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see 1549322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see 1559322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see 1569322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see 1579459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see 1589459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see 1599459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see 1609459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see 1619348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see 1629322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see 1639322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see 1649459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::23 45 # What write queue length does an incoming req see 1659459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see 1669348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 1679459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1689459Ssaidi@eecs.umich.edusystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1699312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1709312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1719312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1729312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1739312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1749459Ssaidi@eecs.umich.edusystem.physmem.totQLat 4891352059 # Total cycles spent in queuing delays 1759459Ssaidi@eecs.umich.edusystem.physmem.totMemAccLat 6777204059 # Sum of mem lat for all requests 1769459Ssaidi@eecs.umich.edusystem.physmem.totBusLat 515028000 # Total cycles spent in databus access 1779459Ssaidi@eecs.umich.edusystem.physmem.totBankLat 1370824000 # Total cycles spent in bank access 1789459Ssaidi@eecs.umich.edusystem.physmem.avgQLat 37989.02 # Average queueing delay per request 1799459Ssaidi@eecs.umich.edusystem.physmem.avgBankLat 10646.60 # Average bank access latency per request 1809312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1819459Ssaidi@eecs.umich.edusystem.physmem.avgMemAccLat 52635.62 # Average memory access latency 1829459Ssaidi@eecs.umich.edusystem.physmem.avgRdBW 313.63 # Average achieved read bandwidth in MB/s 1839459Ssaidi@eecs.umich.edusystem.physmem.avgWrBW 204.47 # Average achieved write bandwidth in MB/s 1849459Ssaidi@eecs.umich.edusystem.physmem.avgConsumedRdBW 313.63 # Average consumed read bandwidth in MB/s 1859459Ssaidi@eecs.umich.edusystem.physmem.avgConsumedWrBW 204.47 # Average consumed write bandwidth in MB/s 1869312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1879348SAli.Saidi@ARM.comsystem.physmem.busUtil 3.24 # Data bus utilization in percentage 1889348SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 0.26 # Average read queue length over time 1899459Ssaidi@eecs.umich.edusystem.physmem.avgWrQLen 9.34 # Average write queue length over time 1909459Ssaidi@eecs.umich.edusystem.physmem.readRowHits 118922 # Number of row buffer hits during reads 1919459Ssaidi@eecs.umich.edusystem.physmem.writeRowHits 27176 # Number of row buffer hits during writes 1929348SAli.Saidi@ARM.comsystem.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads 1939459Ssaidi@eecs.umich.edusystem.physmem.writeRowHitRate 32.37 # Row buffer hit rate for writes 1949459Ssaidi@eecs.umich.edusystem.physmem.avgGap 123527.37 # Average gap between requests 1959481Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 16626972 # Number of BP lookups 1969481Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 12763144 # Number of conditional branches predicted 1979481Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 604576 # Number of conditional branches incorrect 1989481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBLookups 10780847 # Number of BTB lookups 1999481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 7773827 # Number of BTB hits 2009481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2019481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 72.107757 # BTB Hit Percentage 2029481Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 1825491 # Number of times the RAS was used to get a target. 2039481Snilay@cs.wisc.edusystem.cpu.branchPred.RASInCorrect 113784 # Number of incorrect RAS predictions. 2048317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 2058317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 2068317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 2078317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 2088317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2098317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2108317SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 2118317SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2128317SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2138317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2148317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 2158317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2168317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2178317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2188317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2198317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2208317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2218317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 2228317SN/Asystem.cpu.dtb.hits 0 # DTB hits 2238317SN/Asystem.cpu.dtb.misses 0 # DTB misses 2248317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2258317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 2268317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 2278317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2288317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2298317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2308317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2318317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 2328317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2338317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2348317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2358317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 2368317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2378317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2388317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2398317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2408317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2418317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2428317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 2438317SN/Asystem.cpu.itb.hits 0 # DTB hits 2448317SN/Asystem.cpu.itb.misses 0 # DTB misses 2458317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 2468317SN/Asystem.cpu.workload.num_syscalls 1946 # Number of system calls 2479459Ssaidi@eecs.umich.edusystem.cpu.numCycles 52550292 # number of cpu cycles simulated 2488317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2498317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2509459Ssaidi@eecs.umich.edusystem.cpu.fetch.icacheStallCycles 12554350 # Number of cycles fetch is stalled on an Icache miss 2519459Ssaidi@eecs.umich.edusystem.cpu.fetch.Insts 85230964 # Number of instructions fetch has processed 2529459Ssaidi@eecs.umich.edusystem.cpu.fetch.Branches 16626972 # Number of branches that fetch encountered 2539459Ssaidi@eecs.umich.edusystem.cpu.fetch.predictedBranches 9599318 # Number of branches that fetch has predicted taken 2549459Ssaidi@eecs.umich.edusystem.cpu.fetch.Cycles 21200413 # Number of cycles fetch has run and was not squashing or blocked 2559459Ssaidi@eecs.umich.edusystem.cpu.fetch.SquashCycles 2370934 # Number of cycles fetch has spent squashing 2569459Ssaidi@eecs.umich.edusystem.cpu.fetch.BlockedCycles 10497631 # Number of cycles fetch has spent blocked 2579449SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2589459Ssaidi@eecs.umich.edusystem.cpu.fetch.PendingTrapStallCycles 506 # Number of stall cycles due to pending traps 2599459Ssaidi@eecs.umich.edusystem.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR 2609459Ssaidi@eecs.umich.edusystem.cpu.fetch.CacheLines 11689041 # Number of cache lines fetched 2619459Ssaidi@eecs.umich.edusystem.cpu.fetch.IcacheSquashes 183016 # Number of outstanding Icache misses that were squashed 2629459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::samples 45992800 # Number of instructions fetched each cycle (Total) 2639459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::mean 2.594519 # Number of instructions fetched each cycle (Total) 2649459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::stdev 3.335814 # Number of instructions fetched each cycle (Total) 2658317SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2669459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::0 24812491 53.95% 53.95% # Number of instructions fetched each cycle (Total) 2679459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::1 2139973 4.65% 58.60% # Number of instructions fetched each cycle (Total) 2689459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::2 1966955 4.28% 62.88% # Number of instructions fetched each cycle (Total) 2699459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::3 2042614 4.44% 67.32% # Number of instructions fetched each cycle (Total) 2709459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::4 1467231 3.19% 70.51% # Number of instructions fetched each cycle (Total) 2719459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::5 1381601 3.00% 73.51% # Number of instructions fetched each cycle (Total) 2729459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::6 958651 2.08% 75.60% # Number of instructions fetched each cycle (Total) 2739459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::7 1187660 2.58% 78.18% # Number of instructions fetched each cycle (Total) 2749459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::8 10035624 21.82% 100.00% # Number of instructions fetched each cycle (Total) 2758317SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2768317SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2778317SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2789459Ssaidi@eecs.umich.edusystem.cpu.fetch.rateDist::total 45992800 # Number of instructions fetched each cycle (Total) 2799459Ssaidi@eecs.umich.edusystem.cpu.fetch.branchRate 0.316401 # Number of branch fetches per cycle 2809459Ssaidi@eecs.umich.edusystem.cpu.fetch.rate 1.621893 # Number of inst fetches per cycle 2819459Ssaidi@eecs.umich.edusystem.cpu.decode.IdleCycles 14631573 # Number of cycles decode is idle 2829459Ssaidi@eecs.umich.edusystem.cpu.decode.BlockedCycles 8854890 # Number of cycles decode is blocked 2839459Ssaidi@eecs.umich.edusystem.cpu.decode.RunCycles 19476912 # Number of cycles decode is running 2849459Ssaidi@eecs.umich.edusystem.cpu.decode.UnblockCycles 1392472 # Number of cycles decode is unblocking 2859459Ssaidi@eecs.umich.edusystem.cpu.decode.SquashCycles 1636953 # Number of cycles decode is squashing 2869459Ssaidi@eecs.umich.edusystem.cpu.decode.BranchResolved 3331046 # Number of times decode resolved a branch 2879459Ssaidi@eecs.umich.edusystem.cpu.decode.BranchMispred 104815 # Number of times decode detected a branch misprediction 2889459Ssaidi@eecs.umich.edusystem.cpu.decode.DecodedInsts 116877182 # Number of instructions handled by decode 2899459Ssaidi@eecs.umich.edusystem.cpu.decode.SquashedInsts 363170 # Number of squashed instructions handled by decode 2909459Ssaidi@eecs.umich.edusystem.cpu.rename.SquashCycles 1636953 # Number of cycles rename is squashing 2919459Ssaidi@eecs.umich.edusystem.cpu.rename.IdleCycles 16335988 # Number of cycles rename is idle 2929459Ssaidi@eecs.umich.edusystem.cpu.rename.BlockCycles 2535467 # Number of cycles rename is blocking 2939459Ssaidi@eecs.umich.edusystem.cpu.rename.serializeStallCycles 864548 # count of cycles rename stalled for serializing inst 2949459Ssaidi@eecs.umich.edusystem.cpu.rename.RunCycles 19115469 # Number of cycles rename is running 2959459Ssaidi@eecs.umich.edusystem.cpu.rename.UnblockCycles 5504375 # Number of cycles rename is unblocking 2969459Ssaidi@eecs.umich.edusystem.cpu.rename.RenamedInsts 114992065 # Number of instructions processed by rename 2979459Ssaidi@eecs.umich.edusystem.cpu.rename.ROBFullEvents 153 # Number of times rename has blocked due to ROB full 2989459Ssaidi@eecs.umich.edusystem.cpu.rename.IQFullEvents 17001 # Number of times rename has blocked due to IQ full 2999459Ssaidi@eecs.umich.edusystem.cpu.rename.LSQFullEvents 4650627 # Number of times rename has blocked due to LSQ full 3009459Ssaidi@eecs.umich.edusystem.cpu.rename.FullRegisterEvents 317 # Number of times there has been no free registers 3019459Ssaidi@eecs.umich.edusystem.cpu.rename.RenamedOperands 115303250 # Number of destination operands rename has renamed 3029459Ssaidi@eecs.umich.edusystem.cpu.rename.RenameLookups 529787373 # Number of register rename lookups that rename has made 3039459Ssaidi@eecs.umich.edusystem.cpu.rename.int_rename_lookups 529782097 # Number of integer rename lookups 3049459Ssaidi@eecs.umich.edusystem.cpu.rename.fp_rename_lookups 5276 # Number of floating rename lookups 3059459Ssaidi@eecs.umich.edusystem.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed 3069459Ssaidi@eecs.umich.edusystem.cpu.rename.UndoneMaps 16170578 # Number of HB maps that are undone due to squashing 3079459Ssaidi@eecs.umich.edusystem.cpu.rename.serializingInsts 20502 # count of serializing insts renamed 3089459Ssaidi@eecs.umich.edusystem.cpu.rename.tempSerializingInsts 20496 # count of temporary serializing insts renamed 3099459Ssaidi@eecs.umich.edusystem.cpu.rename.skidInsts 13002691 # count of insts added to the skid buffer 3109459Ssaidi@eecs.umich.edusystem.cpu.memDep0.insertedLoads 29626313 # Number of loads inserted to the mem dependence unit. 3119459Ssaidi@eecs.umich.edusystem.cpu.memDep0.insertedStores 22450124 # Number of stores inserted to the mem dependence unit. 3129459Ssaidi@eecs.umich.edusystem.cpu.memDep0.conflictingLoads 3876856 # Number of conflicting loads. 3139459Ssaidi@eecs.umich.edusystem.cpu.memDep0.conflictingStores 4338192 # Number of conflicting stores. 3149459Ssaidi@eecs.umich.edusystem.cpu.iq.iqInstsAdded 111565223 # Number of instructions added to the IQ (excludes non-spec) 3159459Ssaidi@eecs.umich.edusystem.cpu.iq.iqNonSpecInstsAdded 36031 # Number of non-speculative instructions added to the IQ 3169459Ssaidi@eecs.umich.edusystem.cpu.iq.iqInstsIssued 107269202 # Number of instructions issued 3179459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedInstsIssued 275818 # Number of squashed instructions issued 3189459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedInstsExamined 10829565 # Number of squashed instructions iterated over during squash; mainly for profiling 3199459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedOperandsExamined 25919062 # Number of squashed operands that are examined and possibly removed from graph 3209459Ssaidi@eecs.umich.edusystem.cpu.iq.iqSquashedNonSpecRemoved 2245 # Number of squashed non-spec instructions that were removed 3219459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::samples 45992800 # Number of insts issued each cycle 3229459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::mean 2.332304 # Number of insts issued each cycle 3239459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::stdev 1.990217 # Number of insts issued each cycle 3248317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3259459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::0 10779099 23.44% 23.44% # Number of insts issued each cycle 3269459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::1 8049451 17.50% 40.94% # Number of insts issued each cycle 3279459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::2 7422892 16.14% 57.08% # Number of insts issued each cycle 3289459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::3 7126081 15.49% 72.57% # Number of insts issued each cycle 3299459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::4 5395767 11.73% 84.30% # Number of insts issued each cycle 3309459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::5 3928809 8.54% 92.85% # Number of insts issued each cycle 3319459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::6 1841047 4.00% 96.85% # Number of insts issued each cycle 3329459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::7 874903 1.90% 98.75% # Number of insts issued each cycle 3339459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::8 574751 1.25% 100.00% # Number of insts issued each cycle 3348317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3358317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3368317SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3379459Ssaidi@eecs.umich.edusystem.cpu.iq.issued_per_cycle::total 45992800 # Number of insts issued each cycle 3388317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3399459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::IntAlu 114108 4.61% 4.61% # attempts to use FU when none available 3409459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available 3419459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available 3429459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::FloatAdd 1 0.00% 4.61% # attempts to use FU when none available 3439459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available 3449459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available 3459459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available 3469459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available 3479459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available 3489459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available 3499459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available 3509459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available 3519459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available 3529459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available 3539459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available 3549459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available 3559459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available 3569459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available 3579459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available 3589459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available 3599459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available 3609459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available 3619459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available 3629459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available 3639459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available 3649459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available 3659459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available 3669459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available 3679459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available 3689459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::MemRead 1356583 54.78% 59.39% # attempts to use FU when none available 3699459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_full::MemWrite 1005840 40.61% 100.00% # attempts to use FU when none available 3708317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3718317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3728317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 3739459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::IntAlu 56641700 52.80% 52.80% # Type of FU issued 3749459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::IntMult 91676 0.09% 52.89% # Type of FU issued 3759459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued 3769459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatAdd 165 0.00% 52.89% # Type of FU issued 3779459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued 3789459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued 3799459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued 3809459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued 3819459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued 3829459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued 3839459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued 3849459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued 3859459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.89% # Type of FU issued 3869459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.89% # Type of FU issued 3879459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.89% # Type of FU issued 3889459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.89% # Type of FU issued 3899459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.89% # Type of FU issued 3909459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.89% # Type of FU issued 3919459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.89% # Type of FU issued 3929459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.89% # Type of FU issued 3939459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.89% # Type of FU issued 3949459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued 3959459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued 3969459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued 3979459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued 3989459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued 3999459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued 4009459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued 4019459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued 4029459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::MemRead 28901726 26.94% 79.83% # Type of FU issued 4039459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::MemWrite 21633928 20.17% 100.00% # Type of FU issued 4048317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4058317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4069459Ssaidi@eecs.umich.edusystem.cpu.iq.FU_type_0::total 107269202 # Type of FU issued 4079459Ssaidi@eecs.umich.edusystem.cpu.iq.rate 2.041267 # Inst issue rate 4089459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_busy_cnt 2476532 # FU busy when requested 4099459Ssaidi@eecs.umich.edusystem.cpu.iq.fu_busy_rate 0.023087 # FU busy rate (busy events/executed inst) 4109459Ssaidi@eecs.umich.edusystem.cpu.iq.int_inst_queue_reads 263283068 # Number of integer instruction queue reads 4119459Ssaidi@eecs.umich.edusystem.cpu.iq.int_inst_queue_writes 122458972 # Number of integer instruction queue writes 4129459Ssaidi@eecs.umich.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 105581252 # Number of integer instruction queue wakeup accesses 4139459Ssaidi@eecs.umich.edusystem.cpu.iq.fp_inst_queue_reads 486 # Number of floating instruction queue reads 4149459Ssaidi@eecs.umich.edusystem.cpu.iq.fp_inst_queue_writes 768 # Number of floating instruction queue writes 4159348SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses 4169459Ssaidi@eecs.umich.edusystem.cpu.iq.int_alu_accesses 109745491 # Number of integer alu accesses 4179459Ssaidi@eecs.umich.edusystem.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses 4189459Ssaidi@eecs.umich.edusystem.cpu.iew.lsq.thread0.forwLoads 2188417 # Number of loads that had data forwarded from stores 4198317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4209459Ssaidi@eecs.umich.edusystem.cpu.iew.lsq.thread0.squashedLoads 2319205 # Number of loads squashed 4219459Ssaidi@eecs.umich.edusystem.cpu.iew.lsq.thread0.ignoredResponses 6776 # Number of memory responses ignored because the instruction is squashed 4229459Ssaidi@eecs.umich.edusystem.cpu.iew.lsq.thread0.memOrderViolation 29966 # Number of memory ordering violations 4239459Ssaidi@eecs.umich.edusystem.cpu.iew.lsq.thread0.squashedStores 1894386 # Number of stores squashed 4248317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4258317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4269459Ssaidi@eecs.umich.edusystem.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled 4279459Ssaidi@eecs.umich.edusystem.cpu.iew.lsq.thread0.cacheBlocked 503 # Number of times an access to memory failed due to the cache being blocked 4288317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4299459Ssaidi@eecs.umich.edusystem.cpu.iew.iewSquashCycles 1636953 # Number of cycles IEW is squashing 4309459Ssaidi@eecs.umich.edusystem.cpu.iew.iewBlockCycles 1044060 # Number of cycles IEW is blocking 4319459Ssaidi@eecs.umich.edusystem.cpu.iew.iewUnblockCycles 45930 # Number of cycles IEW is unblocking 4329459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispatchedInsts 111611011 # Number of instructions dispatched to IQ 4339459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispSquashedInsts 291580 # Number of squashed instructions skipped by dispatch 4349459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispLoadInsts 29626313 # Number of dispatched load instructions 4359459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispStoreInsts 22450124 # Number of dispatched store instructions 4369459Ssaidi@eecs.umich.edusystem.cpu.iew.iewDispNonSpecInsts 20111 # Number of dispatched non-speculative instructions 4379459Ssaidi@eecs.umich.edusystem.cpu.iew.iewIQFullEvents 6644 # Number of times the IQ has become full, causing a stall 4389459Ssaidi@eecs.umich.edusystem.cpu.iew.iewLSQFullEvents 5462 # Number of times the LSQ has become full, causing a stall 4399459Ssaidi@eecs.umich.edusystem.cpu.iew.memOrderViolationEvents 29966 # Number of memory order violations 4409459Ssaidi@eecs.umich.edusystem.cpu.iew.predictedTakenIncorrect 393316 # Number of branches that were predicted taken incorrectly 4419459Ssaidi@eecs.umich.edusystem.cpu.iew.predictedNotTakenIncorrect 181236 # Number of branches that were predicted not taken incorrectly 4429459Ssaidi@eecs.umich.edusystem.cpu.iew.branchMispredicts 574552 # Number of branch mispredicts detected at execute 4439459Ssaidi@eecs.umich.edusystem.cpu.iew.iewExecutedInsts 106238160 # Number of executed instructions 4449459Ssaidi@eecs.umich.edusystem.cpu.iew.iewExecLoadInsts 28602099 # Number of load instructions executed 4459459Ssaidi@eecs.umich.edusystem.cpu.iew.iewExecSquashedInsts 1031042 # Number of squashed instructions skipped in execute 4468317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4479459Ssaidi@eecs.umich.edusystem.cpu.iew.exec_nop 9757 # number of nop insts executed 4489459Ssaidi@eecs.umich.edusystem.cpu.iew.exec_refs 49948126 # number of memory reference insts executed 4499459Ssaidi@eecs.umich.edusystem.cpu.iew.exec_branches 14604066 # Number of branches executed 4509459Ssaidi@eecs.umich.edusystem.cpu.iew.exec_stores 21346027 # Number of stores executed 4519459Ssaidi@eecs.umich.edusystem.cpu.iew.exec_rate 2.021647 # Inst execution rate 4529459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_sent 105801461 # cumulative count of insts sent to commit 4539459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_count 105581404 # cumulative count of insts written-back 4549459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_producers 53258894 # num instructions producing a value 4559459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_consumers 103486689 # num instructions consuming a value 4568317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4579459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_rate 2.009150 # insts written-back per cycle 4589459Ssaidi@eecs.umich.edusystem.cpu.iew.wb_fanout 0.514645 # average fanout of values written-back 4598317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4609459Ssaidi@eecs.umich.edusystem.cpu.commit.commitSquashedInsts 10979497 # The number of squashed insts skipped by commit 4619459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 4629459Ssaidi@eecs.umich.edusystem.cpu.commit.branchMispredicts 501718 # The number of times a branch was mispredicted 4639459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::samples 44355847 # Number of insts commited each cycle 4649459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::mean 2.268752 # Number of insts commited each cycle 4659459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::stdev 2.766108 # Number of insts commited each cycle 4668241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4679459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::0 15312059 34.52% 34.52% # Number of insts commited each cycle 4689459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::1 11621987 26.20% 60.72% # Number of insts commited each cycle 4699459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::2 3450685 7.78% 68.50% # Number of insts commited each cycle 4709459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::3 2867250 6.46% 74.97% # Number of insts commited each cycle 4719459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::4 1878784 4.24% 79.20% # Number of insts commited each cycle 4729459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::5 1958737 4.42% 83.62% # Number of insts commited each cycle 4739459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::6 685559 1.55% 85.16% # Number of insts commited each cycle 4749459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::7 561142 1.27% 86.43% # Number of insts commited each cycle 4759459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::8 6019644 13.57% 100.00% # Number of insts commited each cycle 4768241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4778241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4788241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4799459Ssaidi@eecs.umich.edusystem.cpu.commit.committed_per_cycle::total 44355847 # Number of insts commited each cycle 4809459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 70913181 # Number of instructions committed 4819459Ssaidi@eecs.umich.edusystem.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed 4828317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4839459Ssaidi@eecs.umich.edusystem.cpu.commit.refs 47862846 # Number of memory references committed 4849459Ssaidi@eecs.umich.edusystem.cpu.commit.loads 27307108 # Number of loads committed 4858317SN/Asystem.cpu.commit.membars 15920 # Number of memory barriers committed 4869459Ssaidi@eecs.umich.edusystem.cpu.commit.branches 13741505 # Number of branches committed 4878241SN/Asystem.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 4889459Ssaidi@eecs.umich.edusystem.cpu.commit.int_insts 91472779 # Number of committed integer instructions. 4898241SN/Asystem.cpu.commit.function_calls 1679850 # Number of function calls committed. 4909459Ssaidi@eecs.umich.edusystem.cpu.commit.bw_lim_events 6019644 # number cycles where commit BW limit reached 4918317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4929459Ssaidi@eecs.umich.edusystem.cpu.rob.rob_reads 149922829 # The number of ROB reads 4939459Ssaidi@eecs.umich.edusystem.cpu.rob.rob_writes 224870236 # The number of ROB writes 4949459Ssaidi@eecs.umich.edusystem.cpu.timesIdled 74082 # Number of times that the entire CPU went into an idle state and unscheduled itself 4959459Ssaidi@eecs.umich.edusystem.cpu.idleCycles 6557492 # Total number of cycles that the CPU has spent unscheduled due to idling 4969459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 70907629 # Number of Instructions Simulated 4979459Ssaidi@eecs.umich.edusystem.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated 4989459Ssaidi@eecs.umich.edusystem.cpu.committedInsts_total 70907629 # Number of Instructions Simulated 4999459Ssaidi@eecs.umich.edusystem.cpu.cpi 0.741109 # CPI: Cycles Per Instruction 5009459Ssaidi@eecs.umich.edusystem.cpu.cpi_total 0.741109 # CPI: Total CPI of All Threads 5019459Ssaidi@eecs.umich.edusystem.cpu.ipc 1.349329 # IPC: Instructions Per Cycle 5029459Ssaidi@eecs.umich.edusystem.cpu.ipc_total 1.349329 # IPC: Total IPC of All Threads 5039459Ssaidi@eecs.umich.edusystem.cpu.int_regfile_reads 511669135 # number of integer regfile reads 5049459Ssaidi@eecs.umich.edusystem.cpu.int_regfile_writes 103349973 # number of integer regfile writes 5059459Ssaidi@eecs.umich.edusystem.cpu.fp_regfile_reads 690 # number of floating regfile reads 5069459Ssaidi@eecs.umich.edusystem.cpu.fp_regfile_writes 602 # number of floating regfile writes 5079459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_reads 49186281 # number of misc regfile reads 5089459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 31840 # number of misc regfile writes 5099459Ssaidi@eecs.umich.edusystem.cpu.icache.replacements 29504 # number of replacements 5109459Ssaidi@eecs.umich.edusystem.cpu.icache.tagsinuse 1815.541660 # Cycle average of tags in use 5119459Ssaidi@eecs.umich.edusystem.cpu.icache.total_refs 11653533 # Total number of references to valid blocks. 5129459Ssaidi@eecs.umich.edusystem.cpu.icache.sampled_refs 31535 # Sample count of references to valid blocks. 5139459Ssaidi@eecs.umich.edusystem.cpu.icache.avg_refs 369.542825 # Average number of references to valid blocks. 5148317SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5159459Ssaidi@eecs.umich.edusystem.cpu.icache.occ_blocks::cpu.inst 1815.541660 # Average occupied blocks per requestor 5169459Ssaidi@eecs.umich.edusystem.cpu.icache.occ_percent::cpu.inst 0.886495 # Average percentage of cache occupancy 5179459Ssaidi@eecs.umich.edusystem.cpu.icache.occ_percent::total 0.886495 # Average percentage of cache occupancy 5189459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_hits::cpu.inst 11653539 # number of ReadReq hits 5199459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_hits::total 11653539 # number of ReadReq hits 5209459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_hits::cpu.inst 11653539 # number of demand (read+write) hits 5219459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_hits::total 11653539 # number of demand (read+write) hits 5229459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_hits::cpu.inst 11653539 # number of overall hits 5239459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_hits::total 11653539 # number of overall hits 5249459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_misses::cpu.inst 35502 # number of ReadReq misses 5259459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_misses::total 35502 # number of ReadReq misses 5269459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_misses::cpu.inst 35502 # number of demand (read+write) misses 5279459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_misses::total 35502 # number of demand (read+write) misses 5289459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_misses::cpu.inst 35502 # number of overall misses 5299459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_misses::total 35502 # number of overall misses 5309459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_latency::cpu.inst 704211999 # number of ReadReq miss cycles 5319459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_latency::total 704211999 # number of ReadReq miss cycles 5329459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_latency::cpu.inst 704211999 # number of demand (read+write) miss cycles 5339459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_latency::total 704211999 # number of demand (read+write) miss cycles 5349459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_latency::cpu.inst 704211999 # number of overall miss cycles 5359459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_latency::total 704211999 # number of overall miss cycles 5369459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 11689041 # number of ReadReq accesses(hits+misses) 5379459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_accesses::total 11689041 # number of ReadReq accesses(hits+misses) 5389459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_accesses::cpu.inst 11689041 # number of demand (read+write) accesses 5399459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_accesses::total 11689041 # number of demand (read+write) accesses 5409459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_accesses::cpu.inst 11689041 # number of overall (read+write) accesses 5419459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_accesses::total 11689041 # number of overall (read+write) accesses 5429459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003037 # miss rate for ReadReq accesses 5439459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.003037 # miss rate for ReadReq accesses 5449459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.003037 # miss rate for demand accesses 5459459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.003037 # miss rate for demand accesses 5469459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.003037 # miss rate for overall accesses 5479459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total 0.003037 # miss rate for overall accesses 5489459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19835.840206 # average ReadReq miss latency 5499459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 19835.840206 # average ReadReq miss latency 5509459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency 5519459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::total 19835.840206 # average overall miss latency 5529459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::cpu.inst 19835.840206 # average overall miss latency 5539459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::total 19835.840206 # average overall miss latency 5549459Ssaidi@eecs.umich.edusystem.cpu.icache.blocked_cycles::no_mshrs 2125 # number of cycles access was blocked 5558317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5569348SAli.Saidi@ARM.comsystem.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked 5578317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5589459Ssaidi@eecs.umich.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs 96.590909 # average number of cycles each access was blocked 5598983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5608317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5618317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5629459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 3638 # number of ReadReq MSHR hits 5639459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_hits::total 3638 # number of ReadReq MSHR hits 5649459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_hits::cpu.inst 3638 # number of demand (read+write) MSHR hits 5659459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_hits::total 3638 # number of demand (read+write) MSHR hits 5669459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_hits::cpu.inst 3638 # number of overall MSHR hits 5679459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_hits::total 3638 # number of overall MSHR hits 5689459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 31864 # number of ReadReq MSHR misses 5699459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_misses::total 31864 # number of ReadReq MSHR misses 5709459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 31864 # number of demand (read+write) MSHR misses 5719459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_misses::total 31864 # number of demand (read+write) MSHR misses 5729459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 31864 # number of overall MSHR misses 5739459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_misses::total 31864 # number of overall MSHR misses 5749459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 575585499 # number of ReadReq MSHR miss cycles 5759459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_latency::total 575585499 # number of ReadReq MSHR miss cycles 5769459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 575585499 # number of demand (read+write) MSHR miss cycles 5779459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_latency::total 575585499 # number of demand (read+write) MSHR miss cycles 5789459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 575585499 # number of overall MSHR miss cycles 5799459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_latency::total 575585499 # number of overall MSHR miss cycles 5809459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for ReadReq accesses 5819459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.002726 # mshr miss rate for ReadReq accesses 5829459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for demand accesses 5839459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.002726 # mshr miss rate for demand accesses 5849459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002726 # mshr miss rate for overall accesses 5859459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.002726 # mshr miss rate for overall accesses 5869459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18063.818071 # average ReadReq mshr miss latency 5879459Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18063.818071 # average ReadReq mshr miss latency 5889459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18063.818071 # average overall mshr miss latency 5899459Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 18063.818071 # average overall mshr miss latency 5909459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18063.818071 # average overall mshr miss latency 5919459Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 18063.818071 # average overall mshr miss latency 5928317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5939459Ssaidi@eecs.umich.edusystem.cpu.l2cache.replacements 95629 # number of replacements 5949459Ssaidi@eecs.umich.edusystem.cpu.l2cache.tagsinuse 30144.051156 # Cycle average of tags in use 5959459Ssaidi@eecs.umich.edusystem.cpu.l2cache.total_refs 89024 # Total number of references to valid blocks. 5969459Ssaidi@eecs.umich.edusystem.cpu.l2cache.sampled_refs 126742 # Sample count of references to valid blocks. 5979459Ssaidi@eecs.umich.edusystem.cpu.l2cache.avg_refs 0.702403 # Average number of references to valid blocks. 5988317SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5999459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_blocks::writebacks 26895.492569 # Average occupied blocks per requestor 6009459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_blocks::cpu.inst 1376.193192 # Average occupied blocks per requestor 6019459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_blocks::cpu.data 1872.365396 # Average occupied blocks per requestor 6029459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_percent::writebacks 0.820785 # Average percentage of cache occupancy 6039459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_percent::cpu.inst 0.041998 # Average percentage of cache occupancy 6049459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_percent::cpu.data 0.057140 # Average percentage of cache occupancy 6059459Ssaidi@eecs.umich.edusystem.cpu.l2cache.occ_percent::total 0.919923 # Average percentage of cache occupancy 6069459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_hits::cpu.inst 26680 # number of ReadReq hits 6079459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_hits::cpu.data 33529 # number of ReadReq hits 6089459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_hits::total 60209 # number of ReadReq hits 6099459Ssaidi@eecs.umich.edusystem.cpu.l2cache.Writeback_hits::writebacks 129085 # number of Writeback hits 6109459Ssaidi@eecs.umich.edusystem.cpu.l2cache.Writeback_hits::total 129085 # number of Writeback hits 6119459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_hits::cpu.data 17 # number of UpgradeReq hits 6129459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits 6139459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_hits::cpu.data 4762 # number of ReadExReq hits 6149459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_hits::total 4762 # number of ReadExReq hits 6159459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_hits::cpu.inst 26680 # number of demand (read+write) hits 6169459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_hits::cpu.data 38291 # number of demand (read+write) hits 6179459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_hits::total 64971 # number of demand (read+write) hits 6189459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_hits::cpu.inst 26680 # number of overall hits 6199459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_hits::cpu.data 38291 # number of overall hits 6209459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_hits::total 64971 # number of overall hits 6219459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_misses::cpu.inst 4675 # number of ReadReq misses 6229459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_misses::cpu.data 21899 # number of ReadReq misses 6239459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_misses::total 26574 # number of ReadReq misses 6249459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_misses::cpu.data 322 # number of UpgradeReq misses 6259459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_misses::total 322 # number of UpgradeReq misses 6269459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_misses::cpu.data 102258 # number of ReadExReq misses 6279459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_misses::total 102258 # number of ReadExReq misses 6289459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_misses::cpu.inst 4675 # number of demand (read+write) misses 6299459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_misses::cpu.data 124157 # number of demand (read+write) misses 6309459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_misses::total 128832 # number of demand (read+write) misses 6319459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_misses::cpu.inst 4675 # number of overall misses 6329459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_misses::cpu.data 124157 # number of overall misses 6339459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_misses::total 128832 # number of overall misses 6349459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 276010000 # number of ReadReq miss cycles 6359459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 1652820000 # number of ReadReq miss cycles 6369459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_latency::total 1928830000 # number of ReadReq miss cycles 6379459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22500 # number of UpgradeReq miss cycles 6389459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_miss_latency::total 22500 # number of UpgradeReq miss cycles 6399459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8120181000 # number of ReadExReq miss cycles 6409459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_latency::total 8120181000 # number of ReadExReq miss cycles 6419459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_latency::cpu.inst 276010000 # number of demand (read+write) miss cycles 6429459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_latency::cpu.data 9773001000 # number of demand (read+write) miss cycles 6439459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_latency::total 10049011000 # number of demand (read+write) miss cycles 6449459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_latency::cpu.inst 276010000 # number of overall miss cycles 6459459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_latency::cpu.data 9773001000 # number of overall miss cycles 6469459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_latency::total 10049011000 # number of overall miss cycles 6479459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_accesses::cpu.inst 31355 # number of ReadReq accesses(hits+misses) 6489459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_accesses::cpu.data 55428 # number of ReadReq accesses(hits+misses) 6499459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_accesses::total 86783 # number of ReadReq accesses(hits+misses) 6509459Ssaidi@eecs.umich.edusystem.cpu.l2cache.Writeback_accesses::writebacks 129085 # number of Writeback accesses(hits+misses) 6519459Ssaidi@eecs.umich.edusystem.cpu.l2cache.Writeback_accesses::total 129085 # number of Writeback accesses(hits+misses) 6529459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 339 # number of UpgradeReq accesses(hits+misses) 6539459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_accesses::total 339 # number of UpgradeReq accesses(hits+misses) 6549459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 107020 # number of ReadExReq accesses(hits+misses) 6559459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_accesses::total 107020 # number of ReadExReq accesses(hits+misses) 6569459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_accesses::cpu.inst 31355 # number of demand (read+write) accesses 6579459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_accesses::cpu.data 162448 # number of demand (read+write) accesses 6589459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_accesses::total 193803 # number of demand (read+write) accesses 6599459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_accesses::cpu.inst 31355 # number of overall (read+write) accesses 6609459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_accesses::cpu.data 162448 # number of overall (read+write) accesses 6619459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_accesses::total 193803 # number of overall (read+write) accesses 6629459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.149099 # miss rate for ReadReq accesses 6639459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395089 # miss rate for ReadReq accesses 6649459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.306212 # miss rate for ReadReq accesses 6659459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.949853 # miss rate for UpgradeReq accesses 6669459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.949853 # miss rate for UpgradeReq accesses 6679459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955504 # miss rate for ReadExReq accesses 6689459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 0.955504 # miss rate for ReadExReq accesses 6699459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.149099 # miss rate for demand accesses 6709459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::cpu.data 0.764288 # miss rate for demand accesses 6719459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.664758 # miss rate for demand accesses 6729459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.149099 # miss rate for overall accesses 6739459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::cpu.data 0.764288 # miss rate for overall accesses 6749459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.664758 # miss rate for overall accesses 6759459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59039.572193 # average ReadReq miss latency 6769459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75474.679209 # average ReadReq miss latency 6779459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 72583.352149 # average ReadReq miss latency 6789459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 69.875776 # average UpgradeReq miss latency 6799459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 69.875776 # average UpgradeReq miss latency 6809459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79408.760195 # average ReadExReq miss latency 6819459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 79408.760195 # average ReadExReq miss latency 6829459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59039.572193 # average overall miss latency 6839459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 78714.861023 # average overall miss latency 6849459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 78000.892635 # average overall miss latency 6859459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59039.572193 # average overall miss latency 6869459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 78714.861023 # average overall miss latency 6879459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 78000.892635 # average overall miss latency 6888317SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6898317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6908317SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6918317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6928983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6938983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6948317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6957860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6969459Ssaidi@eecs.umich.edusystem.cpu.l2cache.writebacks::writebacks 83947 # number of writebacks 6979459Ssaidi@eecs.umich.edusystem.cpu.l2cache.writebacks::total 83947 # number of writebacks 6989459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 17 # number of ReadReq MSHR hits 6999459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits 7009459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits 7019459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_hits::cpu.inst 17 # number of demand (read+write) MSHR hits 7029459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits 7039459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 7049459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_hits::cpu.inst 17 # number of overall MSHR hits 7059459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits 7069459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits 7079459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4658 # number of ReadReq MSHR misses 7089459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21844 # number of ReadReq MSHR misses 7099459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_misses::total 26502 # number of ReadReq MSHR misses 7109459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 322 # number of UpgradeReq MSHR misses 7119459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_mshr_misses::total 322 # number of UpgradeReq MSHR misses 7129459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102258 # number of ReadExReq MSHR misses 7139459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_misses::total 102258 # number of ReadExReq MSHR misses 7149459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_misses::cpu.inst 4658 # number of demand (read+write) MSHR misses 7159459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_misses::cpu.data 124102 # number of demand (read+write) MSHR misses 7169459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_misses::total 128760 # number of demand (read+write) MSHR misses 7179459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_misses::cpu.inst 4658 # number of overall MSHR misses 7189459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_misses::cpu.data 124102 # number of overall MSHR misses 7199459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_misses::total 128760 # number of overall MSHR misses 7209459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 216322911 # number of ReadReq MSHR miss cycles 7219459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1377962821 # number of ReadReq MSHR miss cycles 7229459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 1594285732 # number of ReadReq MSHR miss cycles 7239459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3234820 # number of UpgradeReq MSHR miss cycles 7249459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3234820 # number of UpgradeReq MSHR miss cycles 7259459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6849492072 # number of ReadExReq MSHR miss cycles 7269459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6849492072 # number of ReadExReq MSHR miss cycles 7279459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 216322911 # number of demand (read+write) MSHR miss cycles 7289459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8227454893 # number of demand (read+write) MSHR miss cycles 7299459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_latency::total 8443777804 # number of demand (read+write) MSHR miss cycles 7309459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 216322911 # number of overall MSHR miss cycles 7319459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8227454893 # number of overall MSHR miss cycles 7329459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_latency::total 8443777804 # number of overall MSHR miss cycles 7339459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for ReadReq accesses 7349459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394097 # mshr miss rate for ReadReq accesses 7359459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.305382 # mshr miss rate for ReadReq accesses 7369459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.949853 # mshr miss rate for UpgradeReq accesses 7379459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.949853 # mshr miss rate for UpgradeReq accesses 7389459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955504 # mshr miss rate for ReadExReq accesses 7399459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955504 # mshr miss rate for ReadExReq accesses 7409459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for demand accesses 7419459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.763949 # mshr miss rate for demand accesses 7429459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.664386 # mshr miss rate for demand accesses 7439459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.148557 # mshr miss rate for overall accesses 7449459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.763949 # mshr miss rate for overall accesses 7459459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.664386 # mshr miss rate for overall accesses 7469459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 46441.157364 # average ReadReq mshr miss latency 7479459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63081.982283 # average ReadReq mshr miss latency 7489459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60157.185571 # average ReadReq mshr miss latency 7499459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10046.024845 # average UpgradeReq mshr miss latency 7509459Ssaidi@eecs.umich.edusystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10046.024845 # average UpgradeReq mshr miss latency 7519459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66982.456844 # average ReadExReq mshr miss latency 7529459Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66982.456844 # average ReadExReq mshr miss latency 7539459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency 7549459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency 7559459Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency 7569459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 46441.157364 # average overall mshr miss latency 7579459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66295.908954 # average overall mshr miss latency 7589459Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 65577.646816 # average overall mshr miss latency 7597860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7609459Ssaidi@eecs.umich.edusystem.cpu.dcache.replacements 158352 # number of replacements 7619459Ssaidi@eecs.umich.edusystem.cpu.dcache.tagsinuse 4073.285602 # Cycle average of tags in use 7629459Ssaidi@eecs.umich.edusystem.cpu.dcache.total_refs 44355767 # Total number of references to valid blocks. 7639459Ssaidi@eecs.umich.edusystem.cpu.dcache.sampled_refs 162448 # Sample count of references to valid blocks. 7649459Ssaidi@eecs.umich.edusystem.cpu.dcache.avg_refs 273.045941 # Average number of references to valid blocks. 7659459Ssaidi@eecs.umich.edusystem.cpu.dcache.warmup_cycle 278219000 # Cycle when the warmup percentage was hit. 7669459Ssaidi@eecs.umich.edusystem.cpu.dcache.occ_blocks::cpu.data 4073.285602 # Average occupied blocks per requestor 7679459Ssaidi@eecs.umich.edusystem.cpu.dcache.occ_percent::cpu.data 0.994454 # Average percentage of cache occupancy 7689459Ssaidi@eecs.umich.edusystem.cpu.dcache.occ_percent::total 0.994454 # Average percentage of cache occupancy 7699459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_hits::cpu.data 26058145 # number of ReadReq hits 7709459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_hits::total 26058145 # number of ReadReq hits 7719459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_hits::cpu.data 18265070 # number of WriteReq hits 7729459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_hits::total 18265070 # number of WriteReq hits 7739459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_hits::cpu.data 15998 # number of LoadLockedReq hits 7749459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_hits::total 15998 # number of LoadLockedReq hits 7759459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 7769459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 7779459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_hits::cpu.data 44323215 # number of demand (read+write) hits 7789459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_hits::total 44323215 # number of demand (read+write) hits 7799459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_hits::cpu.data 44323215 # number of overall hits 7809459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_hits::total 44323215 # number of overall hits 7819459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_misses::cpu.data 124984 # number of ReadReq misses 7829459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_misses::total 124984 # number of ReadReq misses 7839459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_misses::cpu.data 1584831 # number of WriteReq misses 7849459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_misses::total 1584831 # number of WriteReq misses 7859459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses 7869459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses 7879459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_misses::cpu.data 1709815 # number of demand (read+write) misses 7889459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_misses::total 1709815 # number of demand (read+write) misses 7899459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_misses::cpu.data 1709815 # number of overall misses 7909459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_misses::total 1709815 # number of overall misses 7919459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 4634379500 # number of ReadReq miss cycles 7929459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_miss_latency::total 4634379500 # number of ReadReq miss cycles 7939459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 120528782979 # number of WriteReq miss cycles 7949459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_latency::total 120528782979 # number of WriteReq miss cycles 7959459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 848000 # number of LoadLockedReq miss cycles 7969459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_miss_latency::total 848000 # number of LoadLockedReq miss cycles 7979459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_miss_latency::cpu.data 125163162479 # number of demand (read+write) miss cycles 7989459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_miss_latency::total 125163162479 # number of demand (read+write) miss cycles 7999459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_miss_latency::cpu.data 125163162479 # number of overall miss cycles 8009459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_miss_latency::total 125163162479 # number of overall miss cycles 8019459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 26183129 # number of ReadReq accesses(hits+misses) 8029459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_accesses::total 26183129 # number of ReadReq accesses(hits+misses) 8039449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 8049449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 8059459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 16039 # number of LoadLockedReq accesses(hits+misses) 8069459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_accesses::total 16039 # number of LoadLockedReq accesses(hits+misses) 8079459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 8089459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 8099459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_accesses::cpu.data 46033030 # number of demand (read+write) accesses 8109459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_accesses::total 46033030 # number of demand (read+write) accesses 8119459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_accesses::cpu.data 46033030 # number of overall (read+write) accesses 8129459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_accesses::total 46033030 # number of overall (read+write) accesses 8139459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004773 # miss rate for ReadReq accesses 8149459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.004773 # miss rate for ReadReq accesses 8159459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079841 # miss rate for WriteReq accesses 8169459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.079841 # miss rate for WriteReq accesses 8179459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002556 # miss rate for LoadLockedReq accesses 8189459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.002556 # miss rate for LoadLockedReq accesses 8199459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.037143 # miss rate for demand accesses 8209459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_miss_rate::total 0.037143 # miss rate for demand accesses 8219459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.037143 # miss rate for overall accesses 8229459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_miss_rate::total 0.037143 # miss rate for overall accesses 8239459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37079.782212 # average ReadReq miss latency 8249459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 37079.782212 # average ReadReq miss latency 8259459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76051.505163 # average WriteReq miss latency 8269459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 76051.505163 # average WriteReq miss latency 8279459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20682.926829 # average LoadLockedReq miss latency 8289459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20682.926829 # average LoadLockedReq miss latency 8299459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency 8309459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_miss_latency::total 73202.751455 # average overall miss latency 8319459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 73202.751455 # average overall miss latency 8329459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_miss_latency::total 73202.751455 # average overall miss latency 8339459Ssaidi@eecs.umich.edusystem.cpu.dcache.blocked_cycles::no_mshrs 3167 # number of cycles access was blocked 8349459Ssaidi@eecs.umich.edusystem.cpu.dcache.blocked_cycles::no_targets 649 # number of cycles access was blocked 8359459Ssaidi@eecs.umich.edusystem.cpu.dcache.blocked::no_mshrs 139 # number of cycles access was blocked 8369449SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked 8379459Ssaidi@eecs.umich.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 22.784173 # average number of cycles each access was blocked 8389459Ssaidi@eecs.umich.edusystem.cpu.dcache.avg_blocked_cycles::no_targets 43.266667 # average number of cycles each access was blocked 8399449SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8409449SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8419459Ssaidi@eecs.umich.edusystem.cpu.dcache.writebacks::writebacks 129085 # number of writebacks 8429459Ssaidi@eecs.umich.edusystem.cpu.dcache.writebacks::total 129085 # number of writebacks 8439459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 69523 # number of ReadReq MSHR hits 8449459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_hits::total 69523 # number of ReadReq MSHR hits 8459459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477505 # number of WriteReq MSHR hits 8469459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_hits::total 1477505 # number of WriteReq MSHR hits 8479459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits 8489459Ssaidi@eecs.umich.edusystem.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits 8499459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_hits::cpu.data 1547028 # number of demand (read+write) MSHR hits 8509459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_hits::total 1547028 # number of demand (read+write) MSHR hits 8519459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_hits::cpu.data 1547028 # number of overall MSHR hits 8529459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_hits::total 1547028 # number of overall MSHR hits 8539459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 55461 # number of ReadReq MSHR misses 8549459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_misses::total 55461 # number of ReadReq MSHR misses 8559459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 107326 # number of WriteReq MSHR misses 8569459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_misses::total 107326 # number of WriteReq MSHR misses 8579459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 162787 # number of demand (read+write) MSHR misses 8589459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_misses::total 162787 # number of demand (read+write) MSHR misses 8599459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 162787 # number of overall MSHR misses 8609459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_misses::total 162787 # number of overall MSHR misses 8619459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2049044000 # number of ReadReq MSHR miss cycles 8629459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 2049044000 # number of ReadReq MSHR miss cycles 8639459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8282203488 # number of WriteReq MSHR miss cycles 8649459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 8282203488 # number of WriteReq MSHR miss cycles 8659459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10331247488 # number of demand (read+write) MSHR miss cycles 8669459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_miss_latency::total 10331247488 # number of demand (read+write) MSHR miss cycles 8679459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10331247488 # number of overall MSHR miss cycles 8689459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_miss_latency::total 10331247488 # number of overall MSHR miss cycles 8699449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses 8709449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses 8719459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses 8729459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses 8739449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses 8749449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses 8759449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses 8769449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses 8779459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36945.673536 # average ReadReq mshr miss latency 8789459Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36945.673536 # average ReadReq mshr miss latency 8799459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77168.658927 # average WriteReq mshr miss latency 8809459Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77168.658927 # average WriteReq mshr miss latency 8819459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency 8829459Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency 8839459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63464.818984 # average overall mshr miss latency 8849459Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 63464.818984 # average overall mshr miss latency 8859449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8867860SN/A 8877860SN/A---------- End Simulation Statistics ---------- 888