stats.txt revision 9449
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 39348SAli.Saidi@ARM.comsim_seconds 0.026292 # Number of seconds simulated 49348SAli.Saidi@ARM.comsim_ticks 26292466000 # Number of ticks simulated 59348SAli.Saidi@ARM.comfinal_tick 26292466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79449SAli.Saidi@ARM.comhost_inst_rate 43892 # Simulator instruction rate (inst/s) 89449SAli.Saidi@ARM.comhost_op_rate 62284 # Simulator op (including micro ops) rate (op/s) 99449SAli.Saidi@ARM.comhost_tick_rate 16271073 # Simulator tick rate (ticks/s) 109449SAli.Saidi@ARM.comhost_mem_usage 263196 # Number of bytes of host memory used 119449SAli.Saidi@ARM.comhost_seconds 1615.90 # Real time elapsed on the host 129348SAli.Saidi@ARM.comsim_insts 70925094 # Number of instructions simulated 139348SAli.Saidi@ARM.comsim_ops 100644341 # Number of ops (including micro ops) simulated 149348SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 298432 # Number of bytes read from this memory 159348SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory 169348SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 8241664 # Number of bytes read from this memory 179348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 298432 # Number of instructions bytes read from this memory 189348SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 298432 # Number of instructions bytes read from this memory 199348SAli.Saidi@ARM.comsystem.physmem.bytes_written::writebacks 5372352 # Number of bytes written to this memory 209348SAli.Saidi@ARM.comsystem.physmem.bytes_written::total 5372352 # Number of bytes written to this memory 219348SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 4663 # Number of read requests responded to by this memory 229348SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.data 124113 # Number of read requests responded to by this memory 239348SAli.Saidi@ARM.comsystem.physmem.num_reads::total 128776 # Number of read requests responded to by this memory 249348SAli.Saidi@ARM.comsystem.physmem.num_writes::writebacks 83943 # Number of write requests responded to by this memory 259348SAli.Saidi@ARM.comsystem.physmem.num_writes::total 83943 # Number of write requests responded to by this memory 269348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 11350476 # Total read bandwidth from this memory (bytes/s) 279348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 302110574 # Total read bandwidth from this memory (bytes/s) 289348SAli.Saidi@ARM.comsystem.physmem.bw_read::total 313461050 # Total read bandwidth from this memory (bytes/s) 299348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 11350476 # Instruction read bandwidth from this memory (bytes/s) 309348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 11350476 # Instruction read bandwidth from this memory (bytes/s) 319348SAli.Saidi@ARM.comsystem.physmem.bw_write::writebacks 204330472 # Write bandwidth from this memory (bytes/s) 329348SAli.Saidi@ARM.comsystem.physmem.bw_write::total 204330472 # Write bandwidth from this memory (bytes/s) 339348SAli.Saidi@ARM.comsystem.physmem.bw_total::writebacks 204330472 # Total bandwidth to/from this memory (bytes/s) 349348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 11350476 # Total bandwidth to/from this memory (bytes/s) 359348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 302110574 # Total bandwidth to/from this memory (bytes/s) 369348SAli.Saidi@ARM.comsystem.physmem.bw_total::total 517791522 # Total bandwidth to/from this memory (bytes/s) 379348SAli.Saidi@ARM.comsystem.physmem.readReqs 128777 # Total number of read requests seen 389348SAli.Saidi@ARM.comsystem.physmem.writeReqs 83943 # Total number of write requests seen 399348SAli.Saidi@ARM.comsystem.physmem.cpureqs 213018 # Reqs generatd by CPU via cache - shady 409348SAli.Saidi@ARM.comsystem.physmem.bytesRead 8241664 # Total number of bytes read from memory 419348SAli.Saidi@ARM.comsystem.physmem.bytesWritten 5372352 # Total number of bytes written to memory 429348SAli.Saidi@ARM.comsystem.physmem.bytesConsumedRd 8241664 # bytesRead derated as per pkt->getSize() 439348SAli.Saidi@ARM.comsystem.physmem.bytesConsumedWr 5372352 # bytesWritten derated as per pkt->getSize() 449322Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q 459348SAli.Saidi@ARM.comsystem.physmem.neitherReadNorWrite 298 # Reqs where no action is needed 469348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::0 8167 # Track reads on a per bank basis 479348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::1 8037 # Track reads on a per bank basis 489322Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 8102 # Track reads on a per bank basis 499348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::3 7896 # Track reads on a per bank basis 509348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::4 7927 # Track reads on a per bank basis 519322Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 8109 # Track reads on a per bank basis 529348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::6 8024 # Track reads on a per bank basis 539348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::7 7958 # Track reads on a per bank basis 549348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::8 7983 # Track reads on a per bank basis 559348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::9 8195 # Track reads on a per bank basis 569348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::10 8177 # Track reads on a per bank basis 579348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::11 8153 # Track reads on a per bank basis 589348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::12 8060 # Track reads on a per bank basis 599348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::13 8008 # Track reads on a per bank basis 609322Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 7995 # Track reads on a per bank basis 619348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::15 7983 # Track reads on a per bank basis 629348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::0 5171 # Track writes on a per bank basis 639322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 5038 # Track writes on a per bank basis 649348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::2 5231 # Track writes on a per bank basis 659348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::3 5234 # Track writes on a per bank basis 669348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::4 5166 # Track writes on a per bank basis 679322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 5377 # Track writes on a per bank basis 689348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::6 5164 # Track writes on a per bank basis 699322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 5136 # Track writes on a per bank basis 709348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::8 5232 # Track writes on a per bank basis 719322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 5377 # Track writes on a per bank basis 729322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 5465 # Track writes on a per bank basis 739322Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 5417 # Track writes on a per bank basis 749348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::12 5372 # Track writes on a per bank basis 759348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::13 5285 # Track writes on a per bank basis 769348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::14 5127 # Track writes on a per bank basis 779348SAli.Saidi@ARM.comsystem.physmem.perBankWrReqs::15 5151 # Track writes on a per bank basis 789312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 799312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 809449SAli.Saidi@ARM.comsystem.physmem.totGap 26292447500 # Total gap between requests 819312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 829312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 839312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 849312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 859312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 879348SAli.Saidi@ARM.comsystem.physmem.readPktSize::6 128777 # Categorize read packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 969348SAli.Saidi@ARM.comsystem.physmem.writePktSize::6 83943 # categorize write packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 1019312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 1029312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 1039312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 1049312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 1059348SAli.Saidi@ARM.comsystem.physmem.neitherpktsize::6 298 # categorize neither packet sizes 1069312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1079312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1089348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::0 71059 # What read queue length does an incoming req see 1099348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::1 55263 # What read queue length does an incoming req see 1109348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::2 2369 # What read queue length does an incoming req see 1119348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see 1129348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see 1139322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1149322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1419348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 3590 # What write queue length does an incoming req see 1429348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 3644 # What write queue length does an incoming req see 1439348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 3649 # What write queue length does an incoming req see 1449348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see 1459348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see 1469322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see 1479322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see 1489322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see 1499322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see 1509322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see 1519322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see 1529322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see 1539322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see 1549322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see 1559322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see 1569322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see 1579348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::16 3649 # What write queue length does an incoming req see 1589348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::17 3649 # What write queue length does an incoming req see 1599348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see 1609348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see 1619348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see 1629322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see 1639322Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see 1649348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::23 60 # What write queue length does an incoming req see 1659348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::24 6 # What write queue length does an incoming req see 1669348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see 1679348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see 1689348SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see 1699312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1709312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1719312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1729312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1739312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1749449SAli.Saidi@ARM.comsystem.physmem.totQLat 4868163034 # Total cycles spent in queuing delays 1759449SAli.Saidi@ARM.comsystem.physmem.totMemAccLat 6756435034 # Sum of mem lat for all requests 1769348SAli.Saidi@ARM.comsystem.physmem.totBusLat 515096000 # Total cycles spent in databus access 1779348SAli.Saidi@ARM.comsystem.physmem.totBankLat 1373176000 # Total cycles spent in bank access 1789449SAli.Saidi@ARM.comsystem.physmem.avgQLat 37803.93 # Average queueing delay per request 1799348SAli.Saidi@ARM.comsystem.physmem.avgBankLat 10663.46 # Average bank access latency per request 1809312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1819449SAli.Saidi@ARM.comsystem.physmem.avgMemAccLat 52467.38 # Average memory access latency 1829348SAli.Saidi@ARM.comsystem.physmem.avgRdBW 313.46 # Average achieved read bandwidth in MB/s 1839348SAli.Saidi@ARM.comsystem.physmem.avgWrBW 204.33 # Average achieved write bandwidth in MB/s 1849348SAli.Saidi@ARM.comsystem.physmem.avgConsumedRdBW 313.46 # Average consumed read bandwidth in MB/s 1859348SAli.Saidi@ARM.comsystem.physmem.avgConsumedWrBW 204.33 # Average consumed write bandwidth in MB/s 1869312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1879348SAli.Saidi@ARM.comsystem.physmem.busUtil 3.24 # Data bus utilization in percentage 1889348SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 0.26 # Average read queue length over time 1899348SAli.Saidi@ARM.comsystem.physmem.avgWrQLen 9.45 # Average write queue length over time 1909348SAli.Saidi@ARM.comsystem.physmem.readRowHits 118938 # Number of row buffer hits during reads 1919348SAli.Saidi@ARM.comsystem.physmem.writeRowHits 27082 # Number of row buffer hits during writes 1929348SAli.Saidi@ARM.comsystem.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads 1939348SAli.Saidi@ARM.comsystem.physmem.writeRowHitRate 32.26 # Row buffer hit rate for writes 1949348SAli.Saidi@ARM.comsystem.physmem.avgGap 123601.20 # Average gap between requests 1958317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 1968317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 1978317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 1988317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 1998317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 2008317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 2018317SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 2028317SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2038317SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2048317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2058317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 2068317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2078317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 2088317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2098317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2108317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 2118317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 2128317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 2138317SN/Asystem.cpu.dtb.hits 0 # DTB hits 2148317SN/Asystem.cpu.dtb.misses 0 # DTB misses 2158317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 2168317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 2178317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 2188317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2198317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2208317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2218317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2228317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 2238317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2248317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 2258317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 2268317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 2278317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2288317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2298317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2308317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2318317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2328317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2338317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 2348317SN/Asystem.cpu.itb.hits 0 # DTB hits 2358317SN/Asystem.cpu.itb.misses 0 # DTB misses 2368317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 2378317SN/Asystem.cpu.workload.num_syscalls 1946 # Number of system calls 2389348SAli.Saidi@ARM.comsystem.cpu.numCycles 52584933 # number of cpu cycles simulated 2398317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2408317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2419348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 16605622 # Number of BP lookups 2429348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 12744819 # Number of conditional branches predicted 2439348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 601134 # Number of conditional branches incorrect 2449348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 10608037 # Number of BTB lookups 2459348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 7769778 # Number of BTB hits 2467860SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2479348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 1827213 # Number of times the RAS was used to get a target. 2489348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 113597 # Number of incorrect RAS predictions. 2499449SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 12549163 # Number of cycles fetch is stalled on an Icache miss 2509348SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 85090933 # Number of instructions fetch has processed 2519348SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 16605622 # Number of branches that fetch encountered 2529348SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 9596991 # Number of branches that fetch has predicted taken 2539348SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 21171852 # Number of cycles fetch has run and was not squashing or blocked 2549348SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 2347507 # Number of cycles fetch has spent squashing 2559449SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 10606959 # Number of cycles fetch has spent blocked 2569449SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 60 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2579348SAli.Saidi@ARM.comsystem.cpu.fetch.PendingTrapStallCycles 522 # Number of stall cycles due to pending traps 2589348SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR 2599449SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 11672225 # Number of cache lines fetched 2609449SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 180780 # Number of outstanding Icache misses that were squashed 2619449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 46048903 # Number of instructions fetched each cycle (Total) 2629449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 2.587177 # Number of instructions fetched each cycle (Total) 2639348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 3.333418 # Number of instructions fetched each cycle (Total) 2648317SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2659449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 24897029 54.07% 54.07% # Number of instructions fetched each cycle (Total) 2669348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 2135353 4.64% 58.70% # Number of instructions fetched each cycle (Total) 2679348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 1967483 4.27% 62.98% # Number of instructions fetched each cycle (Total) 2689348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 2044942 4.44% 67.42% # Number of instructions fetched each cycle (Total) 2699348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 1463280 3.18% 70.59% # Number of instructions fetched each cycle (Total) 2709348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 1379331 3.00% 73.59% # Number of instructions fetched each cycle (Total) 2719348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 959670 2.08% 75.67% # Number of instructions fetched each cycle (Total) 2729348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 1190775 2.59% 78.26% # Number of instructions fetched each cycle (Total) 2739348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 10011040 21.74% 100.00% # Number of instructions fetched each cycle (Total) 2748317SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2758317SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2768317SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2779449SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 46048903 # Number of instructions fetched each cycle (Total) 2789348SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.315787 # Number of branch fetches per cycle 2799348SAli.Saidi@ARM.comsystem.cpu.fetch.rate 1.618162 # Number of inst fetches per cycle 2809348SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 14627644 # Number of cycles decode is idle 2819449SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 8956470 # Number of cycles decode is blocked 2829348SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 19461806 # Number of cycles decode is running 2839348SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 1385483 # Number of cycles decode is unblocking 2849348SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 1617500 # Number of cycles decode is squashing 2859348SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 3326611 # Number of times decode resolved a branch 2869348SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 104659 # Number of times decode detected a branch misprediction 2879348SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 116720432 # Number of instructions handled by decode 2889348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 360894 # Number of squashed instructions handled by decode 2899348SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 1617500 # Number of cycles rename is squashing 2909348SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 16338587 # Number of cycles rename is idle 2919348SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 2555401 # Number of cycles rename is blocking 2929449SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 926854 # count of cycles rename stalled for serializing inst 2939449SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 19086496 # Number of cycles rename is running 2949348SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 5524065 # Number of cycles rename is unblocking 2959449SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 114852319 # Number of instructions processed by rename 2969348SAli.Saidi@ARM.comsystem.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full 2979348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 16183 # Number of times rename has blocked due to IQ full 2989348SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 4665174 # Number of times rename has blocked due to LSQ full 2999348SAli.Saidi@ARM.comsystem.cpu.rename.FullRegisterEvents 343 # Number of times there has been no free registers 3009449SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 115176509 # Number of destination operands rename has renamed 3019449SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 529186363 # Number of register rename lookups that rename has made 3029449SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 529181678 # Number of integer rename lookups 3039348SAli.Saidi@ARM.comsystem.cpu.rename.fp_rename_lookups 4685 # Number of floating rename lookups 3049348SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 99160616 # Number of HB maps that are committed 3059449SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 16015893 # Number of HB maps that are undone due to squashing 3069348SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 24809 # count of serializing insts renamed 3079348SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 24798 # count of temporary serializing insts renamed 3089348SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 13045945 # count of insts added to the skid buffer 3099348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 29582757 # Number of loads inserted to the mem dependence unit. 3109348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 22430841 # Number of stores inserted to the mem dependence unit. 3119348SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingLoads 3912004 # Number of conflicting loads. 3129348SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingStores 4391398 # Number of conflicting stores. 3139348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 111440700 # Number of instructions added to the IQ (excludes non-spec) 3149348SAli.Saidi@ARM.comsystem.cpu.iq.iqNonSpecInstsAdded 41006 # Number of non-speculative instructions added to the IQ 3159348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 107204361 # Number of instructions issued 3169348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 269260 # Number of squashed instructions issued 3179348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 10685136 # Number of squashed instructions iterated over during squash; mainly for profiling 3189348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 25571717 # Number of squashed operands that are examined and possibly removed from graph 3199348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 3727 # Number of squashed non-spec instructions that were removed 3209449SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 46048903 # Number of insts issued each cycle 3219348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 2.328055 # Number of insts issued each cycle 3229348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.987613 # Number of insts issued each cycle 3238317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3249449SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 10795990 23.44% 23.44% # Number of insts issued each cycle 3259348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 8084539 17.56% 41.00% # Number of insts issued each cycle 3269348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 7444488 16.17% 57.17% # Number of insts issued each cycle 3279348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 7134852 15.49% 72.66% # Number of insts issued each cycle 3289348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 5412181 11.75% 84.41% # Number of insts issued each cycle 3299348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 3900032 8.47% 92.88% # Number of insts issued each cycle 3309348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 1833850 3.98% 96.87% # Number of insts issued each cycle 3319348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 869462 1.89% 98.75% # Number of insts issued each cycle 3329348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 573509 1.25% 100.00% # Number of insts issued each cycle 3338317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3348317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3358317SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3369449SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 46048903 # Number of insts issued each cycle 3378317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3389348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 110622 4.49% 4.49% # attempts to use FU when none available 3399348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 4.49% # attempts to use FU when none available 3409348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 4.49% # attempts to use FU when none available 3419348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 4.49% # attempts to use FU when none available 3429348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 4.49% # attempts to use FU when none available 3439348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 4.49% # attempts to use FU when none available 3449348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 4.49% # attempts to use FU when none available 3459348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 4.49% # attempts to use FU when none available 3469348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.49% # attempts to use FU when none available 3479348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 4.49% # attempts to use FU when none available 3489348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.49% # attempts to use FU when none available 3499348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 4.49% # attempts to use FU when none available 3509348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 4.49% # attempts to use FU when none available 3519348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 4.49% # attempts to use FU when none available 3529348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 4.49% # attempts to use FU when none available 3539348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 4.49% # attempts to use FU when none available 3549348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.49% # attempts to use FU when none available 3559348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 4.49% # attempts to use FU when none available 3569348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.49% # attempts to use FU when none available 3579348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.49% # attempts to use FU when none available 3589348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.49% # attempts to use FU when none available 3599348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.49% # attempts to use FU when none available 3609348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.49% # attempts to use FU when none available 3619348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.49% # attempts to use FU when none available 3629348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.49% # attempts to use FU when none available 3639348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.49% # attempts to use FU when none available 3649348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.49% # attempts to use FU when none available 3659348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.49% # attempts to use FU when none available 3669348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.49% # attempts to use FU when none available 3679348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 1351687 54.87% 59.36% # attempts to use FU when none available 3689348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 1001007 40.64% 100.00% # attempts to use FU when none available 3698317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3708317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3718317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 3729348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 56616683 52.81% 52.81% # Type of FU issued 3739348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 91709 0.09% 52.90% # Type of FU issued 3749348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.90% # Type of FU issued 3759348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 161 0.00% 52.90% # Type of FU issued 3769348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.90% # Type of FU issued 3779348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.90% # Type of FU issued 3789348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.90% # Type of FU issued 3799348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.90% # Type of FU issued 3809348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.90% # Type of FU issued 3819348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.90% # Type of FU issued 3829348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.90% # Type of FU issued 3839348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.90% # Type of FU issued 3849348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.90% # Type of FU issued 3859348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.90% # Type of FU issued 3869348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.90% # Type of FU issued 3879348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.90% # Type of FU issued 3889348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.90% # Type of FU issued 3899348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.90% # Type of FU issued 3909348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.90% # Type of FU issued 3919348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.90% # Type of FU issued 3929348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.90% # Type of FU issued 3939348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.90% # Type of FU issued 3949348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.90% # Type of FU issued 3959348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.90% # Type of FU issued 3969348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.90% # Type of FU issued 3979348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.90% # Type of FU issued 3989348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.90% # Type of FU issued 3999348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.90% # Type of FU issued 4009348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.90% # Type of FU issued 4019348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 28875176 26.93% 79.83% # Type of FU issued 4029348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 21620625 20.17% 100.00% # Type of FU issued 4038317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4048317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4059348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 107204361 # Type of FU issued 4069348SAli.Saidi@ARM.comsystem.cpu.iq.rate 2.038690 # Inst issue rate 4079348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 2463316 # FU busy when requested 4089348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.022978 # FU busy rate (busy events/executed inst) 4099449SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 263189737 # Number of integer instruction queue reads 4109348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 122194582 # Number of integer instruction queue writes 4119348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 105533921 # Number of integer instruction queue wakeup accesses 4129348SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_reads 464 # Number of floating instruction queue reads 4139348SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_writes 696 # Number of floating instruction queue writes 4149348SAli.Saidi@ARM.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 152 # Number of floating instruction queue wakeup accesses 4159348SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 109667441 # Number of integer alu accesses 4169348SAli.Saidi@ARM.comsystem.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses 4179348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 2181528 # Number of loads that had data forwarded from stores 4188317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4199348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 2272156 # Number of loads squashed 4209348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.ignoredResponses 6578 # Number of memory responses ignored because the instruction is squashed 4219348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 29396 # Number of memory ordering violations 4229348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 1871610 # Number of stores squashed 4238317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4248317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4259348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 28 # Number of loads that were rescheduled 4269348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 493 # Number of times an access to memory failed due to the cache being blocked 4278317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4289348SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 1617500 # Number of cycles IEW is squashing 4299348SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 1047454 # Number of cycles IEW is blocking 4309348SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 46131 # Number of cycles IEW is unblocking 4319348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 111491510 # Number of instructions dispatched to IQ 4329449SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 290952 # Number of squashed instructions skipped by dispatch 4339348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 29582757 # Number of dispatched load instructions 4349348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 22430841 # Number of dispatched store instructions 4359348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispNonSpecInsts 24336 # Number of dispatched non-speculative instructions 4369348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 6480 # Number of times the IQ has become full, causing a stall 4379348SAli.Saidi@ARM.comsystem.cpu.iew.iewLSQFullEvents 5483 # Number of times the LSQ has become full, causing a stall 4389348SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 29396 # Number of memory order violations 4399348SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 390184 # Number of branches that were predicted taken incorrectly 4409348SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 182395 # Number of branches that were predicted not taken incorrectly 4419348SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 572579 # Number of branch mispredicts detected at execute 4429348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 106179962 # Number of executed instructions 4439348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 28578383 # Number of load instructions executed 4449348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 1024399 # Number of squashed instructions skipped in execute 4458317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4469348SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 9804 # number of nop insts executed 4479348SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 49916161 # number of memory reference insts executed 4489348SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 14598129 # Number of branches executed 4499348SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 21337778 # Number of stores executed 4509348SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 2.019209 # Inst execution rate 4519348SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 105751543 # cumulative count of insts sent to commit 4529348SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 105534073 # cumulative count of insts written-back 4539348SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 53248858 # num instructions producing a value 4549348SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 103476528 # num instructions consuming a value 4558317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4569348SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 2.006926 # insts written-back per cycle 4579348SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.514598 # average fanout of values written-back 4588317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4599348SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 10842444 # The number of squashed insts skipped by commit 4609348SAli.Saidi@ARM.comsystem.cpu.commit.commitNonSpecStalls 37279 # The number of times commit has been forced to stall to communicate backwards 4619348SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 498355 # The number of times a branch was mispredicted 4629449SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 44431403 # Number of insts commited each cycle 4639348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 2.265287 # Number of insts commited each cycle 4649348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 2.763630 # Number of insts commited each cycle 4658241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4669449SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 15343379 34.53% 34.53% # Number of insts commited each cycle 4679348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 11655601 26.23% 60.77% # Number of insts commited each cycle 4689348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 3462235 7.79% 68.56% # Number of insts commited each cycle 4699348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 2874946 6.47% 75.03% # Number of insts commited each cycle 4709348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 1877627 4.23% 79.25% # Number of insts commited each cycle 4719348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 1953879 4.40% 83.65% # Number of insts commited each cycle 4729348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 688656 1.55% 85.20% # Number of insts commited each cycle 4739348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 567495 1.28% 86.48% # Number of insts commited each cycle 4749348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 6007585 13.52% 100.00% # Number of insts commited each cycle 4758241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4768241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4778241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4789449SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 44431403 # Number of insts commited each cycle 4799348SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 70930646 # Number of instructions committed 4809348SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 100649893 # Number of ops (including micro ops) committed 4818317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4829348SAli.Saidi@ARM.comsystem.cpu.commit.refs 47869832 # Number of memory references committed 4839348SAli.Saidi@ARM.comsystem.cpu.commit.loads 27310601 # Number of loads committed 4848317SN/Asystem.cpu.commit.membars 15920 # Number of memory barriers committed 4859348SAli.Saidi@ARM.comsystem.cpu.commit.branches 13744998 # Number of branches committed 4868241SN/Asystem.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 4879348SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 91486751 # Number of committed integer instructions. 4888241SN/Asystem.cpu.commit.function_calls 1679850 # Number of function calls committed. 4899348SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 6007585 # number cycles where commit BW limit reached 4908317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4919449SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 149890856 # The number of ROB reads 4929348SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 224611140 # The number of ROB writes 4939348SAli.Saidi@ARM.comsystem.cpu.timesIdled 74350 # Number of times that the entire CPU went into an idle state and unscheduled itself 4949449SAli.Saidi@ARM.comsystem.cpu.idleCycles 6536030 # Total number of cycles that the CPU has spent unscheduled due to idling 4959348SAli.Saidi@ARM.comsystem.cpu.committedInsts 70925094 # Number of Instructions Simulated 4969348SAli.Saidi@ARM.comsystem.cpu.committedOps 100644341 # Number of Ops (including micro ops) Simulated 4979348SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 70925094 # Number of Instructions Simulated 4989348SAli.Saidi@ARM.comsystem.cpu.cpi 0.741415 # CPI: Cycles Per Instruction 4999348SAli.Saidi@ARM.comsystem.cpu.cpi_total 0.741415 # CPI: Total CPI of All Threads 5009348SAli.Saidi@ARM.comsystem.cpu.ipc 1.348772 # IPC: Instructions Per Cycle 5019348SAli.Saidi@ARM.comsystem.cpu.ipc_total 1.348772 # IPC: Total IPC of All Threads 5029348SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 511431338 # number of integer regfile reads 5039348SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 103318196 # number of integer regfile writes 5049348SAli.Saidi@ARM.comsystem.cpu.fp_regfile_reads 686 # number of floating regfile reads 5059348SAli.Saidi@ARM.comsystem.cpu.fp_regfile_writes 582 # number of floating regfile writes 5069378Snilay@cs.wisc.edusystem.cpu.misc_regfile_reads 49170129 # number of misc regfile reads 5079348SAli.Saidi@ARM.comsystem.cpu.misc_regfile_writes 38826 # number of misc regfile writes 5089348SAli.Saidi@ARM.comsystem.cpu.icache.replacements 30543 # number of replacements 5099449SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 1820.333458 # Cycle average of tags in use 5109348SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 11635566 # Total number of references to valid blocks. 5119348SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 32580 # Sample count of references to valid blocks. 5129348SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 357.138306 # Average number of references to valid blocks. 5138317SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5149449SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 1820.333458 # Average occupied blocks per requestor 5159348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.888835 # Average percentage of cache occupancy 5169348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.888835 # Average percentage of cache occupancy 5179348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 11635567 # number of ReadReq hits 5189348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 11635567 # number of ReadReq hits 5199348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 11635567 # number of demand (read+write) hits 5209348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 11635567 # number of demand (read+write) hits 5219348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 11635567 # number of overall hits 5229348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 11635567 # number of overall hits 5239449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 36658 # number of ReadReq misses 5249449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 36658 # number of ReadReq misses 5259449SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 36658 # number of demand (read+write) misses 5269449SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 36658 # number of demand (read+write) misses 5279449SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 36658 # number of overall misses 5289449SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 36658 # number of overall misses 5299449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 709083999 # number of ReadReq miss cycles 5309449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 709083999 # number of ReadReq miss cycles 5319449SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 709083999 # number of demand (read+write) miss cycles 5329449SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 709083999 # number of demand (read+write) miss cycles 5339449SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 709083999 # number of overall miss cycles 5349449SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 709083999 # number of overall miss cycles 5359449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 11672225 # number of ReadReq accesses(hits+misses) 5369449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 11672225 # number of ReadReq accesses(hits+misses) 5379449SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 11672225 # number of demand (read+write) accesses 5389449SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 11672225 # number of demand (read+write) accesses 5399449SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 11672225 # number of overall (read+write) accesses 5409449SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 11672225 # number of overall (read+write) accesses 5419348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003141 # miss rate for ReadReq accesses 5429348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.003141 # miss rate for ReadReq accesses 5439348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.003141 # miss rate for demand accesses 5449348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.003141 # miss rate for demand accesses 5459348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.003141 # miss rate for overall accesses 5469348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.003141 # miss rate for overall accesses 5479449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19343.226554 # average ReadReq miss latency 5489449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 19343.226554 # average ReadReq miss latency 5499449SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency 5509449SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 19343.226554 # average overall miss latency 5519449SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 19343.226554 # average overall miss latency 5529449SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 19343.226554 # average overall miss latency 5539348SAli.Saidi@ARM.comsystem.cpu.icache.blocked_cycles::no_mshrs 1000 # number of cycles access was blocked 5548317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5559348SAli.Saidi@ARM.comsystem.cpu.icache.blocked::no_mshrs 22 # number of cycles access was blocked 5568317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5579348SAli.Saidi@ARM.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 45.454545 # average number of cycles each access was blocked 5588983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5598317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5608317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5619449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 3774 # number of ReadReq MSHR hits 5629449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 3774 # number of ReadReq MSHR hits 5639449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 3774 # number of demand (read+write) MSHR hits 5649449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 3774 # number of demand (read+write) MSHR hits 5659449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 3774 # number of overall MSHR hits 5669449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 3774 # number of overall MSHR hits 5679348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 32884 # number of ReadReq MSHR misses 5689348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 32884 # number of ReadReq MSHR misses 5699348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 32884 # number of demand (read+write) MSHR misses 5709348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 32884 # number of demand (read+write) MSHR misses 5719348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 32884 # number of overall MSHR misses 5729348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 32884 # number of overall MSHR misses 5739449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 580605499 # number of ReadReq MSHR miss cycles 5749449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 580605499 # number of ReadReq MSHR miss cycles 5759449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 580605499 # number of demand (read+write) MSHR miss cycles 5769449SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 580605499 # number of demand (read+write) MSHR miss cycles 5779449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 580605499 # number of overall MSHR miss cycles 5789449SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 580605499 # number of overall MSHR miss cycles 5799348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for ReadReq accesses 5809348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.002817 # mshr miss rate for ReadReq accesses 5819348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for demand accesses 5829348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.002817 # mshr miss rate for demand accesses 5839348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002817 # mshr miss rate for overall accesses 5849348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.002817 # mshr miss rate for overall accesses 5859449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17656.170144 # average ReadReq mshr miss latency 5869449SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17656.170144 # average ReadReq mshr miss latency 5879449SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency 5889449SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency 5899449SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17656.170144 # average overall mshr miss latency 5909449SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 17656.170144 # average overall mshr miss latency 5918317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5929348SAli.Saidi@ARM.comsystem.cpu.l2cache.replacements 95650 # number of replacements 5939449SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 30136.955699 # Cycle average of tags in use 5949348SAli.Saidi@ARM.comsystem.cpu.l2cache.total_refs 89930 # Total number of references to valid blocks. 5959348SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 126757 # Sample count of references to valid blocks. 5969348SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.709468 # Average number of references to valid blocks. 5978317SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5989348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::writebacks 26880.895911 # Average occupied blocks per requestor 5999449SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 1379.489982 # Average occupied blocks per requestor 6009449SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 1876.569807 # Average occupied blocks per requestor 6019348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::writebacks 0.820340 # Average percentage of cache occupancy 6029348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.042099 # Average percentage of cache occupancy 6039348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.057268 # Average percentage of cache occupancy 6049348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.919707 # Average percentage of cache occupancy 6059348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 27693 # number of ReadReq hits 6069348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 33453 # number of ReadReq hits 6079348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 61146 # number of ReadReq hits 6089348SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_hits::writebacks 129052 # number of Writeback hits 6099348SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_hits::total 129052 # number of Writeback hits 6109348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 19 # number of UpgradeReq hits 6119348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_hits::total 19 # number of UpgradeReq hits 6129348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 4778 # number of ReadExReq hits 6139348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_hits::total 4778 # number of ReadExReq hits 6149348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 27693 # number of demand (read+write) hits 6159348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 38231 # number of demand (read+write) hits 6169348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 65924 # number of demand (read+write) hits 6179348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 27693 # number of overall hits 6189348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 38231 # number of overall hits 6199348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 65924 # number of overall hits 6209348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 4680 # number of ReadReq misses 6219348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 21915 # number of ReadReq misses 6229348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 26595 # number of ReadReq misses 6239348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 298 # number of UpgradeReq misses 6249348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_misses::total 298 # number of UpgradeReq misses 6259348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 102256 # number of ReadExReq misses 6269348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 102256 # number of ReadExReq misses 6279348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 4680 # number of demand (read+write) misses 6289348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 124171 # number of demand (read+write) misses 6299348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 128851 # number of demand (read+write) misses 6309348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 4680 # number of overall misses 6319348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 124171 # number of overall misses 6329348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 128851 # number of overall misses 6339449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269871000 # number of ReadReq miss cycles 6349449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 1664900000 # number of ReadReq miss cycles 6359449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 1934771000 # number of ReadReq miss cycles 6369348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles 6379348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles 6389348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8091962000 # number of ReadExReq miss cycles 6399348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 8091962000 # number of ReadExReq miss cycles 6409449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 269871000 # number of demand (read+write) miss cycles 6419449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9756862000 # number of demand (read+write) miss cycles 6429449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 10026733000 # number of demand (read+write) miss cycles 6439449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 269871000 # number of overall miss cycles 6449449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9756862000 # number of overall miss cycles 6459449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 10026733000 # number of overall miss cycles 6469348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 32373 # number of ReadReq accesses(hits+misses) 6479348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 55368 # number of ReadReq accesses(hits+misses) 6489348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 87741 # number of ReadReq accesses(hits+misses) 6499348SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_accesses::writebacks 129052 # number of Writeback accesses(hits+misses) 6509348SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_accesses::total 129052 # number of Writeback accesses(hits+misses) 6519348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 317 # number of UpgradeReq accesses(hits+misses) 6529348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_accesses::total 317 # number of UpgradeReq accesses(hits+misses) 6539348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) 6549348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) 6559348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 32373 # number of demand (read+write) accesses 6569348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 162402 # number of demand (read+write) accesses 6579348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 194775 # number of demand (read+write) accesses 6589348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 32373 # number of overall (read+write) accesses 6599348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 162402 # number of overall (read+write) accesses 6609348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 194775 # number of overall (read+write) accesses 6619348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.144565 # miss rate for ReadReq accesses 6629348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395806 # miss rate for ReadReq accesses 6639348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.303108 # miss rate for ReadReq accesses 6649348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.940063 # miss rate for UpgradeReq accesses 6659348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.940063 # miss rate for UpgradeReq accesses 6669348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955360 # miss rate for ReadExReq accesses 6679348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.955360 # miss rate for ReadExReq accesses 6689348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.144565 # miss rate for demand accesses 6699348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.764590 # miss rate for demand accesses 6709348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.661538 # miss rate for demand accesses 6719348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.144565 # miss rate for overall accesses 6729348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.764590 # miss rate for overall accesses 6739348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.661538 # miss rate for overall accesses 6749449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 57664.743590 # average ReadReq miss latency 6759449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75970.796258 # average ReadReq miss latency 6769449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 72749.426584 # average ReadReq miss latency 6779348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 77.181208 # average UpgradeReq miss latency 6789348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 77.181208 # average UpgradeReq miss latency 6799348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79134.349085 # average ReadExReq miss latency 6809348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 79134.349085 # average ReadExReq miss latency 6819449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency 6829449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency 6839449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 77816.493469 # average overall miss latency 6849449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 57664.743590 # average overall miss latency 6859449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 78576.012112 # average overall miss latency 6869449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 77816.493469 # average overall miss latency 6878317SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6888317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6898317SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6908317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6918983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6928983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6938317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6947860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6959348SAli.Saidi@ARM.comsystem.cpu.l2cache.writebacks::writebacks 83943 # number of writebacks 6969348SAli.Saidi@ARM.comsystem.cpu.l2cache.writebacks::total 83943 # number of writebacks 6979322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits 6989348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 6999348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 7009322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits 7019348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits 7029348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits 7039322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits 7049348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits 7059348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits 7069348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4664 # number of ReadReq MSHR misses 7079348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21857 # number of ReadReq MSHR misses 7089348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 26521 # number of ReadReq MSHR misses 7099348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 298 # number of UpgradeReq MSHR misses 7109348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 298 # number of UpgradeReq MSHR misses 7119348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102256 # number of ReadExReq MSHR misses 7129348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 102256 # number of ReadExReq MSHR misses 7139348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 4664 # number of demand (read+write) MSHR misses 7149348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 124113 # number of demand (read+write) MSHR misses 7159348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 128777 # number of demand (read+write) MSHR misses 7169348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 4664 # number of overall MSHR misses 7179348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 124113 # number of overall MSHR misses 7189348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 128777 # number of overall MSHR misses 7199449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 210183444 # number of ReadReq MSHR miss cycles 7209348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1389842080 # number of ReadReq MSHR miss cycles 7219449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 1600025524 # number of ReadReq MSHR miss cycles 7229348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2980298 # number of UpgradeReq MSHR miss cycles 7239348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2980298 # number of UpgradeReq MSHR miss cycles 7249348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6821241683 # number of ReadExReq MSHR miss cycles 7259348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6821241683 # number of ReadExReq MSHR miss cycles 7269449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 210183444 # number of demand (read+write) MSHR miss cycles 7279348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8211083763 # number of demand (read+write) MSHR miss cycles 7289449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 8421267207 # number of demand (read+write) MSHR miss cycles 7299449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 210183444 # number of overall MSHR miss cycles 7309348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8211083763 # number of overall MSHR miss cycles 7319449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 8421267207 # number of overall MSHR miss cycles 7329348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for ReadReq accesses 7339348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394759 # mshr miss rate for ReadReq accesses 7349348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.302265 # mshr miss rate for ReadReq accesses 7359348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.940063 # mshr miss rate for UpgradeReq accesses 7369348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.940063 # mshr miss rate for UpgradeReq accesses 7379348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955360 # mshr miss rate for ReadExReq accesses 7389348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955360 # mshr miss rate for ReadExReq accesses 7399348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for demand accesses 7409348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for demand accesses 7419348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.661158 # mshr miss rate for demand accesses 7429348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.144071 # mshr miss rate for overall accesses 7439348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764233 # mshr miss rate for overall accesses 7449348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.661158 # mshr miss rate for overall accesses 7459449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 45065.060892 # average ReadReq mshr miss latency 7469348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63587.961751 # average ReadReq mshr miss latency 7479449SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60330.512575 # average ReadReq mshr miss latency 7489348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 7499348SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 7509348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66707.495726 # average ReadExReq mshr miss latency 7519348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66707.495726 # average ReadExReq mshr miss latency 7529449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency 7539348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency 7549449SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency 7559449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 45065.060892 # average overall mshr miss latency 7569348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66158.128182 # average overall mshr miss latency 7579449SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 65394.186904 # average overall mshr miss latency 7587860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7599449SAli.Saidi@ARM.comsystem.cpu.dcache.replacements 158306 # number of replacements 7609449SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 4072.986678 # Cycle average of tags in use 7619449SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 44343623 # Total number of references to valid blocks. 7629449SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 162402 # Sample count of references to valid blocks. 7639449SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 273.048503 # Average number of references to valid blocks. 7649449SAli.Saidi@ARM.comsystem.cpu.dcache.warmup_cycle 280868000 # Cycle when the warmup percentage was hit. 7659449SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 4072.986678 # Average occupied blocks per requestor 7669449SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.994382 # Average percentage of cache occupancy 7679449SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.994382 # Average percentage of cache occupancy 7689449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 26038019 # number of ReadReq hits 7699449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 26038019 # number of ReadReq hits 7709449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 18265169 # number of WriteReq hits 7719449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 18265169 # number of WriteReq hits 7729449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 20453 # number of LoadLockedReq hits 7739449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::total 20453 # number of LoadLockedReq hits 7749449SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 19412 # number of StoreCondReq hits 7759449SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::total 19412 # number of StoreCondReq hits 7769449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 44303188 # number of demand (read+write) hits 7779449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 44303188 # number of demand (read+write) hits 7789449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 44303188 # number of overall hits 7799449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 44303188 # number of overall hits 7809449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 124631 # number of ReadReq misses 7819449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 124631 # number of ReadReq misses 7829449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1584732 # number of WriteReq misses 7839449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 1584732 # number of WriteReq misses 7849449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 40 # number of LoadLockedReq misses 7859449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::total 40 # number of LoadLockedReq misses 7869449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 1709363 # number of demand (read+write) misses 7879449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 1709363 # number of demand (read+write) misses 7889449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 1709363 # number of overall misses 7899449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 1709363 # number of overall misses 7909449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 4670086500 # number of ReadReq miss cycles 7919449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 4670086500 # number of ReadReq miss cycles 7929449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 120039172981 # number of WriteReq miss cycles 7939449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 120039172981 # number of WriteReq miss cycles 7949449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 743000 # number of LoadLockedReq miss cycles 7959449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 743000 # number of LoadLockedReq miss cycles 7969449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 124709259481 # number of demand (read+write) miss cycles 7979449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 124709259481 # number of demand (read+write) miss cycles 7989449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 124709259481 # number of overall miss cycles 7999449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 124709259481 # number of overall miss cycles 8009449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 26162650 # number of ReadReq accesses(hits+misses) 8019449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 26162650 # number of ReadReq accesses(hits+misses) 8029449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 8039449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 8049449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 20493 # number of LoadLockedReq accesses(hits+misses) 8059449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::total 20493 # number of LoadLockedReq accesses(hits+misses) 8069449SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 19412 # number of StoreCondReq accesses(hits+misses) 8079449SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::total 19412 # number of StoreCondReq accesses(hits+misses) 8089449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 46012551 # number of demand (read+write) accesses 8099449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 46012551 # number of demand (read+write) accesses 8109449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 46012551 # number of overall (read+write) accesses 8119449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 46012551 # number of overall (read+write) accesses 8129449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses 8139449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses 8149449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079836 # miss rate for WriteReq accesses 8159449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.079836 # miss rate for WriteReq accesses 8169449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001952 # miss rate for LoadLockedReq accesses 8179449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.001952 # miss rate for LoadLockedReq accesses 8189449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.037150 # miss rate for demand accesses 8199449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.037150 # miss rate for demand accesses 8209449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.037150 # miss rate for overall accesses 8219449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.037150 # miss rate for overall accesses 8229449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37471.307299 # average ReadReq miss latency 8239449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 37471.307299 # average ReadReq miss latency 8249449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75747.301740 # average WriteReq miss latency 8259449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 75747.301740 # average WriteReq miss latency 8269449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18575 # average LoadLockedReq miss latency 8279449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18575 # average LoadLockedReq miss latency 8289449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency 8299449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 72956.568898 # average overall miss latency 8309449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 72956.568898 # average overall miss latency 8319449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 72956.568898 # average overall miss latency 8329449SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_mshrs 4330 # number of cycles access was blocked 8339449SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 648 # number of cycles access was blocked 8349449SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked 8359449SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked 8369449SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 31.605839 # average number of cycles each access was blocked 8379449SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 43.200000 # average number of cycles each access was blocked 8389449SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8399449SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8409449SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::writebacks 129052 # number of writebacks 8419449SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::total 129052 # number of writebacks 8429449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 69229 # number of ReadReq MSHR hits 8439449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 69229 # number of ReadReq MSHR hits 8449449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1477415 # number of WriteReq MSHR hits 8459449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1477415 # number of WriteReq MSHR hits 8469449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 40 # number of LoadLockedReq MSHR hits 8479449SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 40 # number of LoadLockedReq MSHR hits 8489449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 1546644 # number of demand (read+write) MSHR hits 8499449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 1546644 # number of demand (read+write) MSHR hits 8509449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 1546644 # number of overall MSHR hits 8519449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 1546644 # number of overall MSHR hits 8529449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 55402 # number of ReadReq MSHR misses 8539449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 55402 # number of ReadReq MSHR misses 8549449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 107317 # number of WriteReq MSHR misses 8559449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 107317 # number of WriteReq MSHR misses 8569449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 162719 # number of demand (read+write) MSHR misses 8579449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 162719 # number of demand (read+write) MSHR misses 8589449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 162719 # number of overall MSHR misses 8599449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 162719 # number of overall MSHR misses 8609449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2060279000 # number of ReadReq MSHR miss cycles 8619449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 2060279000 # number of ReadReq MSHR miss cycles 8629449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8253592492 # number of WriteReq MSHR miss cycles 8639449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 8253592492 # number of WriteReq MSHR miss cycles 8649449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10313871492 # number of demand (read+write) MSHR miss cycles 8659449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10313871492 # number of demand (read+write) MSHR miss cycles 8669449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10313871492 # number of overall MSHR miss cycles 8679449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10313871492 # number of overall MSHR miss cycles 8689449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002118 # mshr miss rate for ReadReq accesses 8699449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002118 # mshr miss rate for ReadReq accesses 8709449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005406 # mshr miss rate for WriteReq accesses 8719449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005406 # mshr miss rate for WriteReq accesses 8729449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses 8739449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses 8749449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses 8759449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses 8769449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37187.809104 # average ReadReq mshr miss latency 8779449SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37187.809104 # average ReadReq mshr miss latency 8789449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76908.527931 # average WriteReq mshr miss latency 8799449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76908.527931 # average WriteReq mshr miss latency 8809449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency 8819449SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency 8829449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63384.555534 # average overall mshr miss latency 8839449SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 63384.555534 # average overall mshr miss latency 8849449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8857860SN/A 8867860SN/A---------- End Simulation Statistics ---------- 887