stats.txt revision 8317
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.036348 # Number of seconds simulated 4sim_ticks 36348210000 # Number of ticks simulated 5sim_freq 1000000000000 # Frequency of simulated ticks 6host_inst_rate 54516 # Simulator instruction rate (inst/s) 7host_tick_rate 19691005 # Simulator tick rate (ticks/s) 8host_mem_usage 264076 # Number of bytes of host memory used 9host_seconds 1845.93 # Real time elapsed on the host 10sim_insts 100633035 # Number of instructions simulated 11system.cpu.dtb.inst_hits 0 # ITB inst hits 12system.cpu.dtb.inst_misses 0 # ITB inst misses 13system.cpu.dtb.read_hits 0 # DTB read hits 14system.cpu.dtb.read_misses 0 # DTB read misses 15system.cpu.dtb.write_hits 0 # DTB write hits 16system.cpu.dtb.write_misses 0 # DTB write misses 17system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 18system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 20system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 21system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 22system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 23system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 24system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 25system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 26system.cpu.dtb.read_accesses 0 # DTB read accesses 27system.cpu.dtb.write_accesses 0 # DTB write accesses 28system.cpu.dtb.inst_accesses 0 # ITB inst accesses 29system.cpu.dtb.hits 0 # DTB hits 30system.cpu.dtb.misses 0 # DTB misses 31system.cpu.dtb.accesses 0 # DTB accesses 32system.cpu.itb.inst_hits 0 # ITB inst hits 33system.cpu.itb.inst_misses 0 # ITB inst misses 34system.cpu.itb.read_hits 0 # DTB read hits 35system.cpu.itb.read_misses 0 # DTB read misses 36system.cpu.itb.write_hits 0 # DTB write hits 37system.cpu.itb.write_misses 0 # DTB write misses 38system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 39system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 43system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 44system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 45system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 46system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 47system.cpu.itb.read_accesses 0 # DTB read accesses 48system.cpu.itb.write_accesses 0 # DTB write accesses 49system.cpu.itb.inst_accesses 0 # ITB inst accesses 50system.cpu.itb.hits 0 # DTB hits 51system.cpu.itb.misses 0 # DTB misses 52system.cpu.itb.accesses 0 # DTB accesses 53system.cpu.workload.num_syscalls 1946 # Number of system calls 54system.cpu.numCycles 72696421 # number of cpu cycles simulated 55system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 56system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 57system.cpu.BPredUnit.lookups 17573172 # Number of BP lookups 58system.cpu.BPredUnit.condPredicted 11453458 # Number of conditional branches predicted 59system.cpu.BPredUnit.condIncorrect 851549 # Number of conditional branches incorrect 60system.cpu.BPredUnit.BTBLookups 14915035 # Number of BTB lookups 61system.cpu.BPredUnit.BTBHits 9554942 # Number of BTB hits 62system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 63system.cpu.BPredUnit.usedRAS 1842823 # Number of times the RAS was used to get a target. 64system.cpu.BPredUnit.RASInCorrect 176515 # Number of incorrect RAS predictions. 65system.cpu.fetch.icacheStallCycles 11675232 # Number of cycles fetch is stalled on an Icache miss 66system.cpu.fetch.Insts 87296891 # Number of instructions fetch has processed 67system.cpu.fetch.Branches 17573172 # Number of branches that fetch encountered 68system.cpu.fetch.predictedBranches 11397765 # Number of branches that fetch has predicted taken 69system.cpu.fetch.Cycles 22503406 # Number of cycles fetch has run and was not squashing or blocked 70system.cpu.fetch.SquashCycles 923751 # Number of cycles fetch has spent squashing 71system.cpu.fetch.MiscStallCycles 51 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 72system.cpu.fetch.CacheLines 11675232 # Number of cache lines fetched 73system.cpu.fetch.IcacheSquashes 177839 # Number of outstanding Icache misses that were squashed 74system.cpu.fetch.rateDist::samples 71670018 # Number of instructions fetched each cycle (Total) 75system.cpu.fetch.rateDist::mean 1.692121 # Number of instructions fetched each cycle (Total) 76system.cpu.fetch.rateDist::stdev 2.915842 # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 78system.cpu.fetch.rateDist::0 49181996 68.62% 68.62% # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::1 2373056 3.31% 71.93% # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::2 2569214 3.58% 75.52% # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::3 2298620 3.21% 78.73% # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.rateDist::4 1644656 2.29% 81.02% # Number of instructions fetched each cycle (Total) 83system.cpu.fetch.rateDist::5 1723119 2.40% 83.42% # Number of instructions fetched each cycle (Total) 84system.cpu.fetch.rateDist::6 990721 1.38% 84.81% # Number of instructions fetched each cycle (Total) 85system.cpu.fetch.rateDist::7 1380652 1.93% 86.73% # Number of instructions fetched each cycle (Total) 86system.cpu.fetch.rateDist::8 9507984 13.27% 100.00% # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::total 71670018 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.branchRate 0.241734 # Number of branch fetches per cycle 92system.cpu.fetch.rate 1.200842 # Number of inst fetches per cycle 93system.cpu.decode.IdleCycles 25114154 # Number of cycles decode is idle 94system.cpu.decode.BlockedCycles 22709447 # Number of cycles decode is blocked 95system.cpu.decode.RunCycles 21527142 # Number of cycles decode is running 96system.cpu.decode.UnblockCycles 497633 # Number of cycles decode is unblocking 97system.cpu.decode.SquashCycles 1821642 # Number of cycles decode is squashing 98system.cpu.decode.BranchResolved 3527413 # Number of times decode resolved a branch 99system.cpu.decode.BranchMispred 94287 # Number of times decode detected a branch misprediction 100system.cpu.decode.DecodedInsts 118399354 # Number of instructions handled by decode 101system.cpu.decode.SquashedInsts 324192 # Number of squashed instructions handled by decode 102system.cpu.rename.SquashCycles 1821642 # Number of cycles rename is squashing 103system.cpu.rename.IdleCycles 26632137 # Number of cycles rename is idle 104system.cpu.rename.BlockCycles 2439992 # Number of cycles rename is blocking 105system.cpu.rename.serializeStallCycles 16812666 # count of cycles rename stalled for serializing inst 106system.cpu.rename.RunCycles 20410601 # Number of cycles rename is running 107system.cpu.rename.UnblockCycles 3552980 # Number of cycles rename is unblocking 108system.cpu.rename.RenamedInsts 115899857 # Number of instructions processed by rename 109system.cpu.rename.IQFullEvents 27143 # Number of times rename has blocked due to IQ full 110system.cpu.rename.LSQFullEvents 2453549 # Number of times rename has blocked due to LSQ full 111system.cpu.rename.RenamedOperands 118034319 # Number of destination operands rename has renamed 112system.cpu.rename.RenameLookups 532748209 # Number of register rename lookups that rename has made 113system.cpu.rename.int_rename_lookups 532647632 # Number of integer rename lookups 114system.cpu.rename.fp_rename_lookups 100577 # Number of floating rename lookups 115system.cpu.rename.CommittedMaps 99142525 # Number of HB maps that are committed 116system.cpu.rename.UndoneMaps 18891789 # Number of HB maps that are undone due to squashing 117system.cpu.rename.serializingInsts 756618 # count of serializing insts renamed 118system.cpu.rename.tempSerializingInsts 756606 # count of temporary serializing insts renamed 119system.cpu.rename.skidInsts 10359843 # count of insts added to the skid buffer 120system.cpu.memDep0.insertedLoads 29552116 # Number of loads inserted to the mem dependence unit. 121system.cpu.memDep0.insertedStores 22027852 # Number of stores inserted to the mem dependence unit. 122system.cpu.memDep0.conflictingLoads 13146932 # Number of conflicting loads. 123system.cpu.memDep0.conflictingStores 13132796 # Number of conflicting stores. 124system.cpu.iq.iqInstsAdded 110916590 # Number of instructions added to the IQ (excludes non-spec) 125system.cpu.iq.iqNonSpecInstsAdded 749122 # Number of non-speculative instructions added to the IQ 126system.cpu.iq.iqInstsIssued 106735970 # Number of instructions issued 127system.cpu.iq.iqSquashedInstsIssued 111004 # Number of squashed instructions issued 128system.cpu.iq.iqSquashedInstsExamined 10702418 # Number of squashed instructions iterated over during squash; mainly for profiling 129system.cpu.iq.iqSquashedOperandsExamined 27336640 # Number of squashed operands that are examined and possibly removed from graph 130system.cpu.iq.iqSquashedNonSpecRemoved 48262 # Number of squashed non-spec instructions that were removed 131system.cpu.iq.issued_per_cycle::samples 71670018 # Number of insts issued each cycle 132system.cpu.iq.issued_per_cycle::mean 1.489269 # Number of insts issued each cycle 133system.cpu.iq.issued_per_cycle::stdev 1.647816 # Number of insts issued each cycle 134system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 135system.cpu.iq.issued_per_cycle::0 26697633 37.25% 37.25% # Number of insts issued each cycle 136system.cpu.iq.issued_per_cycle::1 17182939 23.98% 61.23% # Number of insts issued each cycle 137system.cpu.iq.issued_per_cycle::2 10552290 14.72% 75.95% # Number of insts issued each cycle 138system.cpu.iq.issued_per_cycle::3 7611894 10.62% 86.57% # Number of insts issued each cycle 139system.cpu.iq.issued_per_cycle::4 5202284 7.26% 93.83% # Number of insts issued each cycle 140system.cpu.iq.issued_per_cycle::5 2658918 3.71% 97.54% # Number of insts issued each cycle 141system.cpu.iq.issued_per_cycle::6 1053563 1.47% 99.01% # Number of insts issued each cycle 142system.cpu.iq.issued_per_cycle::7 496311 0.69% 99.70% # Number of insts issued each cycle 143system.cpu.iq.issued_per_cycle::8 214186 0.30% 100.00% # Number of insts issued each cycle 144system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::total 71670018 # Number of insts issued each cycle 148system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 149system.cpu.iq.fu_full::IntAlu 81861 4.61% 4.61% # attempts to use FU when none available 150system.cpu.iq.fu_full::IntMult 0 0.00% 4.61% # attempts to use FU when none available 151system.cpu.iq.fu_full::IntDiv 0 0.00% 4.61% # attempts to use FU when none available 152system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.61% # attempts to use FU when none available 153system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.61% # attempts to use FU when none available 154system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.61% # attempts to use FU when none available 155system.cpu.iq.fu_full::FloatMult 0 0.00% 4.61% # attempts to use FU when none available 156system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.61% # attempts to use FU when none available 157system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.61% # attempts to use FU when none available 158system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.61% # attempts to use FU when none available 159system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.61% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.61% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.61% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.61% # attempts to use FU when none available 163system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.61% # attempts to use FU when none available 164system.cpu.iq.fu_full::SimdMult 0 0.00% 4.61% # attempts to use FU when none available 165system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.61% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdShift 0 0.00% 4.61% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.61% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.61% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.61% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.61% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.61% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.61% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.61% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.61% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.61% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.61% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.61% # attempts to use FU when none available 178system.cpu.iq.fu_full::MemRead 1408075 79.27% 83.88% # attempts to use FU when none available 179system.cpu.iq.fu_full::MemWrite 286311 16.12% 100.00% # attempts to use FU when none available 180system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 181system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 182system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 183system.cpu.iq.FU_type_0::IntAlu 56941286 53.35% 53.35% # Type of FU issued 184system.cpu.iq.FU_type_0::IntMult 86568 0.08% 53.43% # Type of FU issued 185system.cpu.iq.FU_type_0::IntDiv 0 0.00% 53.43% # Type of FU issued 186system.cpu.iq.FU_type_0::FloatAdd 21 0.00% 53.43% # Type of FU issued 187system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 53.43% # Type of FU issued 188system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 53.43% # Type of FU issued 189system.cpu.iq.FU_type_0::FloatMult 0 0.00% 53.43% # Type of FU issued 190system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 53.43% # Type of FU issued 191system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 53.43% # Type of FU issued 192system.cpu.iq.FU_type_0::SimdAdd 2 0.00% 53.43% # Type of FU issued 193system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 53.43% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 53.43% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 53.43% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 53.43% # Type of FU issued 197system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 53.43% # Type of FU issued 198system.cpu.iq.FU_type_0::SimdMult 0 0.00% 53.43% # Type of FU issued 199system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 53.43% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdShift 0 0.00% 53.43% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 53.43% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 53.43% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 53.43% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 53.43% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 53.43% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 53.43% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 53.43% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 53.43% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 53.43% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 53.43% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 53.43% # Type of FU issued 212system.cpu.iq.FU_type_0::MemRead 28575402 26.77% 80.20% # Type of FU issued 213system.cpu.iq.FU_type_0::MemWrite 21132684 19.80% 100.00% # Type of FU issued 214system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 215system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 216system.cpu.iq.FU_type_0::total 106735970 # Type of FU issued 217system.cpu.iq.rate 1.468242 # Inst issue rate 218system.cpu.iq.fu_busy_cnt 1776247 # FU busy when requested 219system.cpu.iq.fu_busy_rate 0.016642 # FU busy rate (busy events/executed inst) 220system.cpu.iq.int_inst_queue_reads 287029038 # Number of integer instruction queue reads 221system.cpu.iq.int_inst_queue_writes 122376660 # Number of integer instruction queue writes 222system.cpu.iq.int_inst_queue_wakeup_accesses 105058655 # Number of integer instruction queue wakeup accesses 223system.cpu.iq.fp_inst_queue_reads 171 # Number of floating instruction queue reads 224system.cpu.iq.fp_inst_queue_writes 178 # Number of floating instruction queue writes 225system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses 226system.cpu.iq.int_alu_accesses 108512130 # Number of integer alu accesses 227system.cpu.iq.fp_alu_accesses 87 # Number of floating point alu accesses 228system.cpu.iew.lsq.thread0.forwLoads 1096048 # Number of loads that had data forwarded from stores 229system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 230system.cpu.iew.lsq.thread0.squashedLoads 2243776 # Number of loads squashed 231system.cpu.iew.lsq.thread0.ignoredResponses 2146 # Number of memory responses ignored because the instruction is squashed 232system.cpu.iew.lsq.thread0.memOrderViolation 9239 # Number of memory ordering violations 233system.cpu.iew.lsq.thread0.squashedStores 1470884 # Number of stores squashed 234system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 235system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 236system.cpu.iew.lsq.thread0.rescheduledLoads 41 # Number of loads that were rescheduled 237system.cpu.iew.lsq.thread0.cacheBlocked 45 # Number of times an access to memory failed due to the cache being blocked 238system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 239system.cpu.iew.iewSquashCycles 1821642 # Number of cycles IEW is squashing 240system.cpu.iew.iewBlockCycles 971169 # Number of cycles IEW is blocking 241system.cpu.iew.iewUnblockCycles 52846 # Number of cycles IEW is unblocking 242system.cpu.iew.iewDispatchedInsts 111742721 # Number of instructions dispatched to IQ 243system.cpu.iew.iewDispSquashedInsts 886869 # Number of squashed instructions skipped by dispatch 244system.cpu.iew.iewDispLoadInsts 29552116 # Number of dispatched load instructions 245system.cpu.iew.iewDispStoreInsts 22027852 # Number of dispatched store instructions 246system.cpu.iew.iewDispNonSpecInsts 732058 # Number of dispatched non-speculative instructions 247system.cpu.iew.iewIQFullEvents 3681 # Number of times the IQ has become full, causing a stall 248system.cpu.iew.iewLSQFullEvents 5880 # Number of times the LSQ has become full, causing a stall 249system.cpu.iew.memOrderViolationEvents 9239 # Number of memory order violations 250system.cpu.iew.predictedTakenIncorrect 680356 # Number of branches that were predicted taken incorrectly 251system.cpu.iew.predictedNotTakenIncorrect 238968 # Number of branches that were predicted not taken incorrectly 252system.cpu.iew.branchMispredicts 919324 # Number of branch mispredicts detected at execute 253system.cpu.iew.iewExecutedInsts 105624762 # Number of executed instructions 254system.cpu.iew.iewExecLoadInsts 28223458 # Number of load instructions executed 255system.cpu.iew.iewExecSquashedInsts 1111208 # Number of squashed instructions skipped in execute 256system.cpu.iew.exec_swp 0 # number of swp insts executed 257system.cpu.iew.exec_nop 77009 # number of nop insts executed 258system.cpu.iew.exec_refs 49234670 # number of memory reference insts executed 259system.cpu.iew.exec_branches 14652571 # Number of branches executed 260system.cpu.iew.exec_stores 21011212 # Number of stores executed 261system.cpu.iew.exec_rate 1.452957 # Inst execution rate 262system.cpu.iew.wb_sent 105223313 # cumulative count of insts sent to commit 263system.cpu.iew.wb_count 105058729 # cumulative count of insts written-back 264system.cpu.iew.wb_producers 51964381 # num instructions producing a value 265system.cpu.iew.wb_consumers 99748825 # num instructions consuming a value 266system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 267system.cpu.iew.wb_rate 1.445171 # insts written-back per cycle 268system.cpu.iew.wb_fanout 0.520952 # average fanout of values written-back 269system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 270system.cpu.commit.commitCommittedInsts 100638587 # The number of committed instructions 271system.cpu.commit.commitSquashedInsts 11026953 # The number of squashed insts skipped by commit 272system.cpu.commit.commitNonSpecStalls 700860 # The number of times commit has been forced to stall to communicate backwards 273system.cpu.commit.branchMispredicts 821298 # The number of times a branch was mispredicted 274system.cpu.commit.committed_per_cycle::samples 69848377 # Number of insts commited each cycle 275system.cpu.commit.committed_per_cycle::mean 1.440815 # Number of insts commited each cycle 276system.cpu.commit.committed_per_cycle::stdev 2.128695 # Number of insts commited each cycle 277system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 278system.cpu.commit.committed_per_cycle::0 31252601 44.74% 44.74% # Number of insts commited each cycle 279system.cpu.commit.committed_per_cycle::1 20067748 28.73% 73.47% # Number of insts commited each cycle 280system.cpu.commit.committed_per_cycle::2 4700774 6.73% 80.20% # Number of insts commited each cycle 281system.cpu.commit.committed_per_cycle::3 4062261 5.82% 86.02% # Number of insts commited each cycle 282system.cpu.commit.committed_per_cycle::4 3060219 4.38% 90.40% # Number of insts commited each cycle 283system.cpu.commit.committed_per_cycle::5 1682719 2.41% 92.81% # Number of insts commited each cycle 284system.cpu.commit.committed_per_cycle::6 680213 0.97% 93.78% # Number of insts commited each cycle 285system.cpu.commit.committed_per_cycle::7 487977 0.70% 94.48% # Number of insts commited each cycle 286system.cpu.commit.committed_per_cycle::8 3853865 5.52% 100.00% # Number of insts commited each cycle 287system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 288system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 289system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::total 69848377 # Number of insts commited each cycle 291system.cpu.commit.count 100638587 # Number of instructions committed 292system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 293system.cpu.commit.refs 47865307 # Number of memory references committed 294system.cpu.commit.loads 27308339 # Number of loads committed 295system.cpu.commit.membars 15920 # Number of memory barriers committed 296system.cpu.commit.branches 13669858 # Number of branches committed 297system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 298system.cpu.commit.int_insts 91477707 # Number of committed integer instructions. 299system.cpu.commit.function_calls 1679850 # Number of function calls committed. 300system.cpu.commit.bw_lim_events 3853865 # number cycles where commit BW limit reached 301system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 302system.cpu.rob.rob_reads 177634753 # The number of ROB reads 303system.cpu.rob.rob_writes 225156428 # The number of ROB writes 304system.cpu.timesIdled 61363 # Number of times that the entire CPU went into an idle state and unscheduled itself 305system.cpu.idleCycles 1026403 # Total number of cycles that the CPU has spent unscheduled due to idling 306system.cpu.committedInsts 100633035 # Number of Instructions Simulated 307system.cpu.committedInsts_total 100633035 # Number of Instructions Simulated 308system.cpu.cpi 0.722391 # CPI: Cycles Per Instruction 309system.cpu.cpi_total 0.722391 # CPI: Total CPI of All Threads 310system.cpu.ipc 1.384291 # IPC: Instructions Per Cycle 311system.cpu.ipc_total 1.384291 # IPC: Total IPC of All Threads 312system.cpu.int_regfile_reads 508078422 # number of integer regfile reads 313system.cpu.int_regfile_writes 103555080 # number of integer regfile writes 314system.cpu.fp_regfile_reads 153 # number of floating regfile reads 315system.cpu.fp_regfile_writes 125 # number of floating regfile writes 316system.cpu.misc_regfile_reads 144338885 # number of misc regfile reads 317system.cpu.misc_regfile_writes 34300 # number of misc regfile writes 318system.cpu.icache.replacements 23105 # number of replacements 319system.cpu.icache.tagsinuse 1790.585512 # Cycle average of tags in use 320system.cpu.icache.total_refs 11649212 # Total number of references to valid blocks. 321system.cpu.icache.sampled_refs 25136 # Sample count of references to valid blocks. 322system.cpu.icache.avg_refs 463.447327 # Average number of references to valid blocks. 323system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 324system.cpu.icache.occ_blocks::0 1790.585512 # Average occupied blocks per context 325system.cpu.icache.occ_percent::0 0.874309 # Average percentage of cache occupancy 326system.cpu.icache.ReadReq_hits 11649212 # number of ReadReq hits 327system.cpu.icache.demand_hits 11649212 # number of demand (read+write) hits 328system.cpu.icache.overall_hits 11649212 # number of overall hits 329system.cpu.icache.ReadReq_misses 26020 # number of ReadReq misses 330system.cpu.icache.demand_misses 26020 # number of demand (read+write) misses 331system.cpu.icache.overall_misses 26020 # number of overall misses 332system.cpu.icache.ReadReq_miss_latency 329928500 # number of ReadReq miss cycles 333system.cpu.icache.demand_miss_latency 329928500 # number of demand (read+write) miss cycles 334system.cpu.icache.overall_miss_latency 329928500 # number of overall miss cycles 335system.cpu.icache.ReadReq_accesses 11675232 # number of ReadReq accesses(hits+misses) 336system.cpu.icache.demand_accesses 11675232 # number of demand (read+write) accesses 337system.cpu.icache.overall_accesses 11675232 # number of overall (read+write) accesses 338system.cpu.icache.ReadReq_miss_rate 0.002229 # miss rate for ReadReq accesses 339system.cpu.icache.demand_miss_rate 0.002229 # miss rate for demand accesses 340system.cpu.icache.overall_miss_rate 0.002229 # miss rate for overall accesses 341system.cpu.icache.ReadReq_avg_miss_latency 12679.803997 # average ReadReq miss latency 342system.cpu.icache.demand_avg_miss_latency 12679.803997 # average overall miss latency 343system.cpu.icache.overall_avg_miss_latency 12679.803997 # average overall miss latency 344system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 345system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 346system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 347system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 348system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 349system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 350system.cpu.icache.fast_writes 0 # number of fast writes performed 351system.cpu.icache.cache_copies 0 # number of cache copies performed 352system.cpu.icache.writebacks 0 # number of writebacks 353system.cpu.icache.ReadReq_mshr_hits 875 # number of ReadReq MSHR hits 354system.cpu.icache.demand_mshr_hits 875 # number of demand (read+write) MSHR hits 355system.cpu.icache.overall_mshr_hits 875 # number of overall MSHR hits 356system.cpu.icache.ReadReq_mshr_misses 25145 # number of ReadReq MSHR misses 357system.cpu.icache.demand_mshr_misses 25145 # number of demand (read+write) MSHR misses 358system.cpu.icache.overall_mshr_misses 25145 # number of overall MSHR misses 359system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 360system.cpu.icache.ReadReq_mshr_miss_latency 230769000 # number of ReadReq MSHR miss cycles 361system.cpu.icache.demand_mshr_miss_latency 230769000 # number of demand (read+write) MSHR miss cycles 362system.cpu.icache.overall_mshr_miss_latency 230769000 # number of overall MSHR miss cycles 363system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 364system.cpu.icache.ReadReq_mshr_miss_rate 0.002154 # mshr miss rate for ReadReq accesses 365system.cpu.icache.demand_mshr_miss_rate 0.002154 # mshr miss rate for demand accesses 366system.cpu.icache.overall_mshr_miss_rate 0.002154 # mshr miss rate for overall accesses 367system.cpu.icache.ReadReq_avg_mshr_miss_latency 9177.530324 # average ReadReq mshr miss latency 368system.cpu.icache.demand_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency 369system.cpu.icache.overall_avg_mshr_miss_latency 9177.530324 # average overall mshr miss latency 370system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 371system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 372system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 373system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 374system.cpu.dcache.replacements 157197 # number of replacements 375system.cpu.dcache.tagsinuse 4074.737833 # Cycle average of tags in use 376system.cpu.dcache.total_refs 45133660 # Total number of references to valid blocks. 377system.cpu.dcache.sampled_refs 161293 # Sample count of references to valid blocks. 378system.cpu.dcache.avg_refs 279.824047 # Average number of references to valid blocks. 379system.cpu.dcache.warmup_cycle 314597000 # Cycle when the warmup percentage was hit. 380system.cpu.dcache.occ_blocks::0 4074.737833 # Average occupied blocks per context 381system.cpu.dcache.occ_percent::0 0.994809 # Average percentage of cache occupancy 382system.cpu.dcache.ReadReq_hits 26793039 # number of ReadReq hits 383system.cpu.dcache.WriteReq_hits 18304159 # number of WriteReq hits 384system.cpu.dcache.LoadLockedReq_hits 19298 # number of LoadLockedReq hits 385system.cpu.dcache.StoreCondReq_hits 17149 # number of StoreCondReq hits 386system.cpu.dcache.demand_hits 45097198 # number of demand (read+write) hits 387system.cpu.dcache.overall_hits 45097198 # number of overall hits 388system.cpu.dcache.ReadReq_misses 104208 # number of ReadReq misses 389system.cpu.dcache.WriteReq_misses 1545742 # number of WriteReq misses 390system.cpu.dcache.LoadLockedReq_misses 31 # number of LoadLockedReq misses 391system.cpu.dcache.demand_misses 1649950 # number of demand (read+write) misses 392system.cpu.dcache.overall_misses 1649950 # number of overall misses 393system.cpu.dcache.ReadReq_miss_latency 2387617500 # number of ReadReq miss cycles 394system.cpu.dcache.WriteReq_miss_latency 50445288500 # number of WriteReq miss cycles 395system.cpu.dcache.LoadLockedReq_miss_latency 403500 # number of LoadLockedReq miss cycles 396system.cpu.dcache.demand_miss_latency 52832906000 # number of demand (read+write) miss cycles 397system.cpu.dcache.overall_miss_latency 52832906000 # number of overall miss cycles 398system.cpu.dcache.ReadReq_accesses 26897247 # number of ReadReq accesses(hits+misses) 399system.cpu.dcache.WriteReq_accesses 19849901 # number of WriteReq accesses(hits+misses) 400system.cpu.dcache.LoadLockedReq_accesses 19329 # number of LoadLockedReq accesses(hits+misses) 401system.cpu.dcache.StoreCondReq_accesses 17149 # number of StoreCondReq accesses(hits+misses) 402system.cpu.dcache.demand_accesses 46747148 # number of demand (read+write) accesses 403system.cpu.dcache.overall_accesses 46747148 # number of overall (read+write) accesses 404system.cpu.dcache.ReadReq_miss_rate 0.003874 # miss rate for ReadReq accesses 405system.cpu.dcache.WriteReq_miss_rate 0.077872 # miss rate for WriteReq accesses 406system.cpu.dcache.LoadLockedReq_miss_rate 0.001604 # miss rate for LoadLockedReq accesses 407system.cpu.dcache.demand_miss_rate 0.035295 # miss rate for demand accesses 408system.cpu.dcache.overall_miss_rate 0.035295 # miss rate for overall accesses 409system.cpu.dcache.ReadReq_avg_miss_latency 22912.036504 # average ReadReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency 32634.998920 # average WriteReq miss latency 411system.cpu.dcache.LoadLockedReq_avg_miss_latency 13016.129032 # average LoadLockedReq miss latency 412system.cpu.dcache.demand_avg_miss_latency 32020.913361 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency 32020.913361 # average overall miss latency 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 170000 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets 18888.888889 # average number of cycles each access was blocked 420system.cpu.dcache.fast_writes 0 # number of fast writes performed 421system.cpu.dcache.cache_copies 0 # number of cache copies performed 422system.cpu.dcache.writebacks 123219 # number of writebacks 423system.cpu.dcache.ReadReq_mshr_hits 49816 # number of ReadReq MSHR hits 424system.cpu.dcache.WriteReq_mshr_hits 1438831 # number of WriteReq MSHR hits 425system.cpu.dcache.LoadLockedReq_mshr_hits 31 # number of LoadLockedReq MSHR hits 426system.cpu.dcache.demand_mshr_hits 1488647 # number of demand (read+write) MSHR hits 427system.cpu.dcache.overall_mshr_hits 1488647 # number of overall MSHR hits 428system.cpu.dcache.ReadReq_mshr_misses 54392 # number of ReadReq MSHR misses 429system.cpu.dcache.WriteReq_mshr_misses 106911 # number of WriteReq MSHR misses 430system.cpu.dcache.demand_mshr_misses 161303 # number of demand (read+write) MSHR misses 431system.cpu.dcache.overall_mshr_misses 161303 # number of overall MSHR misses 432system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 433system.cpu.dcache.ReadReq_mshr_miss_latency 1030956000 # number of ReadReq MSHR miss cycles 434system.cpu.dcache.WriteReq_mshr_miss_latency 3651524500 # number of WriteReq MSHR miss cycles 435system.cpu.dcache.demand_mshr_miss_latency 4682480500 # number of demand (read+write) MSHR miss cycles 436system.cpu.dcache.overall_mshr_miss_latency 4682480500 # number of overall MSHR miss cycles 437system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 438system.cpu.dcache.ReadReq_mshr_miss_rate 0.002022 # mshr miss rate for ReadReq accesses 439system.cpu.dcache.WriteReq_mshr_miss_rate 0.005386 # mshr miss rate for WriteReq accesses 440system.cpu.dcache.demand_mshr_miss_rate 0.003451 # mshr miss rate for demand accesses 441system.cpu.dcache.overall_mshr_miss_rate 0.003451 # mshr miss rate for overall accesses 442system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18954.184439 # average ReadReq mshr miss latency 443system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34154.806334 # average WriteReq mshr miss latency 444system.cpu.dcache.demand_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency 445system.cpu.dcache.overall_avg_mshr_miss_latency 29029.097413 # average overall mshr miss latency 446system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 447system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 448system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 449system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 450system.cpu.l2cache.replacements 114546 # number of replacements 451system.cpu.l2cache.tagsinuse 18280.291791 # Cycle average of tags in use 452system.cpu.l2cache.total_refs 68908 # Total number of references to valid blocks. 453system.cpu.l2cache.sampled_refs 133392 # Sample count of references to valid blocks. 454system.cpu.l2cache.avg_refs 0.516583 # Average number of references to valid blocks. 455system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 456system.cpu.l2cache.occ_blocks::0 2302.452210 # Average occupied blocks per context 457system.cpu.l2cache.occ_blocks::1 15977.839581 # Average occupied blocks per context 458system.cpu.l2cache.occ_percent::0 0.070265 # Average percentage of cache occupancy 459system.cpu.l2cache.occ_percent::1 0.487605 # Average percentage of cache occupancy 460system.cpu.l2cache.ReadReq_hits 47261 # number of ReadReq hits 461system.cpu.l2cache.Writeback_hits 123219 # number of Writeback hits 462system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits 463system.cpu.l2cache.ReadExReq_hits 4298 # number of ReadExReq hits 464system.cpu.l2cache.demand_hits 51559 # number of demand (read+write) hits 465system.cpu.l2cache.overall_hits 51559 # number of overall hits 466system.cpu.l2cache.ReadReq_misses 32262 # number of ReadReq misses 467system.cpu.l2cache.UpgradeReq_misses 4 # number of UpgradeReq misses 468system.cpu.l2cache.ReadExReq_misses 102605 # number of ReadExReq misses 469system.cpu.l2cache.demand_misses 134867 # number of demand (read+write) misses 470system.cpu.l2cache.overall_misses 134867 # number of overall misses 471system.cpu.l2cache.ReadReq_miss_latency 1107753000 # number of ReadReq miss cycles 472system.cpu.l2cache.UpgradeReq_miss_latency 34000 # number of UpgradeReq miss cycles 473system.cpu.l2cache.ReadExReq_miss_latency 3528908000 # number of ReadExReq miss cycles 474system.cpu.l2cache.demand_miss_latency 4636661000 # number of demand (read+write) miss cycles 475system.cpu.l2cache.overall_miss_latency 4636661000 # number of overall miss cycles 476system.cpu.l2cache.ReadReq_accesses 79523 # number of ReadReq accesses(hits+misses) 477system.cpu.l2cache.Writeback_accesses 123219 # number of Writeback accesses(hits+misses) 478system.cpu.l2cache.UpgradeReq_accesses 9 # number of UpgradeReq accesses(hits+misses) 479system.cpu.l2cache.ReadExReq_accesses 106903 # number of ReadExReq accesses(hits+misses) 480system.cpu.l2cache.demand_accesses 186426 # number of demand (read+write) accesses 481system.cpu.l2cache.overall_accesses 186426 # number of overall (read+write) accesses 482system.cpu.l2cache.ReadReq_miss_rate 0.405694 # miss rate for ReadReq accesses 483system.cpu.l2cache.UpgradeReq_miss_rate 0.444444 # miss rate for UpgradeReq accesses 484system.cpu.l2cache.ReadExReq_miss_rate 0.959795 # miss rate for ReadExReq accesses 485system.cpu.l2cache.demand_miss_rate 0.723434 # miss rate for demand accesses 486system.cpu.l2cache.overall_miss_rate 0.723434 # miss rate for overall accesses 487system.cpu.l2cache.ReadReq_avg_miss_latency 34336.153989 # average ReadReq miss latency 488system.cpu.l2cache.UpgradeReq_avg_miss_latency 8500 # average UpgradeReq miss latency 489system.cpu.l2cache.ReadExReq_avg_miss_latency 34393.138736 # average ReadExReq miss latency 490system.cpu.l2cache.demand_avg_miss_latency 34379.507218 # average overall miss latency 491system.cpu.l2cache.overall_avg_miss_latency 34379.507218 # average overall miss latency 492system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 493system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 494system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 495system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 496system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 497system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 498system.cpu.l2cache.fast_writes 0 # number of fast writes performed 499system.cpu.l2cache.cache_copies 0 # number of cache copies performed 500system.cpu.l2cache.writebacks 88455 # number of writebacks 501system.cpu.l2cache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits 502system.cpu.l2cache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits 503system.cpu.l2cache.overall_mshr_hits 63 # number of overall MSHR hits 504system.cpu.l2cache.ReadReq_mshr_misses 32199 # number of ReadReq MSHR misses 505system.cpu.l2cache.UpgradeReq_mshr_misses 4 # number of UpgradeReq MSHR misses 506system.cpu.l2cache.ReadExReq_mshr_misses 102605 # number of ReadExReq MSHR misses 507system.cpu.l2cache.demand_mshr_misses 134804 # number of demand (read+write) MSHR misses 508system.cpu.l2cache.overall_mshr_misses 134804 # number of overall MSHR misses 509system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 510system.cpu.l2cache.ReadReq_mshr_miss_latency 1001736500 # number of ReadReq MSHR miss cycles 511system.cpu.l2cache.UpgradeReq_mshr_miss_latency 124000 # number of UpgradeReq MSHR miss cycles 512system.cpu.l2cache.ReadExReq_mshr_miss_latency 3205255000 # number of ReadExReq MSHR miss cycles 513system.cpu.l2cache.demand_mshr_miss_latency 4206991500 # number of demand (read+write) MSHR miss cycles 514system.cpu.l2cache.overall_mshr_miss_latency 4206991500 # number of overall MSHR miss cycles 515system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 516system.cpu.l2cache.ReadReq_mshr_miss_rate 0.404902 # mshr miss rate for ReadReq accesses 517system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.444444 # mshr miss rate for UpgradeReq accesses 518system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959795 # mshr miss rate for ReadExReq accesses 519system.cpu.l2cache.demand_mshr_miss_rate 0.723097 # mshr miss rate for demand accesses 520system.cpu.l2cache.overall_mshr_miss_rate 0.723097 # mshr miss rate for overall accesses 521system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31110.795366 # average ReadReq mshr miss latency 522system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency 523system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31238.779787 # average ReadExReq mshr miss latency 524system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency 525system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.209697 # average overall mshr miss latency 526system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 527system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 528system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 529system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 530 531---------- End Simulation Statistics ---------- 532