stats.txt revision 7860
1 2---------- Begin Simulation Statistics ---------- 3host_inst_rate 156565 # Simulator instruction rate (inst/s) 4host_mem_usage 260328 # Number of bytes of host memory used 5host_seconds 631.29 # Real time elapsed on the host 6host_tick_rate 93871242 # Simulator tick rate (ticks/s) 7sim_freq 1000000000000 # Frequency of simulated ticks 8sim_insts 98838077 # Number of instructions simulated 9sim_seconds 0.059260 # Number of seconds simulated 10sim_ticks 59259979500 # Number of ticks simulated 11system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 12system.cpu.BPredUnit.BTBHits 10631376 # Number of BTB hits 13system.cpu.BPredUnit.BTBLookups 17355232 # Number of BTB lookups 14system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 15system.cpu.BPredUnit.condIncorrect 914560 # Number of conditional branches incorrect 16system.cpu.BPredUnit.condPredicted 17451382 # Number of conditional branches predicted 17system.cpu.BPredUnit.lookups 17451382 # Number of BP lookups 18system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 19system.cpu.commit.COM:branches 12133384 # Number of branches committed 20system.cpu.commit.COM:bw_lim_events 1268932 # number cycles where commit BW limit reached 21system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits 22system.cpu.commit.COM:committed_per_cycle::samples 114018884 # Number of insts commited each cycle 23system.cpu.commit.COM:committed_per_cycle::mean 0.866857 # Number of insts commited each cycle 24system.cpu.commit.COM:committed_per_cycle::stdev 1.400756 # Number of insts commited each cycle 25system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 26system.cpu.commit.COM:committed_per_cycle::0 59418042 52.11% 52.11% # Number of insts commited each cycle 27system.cpu.commit.COM:committed_per_cycle::1 36575306 32.08% 84.19% # Number of insts commited each cycle 28system.cpu.commit.COM:committed_per_cycle::2 7815756 6.85% 91.05% # Number of insts commited each cycle 29system.cpu.commit.COM:committed_per_cycle::3 3335762 2.93% 93.97% # Number of insts commited each cycle 30system.cpu.commit.COM:committed_per_cycle::4 3218602 2.82% 96.79% # Number of insts commited each cycle 31system.cpu.commit.COM:committed_per_cycle::5 1142108 1.00% 97.80% # Number of insts commited each cycle 32system.cpu.commit.COM:committed_per_cycle::6 823063 0.72% 98.52% # Number of insts commited each cycle 33system.cpu.commit.COM:committed_per_cycle::7 421313 0.37% 98.89% # Number of insts commited each cycle 34system.cpu.commit.COM:committed_per_cycle::8 1268932 1.11% 100.00% # Number of insts commited each cycle 35system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 36system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle 37system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle 38system.cpu.commit.COM:committed_per_cycle::total 114018884 # Number of insts commited each cycle 39system.cpu.commit.COM:count 98838077 # Number of instructions committed 40system.cpu.commit.COM:loads 27315295 # Number of loads committed 41system.cpu.commit.COM:membars 0 # Number of memory barriers committed 42system.cpu.commit.COM:refs 47871033 # Number of memory references committed 43system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed 44system.cpu.commit.branchMispredicts 2496869 # The number of times a branch was mispredicted 45system.cpu.commit.commitCommittedInsts 98838077 # The number of committed instructions 46system.cpu.commit.commitNonSpecStalls 667791 # The number of times commit has been forced to stall to communicate backwards 47system.cpu.commit.commitSquashedInsts 18231626 # The number of squashed insts skipped by commit 48system.cpu.committedInsts 98838077 # Number of Instructions Simulated 49system.cpu.committedInsts_total 98838077 # Number of Instructions Simulated 50system.cpu.cpi 1.199133 # CPI: Cycles Per Instruction 51system.cpu.cpi_total 1.199133 # CPI: Total CPI of All Threads 52system.cpu.dcache.ReadReq_accesses 28495397 # number of ReadReq accesses(hits+misses) 53system.cpu.dcache.ReadReq_avg_miss_latency 22617.028157 # average ReadReq miss latency 54system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18828.183694 # average ReadReq mshr miss latency 55system.cpu.dcache.ReadReq_hits 28388709 # number of ReadReq hits 56system.cpu.dcache.ReadReq_miss_latency 2412965500 # number of ReadReq miss cycles 57system.cpu.dcache.ReadReq_miss_rate 0.003744 # miss rate for ReadReq accesses 58system.cpu.dcache.ReadReq_misses 106688 # number of ReadReq misses 59system.cpu.dcache.ReadReq_mshr_hits 49985 # number of ReadReq MSHR hits 60system.cpu.dcache.ReadReq_mshr_miss_latency 1067614500 # number of ReadReq MSHR miss cycles 61system.cpu.dcache.ReadReq_mshr_miss_rate 0.001990 # mshr miss rate for ReadReq accesses 62system.cpu.dcache.ReadReq_mshr_misses 56703 # number of ReadReq MSHR misses 63system.cpu.dcache.WriteReq_accesses 19865820 # number of WriteReq accesses(hits+misses) 64system.cpu.dcache.WriteReq_avg_miss_latency 32612.870291 # average WriteReq miss latency 65system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34110.136388 # average WriteReq mshr miss latency 66system.cpu.dcache.WriteReq_hits 18320719 # number of WriteReq hits 67system.cpu.dcache.WriteReq_miss_latency 50390178500 # number of WriteReq miss cycles 68system.cpu.dcache.WriteReq_miss_rate 0.077777 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses 1545101 # number of WriteReq misses 70system.cpu.dcache.WriteReq_mshr_hits 1438347 # number of WriteReq MSHR hits 71system.cpu.dcache.WriteReq_mshr_miss_latency 3641393500 # number of WriteReq MSHR miss cycles 72system.cpu.dcache.WriteReq_mshr_miss_rate 0.005374 # mshr miss rate for WriteReq accesses 73system.cpu.dcache.WriteReq_mshr_misses 106754 # number of WriteReq MSHR misses 74system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 75system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked 76system.cpu.dcache.avg_refs 285.786157 # Average number of references to valid blocks. 77system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 79system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked 81system.cpu.dcache.cache_copies 0 # number of cache copies performed 82system.cpu.dcache.demand_accesses 48361217 # number of demand (read+write) accesses 83system.cpu.dcache.demand_avg_miss_latency 31967.245211 # average overall miss latency 84system.cpu.dcache.demand_avg_mshr_miss_latency 28808.848810 # average overall mshr miss latency 85system.cpu.dcache.demand_hits 46709428 # number of demand (read+write) hits 86system.cpu.dcache.demand_miss_latency 52803144000 # number of demand (read+write) miss cycles 87system.cpu.dcache.demand_miss_rate 0.034155 # miss rate for demand accesses 88system.cpu.dcache.demand_misses 1651789 # number of demand (read+write) misses 89system.cpu.dcache.demand_mshr_hits 1488332 # number of demand (read+write) MSHR hits 90system.cpu.dcache.demand_mshr_miss_latency 4709008000 # number of demand (read+write) MSHR miss cycles 91system.cpu.dcache.demand_mshr_miss_rate 0.003380 # mshr miss rate for demand accesses 92system.cpu.dcache.demand_mshr_misses 163457 # number of demand (read+write) MSHR misses 93system.cpu.dcache.fast_writes 0 # number of fast writes performed 94system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 95system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 96system.cpu.dcache.occ_%::0 0.995663 # Average percentage of cache occupancy 97system.cpu.dcache.occ_blocks::0 4078.236319 # Average occupied blocks per context 98system.cpu.dcache.overall_accesses 48361217 # number of overall (read+write) accesses 99system.cpu.dcache.overall_avg_miss_latency 31967.245211 # average overall miss latency 100system.cpu.dcache.overall_avg_mshr_miss_latency 28808.848810 # average overall mshr miss latency 101system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 102system.cpu.dcache.overall_hits 46709428 # number of overall hits 103system.cpu.dcache.overall_miss_latency 52803144000 # number of overall miss cycles 104system.cpu.dcache.overall_miss_rate 0.034155 # miss rate for overall accesses 105system.cpu.dcache.overall_misses 1651789 # number of overall misses 106system.cpu.dcache.overall_mshr_hits 1488332 # number of overall MSHR hits 107system.cpu.dcache.overall_mshr_miss_latency 4709008000 # number of overall MSHR miss cycles 108system.cpu.dcache.overall_mshr_miss_rate 0.003380 # mshr miss rate for overall accesses 109system.cpu.dcache.overall_mshr_misses 163457 # number of overall MSHR misses 110system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 111system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 112system.cpu.dcache.replacements 159346 # number of replacements 113system.cpu.dcache.sampled_refs 163442 # Sample count of references to valid blocks. 114system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 115system.cpu.dcache.tagsinuse 4078.236319 # Cycle average of tags in use 116system.cpu.dcache.total_refs 46709461 # Total number of references to valid blocks. 117system.cpu.dcache.warmup_cycle 393981000 # Cycle when the warmup percentage was hit. 118system.cpu.dcache.writebacks 124385 # number of writebacks 119system.cpu.decode.DECODE:BlockedCycles 14942645 # Number of cycles decode is blocked 120system.cpu.decode.DECODE:DecodedInsts 127014948 # Number of instructions handled by decode 121system.cpu.decode.DECODE:IdleCycles 27511704 # Number of cycles decode is idle 122system.cpu.decode.DECODE:RunCycles 70998513 # Number of cycles decode is running 123system.cpu.decode.DECODE:SquashCycles 3514572 # Number of cycles decode is squashing 124system.cpu.decode.DECODE:UnblockCycles 566022 # Number of cycles decode is unblocking 125system.cpu.dtb.accesses 0 # DTB accesses 126system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 127system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 128system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 129system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 130system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 131system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 132system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 133system.cpu.dtb.hits 0 # DTB hits 134system.cpu.dtb.inst_accesses 0 # ITB inst accesses 135system.cpu.dtb.inst_hits 0 # ITB inst hits 136system.cpu.dtb.inst_misses 0 # ITB inst misses 137system.cpu.dtb.misses 0 # DTB misses 138system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 139system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 140system.cpu.dtb.read_accesses 0 # DTB read accesses 141system.cpu.dtb.read_hits 0 # DTB read hits 142system.cpu.dtb.read_misses 0 # DTB read misses 143system.cpu.dtb.write_accesses 0 # DTB write accesses 144system.cpu.dtb.write_hits 0 # DTB write hits 145system.cpu.dtb.write_misses 0 # DTB write misses 146system.cpu.fetch.Branches 17451382 # Number of branches that fetch encountered 147system.cpu.fetch.CacheLines 12122688 # Number of cache lines fetched 148system.cpu.fetch.Cycles 73872074 # Number of cycles fetch has run and was not squashing or blocked 149system.cpu.fetch.IcacheSquashes 96174 # Number of outstanding Icache misses that were squashed 150system.cpu.fetch.Insts 95885012 # Number of instructions fetch has processed 151system.cpu.fetch.MiscStallCycles 34128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 152system.cpu.fetch.SquashCycles 2507897 # Number of cycles fetch has spent squashing 153system.cpu.fetch.branchRate 0.147244 # Number of branch fetches per cycle 154system.cpu.fetch.icacheStallCycles 12122688 # Number of cycles fetch is stalled on an Icache miss 155system.cpu.fetch.predictedBranches 10631376 # Number of branches that fetch has predicted taken 156system.cpu.fetch.rate 0.809020 # Number of inst fetches per cycle 157system.cpu.fetch.rateDist::samples 117533456 # Number of instructions fetched each cycle (Total) 158system.cpu.fetch.rateDist::mean 1.108172 # Number of instructions fetched each cycle (Total) 159system.cpu.fetch.rateDist::stdev 1.634523 # Number of instructions fetched each cycle (Total) 160system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 161system.cpu.fetch.rateDist::0 43866274 37.32% 37.32% # Number of instructions fetched each cycle (Total) 162system.cpu.fetch.rateDist::1 53998301 45.94% 83.27% # Number of instructions fetched each cycle (Total) 163system.cpu.fetch.rateDist::2 9118937 7.76% 91.02% # Number of instructions fetched each cycle (Total) 164system.cpu.fetch.rateDist::3 3358983 2.86% 93.88% # Number of instructions fetched each cycle (Total) 165system.cpu.fetch.rateDist::4 1352835 1.15% 95.03% # Number of instructions fetched each cycle (Total) 166system.cpu.fetch.rateDist::5 476061 0.41% 95.44% # Number of instructions fetched each cycle (Total) 167system.cpu.fetch.rateDist::6 1116299 0.95% 96.39% # Number of instructions fetched each cycle (Total) 168system.cpu.fetch.rateDist::7 521407 0.44% 96.83% # Number of instructions fetched each cycle (Total) 169system.cpu.fetch.rateDist::8 3724359 3.17% 100.00% # Number of instructions fetched each cycle (Total) 170system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 171system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 172system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 173system.cpu.fetch.rateDist::total 117533456 # Number of instructions fetched each cycle (Total) 174system.cpu.icache.ReadReq_accesses 12122688 # number of ReadReq accesses(hits+misses) 175system.cpu.icache.ReadReq_avg_miss_latency 12759.423411 # average ReadReq miss latency 176system.cpu.icache.ReadReq_avg_mshr_miss_latency 9476.994450 # average ReadReq mshr miss latency 177system.cpu.icache.ReadReq_hits 12098546 # number of ReadReq hits 178system.cpu.icache.ReadReq_miss_latency 308038000 # number of ReadReq miss cycles 179system.cpu.icache.ReadReq_miss_rate 0.001991 # miss rate for ReadReq accesses 180system.cpu.icache.ReadReq_misses 24142 # number of ReadReq misses 181system.cpu.icache.ReadReq_mshr_hits 539 # number of ReadReq MSHR hits 182system.cpu.icache.ReadReq_mshr_miss_latency 223685500 # number of ReadReq MSHR miss cycles 183system.cpu.icache.ReadReq_mshr_miss_rate 0.001947 # mshr miss rate for ReadReq accesses 184system.cpu.icache.ReadReq_mshr_misses 23603 # number of ReadReq MSHR misses 185system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 186system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 187system.cpu.icache.avg_refs 512.911056 # Average number of references to valid blocks. 188system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 189system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 190system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 191system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 192system.cpu.icache.cache_copies 0 # number of cache copies performed 193system.cpu.icache.demand_accesses 12122688 # number of demand (read+write) accesses 194system.cpu.icache.demand_avg_miss_latency 12759.423411 # average overall miss latency 195system.cpu.icache.demand_avg_mshr_miss_latency 9476.994450 # average overall mshr miss latency 196system.cpu.icache.demand_hits 12098546 # number of demand (read+write) hits 197system.cpu.icache.demand_miss_latency 308038000 # number of demand (read+write) miss cycles 198system.cpu.icache.demand_miss_rate 0.001991 # miss rate for demand accesses 199system.cpu.icache.demand_misses 24142 # number of demand (read+write) misses 200system.cpu.icache.demand_mshr_hits 539 # number of demand (read+write) MSHR hits 201system.cpu.icache.demand_mshr_miss_latency 223685500 # number of demand (read+write) MSHR miss cycles 202system.cpu.icache.demand_mshr_miss_rate 0.001947 # mshr miss rate for demand accesses 203system.cpu.icache.demand_mshr_misses 23603 # number of demand (read+write) MSHR misses 204system.cpu.icache.fast_writes 0 # number of fast writes performed 205system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 206system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 207system.cpu.icache.occ_%::0 0.878284 # Average percentage of cache occupancy 208system.cpu.icache.occ_blocks::0 1798.726213 # Average occupied blocks per context 209system.cpu.icache.overall_accesses 12122688 # number of overall (read+write) accesses 210system.cpu.icache.overall_avg_miss_latency 12759.423411 # average overall miss latency 211system.cpu.icache.overall_avg_mshr_miss_latency 9476.994450 # average overall mshr miss latency 212system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 213system.cpu.icache.overall_hits 12098546 # number of overall hits 214system.cpu.icache.overall_miss_latency 308038000 # number of overall miss cycles 215system.cpu.icache.overall_miss_rate 0.001991 # miss rate for overall accesses 216system.cpu.icache.overall_misses 24142 # number of overall misses 217system.cpu.icache.overall_mshr_hits 539 # number of overall MSHR hits 218system.cpu.icache.overall_mshr_miss_latency 223685500 # number of overall MSHR miss cycles 219system.cpu.icache.overall_mshr_miss_rate 0.001947 # mshr miss rate for overall accesses 220system.cpu.icache.overall_mshr_misses 23603 # number of overall MSHR misses 221system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 222system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 223system.cpu.icache.replacements 21558 # number of replacements 224system.cpu.icache.sampled_refs 23588 # Sample count of references to valid blocks. 225system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 226system.cpu.icache.tagsinuse 1798.726213 # Cycle average of tags in use 227system.cpu.icache.total_refs 12098546 # Total number of references to valid blocks. 228system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 229system.cpu.icache.writebacks 0 # number of writebacks 230system.cpu.idleCycles 986504 # Total number of cycles that the CPU has spent unscheduled due to idling 231system.cpu.iew.EXEC:branches 13347127 # Number of branches executed 232system.cpu.iew.EXEC:nop 0 # number of nop insts executed 233system.cpu.iew.EXEC:rate 0.903568 # Inst execution rate 234system.cpu.iew.EXEC:refs 50902903 # number of memory reference insts executed 235system.cpu.iew.EXEC:stores 21266898 # Number of stores executed 236system.cpu.iew.EXEC:swp 0 # number of swp insts executed 237system.cpu.iew.WB:consumers 83917531 # num instructions consuming a value 238system.cpu.iew.WB:count 104978436 # cumulative count of insts written-back 239system.cpu.iew.WB:fanout 0.516830 # average fanout of values written-back 240system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ 241system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 242system.cpu.iew.WB:producers 43371139 # num instructions producing a value 243system.cpu.iew.WB:rate 0.885745 # insts written-back per cycle 244system.cpu.iew.WB:sent 106195350 # cumulative count of insts sent to commit 245system.cpu.iew.branchMispredicts 2628455 # Number of branch mispredicts detected at execute 246system.cpu.iew.iewBlockCycles 987035 # Number of cycles IEW is blocking 247system.cpu.iew.iewDispLoadInsts 32508348 # Number of dispatched load instructions 248system.cpu.iew.iewDispNonSpecInsts 1016199 # Number of dispatched non-speculative instructions 249system.cpu.iew.iewDispSquashedInsts 2305298 # Number of squashed instructions skipped by dispatch 250system.cpu.iew.iewDispStoreInsts 23389031 # Number of dispatched store instructions 251system.cpu.iew.iewDispatchedInsts 117101137 # Number of instructions dispatched to IQ 252system.cpu.iew.iewExecLoadInsts 29636005 # Number of load instructions executed 253system.cpu.iew.iewExecSquashedInsts 2065669 # Number of squashed instructions skipped in execute 254system.cpu.iew.iewExecutedInsts 107090838 # Number of executed instructions 255system.cpu.iew.iewIQFullEvents 2107 # Number of times the IQ has become full, causing a stall 256system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 257system.cpu.iew.iewLSQFullEvents 908 # Number of times the LSQ has become full, causing a stall 258system.cpu.iew.iewSquashCycles 3514572 # Number of cycles IEW is squashing 259system.cpu.iew.iewUnblockCycles 39558 # Number of cycles IEW is unblocking 260system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 261system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked 262system.cpu.iew.lsq.thread.0.forwLoads 247077 # Number of loads that had data forwarded from stores 263system.cpu.iew.lsq.thread.0.ignoredResponses 2317 # Number of memory responses ignored because the instruction is squashed 264system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address 265system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 266system.cpu.iew.lsq.thread.0.memOrderViolation 39532 # Number of memory ordering violations 267system.cpu.iew.lsq.thread.0.rescheduledLoads 7 # Number of loads that were rescheduled 268system.cpu.iew.lsq.thread.0.squashedLoads 5193052 # Number of loads squashed 269system.cpu.iew.lsq.thread.0.squashedStores 2833293 # Number of stores squashed 270system.cpu.iew.memOrderViolationEvents 39532 # Number of memory order violations 271system.cpu.iew.predictedNotTakenIncorrect 1768227 # Number of branches that were predicted not taken incorrectly 272system.cpu.iew.predictedTakenIncorrect 860228 # Number of branches that were predicted taken incorrectly 273system.cpu.ipc 0.833936 # IPC: Instructions Per Cycle 274system.cpu.ipc_total 0.833936 # IPC: Total IPC of All Threads 275system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 276system.cpu.iq.ISSUE:FU_type_0::IntAlu 57364104 52.55% 52.55% # Type of FU issued 277system.cpu.iq.ISSUE:FU_type_0::IntMult 80354 0.07% 52.63% # Type of FU issued 278system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 52.63% # Type of FU issued 279system.cpu.iq.ISSUE:FU_type_0::FloatAdd 124 0.00% 52.63% # Type of FU issued 280system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 52.63% # Type of FU issued 281system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 52.63% # Type of FU issued 282system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 52.63% # Type of FU issued 283system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 52.63% # Type of FU issued 284system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 52.63% # Type of FU issued 285system.cpu.iq.ISSUE:FU_type_0::SimdAdd 1 0.00% 52.63% # Type of FU issued 286system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 52.63% # Type of FU issued 287system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 52.63% # Type of FU issued 288system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 52.63% # Type of FU issued 289system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 52.63% # Type of FU issued 290system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 52.63% # Type of FU issued 291system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 52.63% # Type of FU issued 292system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 52.63% # Type of FU issued 293system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 52.63% # Type of FU issued 294system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 52.63% # Type of FU issued 295system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 52.63% # Type of FU issued 296system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 52.63% # Type of FU issued 297system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 52.63% # Type of FU issued 298system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 52.63% # Type of FU issued 299system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 52.63% # Type of FU issued 300system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 52.63% # Type of FU issued 301system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 52.63% # Type of FU issued 302system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 52.63% # Type of FU issued 303system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 52.63% # Type of FU issued 304system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 52.63% # Type of FU issued 305system.cpu.iq.ISSUE:FU_type_0::MemRead 30140236 27.61% 80.24% # Type of FU issued 306system.cpu.iq.ISSUE:FU_type_0::MemWrite 21571681 19.76% 100.00% # Type of FU issued 307system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 308system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 309system.cpu.iq.ISSUE:FU_type_0::total 109156507 # Type of FU issued 310system.cpu.iq.ISSUE:fu_busy_cnt 1323138 # FU busy when requested 311system.cpu.iq.ISSUE:fu_busy_rate 0.012121 # FU busy rate (busy events/executed inst) 312system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 313system.cpu.iq.ISSUE:fu_full::IntAlu 1303 0.10% 0.10% # attempts to use FU when none available 314system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.10% # attempts to use FU when none available 315system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.10% # attempts to use FU when none available 316system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.10% # attempts to use FU when none available 317system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.10% # attempts to use FU when none available 318system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.10% # attempts to use FU when none available 319system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.10% # attempts to use FU when none available 320system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.10% # attempts to use FU when none available 321system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.10% # attempts to use FU when none available 322system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 0.10% # attempts to use FU when none available 323system.cpu.iq.ISSUE:fu_full::SimdAddAcc 0 0.00% 0.10% # attempts to use FU when none available 324system.cpu.iq.ISSUE:fu_full::SimdAlu 0 0.00% 0.10% # attempts to use FU when none available 325system.cpu.iq.ISSUE:fu_full::SimdCmp 0 0.00% 0.10% # attempts to use FU when none available 326system.cpu.iq.ISSUE:fu_full::SimdCvt 0 0.00% 0.10% # attempts to use FU when none available 327system.cpu.iq.ISSUE:fu_full::SimdMisc 0 0.00% 0.10% # attempts to use FU when none available 328system.cpu.iq.ISSUE:fu_full::SimdMult 0 0.00% 0.10% # attempts to use FU when none available 329system.cpu.iq.ISSUE:fu_full::SimdMultAcc 0 0.00% 0.10% # attempts to use FU when none available 330system.cpu.iq.ISSUE:fu_full::SimdShift 0 0.00% 0.10% # attempts to use FU when none available 331system.cpu.iq.ISSUE:fu_full::SimdShiftAcc 0 0.00% 0.10% # attempts to use FU when none available 332system.cpu.iq.ISSUE:fu_full::SimdSqrt 0 0.00% 0.10% # attempts to use FU when none available 333system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 0.10% # attempts to use FU when none available 334system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 0.10% # attempts to use FU when none available 335system.cpu.iq.ISSUE:fu_full::SimdFloatCmp 0 0.00% 0.10% # attempts to use FU when none available 336system.cpu.iq.ISSUE:fu_full::SimdFloatCvt 0 0.00% 0.10% # attempts to use FU when none available 337system.cpu.iq.ISSUE:fu_full::SimdFloatDiv 0 0.00% 0.10% # attempts to use FU when none available 338system.cpu.iq.ISSUE:fu_full::SimdFloatMisc 0 0.00% 0.10% # attempts to use FU when none available 339system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.10% # attempts to use FU when none available 340system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.10% # attempts to use FU when none available 341system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.10% # attempts to use FU when none available 342system.cpu.iq.ISSUE:fu_full::MemRead 1094336 82.71% 82.81% # attempts to use FU when none available 343system.cpu.iq.ISSUE:fu_full::MemWrite 227499 17.19% 100.00% # attempts to use FU when none available 344system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 345system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 346system.cpu.iq.ISSUE:issued_per_cycle::samples 117533456 # Number of insts issued each cycle 347system.cpu.iq.ISSUE:issued_per_cycle::mean 0.928727 # Number of insts issued each cycle 348system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.126434 # Number of insts issued each cycle 349system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 350system.cpu.iq.ISSUE:issued_per_cycle::0 53481972 45.50% 45.50% # Number of insts issued each cycle 351system.cpu.iq.ISSUE:issued_per_cycle::1 35549975 30.25% 75.75% # Number of insts issued each cycle 352system.cpu.iq.ISSUE:issued_per_cycle::2 18295748 15.57% 91.32% # Number of insts issued each cycle 353system.cpu.iq.ISSUE:issued_per_cycle::3 5807729 4.94% 96.26% # Number of insts issued each cycle 354system.cpu.iq.ISSUE:issued_per_cycle::4 2883694 2.45% 98.71% # Number of insts issued each cycle 355system.cpu.iq.ISSUE:issued_per_cycle::5 1109227 0.94% 99.66% # Number of insts issued each cycle 356system.cpu.iq.ISSUE:issued_per_cycle::6 329629 0.28% 99.94% # Number of insts issued each cycle 357system.cpu.iq.ISSUE:issued_per_cycle::7 70692 0.06% 100.00% # Number of insts issued each cycle 358system.cpu.iq.ISSUE:issued_per_cycle::8 4790 0.00% 100.00% # Number of insts issued each cycle 359system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 360system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle 361system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle 362system.cpu.iq.ISSUE:issued_per_cycle::total 117533456 # Number of insts issued each cycle 363system.cpu.iq.ISSUE:rate 0.920997 # Inst issue rate 364system.cpu.iq.iqInstsAdded 116084938 # Number of instructions added to the IQ (excludes non-spec) 365system.cpu.iq.iqInstsIssued 109156507 # Number of instructions issued 366system.cpu.iq.iqNonSpecInstsAdded 1016199 # Number of non-speculative instructions added to the IQ 367system.cpu.iq.iqSquashedInstsExamined 17094247 # Number of squashed instructions iterated over during squash; mainly for profiling 368system.cpu.iq.iqSquashedInstsIssued 68325 # Number of squashed instructions issued 369system.cpu.iq.iqSquashedNonSpecRemoved 348408 # Number of squashed non-spec instructions that were removed 370system.cpu.iq.iqSquashedOperandsExamined 30276342 # Number of squashed operands that are examined and possibly removed from graph 371system.cpu.itb.accesses 0 # DTB accesses 372system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 373system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 375system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 376system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 377system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu.itb.hits 0 # DTB hits 380system.cpu.itb.inst_accesses 0 # ITB inst accesses 381system.cpu.itb.inst_hits 0 # ITB inst hits 382system.cpu.itb.inst_misses 0 # ITB inst misses 383system.cpu.itb.misses 0 # DTB misses 384system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 386system.cpu.itb.read_accesses 0 # DTB read accesses 387system.cpu.itb.read_hits 0 # DTB read hits 388system.cpu.itb.read_misses 0 # DTB read misses 389system.cpu.itb.write_accesses 0 # DTB write accesses 390system.cpu.itb.write_hits 0 # DTB write hits 391system.cpu.itb.write_misses 0 # DTB write misses 392system.cpu.l2cache.ReadExReq_accesses 106739 # number of ReadExReq accesses(hits+misses) 393system.cpu.l2cache.ReadExReq_avg_miss_latency 34385.177402 # average ReadExReq miss latency 394system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31198.626723 # average ReadExReq mshr miss latency 395system.cpu.l2cache.ReadExReq_hits 4429 # number of ReadExReq hits 396system.cpu.l2cache.ReadExReq_miss_latency 3517947500 # number of ReadExReq miss cycles 397system.cpu.l2cache.ReadExReq_miss_rate 0.958506 # miss rate for ReadExReq accesses 398system.cpu.l2cache.ReadExReq_misses 102310 # number of ReadExReq misses 399system.cpu.l2cache.ReadExReq_mshr_miss_latency 3191931500 # number of ReadExReq MSHR miss cycles 400system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.958506 # mshr miss rate for ReadExReq accesses 401system.cpu.l2cache.ReadExReq_mshr_misses 102310 # number of ReadExReq MSHR misses 402system.cpu.l2cache.ReadReq_accesses 80290 # number of ReadReq accesses(hits+misses) 403system.cpu.l2cache.ReadReq_avg_miss_latency 34268.509897 # average ReadReq miss latency 404system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31112.930905 # average ReadReq mshr miss latency 405system.cpu.l2cache.ReadReq_hits 46997 # number of ReadReq hits 406system.cpu.l2cache.ReadReq_miss_latency 1140901500 # number of ReadReq miss cycles 407system.cpu.l2cache.ReadReq_miss_rate 0.414659 # miss rate for ReadReq accesses 408system.cpu.l2cache.ReadReq_misses 33293 # number of ReadReq misses 409system.cpu.l2cache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits 410system.cpu.l2cache.ReadReq_mshr_miss_latency 1033416000 # number of ReadReq MSHR miss cycles 411system.cpu.l2cache.ReadReq_mshr_miss_rate 0.413688 # mshr miss rate for ReadReq accesses 412system.cpu.l2cache.ReadReq_mshr_misses 33215 # number of ReadReq MSHR misses 413system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses) 414system.cpu.l2cache.UpgradeReq_avg_miss_latency 3450 # average UpgradeReq miss latency 415system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31300 # average UpgradeReq mshr miss latency 416system.cpu.l2cache.UpgradeReq_hits 5 # number of UpgradeReq hits 417system.cpu.l2cache.UpgradeReq_miss_latency 34500 # number of UpgradeReq miss cycles 418system.cpu.l2cache.UpgradeReq_miss_rate 0.666667 # miss rate for UpgradeReq accesses 419system.cpu.l2cache.UpgradeReq_misses 10 # number of UpgradeReq misses 420system.cpu.l2cache.UpgradeReq_mshr_miss_latency 313000 # number of UpgradeReq MSHR miss cycles 421system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.666667 # mshr miss rate for UpgradeReq accesses 422system.cpu.l2cache.UpgradeReq_mshr_misses 10 # number of UpgradeReq MSHR misses 423system.cpu.l2cache.Writeback_accesses 124385 # number of Writeback accesses(hits+misses) 424system.cpu.l2cache.Writeback_hits 124385 # number of Writeback hits 425system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 426system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 427system.cpu.l2cache.avg_refs 0.522459 # Average number of references to valid blocks. 428system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 429system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 430system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 431system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 432system.cpu.l2cache.cache_copies 0 # number of cache copies performed 433system.cpu.l2cache.demand_accesses 187029 # number of demand (read+write) accesses 434system.cpu.l2cache.demand_avg_miss_latency 34356.533410 # average overall miss latency 435system.cpu.l2cache.demand_avg_mshr_miss_latency 31177.624055 # average overall mshr miss latency 436system.cpu.l2cache.demand_hits 51426 # number of demand (read+write) hits 437system.cpu.l2cache.demand_miss_latency 4658849000 # number of demand (read+write) miss cycles 438system.cpu.l2cache.demand_miss_rate 0.725037 # miss rate for demand accesses 439system.cpu.l2cache.demand_misses 135603 # number of demand (read+write) misses 440system.cpu.l2cache.demand_mshr_hits 78 # number of demand (read+write) MSHR hits 441system.cpu.l2cache.demand_mshr_miss_latency 4225347500 # number of demand (read+write) MSHR miss cycles 442system.cpu.l2cache.demand_mshr_miss_rate 0.724620 # mshr miss rate for demand accesses 443system.cpu.l2cache.demand_mshr_misses 135525 # number of demand (read+write) MSHR misses 444system.cpu.l2cache.fast_writes 0 # number of fast writes performed 445system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 446system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 447system.cpu.l2cache.occ_%::0 0.075665 # Average percentage of cache occupancy 448system.cpu.l2cache.occ_%::1 0.490596 # Average percentage of cache occupancy 449system.cpu.l2cache.occ_blocks::0 2479.385419 # Average occupied blocks per context 450system.cpu.l2cache.occ_blocks::1 16075.863311 # Average occupied blocks per context 451system.cpu.l2cache.overall_accesses 187029 # number of overall (read+write) accesses 452system.cpu.l2cache.overall_avg_miss_latency 34356.533410 # average overall miss latency 453system.cpu.l2cache.overall_avg_mshr_miss_latency 31177.624055 # average overall mshr miss latency 454system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 455system.cpu.l2cache.overall_hits 51426 # number of overall hits 456system.cpu.l2cache.overall_miss_latency 4658849000 # number of overall miss cycles 457system.cpu.l2cache.overall_miss_rate 0.725037 # miss rate for overall accesses 458system.cpu.l2cache.overall_misses 135603 # number of overall misses 459system.cpu.l2cache.overall_mshr_hits 78 # number of overall MSHR hits 460system.cpu.l2cache.overall_mshr_miss_latency 4225347500 # number of overall MSHR miss cycles 461system.cpu.l2cache.overall_mshr_miss_rate 0.724620 # mshr miss rate for overall accesses 462system.cpu.l2cache.overall_mshr_misses 135525 # number of overall MSHR misses 463system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 464system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 465system.cpu.l2cache.replacements 115260 # number of replacements 466system.cpu.l2cache.sampled_refs 134133 # Sample count of references to valid blocks. 467system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 468system.cpu.l2cache.tagsinuse 18555.248730 # Cycle average of tags in use 469system.cpu.l2cache.total_refs 70079 # Total number of references to valid blocks. 470system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 471system.cpu.l2cache.writebacks 88459 # number of writebacks 472system.cpu.memDep0.conflictingLoads 7990320 # Number of conflicting loads. 473system.cpu.memDep0.conflictingStores 10924699 # Number of conflicting stores. 474system.cpu.memDep0.insertedLoads 32508348 # Number of loads inserted to the mem dependence unit. 475system.cpu.memDep0.insertedStores 23389031 # Number of stores inserted to the mem dependence unit. 476system.cpu.numCycles 118519960 # number of cpu cycles simulated 477system.cpu.rename.RENAME:BlockCycles 1866194 # Number of cycles rename is blocking 478system.cpu.rename.RENAME:CommittedMaps 74745628 # Number of HB maps that are committed 479system.cpu.rename.RENAME:IQFullEvents 1883 # Number of times rename has blocked due to IQ full 480system.cpu.rename.RENAME:IdleCycles 30389505 # Number of cycles rename is idle 481system.cpu.rename.RENAME:LSQFullEvents 833530 # Number of times rename has blocked due to LSQ full 482system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full 483system.cpu.rename.RENAME:RenameLookups 333412635 # Number of register rename lookups that rename has made 484system.cpu.rename.RENAME:RenamedInsts 124050705 # Number of instructions processed by rename 485system.cpu.rename.RENAME:RenamedOperands 93358658 # Number of destination operands rename has renamed 486system.cpu.rename.RENAME:RunCycles 68672790 # Number of cycles rename is running 487system.cpu.rename.RENAME:SquashCycles 3514572 # Number of cycles rename is squashing 488system.cpu.rename.RENAME:UnblockCycles 1591233 # Number of cycles rename is unblocking 489system.cpu.rename.RENAME:UndoneMaps 18613027 # Number of HB maps that are undone due to squashing 490system.cpu.rename.RENAME:serializeStallCycles 11499162 # count of cycles rename stalled for serializing inst 491system.cpu.rename.RENAME:serializingInsts 818368 # count of serializing insts renamed 492system.cpu.rename.RENAME:skidInsts 3724500 # count of insts added to the skid buffer 493system.cpu.rename.RENAME:tempSerializingInsts 819368 # count of temporary serializing insts renamed 494system.cpu.timesIdled 60726 # Number of times that the entire CPU went into an idle state and unscheduled itself 495system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls 496 497---------- End Simulation Statistics ---------- 498