xref: /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.033295                       # Number of seconds simulated
sim_ticks                                 33294994000                       # Number of ticks simulated
final_tick                                33294994000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 125667                       # Simulator instruction rate (inst/s)
host_op_rate                                   160714                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               59007684                       # Simulator tick rate (ticks/s)
host_mem_usage                                 325068                       # Number of bytes of host memory used
host_seconds                                   564.25                       # Real time elapsed on the host
sim_insts                                    70907630                       # Number of instructions simulated
sim_ops                                      90682585                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            579648                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           2508288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher      6196352                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9284288                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       579648                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          579648                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6263808                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6263808                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               9057                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              39192                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        96818                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                145067                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97872                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97872                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             17409464                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             75335289                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher    186104614                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               278849367                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        17409464                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           17409464                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         188130624                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              188130624                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         188130624                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            17409464                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            75335289                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher    186104614                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              466979991                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        145067                       # Number of read requests accepted
system.physmem.writeReqs                        97872                       # Number of write requests accepted
system.physmem.readBursts                      145067                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97872                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9276928                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6262080                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9284288                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6263808                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              6                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9133                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9402                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9189                       # Per bank write bursts
system.physmem.perBankRdBursts::3                9501                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9688                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9749                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9050                       # Per bank write bursts
system.physmem.perBankRdBursts::7                9017                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9142                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8554                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8859                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8689                       # Per bank write bursts
system.physmem.perBankRdBursts::12               8621                       # Per bank write bursts
system.physmem.perBankRdBursts::13               8707                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8654                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8997                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5994                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6239                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6113                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6223                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6099                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6360                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6100                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5988                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5999                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6164                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6223                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5911                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6098                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6094                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6156                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6084                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     33294791000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  145067                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97872                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     42425                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     52688                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     16531                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9335                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6069                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5279                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4636                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4301                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3567                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        90                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1172                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1878                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2564                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3428                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4425                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5268                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5944                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6608                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     7072                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7612                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8290                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     7674                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6888                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6385                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      206                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       64                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        9                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        88605                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      175.366717                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     110.599846                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     238.987527                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          52022     58.71%     58.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        22627     25.54%     84.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4475      5.05%     89.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1626      1.84%     91.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1127      1.27%     92.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          853      0.96%     93.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          741      0.84%     94.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          771      0.87%     95.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4363      4.92%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          88605                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5911                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.519032                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       21.016952                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      186.911555                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            5910     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5911                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5911                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.553037                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.510340                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.264183                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4718     79.82%     79.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 30      0.51%     80.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                754     12.76%     93.08% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                178      3.01%     96.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 93      1.57%     97.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 63      1.07%     98.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 39      0.66%     99.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 18      0.30%     99.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 13      0.22%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  4      0.07%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5911                       # Writes before turning the bus around for reads
system.physmem.totQLat                     7210112096                       # Total ticks spent queuing
system.physmem.totMemAccLat                9927962096                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    724760000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       49741.38                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  68491.38                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         278.63                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         188.08                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      278.85                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      188.13                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.65                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.18                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.47                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.60                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.54                       # Average write queue length when enqueuing
system.physmem.readRowHits                     117862                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     36326                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.31                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  37.12                       # Row buffer hit rate for writes
system.physmem.avgGap                       137050.00                       # Average gap between requests
system.physmem.pageHitRate                      63.50                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  341636400                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  186408750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 582823800                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                318271680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             2174602560                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            11786161320                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             9637821000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              25027725510                       # Total energy per rank (pJ)
system.physmem_0.averagePower              751.712810                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    15936534744                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1111760000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     16245984006                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  328217400                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  179086875                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 547723800                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                315763920                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             2174602560                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            11208088125                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            10144902750                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              24898385430                       # Total energy per rank (pJ)
system.physmem_1.averagePower              747.828055                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    16783464024                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1111760000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     15399360476                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                17206050                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11517760                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            648066                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9347785                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7673761                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             82.091758                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1873139                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             101558                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         66589989                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            5006781                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       88183966                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    17206050                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9546900                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      60089478                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1322083                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 6754                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            23                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        13752                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  22762089                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 69210                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           65777829                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.696584                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.296287                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 20002417     30.41%     30.41% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  8264821     12.56%     42.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9199012     13.98%     56.96% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 28311579     43.04%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             65777829                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.258388                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.324283                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8581179                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              19502182                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  31574906                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               5627602                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 491960                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3179377                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                170933                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              101404474                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               3045182                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 491960                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 13335070                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 5313056                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         801397                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  32234531                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13601815                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               99199856                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                982546                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               3844821                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  62523                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                4317608                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                5297882                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           103921297                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             457696388                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        115410759                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 10292071                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              18659                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          18651                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12693629                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             24321623                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            21992796                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1398027                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2340833                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   98163899                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               34521                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  94893533                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            694347                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         7515835                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     20236855                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            735                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      65777829                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.442637                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.149664                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            17511633     26.62%     26.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            17428256     26.50%     53.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            17102675     26.00%     79.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            11682123     17.76%     96.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2052152      3.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 990      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        65777829                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 6715699     22.40%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     38      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11201748     37.36%     59.75% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              12068794     40.25%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49496640     52.16%     52.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                89875      0.09%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24065423     25.36%     77.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21241557     22.38%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               94893533                       # Type of FU issued
system.cpu.iq.rate                           1.425042                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    29986279                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.315999                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          286245314                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         105725496                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     93465397                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           57                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              124879694                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     118                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1364211                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1455361                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         2068                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11748                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1437058                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       140354                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        182528                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 491960                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  620291                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                463716                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            98208276                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              24321623                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             21992796                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              18601                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   1628                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                459155                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11748                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         302696                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       221540                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               524236                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              93976140                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23758122                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            917393                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9856                       # number of nop insts executed
system.cpu.iew.exec_refs                     44743070                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14251776                       # Number of branches executed
system.cpu.iew.exec_stores                   20984948                       # Number of stores executed
system.cpu.iew.exec_rate                     1.411265                       # Inst execution rate
system.cpu.iew.wb_sent                       93586994                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      93465454                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  44981756                       # num instructions producing a value
system.cpu.iew.wb_consumers                  76565949                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.403596                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.587490                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         6535729                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            478985                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     64719651                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.401246                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.164864                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     31116285     48.08%     48.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     16809912     25.97%     74.05% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4342534      6.71%     80.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      4161990      6.43%     87.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1938865      3.00%     90.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1263903      1.95%     92.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       739138      1.14%     93.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       578808      0.89%     94.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3768216      5.82%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     64719651                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913182                       # Number of instructions committed
system.cpu.commit.committedOps               90688137                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       43422000                       # Number of memory references committed
system.cpu.commit.loads                      22866262                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741486                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  81528487                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         47186011     52.03%     52.03% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22866262     25.21%     77.33% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          90688137                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3768216                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    158150002                       # The number of ROB reads
system.cpu.rob.rob_writes                   195507605                       # The number of ROB writes
system.cpu.timesIdled                           23773                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          812160                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907630                       # Number of Instructions Simulated
system.cpu.committedOps                      90682585                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.939109                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.939109                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.064839                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.064839                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                102273698                       # number of integer regfile reads
system.cpu.int_regfile_writes                56793498                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       21                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 346096996                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 38804962                       # number of cc regfile writes
system.cpu.misc_regfile_reads                44209976                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.dcache.tags.replacements            485041                       # number of replacements
system.cpu.dcache.tags.tagsinuse           510.740827                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40418511                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            485553                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             83.242223                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         152851500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   510.740827                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997541                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997541                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          454                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          84611501                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         84611501                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     21495962                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21495962                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18831064                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18831064                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        60188                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         60188                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15352                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15352                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40327026                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40327026                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40387214                       # number of overall hits
system.cpu.dcache.overall_hits::total        40387214                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       556411                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        556411                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1018837                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1018837                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        68667                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        68667                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          574                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          574                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1575248                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1575248                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1643915                       # number of overall misses
system.cpu.dcache.overall_misses::total       1643915                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   8968261000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   8968261000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  14556255401                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  14556255401                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      4964500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      4964500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  23524516401                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  23524516401                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  23524516401                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  23524516401                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22052373                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22052373                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       128855                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       128855                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41902274                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41902274                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42031129                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42031129                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025231                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.025231                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051327                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.051327                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.532901                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.532901                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.036042                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.036042                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037593                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037593                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.039112                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.039112                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16118.051225                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16118.051225                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14287.128757                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14287.128757                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8648.954704                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8648.954704                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14933.849401                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14933.849401                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14310.056421                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14310.056421                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           45                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3094334                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 8                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          130016                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     5.625000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    23.799640                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       256956                       # number of writebacks
system.cpu.dcache.writebacks::total            256956                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       256971                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       256971                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       870307                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       870307                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          574                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          574                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1127278                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1127278                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1127278                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1127278                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299440                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       299440                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148530                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       148530                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37596                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        37596                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       447970                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       447970                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       485566                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       485566                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3182608500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3182608500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2345597960                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2345597960                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2017960000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2017960000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5528206460                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   5528206460                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7546166460                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   7546166460                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013579                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013579                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291770                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291770                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010691                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010691                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011553                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.011553                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10628.534932                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10628.534932                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15792.082138                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15792.082138                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53674.859028                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53674.859028                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12340.572940                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12340.572940                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15540.969631                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15540.969631                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            322718                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.301604                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            22427944                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            323227                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             69.387594                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        1102167500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.301604                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996683                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996683                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          509                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           59                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            7                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          347                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.994141                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          45847164                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         45847164                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     22427950                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        22427950                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      22427950                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         22427950                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     22427950                       # number of overall hits
system.cpu.icache.overall_hits::total        22427950                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       334012                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        334012                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       334012                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         334012                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       334012                       # number of overall misses
system.cpu.icache.overall_misses::total        334012                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   3359547390                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   3359547390                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   3359547390                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   3359547390                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   3359547390                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   3359547390                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     22761962                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     22761962                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     22761962                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     22761962                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     22761962                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     22761962                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014674                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014674                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014674                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014674                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014674                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014674                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10058.163749                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 10058.163749                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 10058.163749                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 10058.163749                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 10058.163749                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 10058.163749                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       273191                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets          314                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs             16668                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    16.390149                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          157                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst        10772                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total        10772                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst        10772                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total        10772                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst        10772                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total        10772                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323240                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       323240                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       323240                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       323240                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       323240                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       323240                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   3075719938                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   3075719938                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   3075719938                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   3075719938                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   3075719938                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   3075719938                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014201                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014201                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014201                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014201                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014201                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014201                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9515.282570                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9515.282570                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9515.282570                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  9515.282570                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9515.282570                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  9515.282570                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued       823311                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified       826037                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         2394                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage        78819                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           129183                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16078.827633                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1332410                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           145465                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             9.159660                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 12584.053825                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1451.251559                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1933.402514                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   110.119734                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.768070                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.088577                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.118006                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006721                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.981374                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022           37                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        16245                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2            7                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3           17                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4            5                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2635                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        12009                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          573                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          872                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.002258                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.991516                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         24881143                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        24881143                       # Number of data accesses
system.cpu.l2cache.Writeback_hits::writebacks       256956                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       256956                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            7                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            7                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       137103                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       137103                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst       314121                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total       314121                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       305949                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       305949                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst       314121                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       443052                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          757173                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       314121                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       443052                       # number of overall hits
system.cpu.l2cache.overall_hits::total         757173                       # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        11464                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        11464                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9103                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         9103                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data        31037                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total        31037                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         9103                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        42501                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         51604                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         9103                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        42501                       # number of overall misses
system.cpu.l2cache.overall_misses::total        51604                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1228965000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1228965000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    707735000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    707735000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data   2684182500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total   2684182500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    707735000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   3913147500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   4620882500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    707735000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   3913147500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   4620882500                       # number of overall miss cycles
system.cpu.l2cache.Writeback_accesses::writebacks       256956                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       256956                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           13                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           13                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       148567                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       148567                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst       323224                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total       323224                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       336986                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       336986                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       323224                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       485553                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       808777                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       323224                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       485553                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       808777                       # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.461538                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.461538                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.077164                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.077164                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.028163                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.028163                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.092102                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.092102                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.028163                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087531                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063805                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.028163                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087531                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063805                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107202.110956                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 107202.110956                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77747.445897                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77747.445897                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86483.310243                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86483.310243                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77747.445897                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92071.892426                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 89545.044958                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77747.445897                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92071.892426                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 89545.044958                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97872                       # number of writebacks
system.cpu.l2cache.writebacks::total            97872                       # number of writebacks
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3181                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3181                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst           46                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total           46                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data          128                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total          128                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           46                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         3309                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         3355                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           46                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         3309                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         3355                       # number of overall MSHR hits
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks         3506                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total         3506                       # number of CleanEvict MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112459                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       112459                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8283                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         8283                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9057                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9057                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data        30909                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total        30909                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         9057                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        39192                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        48249                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         9057                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        39192                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112459                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       160708                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10889744040                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10889744040                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       101500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       101500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    639425500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    639425500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    650223000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    650223000                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data   2490483000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total   2490483000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    650223000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3129908500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   3780131500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    650223000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3129908500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10889744040                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14669875540                       # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.461538                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.461538                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.055753                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.055753                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.028021                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.028021                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.091722                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.091722                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028021                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.080716                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.059657                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028021                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.080716                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.198705                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96833.015054                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16916.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16916.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77197.331885                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77197.331885                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71792.315336                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71792.315336                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80574.686984                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80574.686984                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71792.315336                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79860.902735                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78346.318058                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71792.315336                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79860.902735                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96833.015054                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91282.795754                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadResp        660226                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       354828                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       502259                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       152780                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           13                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           13                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       148567                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       148567                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq       323240                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       336986                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       938639                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1406861                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2345500                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20686336                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     47520576                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           68206912                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      281979                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1898528                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.148517                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.355611                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            1616565     85.15%     85.15% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             281963     14.85%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1898528                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy     1065238500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          3.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     485020678                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     728403365                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             136784                       # Transaction distribution
system.membus.trans_dist::Writeback             97872                       # Transaction distribution
system.membus.trans_dist::CleanEvict            30200                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               6                       # Transaction distribution
system.membus.trans_dist::ReadExReq              8283                       # Transaction distribution
system.membus.trans_dist::ReadExResp             8283                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        136784                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       418218                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 418218                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15548096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15548096                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            273145                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  273145    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              273145                       # Request fanout histogram
system.membus.reqLayer0.occupancy           717072511                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy          756625908                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------