xref: /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.033331                       # Number of seconds simulated
sim_ticks                                 33330913000                       # Number of ticks simulated
final_tick                                33330913000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 123947                       # Simulator instruction rate (inst/s)
host_op_rate                                   158514                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               58262578                       # Simulator tick rate (ticks/s)
host_mem_usage                                 323704                       # Number of bytes of host memory used
host_seconds                                   572.08                       # Real time elapsed on the host
sim_insts                                    70907630                       # Number of instructions simulated
sim_ops                                      90682585                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            583488                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           2505024                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher      6203200                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9291712                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       583488                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          583488                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6256128                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6256128                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               9117                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              39141                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        96925                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                145183                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97752                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97752                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             17505911                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             75156177                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher    186109513                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               278771602                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        17505911                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           17505911                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         187697469                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              187697469                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         187697469                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            17505911                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            75156177                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher    186109513                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              466469070                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        145183                       # Number of read requests accepted
system.physmem.writeReqs                        97752                       # Number of write requests accepted
system.physmem.readBursts                      145183                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97752                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9284992                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      6720                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6254720                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9291712                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6256128                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      105                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              6                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9145                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9372                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9233                       # Per bank write bursts
system.physmem.perBankRdBursts::3                9500                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9743                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9700                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9083                       # Per bank write bursts
system.physmem.perBankRdBursts::7                8995                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9233                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8567                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8856                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8704                       # Per bank write bursts
system.physmem.perBankRdBursts::12               8629                       # Per bank write bursts
system.physmem.perBankRdBursts::13               8694                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8697                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8927                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5993                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6233                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6131                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6188                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6147                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6290                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6056                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6014                       # Per bank write bursts
system.physmem.perBankWrBursts::8                6000                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6152                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6228                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5920                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6078                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6086                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6193                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6021                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     33330641500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  145183                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97752                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     41867                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     51877                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     18150                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9231                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6097                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5279                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4608                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4276                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3567                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        88                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       31                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1146                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1898                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2645                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5631                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5913                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6185                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6430                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6850                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7378                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8166                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     8983                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8099                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7186                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6431                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      258                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      127                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       55                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       21                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       17                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        88649                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      175.273178                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     110.551570                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     239.030923                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          52157     58.84%     58.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        22538     25.42%     84.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4461      5.03%     89.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1758      1.98%     91.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1068      1.20%     92.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          785      0.89%     93.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          713      0.80%     94.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          748      0.84%     95.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4421      4.99%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          88649                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5905                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.566130                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       21.054973                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      187.117675                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            5904     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5905                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5905                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.550381                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.508750                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.243905                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4712     79.80%     79.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 29      0.49%     80.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                757     12.82%     93.11% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                163      2.76%     95.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                111      1.88%     97.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 62      1.05%     98.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 43      0.73%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 20      0.34%     99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                  6      0.10%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  2      0.03%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5905                       # Writes before turning the bus around for reads
system.physmem.totQLat                     7425181339                       # Total ticks spent queuing
system.physmem.totMemAccLat               10145393839                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    725390000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       51180.62                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  69930.62                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         278.57                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         187.66                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      278.77                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      187.70                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.64                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.18                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.47                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.64                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.63                       # Average write queue length when enqueuing
system.physmem.readRowHits                     117819                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     36329                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.21                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  37.16                       # Row buffer hit rate for writes
system.physmem.avgGap                       137199.83                       # Average gap between requests
system.physmem.pageHitRate                      63.48                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  342679680                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  186978000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 582769200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                317714400                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             2176636800                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            11943657450                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             9518358000                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              25068793530                       # Total energy per rank (pJ)
system.physmem_0.averagePower              752.242445                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    15735797307                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1112800000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     16476833443                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  327053160                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  178451625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 548121600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                315264960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             2176636800                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            11265215805                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            10113486000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              24924229950                       # Total energy per rank (pJ)
system.physmem_1.averagePower              747.904367                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    16730540892                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1112800000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     15482244108                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                17205793                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11516695                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            648305                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9352037                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7676056                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             82.078974                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1873350                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             101557                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         66661827                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            4979954                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       88191186                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    17205793                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9549406                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      60159688                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1322593                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 6446                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            25                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        13285                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  22768352                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 68999                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           65820694                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.695691                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.296532                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 20039717     30.45%     30.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  8265549     12.56%     43.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9200264     13.98%     56.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 28315164     43.02%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             65820694                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.258106                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.322964                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8562659                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              19557917                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  31575920                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               5632021                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 492177                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3179708                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                171007                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              101418024                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               3051775                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 492177                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 13320782                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 5331170                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         788978                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  32236803                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13650784                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               99206458                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                984473                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               3857341                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  63915                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                4307533                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                5353775                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           103928524                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             457724306                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        115417327                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 10299298                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              18661                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          18655                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12693692                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             24322711                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            21993814                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1396246                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2340033                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   98168548                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               34521                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  94889336                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            694958                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         7520484                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     20257229                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            735                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      65820694                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.441634                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.150001                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            17560123     26.68%     26.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            17422684     26.47%     53.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            17103546     25.99%     79.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            11678791     17.74%     96.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2054563      3.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 987      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        65820694                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 6715459     22.40%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     39      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.40% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11205581     37.37%     59.77% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              12062957     40.23%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49498174     52.16%     52.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                89865      0.09%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24060336     25.36%     77.62% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21240923     22.38%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               94889336                       # Type of FU issued
system.cpu.iq.rate                           1.423443                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    29984036                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.315990                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          286278153                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         105734805                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     93465836                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           57                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              124873254                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     118                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1363649                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1456449                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         2030                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11752                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1438076                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       138616                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        176709                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 492177                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  621288                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                454814                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            98212928                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              24322711                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             21993814                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              18601                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   1642                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                450257                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11752                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         303335                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       221647                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               524982                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              93971179                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23753264                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            918157                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9859                       # number of nop insts executed
system.cpu.iew.exec_refs                     44736876                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14252919                       # Number of branches executed
system.cpu.iew.exec_stores                   20983612                       # Number of stores executed
system.cpu.iew.exec_rate                     1.409670                       # Inst execution rate
system.cpu.iew.wb_sent                       93587571                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      93465893                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  44982416                       # num instructions producing a value
system.cpu.iew.wb_consumers                  76564206                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.402090                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.587512                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         6539953                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            479186                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     64761460                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.400341                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.165093                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     31172018     48.13%     48.13% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     16800427     25.94%     74.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4337432      6.70%     80.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      4161423      6.43%     87.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1935218      2.99%     90.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1264756      1.95%     92.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       739046      1.14%     93.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       579471      0.89%     94.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3771669      5.82%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     64761460                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913182                       # Number of instructions committed
system.cpu.commit.committedOps               90688137                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       43422000                       # Number of memory references committed
system.cpu.commit.loads                      22866262                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741486                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  81528487                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         47186011     52.03%     52.03% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22866262     25.21%     77.33% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          90688137                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3771669                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    158192582                       # The number of ROB reads
system.cpu.rob.rob_writes                   195517129                       # The number of ROB writes
system.cpu.timesIdled                           23763                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          841133                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907630                       # Number of Instructions Simulated
system.cpu.committedOps                      90682585                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.940122                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.940122                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.063692                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.063692                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                102266688                       # number of integer regfile reads
system.cpu.int_regfile_writes                56794481                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       21                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 346084159                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 38805382                       # number of cc regfile writes
system.cpu.misc_regfile_reads                44209334                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.dcache.tags.replacements            485106                       # number of replacements
system.cpu.dcache.tags.tagsinuse           510.740457                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40427935                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            485618                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             83.250487                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         152807000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   510.740457                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997540                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997540                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          454                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          84615616                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         84615616                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     21501539                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21501539                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18833357                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18833357                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        61715                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         61715                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15379                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15379                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40334896                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40334896                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40396611                       # number of overall hits
system.cpu.dcache.overall_hits::total        40396611                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       552871                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        552871                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1016544                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1016544                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        67128                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        67128                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          547                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          547                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1569415                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1569415                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1636543                       # number of overall misses
system.cpu.dcache.overall_misses::total       1636543                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   9102953011                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   9102953011                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  14661434456                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  14661434456                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5113500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      5113500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  23764387467                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  23764387467                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  23764387467                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  23764387467                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22054410                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22054410                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       128843                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       128843                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41904311                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41904311                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42033154                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42033154                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025069                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.025069                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051212                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.051212                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.521006                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.521006                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.034346                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.034346                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037452                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037452                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.038935                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.038935                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16464.876998                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16464.876998                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14422.823268                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14422.823268                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9348.263254                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9348.263254                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15142.194682                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15142.194682                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14521.089557                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14521.089557                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           25                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3013610                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 4                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          128472                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     6.250000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    23.457329                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       264409                       # number of writebacks
system.cpu.dcache.writebacks::total            264409                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       253375                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       253375                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       868011                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       868011                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          547                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          547                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1121386                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1121386                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1121386                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1121386                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299496                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       299496                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148533                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       148533                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37600                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        37600                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       448029                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       448029                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       485629                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       485629                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3035888114                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3035888114                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2279411901                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2279411901                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2033283784                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2033283784                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5315300015                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   5315300015                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7348583799                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   7348583799                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013580                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013580                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007483                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007483                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291828                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291828                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010692                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010692                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011553                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.011553                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10136.656630                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10136.656630                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15346.164832                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15346.164832                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54076.696383                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54076.696383                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11863.740997                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11863.740997                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15132.094251                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15132.094251                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            322771                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.304013                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            22435446                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            323283                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             69.398781                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        1099609250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.304013                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996688                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996688                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           56                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          354                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          45859770                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         45859770                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     22435446                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        22435446                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      22435446                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         22435446                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     22435446                       # number of overall hits
system.cpu.icache.overall_hits::total        22435446                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       332792                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        332792                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       332792                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         332792                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       332792                       # number of overall misses
system.cpu.icache.overall_misses::total        332792                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   3372368098                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   3372368098                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   3372368098                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   3372368098                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   3372368098                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   3372368098                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     22768238                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     22768238                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     22768238                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     22768238                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     22768238                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     22768238                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014617                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014617                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014617                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014617                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014617                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014617                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10133.561197                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 10133.561197                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 10133.561197                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 10133.561197                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 10133.561197                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 10133.561197                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       259166                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           49                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs             14826                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    17.480507                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    24.500000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         9498                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         9498                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         9498                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         9498                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         9498                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         9498                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323294                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       323294                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       323294                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       323294                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       323294                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       323294                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2922927754                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   2922927754                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2922927754                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   2922927754                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2922927754                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   2922927754                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014199                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014199                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014199                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014199                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014199                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014199                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9041.082587                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9041.082587                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9041.082587                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  9041.082587                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9041.082587                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  9041.082587                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued       824420                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified       826170                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         1539                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage        78694                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           129309                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16078.989093                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             872580                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           145594                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             5.993241                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 12596.793225                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1430.956994                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1951.680185                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher    99.558690                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.768847                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087339                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.119121                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006077                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.981384                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022           24                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        16261                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3           13                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4            3                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          156                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2623                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11971                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          617                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          894                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.001465                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.992493                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         17467290                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        17467290                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       314129                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       305935                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         620064                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       264409                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       264409                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       137264                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       137264                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       314129                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       443199                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          757328                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       314129                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       443199                       # number of overall hits
system.cpu.l2cache.overall_hits::total         757328                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         9153                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        31112                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        40265                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        11307                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        11307                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         9153                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        42419                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         51572                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         9153                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        42419                       # number of overall misses
system.cpu.l2cache.overall_misses::total        51572                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    716537990                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2723567713                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3440105703                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1235437442                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1235437442                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    716537990                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   3959005155                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   4675543145                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    716537990                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   3959005155                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   4675543145                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       323282                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       337047                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       660329                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       264409                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       264409                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           11                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           11                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       148571                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       148571                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       323282                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       485618                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       808900                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       323282                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       485618                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       808900                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.028313                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.092308                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.060977                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.545455                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.545455                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076105                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.076105                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.028313                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087351                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.063756                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.028313                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087351                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.063756                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78284.495794                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87540.746754                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 85436.624935                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109263.061997                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109263.061997                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78284.495794                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93330.940263                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 90660.496878                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78284.495794                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93330.940263                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 90660.496878                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97752                       # number of writebacks
system.cpu.l2cache.writebacks::total            97752                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           36                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          124                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total          160                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3154                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3154                       # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           36                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         3278                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         3314                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           36                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         3278                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         3314                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         9117                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        30988                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        40105                       # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112705                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       112705                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8153                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         8153                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         9117                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        39141                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        48258                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         9117                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        39141                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112705                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       160963                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    636175260                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2451921294                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3088096554                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10874977234                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10874977234                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        82006                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        82006                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    605818037                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    605818037                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    636175260                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3057739331                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   3693914591                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    636175260                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3057739331                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10874977234                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14568891825                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.028201                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.091940                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.060735                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.545455                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.545455                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.054876                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.054876                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028201                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.080600                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.059659                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028201                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.080600                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.198990                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69779.012833                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79124.864270                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77000.288094                       # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96490.636919                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13667.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13667.666667                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74306.149516                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74306.149516                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69779.012833                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78121.134641                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76545.123938                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69779.012833                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78121.134641                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96490.636919                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90510.811957                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         660341                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        660341                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       264409                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       151292                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           11                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           11                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       148571                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       148571                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       646576                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1235667                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           1882243                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20690048                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     48001728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           68691776                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      151304                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1224624                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        1.123542                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.329058                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1            1073332     87.65%     87.65% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2             151292     12.35%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1224624                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      801075000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.4                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     486570693                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     734618165                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
system.membus.trans_dist::ReadReq              137030                       # Transaction distribution
system.membus.trans_dist::ReadResp             137030                       # Transaction distribution
system.membus.trans_dist::Writeback             97752                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               6                       # Transaction distribution
system.membus.trans_dist::ReadExReq              8153                       # Transaction distribution
system.membus.trans_dist::ReadExResp             8153                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       388130                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 388130                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15547840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15547840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            242941                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  242941    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              242941                       # Request fanout histogram
system.membus.reqLayer0.occupancy           691321050                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy          757153835                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------