xref: /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.033359                       # Number of seconds simulated
sim_ticks                                 33359312000                       # Number of ticks simulated
final_tick                                33359312000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 125450                       # Simulator instruction rate (inst/s)
host_op_rate                                   160435                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               59019201                       # Simulator tick rate (ticks/s)
host_mem_usage                                 322444                       # Number of bytes of host memory used
host_seconds                                   565.23                       # Real time elapsed on the host
sim_insts                                    70907629                       # Number of instructions simulated
sim_ops                                      90682584                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            593600                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           2515776                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher      6204544                       # Number of bytes read from this memory
system.physmem.bytes_read::total              9313920                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       593600                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          593600                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6264768                       # Number of bytes written to this memory
system.physmem.bytes_written::total           6264768                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               9275                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data              39309                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher        96946                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                145530                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           97887                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                97887                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             17794132                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             75414505                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher    185991366                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               279200003                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        17794132                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           17794132                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         187796679                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              187796679                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         187796679                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            17794132                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            75414505                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher    185991366                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              466996681                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        145530                       # Number of read requests accepted
system.physmem.writeReqs                        97887                       # Number of write requests accepted
system.physmem.readBursts                      145530                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      97887                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  9306560                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                      7360                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   6263296                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   9313920                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                6264768                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      115                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              6                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                9160                       # Per bank write bursts
system.physmem.perBankRdBursts::1                9419                       # Per bank write bursts
system.physmem.perBankRdBursts::2                9305                       # Per bank write bursts
system.physmem.perBankRdBursts::3                9483                       # Per bank write bursts
system.physmem.perBankRdBursts::4                9789                       # Per bank write bursts
system.physmem.perBankRdBursts::5                9711                       # Per bank write bursts
system.physmem.perBankRdBursts::6                9074                       # Per bank write bursts
system.physmem.perBankRdBursts::7                9074                       # Per bank write bursts
system.physmem.perBankRdBursts::8                9205                       # Per bank write bursts
system.physmem.perBankRdBursts::9                8628                       # Per bank write bursts
system.physmem.perBankRdBursts::10               8849                       # Per bank write bursts
system.physmem.perBankRdBursts::11               8741                       # Per bank write bursts
system.physmem.perBankRdBursts::12               8642                       # Per bank write bursts
system.physmem.perBankRdBursts::13               8695                       # Per bank write bursts
system.physmem.perBankRdBursts::14               8691                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8949                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5976                       # Per bank write bursts
system.physmem.perBankWrBursts::1                6255                       # Per bank write bursts
system.physmem.perBankWrBursts::2                6149                       # Per bank write bursts
system.physmem.perBankWrBursts::3                6169                       # Per bank write bursts
system.physmem.perBankWrBursts::4                6151                       # Per bank write bursts
system.physmem.perBankWrBursts::5                6334                       # Per bank write bursts
system.physmem.perBankWrBursts::6                6086                       # Per bank write bursts
system.physmem.perBankWrBursts::7                6007                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5979                       # Per bank write bursts
system.physmem.perBankWrBursts::9                6153                       # Per bank write bursts
system.physmem.perBankWrBursts::10               6241                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5938                       # Per bank write bursts
system.physmem.perBankWrBursts::12               6061                       # Per bank write bursts
system.physmem.perBankWrBursts::13               6105                       # Per bank write bursts
system.physmem.perBankWrBursts::14               6219                       # Per bank write bursts
system.physmem.perBankWrBursts::15               6041                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     33359040500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  145530                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  97887                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     42093                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     51689                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                     18360                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      9225                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                      6081                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                      5319                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                      4669                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      4300                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                      3562                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                        86                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                       26                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        4                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     1144                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     1175                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     1920                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2607                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3444                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4432                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5283                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5659                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5932                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     6165                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     6447                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     6873                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     7427                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     8222                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     9030                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     8085                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     7129                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     6411                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                      253                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      112                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       60                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       12                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        6                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        3                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        88927                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      175.072858                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     110.491943                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     238.713124                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          52339     58.86%     58.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        22656     25.48%     84.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         4441      4.99%     89.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1741      1.96%     91.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         1037      1.17%     92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          849      0.95%     93.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          689      0.77%     94.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          765      0.86%     95.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4410      4.96%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          88927                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5911                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        24.598207                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       21.088924                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      187.219466                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511            5910     99.98%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::14336-14847            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5911                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5911                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.556251                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.512708                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        1.281856                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4715     79.77%     79.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 33      0.56%     80.32% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                741     12.54%     92.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                193      3.27%     96.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                104      1.76%     97.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 53      0.90%     98.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 34      0.58%     99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 17      0.29%     99.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 11      0.19%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  4      0.07%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  2      0.03%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  3      0.05%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5911                       # Writes before turning the bus around for reads
system.physmem.totQLat                     7478329771                       # Total ticks spent queuing
system.physmem.totMemAccLat               10204861021                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    727075000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       51427.50                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  70177.50                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         278.98                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         187.75                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      279.20                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      187.80                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.65                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.18                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.47                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.61                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.70                       # Average write queue length when enqueuing
system.physmem.readRowHits                     118188                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     36158                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   81.28                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  36.94                       # Row buffer hit rate for writes
system.physmem.avgGap                       137044.83                       # Average gap between requests
system.physmem.pageHitRate                      63.44                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  343556640                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  187456500                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                 584859600                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                318226320                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             2178671040                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            11869125390                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             9602419500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              25084314990                       # Total energy per rank (pJ)
system.physmem_0.averagePower              752.005565                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    15876395968                       # Time in different power states
system.physmem_0.memoryStateTime::REF      1113840000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     16366332782                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  328413960                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  179194125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                 548948400                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                315725040                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             2178671040                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            11416289175                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             9999644250                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              24966885990                       # Total energy per rank (pJ)
system.physmem_1.averagePower              748.485148                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    16542747198                       # Time in different power states
system.physmem_1.memoryStateTime::REF      1113840000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     15699981552                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                17207670                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11518844                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            648137                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups              9345275                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7675164                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             82.128819                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1873048                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             101561                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         66718625                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            4981358                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       88194612                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    17207670                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9548212                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      60206161                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1322349                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 5969                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles            25                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles        13195                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  22764676                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 68972                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           65867882                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              1.694526                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.296864                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 20086614     30.50%     30.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  8263984     12.55%     43.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  9201027     13.97%     57.01% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 28316257     42.99%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             65867882                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.257914                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.321889                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  8560400                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              19609685                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  31575881                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               5629864                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 492052                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3179520                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                171002                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              101414286                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts               3048471                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 492052                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 13316863                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 5341740                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         787564                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  32235527                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              13694136                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts               99203918                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts                983561                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               3871797                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  66642                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                4317748                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                5384160                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           103925780                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             457714134                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        115415425                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups               550                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 10296554                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              18659                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          18650                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12695794                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             24322207                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            21994092                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           1403605                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          2365005                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                   98166864                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               34522                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  94891849                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            694587                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined         7414208                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     20250811                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            736                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      65867882                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.440639                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.150059                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            17597825     26.72%     26.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            17436284     26.47%     53.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            17101122     25.96%     79.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            11678255     17.73%     96.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             2053424      3.12%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5                 972      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        65867882                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                 6717330     22.42%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                     38      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     22.42% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               11201861     37.39%     59.81% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              12041280     40.19%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              49497025     52.16%     52.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                89873      0.09%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                  31      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.26% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             24063293     25.36%     77.61% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21241620     22.39%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               94891849                       # Type of FU issued
system.cpu.iq.rate                           1.422269                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    29960509                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.315733                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          286306469                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         105626883                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     93465742                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 207                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                248                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses           57                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              124852240                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     118                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1363033                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      1455945                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         2039                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        11790                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1438354                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       142055                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked        176720                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 492052                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                  623106                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                467581                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts            98211247                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              24322207                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             21994092                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              18602                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   1655                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                463043                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          11790                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         303168                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       221686                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               524854                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              93974313                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              23756309                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts            917536                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9861                       # number of nop insts executed
system.cpu.iew.exec_refs                     44740784                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14252664                       # Number of branches executed
system.cpu.iew.exec_stores                   20984475                       # Number of stores executed
system.cpu.iew.exec_rate                     1.408517                       # Inst execution rate
system.cpu.iew.wb_sent                       93587501                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      93465799                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  44986533                       # num instructions producing a value
system.cpu.iew.wb_consumers                  76576760                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.400895                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.587470                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts         6538748                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            479015                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     64808930                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.399315                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.164562                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     31222194     48.18%     48.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     16795938     25.92%     74.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      4338232      6.69%     80.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      4159188      6.42%     87.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1936724      2.99%     90.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1268170      1.96%     92.15% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       738929      1.14%     93.29% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       579590      0.89%     94.18% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3769965      5.82%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     64808930                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
system.cpu.commit.committedOps               90688136                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       43422000                       # Number of memory references committed
system.cpu.commit.loads                      22866262                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741485                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  81528487                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         47186010     52.03%     52.03% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22866262     25.21%     77.33% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          90688136                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3769965                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    158240550                       # The number of ROB reads
system.cpu.rob.rob_writes                   195514428                       # The number of ROB writes
system.cpu.timesIdled                           23835                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          850743                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
system.cpu.committedOps                      90682584                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.940923                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.940923                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.062786                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.062786                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                102271067                       # number of integer regfile reads
system.cpu.int_regfile_writes                56793819                       # number of integer regfile writes
system.cpu.fp_regfile_reads                        36                       # number of floating regfile reads
system.cpu.fp_regfile_writes                       21                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 346093039                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 38805147                       # number of cc regfile writes
system.cpu.misc_regfile_reads                44210055                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.dcache.tags.replacements            485079                       # number of replacements
system.cpu.dcache.tags.tagsinuse           510.744077                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40428139                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            485591                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             83.255536                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         152734000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   510.744077                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.997547                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.997547                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           58                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          454                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          84616103                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         84616103                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     21501727                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21501727                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18833421                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18833421                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        61667                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         61667                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15379                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15379                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40335148                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40335148                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40396815                       # number of overall hits
system.cpu.dcache.overall_hits::total        40396815                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       552941                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        552941                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1016480                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1016480                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        67175                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        67175                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          547                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          547                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1569421                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1569421                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1636596                       # number of overall misses
system.cpu.dcache.overall_misses::total       1636596                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   9116754245                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   9116754245                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  14723087903                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  14723087903                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      5168250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      5168250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  23839842148                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  23839842148                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  23839842148                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  23839842148                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22054668                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22054668                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       128842                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       128842                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        15926                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41904569                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41904569                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42033411                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42033411                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.025071                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.025071                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.051208                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.051208                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.521375                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.521375                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.034346                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.034346                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037452                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037452                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.038936                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.038936                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16487.752301                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 16487.752301                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14484.385234                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 14484.385234                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9448.354662                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  9448.354662                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 15190.214830                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 15190.214830                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14566.723949                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14566.723949                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs           97                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      3023244                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                11                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets          128456                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs     8.818182                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    23.535249                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       262833                       # number of writebacks
system.cpu.dcache.writebacks::total            262833                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       253459                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       253459                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data       867955                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total       867955                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          547                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          547                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1121414                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1121414                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1121414                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1121414                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       299482                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       299482                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       148525                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       148525                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        37595                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        37595                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       448007                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       448007                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       485602                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       485602                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3044598863                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   3044598863                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2289083292                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   2289083292                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   2038189218                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   2038189218                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5333682155                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   5333682155                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7371871373                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   7371871373                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013579                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.013579                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.007482                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.007482                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.291791                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.291791                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.010691                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.010691                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.011553                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.011553                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10166.216544                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10166.216544                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15412.107672                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15412.107672                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54214.369411                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54214.369411                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11905.354503                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11905.354503                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15180.891703                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 15180.891703                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            322801                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.305225                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            22431720                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            323313                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             69.380817                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle        1103729250                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.305225                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.996690                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.996690                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           58                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            6                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3          352                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4            7                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          45852448                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         45852448                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     22431720                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        22431720                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      22431720                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         22431720                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     22431720                       # number of overall hits
system.cpu.icache.overall_hits::total        22431720                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       332842                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        332842                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       332842                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         332842                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       332842                       # number of overall misses
system.cpu.icache.overall_misses::total        332842                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   3383637839                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   3383637839                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   3383637839                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   3383637839                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   3383637839                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   3383637839                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     22764562                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     22764562                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     22764562                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     22764562                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     22764562                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     22764562                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014621                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014621                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014621                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014621                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014621                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014621                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10165.898051                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 10165.898051                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 10165.898051                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 10165.898051                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 10165.898051                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 10165.898051                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs       260603                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           49                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs             14904                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    17.485440                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    24.500000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         9518                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         9518                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         9518                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         9518                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         9518                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         9518                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst       323324                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       323324                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst       323324                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       323324                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst       323324                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       323324                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2932923000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   2932923000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2932923000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   2932923000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2932923000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   2932923000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.014203                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.014203                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014203                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.014203                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  9071.157724                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  9071.157724                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  9071.157724                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total  9071.157724                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  9071.157724                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total  9071.157724                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued       824674                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified       826525                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit         1627                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage        78731                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements           129661                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        16079.092385                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             870667                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           145945                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             5.965720                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 12574.733150                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1436.327637                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1964.109767                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   103.921830                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.767501                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.087666                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.119880                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.006343                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.981390                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022           37                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        16247                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1            8                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2            4                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::3           19                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4            6                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          154                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2630                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        11951                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          605                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          907                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.002258                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.991638                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         17442481                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        17442481                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst       313998                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data       305857                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         619855                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       262833                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       262833                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data            5                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total            5                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       137138                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       137138                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst       313998                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       442995                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          756993                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst       313998                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       442995                       # number of overall hits
system.cpu.l2cache.overall_hits::total         756993                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         9315                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        31171                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        40486                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data            6                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total            6                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data        11425                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        11425                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         9315                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data        42596                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         51911                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         9315                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data        42596                       # number of overall misses
system.cpu.l2cache.overall_misses::total        51911                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    727315493                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2737689508                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   3465005001                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1245872330                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   1245872330                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    727315493                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   3983561838                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total   4710877331                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    727315493                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   3983561838                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total   4710877331                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst       323313                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data       337028                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       660341                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       262833                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       262833                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data           11                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total           11                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       148563                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       148563                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst       323313                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       485591                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       808904                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       323313                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       485591                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       808904                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.028811                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.092488                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.061311                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.545455                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.545455                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.076903                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.076903                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.028811                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.087720                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.064174                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.028811                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.087720                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.064174                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78080.031455                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87828.093677                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 85585.264067                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109047.906346                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109047.906346                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78080.031455                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93519.622453                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 90749.115428                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78080.031455                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93519.622453                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 90749.115428                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        97887                       # number of writebacks
system.cpu.l2cache.writebacks::total            97887                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           40                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          132                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total          172                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data         3155                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total         3155                       # number of ReadExReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           40                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data         3287                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total         3327                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           40                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data         3287                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total         3327                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         9275                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31039                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        40314                       # number of ReadReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher       112789                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total       112789                       # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total            6                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         8270                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total         8270                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         9275                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data        39309                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        48584                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         9275                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data        39309                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher       112789                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       161373                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    645635507                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   2465712994                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   3111348501                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher  10913543372                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total  10913543372                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        83006                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        83006                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    614828776                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    614828776                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    645635507                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3080541770                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   3726177277                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    645635507                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3080541770                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher  10913543372                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  14639720649                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.028687                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.092096                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.061050                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.545455                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.545455                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.055667                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.055667                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.028687                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.080951                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.060062                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.028687                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.080951                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.199496                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69610.297251                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79439.189214                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77177.866275                       # average ReadReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96760.706913                       # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13834.333333                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13834.333333                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74344.471100                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74344.471100                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69610.297251                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78367.340049                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76695.563910                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69610.297251                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78367.340049                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90719.765072                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq         660352                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp        660352                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       262833                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq       151427                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq           11                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp           11                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       148563                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       148563                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       646637                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      1234037                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           1880674                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     20692032                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     47899136                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           68591168                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      151438                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1223186                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.123797                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.329350                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3            1071759     87.62%     87.62% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4             151427     12.38%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1223186                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      798712500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          2.4                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy     486658187                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          1.5                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     734620345                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          2.2                       # Layer utilization (%)
system.membus.trans_dist::ReadReq              137260                       # Transaction distribution
system.membus.trans_dist::ReadResp             137260                       # Transaction distribution
system.membus.trans_dist::Writeback             97887                       # Transaction distribution
system.membus.trans_dist::UpgradeReq                6                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               6                       # Transaction distribution
system.membus.trans_dist::ReadExReq              8270                       # Transaction distribution
system.membus.trans_dist::ReadExResp             8270                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       388959                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 388959                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     15578688                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                15578688                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            243423                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  243423    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              243423                       # Request fanout histogram
system.membus.reqLayer0.occupancy           692237323                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               2.1                       # Layer utilization (%)
system.membus.respLayer1.occupancy          758965490                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------