stats.txt revision 10628
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 310628Sandreas.hansson@arm.comsim_seconds 0.033020 # Number of seconds simulated 410628Sandreas.hansson@arm.comsim_ticks 33019504000 # Number of ticks simulated 510628Sandreas.hansson@arm.comfinal_tick 33019504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710628Sandreas.hansson@arm.comhost_inst_rate 123822 # Simulator instruction rate (inst/s) 810628Sandreas.hansson@arm.comhost_op_rate 158353 # Simulator op (including micro ops) rate (op/s) 910628Sandreas.hansson@arm.comhost_tick_rate 57659893 # Simulator tick rate (ticks/s) 1010628Sandreas.hansson@arm.comhost_mem_usage 322352 # Number of bytes of host memory used 1110628Sandreas.hansson@arm.comhost_seconds 572.66 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 70907629 # Number of instructions simulated 1310352Sandreas.hansson@arm.comsim_ops 90682584 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 588736 # Number of bytes read from this memory 1710628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 2517376 # Number of bytes read from this memory 1810628Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 6201600 # Number of bytes read from this memory 1910628Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 9307712 # Number of bytes read from this memory 2010628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 588736 # Number of instructions bytes read from this memory 2110628Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 588736 # Number of instructions bytes read from this memory 2210628Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 6262016 # Number of bytes written to this memory 2310628Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 6262016 # Number of bytes written to this memory 2410628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 9199 # Number of read requests responded to by this memory 2510628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 39334 # Number of read requests responded to by this memory 2610628Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 96900 # Number of read requests responded to by this memory 2710628Sandreas.hansson@arm.comsystem.physmem.num_reads::total 145433 # Number of read requests responded to by this memory 2810628Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 97844 # Number of write requests responded to by this memory 2910628Sandreas.hansson@arm.comsystem.physmem.num_writes::total 97844 # Number of write requests responded to by this memory 3010628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 17829947 # Total read bandwidth from this memory (bytes/s) 3110628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 76239062 # Total read bandwidth from this memory (bytes/s) 3210628Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 187816268 # Total read bandwidth from this memory (bytes/s) 3310628Sandreas.hansson@arm.comsystem.physmem.bw_read::total 281885276 # Total read bandwidth from this memory (bytes/s) 3410628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 17829947 # Instruction read bandwidth from this memory (bytes/s) 3510628Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 17829947 # Instruction read bandwidth from this memory (bytes/s) 3610628Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 189645974 # Write bandwidth from this memory (bytes/s) 3710628Sandreas.hansson@arm.comsystem.physmem.bw_write::total 189645974 # Write bandwidth from this memory (bytes/s) 3810628Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 189645974 # Total bandwidth to/from this memory (bytes/s) 3910628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 17829947 # Total bandwidth to/from this memory (bytes/s) 4010628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 76239062 # Total bandwidth to/from this memory (bytes/s) 4110628Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 187816268 # Total bandwidth to/from this memory (bytes/s) 4210628Sandreas.hansson@arm.comsystem.physmem.bw_total::total 471531250 # Total bandwidth to/from this memory (bytes/s) 4310628Sandreas.hansson@arm.comsystem.physmem.readReqs 145433 # Number of read requests accepted 4410628Sandreas.hansson@arm.comsystem.physmem.writeReqs 97844 # Number of write requests accepted 4510628Sandreas.hansson@arm.comsystem.physmem.readBursts 145433 # Number of DRAM read bursts, including those serviced by the write queue 4610628Sandreas.hansson@arm.comsystem.physmem.writeBursts 97844 # Number of DRAM write bursts, including those merged in the write queue 4710628Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 9300480 # Total number of bytes read from DRAM 4810628Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue 4910628Sandreas.hansson@arm.comsystem.physmem.bytesWritten 6260352 # Total number of bytes written to DRAM 5010628Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 9307712 # Total read bytes from the system interface side 5110628Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 6262016 # Total written bytes from the system interface side 5210628Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue 539978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5410409Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write 5510628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 9146 # Per bank write bursts 5610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 9381 # Per bank write bursts 5710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 9349 # Per bank write bursts 5810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 9489 # Per bank write bursts 5910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 9691 # Per bank write bursts 6010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 9742 # Per bank write bursts 6110628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 9065 # Per bank write bursts 6210628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 9033 # Per bank write bursts 6310628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 9160 # Per bank write bursts 6410628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 8585 # Per bank write bursts 6510628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 8818 # Per bank write bursts 6610628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 8754 # Per bank write bursts 6710628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 8666 # Per bank write bursts 6810628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 8713 # Per bank write bursts 6910628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 8726 # Per bank write bursts 7010628Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 9002 # Per bank write bursts 7110628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 5993 # Per bank write bursts 7210628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 6194 # Per bank write bursts 7310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 6159 # Per bank write bursts 7410628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 6198 # Per bank write bursts 7510628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 6133 # Per bank write bursts 7610628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6325 # Per bank write bursts 7710628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6074 # Per bank write bursts 7810628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6046 # Per bank write bursts 7910628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 6012 # Per bank write bursts 8010628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6139 # Per bank write bursts 8110628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 6243 # Per bank write bursts 8210628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 5934 # Per bank write bursts 8310628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 6049 # Per bank write bursts 8410628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 6103 # Per bank write bursts 8510628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 6164 # Per bank write bursts 8610628Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 6052 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 889978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8910628Sandreas.hansson@arm.comsystem.physmem.totGap 33019298500 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9610628Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 145433 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10310628Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 97844 # Write request sizes (log2) 10410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 47136 # What read queue length does an incoming req see 10510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 46826 # What read queue length does an incoming req see 10610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 17078 # What read queue length does an incoming req see 10710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 9801 # What read queue length does an incoming req see 10810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 6398 # What read queue length does an incoming req see 10910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 5373 # What read queue length does an incoming req see 11010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 4750 # What read queue length does an incoming req see 11110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 4278 # What read queue length does an incoming req see 11210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 3551 # What read queue length does an incoming req see 11310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see 11410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 11510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see 11610628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 11710628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11810628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1117 # What write queue length does an incoming req see 15210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 1152 # What write queue length does an incoming req see 15310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 1935 # What write queue length does an incoming req see 15410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 2597 # What write queue length does an incoming req see 15510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 3403 # What write queue length does an incoming req see 15610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 4356 # What write queue length does an incoming req see 15710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 5168 # What write queue length does an incoming req see 15810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 5608 # What write queue length does an incoming req see 15910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 5930 # What write queue length does an incoming req see 16010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 6190 # What write queue length does an incoming req see 16110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 6581 # What write queue length does an incoming req see 16210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 7181 # What write queue length does an incoming req see 16310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 7838 # What write queue length does an incoming req see 16410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see 16510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 8277 # What write queue length does an incoming req see 16610628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 7722 # What write queue length does an incoming req see 16710628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 7174 # What write queue length does an incoming req see 16810628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 6437 # What write queue length does an incoming req see 16910628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see 17010628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 72 # What write queue length does an incoming req see 17110628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see 17210628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see 17310628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see 17410628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see 17510628Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see 17610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 18010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 18110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 18210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 19010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 19110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 19210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 20010628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 88783 # Bytes accessed per row activation 20110628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 175.237151 # Bytes accessed per row activation 20210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 110.501041 # Bytes accessed per row activation 20310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 239.251674 # Bytes accessed per row activation 20410628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 52191 58.78% 58.78% # Bytes accessed per row activation 20510628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 22671 25.54% 84.32% # Bytes accessed per row activation 20610628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4463 5.03% 89.35% # Bytes accessed per row activation 20710628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 1678 1.89% 91.24% # Bytes accessed per row activation 20810628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 979 1.10% 92.34% # Bytes accessed per row activation 20910628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 876 0.99% 93.33% # Bytes accessed per row activation 21010628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 737 0.83% 94.16% # Bytes accessed per row activation 21110628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 796 0.90% 95.05% # Bytes accessed per row activation 21210628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 4392 4.95% 100.00% # Bytes accessed per row activation 21310628Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 88783 # Bytes accessed per row activation 21410628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5909 # Reads before turning the bus around for writes 21510628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 24.589101 # Reads before turning the bus around for writes 21610628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::gmean 21.077809 # Reads before turning the bus around for writes 21710628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 187.247746 # Reads before turning the bus around for writes 21810628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-511 5908 99.98% 99.98% # Reads before turning the bus around for writes 21910409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes 22010628Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5909 # Reads before turning the bus around for writes 22110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5909 # Writes before turning the bus around for reads 22210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 16.554070 # Writes before turning the bus around for reads 22310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.510446 # Writes before turning the bus around for reads 22410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 1.278697 # Writes before turning the bus around for reads 22510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 4738 80.18% 80.18% # Writes before turning the bus around for reads 22610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::17 25 0.42% 80.61% # Writes before turning the bus around for reads 22710628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 725 12.27% 92.88% # Writes before turning the bus around for reads 22810628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::19 165 2.79% 95.67% # Writes before turning the bus around for reads 22910628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20 107 1.81% 97.48% # Writes before turning the bus around for reads 23010628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::21 76 1.29% 98.76% # Writes before turning the bus around for reads 23110628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::22 36 0.61% 99.37% # Writes before turning the bus around for reads 23210628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::23 24 0.41% 99.78% # Writes before turning the bus around for reads 23310628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24 8 0.14% 99.92% # Writes before turning the bus around for reads 23410628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads 23510628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads 23610628Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5909 # Writes before turning the bus around for reads 23710628Sandreas.hansson@arm.comsystem.physmem.totQLat 7598607995 # Total ticks spent queuing 23810628Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 10323357995 # Total ticks spent from burst creation until serviced by the DRAM 23910628Sandreas.hansson@arm.comsystem.physmem.totBusLat 726600000 # Total ticks spent in databus transfers 24010628Sandreas.hansson@arm.comsystem.physmem.avgQLat 52288.80 # Average queueing delay per DRAM burst 2419978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 24210628Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 71038.80 # Average memory access latency per DRAM burst 24310628Sandreas.hansson@arm.comsystem.physmem.avgRdBW 281.67 # Average DRAM read bandwidth in MiByte/s 24410628Sandreas.hansson@arm.comsystem.physmem.avgWrBW 189.60 # Average achieved write bandwidth in MiByte/s 24510628Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 281.89 # Average system read bandwidth in MiByte/s 24610628Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 189.65 # Average system write bandwidth in MiByte/s 2479978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 24810628Sandreas.hansson@arm.comsystem.physmem.busUtil 3.68 # Data bus utilization in percentage 24910628Sandreas.hansson@arm.comsystem.physmem.busUtilRead 2.20 # Data bus utilization in percentage for reads 25010628Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 1.48 # Data bus utilization in percentage for writes 25110628Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing 25210628Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing 25310628Sandreas.hansson@arm.comsystem.physmem.readRowHits 118226 # Number of row buffer hits during reads 25410628Sandreas.hansson@arm.comsystem.physmem.writeRowHits 36119 # Number of row buffer hits during writes 25510628Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads 25610628Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 36.91 # Row buffer hit rate for writes 25710628Sandreas.hansson@arm.comsystem.physmem.avgGap 135727.17 # Average gap between requests 25810628Sandreas.hansson@arm.comsystem.physmem.pageHitRate 63.47 # Row buffer hit rate, read and write combined 25910628Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 342362160 # Energy for activate commands per rank (pJ) 26010628Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 186804750 # Energy for precharge commands per rank (pJ) 26110628Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 583720800 # Energy for read commands per rank (pJ) 26210628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 318193920 # Energy for write commands per rank (pJ) 26310628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) 26410628Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 11787255720 # Energy for active background per rank (pJ) 26510628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 9468687000 # Energy for precharge background per rank (pJ) 26610628Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 24843318750 # Total energy per rank (pJ) 26710628Sandreas.hansson@arm.comsystem.physmem_0.averagePower 752.509165 # Core power per rank (mW) 26810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 15653624306 # Time in different power states 26910628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1102400000 # Time in different power states 27010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 27110628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 16257963444 # Time in different power states 27210628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 27310628Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 328376160 # Energy for activate commands per rank (pJ) 27410628Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 179173500 # Energy for precharge commands per rank (pJ) 27510628Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 549010800 # Energy for read commands per rank (pJ) 27610628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 315414000 # Energy for write commands per rank (pJ) 27710628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) 27810628Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 11313288180 # Energy for active background per rank (pJ) 27910628Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 9884473500 # Energy for precharge background per rank (pJ) 28010628Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 24726030540 # Total energy per rank (pJ) 28110628Sandreas.hansson@arm.comsystem.physmem_1.averagePower 748.955517 # Core power per rank (mW) 28210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 16351310453 # Time in different power states 28310628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1102400000 # Time in different power states 28410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 28510628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 15560341797 # Time in different power states 28610628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 28710628Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 17204705 # Number of BP lookups 28810628Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 11516912 # Number of conditional branches predicted 28910628Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 648025 # Number of conditional branches incorrect 29010628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 9345879 # Number of BTB lookups 29110628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 7673903 # Number of BTB hits 29210628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 29310628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 82.110019 # BTB Hit Percentage 29410628Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 1872530 # Number of times the RAS was used to get a target. 29510628Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 101564 # Number of incorrect RAS predictions. 29610036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 29710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 29810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 30510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 30610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 30710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 30810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 30910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 31010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 31110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 31210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 31610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 31710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 31810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 31910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 32010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 32110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 32210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 32310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 32410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 32510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 32610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 32710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 32910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3348317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3358317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3368317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3378317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3388317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3398317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3408317SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3418317SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3428317SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3438317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3448317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3458317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3468317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3478317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3488317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3498317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3508317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3518317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3528317SN/Asystem.cpu.dtb.hits 0 # DTB hits 3538317SN/Asystem.cpu.dtb.misses 0 # DTB misses 3548317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 35510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 35610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 36410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 36610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 36810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 36910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 37010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 37410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 37610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 37910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 38010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 38110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 38210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 38310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 38410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 38510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3928317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3938317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3948317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3958317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3968317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3978317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3988317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 3998317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4008317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4018317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4028317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 4038317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4048317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4058317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4068317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4078317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 4088317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 4098317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 4108317SN/Asystem.cpu.itb.hits 0 # DTB hits 4118317SN/Asystem.cpu.itb.misses 0 # DTB misses 4128317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 4138317SN/Asystem.cpu.workload.num_syscalls 1946 # Number of system calls 41410628Sandreas.hansson@arm.comsystem.cpu.numCycles 66039009 # number of cpu cycles simulated 4158317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4168317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41710628Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 4981802 # Number of cycles fetch is stalled on an Icache miss 41810628Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 88178088 # Number of instructions fetch has processed 41910628Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 17204705 # Number of branches that fetch encountered 42010628Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 9546433 # Number of branches that fetch has predicted taken 42110628Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 59635234 # Number of cycles fetch has run and was not squashing or blocked 42210628Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1322107 # Number of cycles fetch has spent squashing 42310628Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 4931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 42410409Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps 42510628Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 10977 # Number of stall cycles due to full MSHR 42610628Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 22758925 # Number of cache lines fetched 42710628Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 68935 # Number of outstanding Icache misses that were squashed 42810628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 65294039 # Number of instructions fetched each cycle (Total) 42910628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.709071 # Number of instructions fetched each cycle (Total) 43010628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.292735 # Number of instructions fetched each cycle (Total) 4318317SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 43210628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 19515211 29.89% 29.89% # Number of instructions fetched each cycle (Total) 43310628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 8274054 12.67% 42.56% # Number of instructions fetched each cycle (Total) 43410628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 9196195 14.08% 56.64% # Number of instructions fetched each cycle (Total) 43510628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 28308579 43.36% 100.00% # Number of instructions fetched each cycle (Total) 4368317SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4378317SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 43810409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 43910628Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 65294039 # Number of instructions fetched each cycle (Total) 44010628Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.260523 # Number of branch fetches per cycle 44110628Sandreas.hansson@arm.comsystem.cpu.fetch.rate 1.335242 # Number of inst fetches per cycle 44210628Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8590503 # Number of cycles decode is idle 44310628Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 19016582 # Number of cycles decode is blocked 44410628Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 31530881 # Number of cycles decode is running 44510628Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 5663983 # Number of cycles decode is unblocking 44610628Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 492090 # Number of cycles decode is squashing 44710628Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 3178633 # Number of times decode resolved a branch 44810628Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 170869 # Number of times decode detected a branch misprediction 44910628Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 101389113 # Number of instructions handled by decode 45010628Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 3042046 # Number of squashed instructions handled by decode 45110628Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 492090 # Number of cycles rename is squashing 45210628Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 13367671 # Number of cycles rename is idle 45310628Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 5222790 # Number of cycles rename is blocking 45410628Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 763292 # count of cycles rename stalled for serializing inst 45510628Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 32193949 # Number of cycles rename is running 45610628Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 13254247 # Number of cycles rename is unblocking 45710628Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 99181436 # Number of instructions processed by rename 45810628Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 981589 # Number of squashed instructions processed by rename 45910628Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 3720885 # Number of times rename has blocked due to ROB full 46010628Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 53337 # Number of times rename has blocked due to IQ full 46110628Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 4029509 # Number of times rename has blocked due to LQ full 46210628Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 5185175 # Number of times rename has blocked due to SQ full 46310628Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 103906436 # Number of destination operands rename has renamed 46410628Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 457606733 # Number of register rename lookups that rename has made 46510628Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 115387380 # Number of integer rename lookups 46610628Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups 46710352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed 46810628Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 10277210 # Number of HB maps that are undone due to squashing 46910628Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 18665 # count of serializing insts renamed 47010628Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed 47110628Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 12765420 # count of insts added to the skid buffer 47210628Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 24319642 # Number of loads inserted to the mem dependence unit. 47310628Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 21987038 # Number of stores inserted to the mem dependence unit. 47410628Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1312197 # Number of conflicting loads. 47510628Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 2209009 # Number of conflicting stores. 47610628Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 98145273 # Number of instructions added to the IQ (excludes non-spec) 47710628Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 34526 # Number of non-speculative instructions added to the IQ 47810628Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 94858951 # Number of instructions issued 47910628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 691771 # Number of squashed instructions issued 48010628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 7393055 # Number of squashed instructions iterated over during squash; mainly for profiling 48110628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 20168064 # Number of squashed operands that are examined and possibly removed from graph 48210628Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed 48310628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 65294039 # Number of insts issued each cycle 48410628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.452796 # Number of insts issued each cycle 48510628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.148580 # Number of insts issued each cycle 4868317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 48710628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 17159256 26.28% 26.28% # Number of insts issued each cycle 48810628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 17193875 26.33% 52.61% # Number of insts issued each cycle 48910628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 17194261 26.33% 78.95% # Number of insts issued each cycle 49010628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 11711028 17.94% 96.88% # Number of insts issued each cycle 49110628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 2034625 3.12% 100.00% # Number of insts issued each cycle 49210628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 994 0.00% 100.00% # Number of insts issued each cycle 49310409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 49410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 49510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 4968317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4978317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 49810409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 49910628Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 65294039 # Number of insts issued each cycle 5008317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 50110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 6670808 22.11% 22.11% # attempts to use FU when none available 50210628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 41 0.00% 22.11% # attempts to use FU when none available 50310628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 22.11% # attempts to use FU when none available 50410628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 22.11% # attempts to use FU when none available 50510628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 22.11% # attempts to use FU when none available 50610628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 22.11% # attempts to use FU when none available 50710628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 22.11% # attempts to use FU when none available 50810628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 22.11% # attempts to use FU when none available 50910628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.11% # attempts to use FU when none available 51010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 22.11% # attempts to use FU when none available 51110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.11% # attempts to use FU when none available 51210628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 22.11% # attempts to use FU when none available 51310628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 22.11% # attempts to use FU when none available 51410628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 22.11% # attempts to use FU when none available 51510628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 22.11% # attempts to use FU when none available 51610628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 22.11% # attempts to use FU when none available 51710628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.11% # attempts to use FU when none available 51810628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 22.11% # attempts to use FU when none available 51910628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.11% # attempts to use FU when none available 52010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.11% # attempts to use FU when none available 52110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.11% # attempts to use FU when none available 52210628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.11% # attempts to use FU when none available 52310628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.11% # attempts to use FU when none available 52410628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.11% # attempts to use FU when none available 52510628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.11% # attempts to use FU when none available 52610628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.11% # attempts to use FU when none available 52710628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.11% # attempts to use FU when none available 52810628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.11% # attempts to use FU when none available 52910628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.11% # attempts to use FU when none available 53010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 11293243 37.42% 59.53% # attempts to use FU when none available 53110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 12213472 40.47% 100.00% # attempts to use FU when none available 5328317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5338317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5348317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 53510628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 49494148 52.18% 52.18% # Type of FU issued 53610628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 89879 0.09% 52.27% # Type of FU issued 53710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued 53810628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.27% # Type of FU issued 53910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued 54010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued 54110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued 54210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued 54310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued 54410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued 54510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued 54610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued 54710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued 54810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued 54910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued 55010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued 55110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued 55210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued 55310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued 55410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued 55510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued 55610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued 55710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued 55810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued 55910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued 56010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued 56110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued 56210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued 56310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued 56410628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 24035201 25.34% 77.61% # Type of FU issued 56510628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 21239685 22.39% 100.00% # Type of FU issued 5668317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5678317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 56810628Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 94858951 # Type of FU issued 56910628Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.436408 # Inst issue rate 57010628Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 30177564 # FU busy when requested 57110628Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.318131 # FU busy rate (busy events/executed inst) 57210628Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 285881069 # Number of integer instruction queue reads 57310628Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 105584154 # Number of integer instruction queue writes 57410628Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 93463006 # Number of integer instruction queue wakeup accesses 57510628Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads 57610628Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes 57710409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses 57810628Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 125036397 # Number of integer alu accesses 57910628Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses 58010628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 1353483 # Number of loads that had data forwarded from stores 5818317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 58210628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1453380 # Number of loads squashed 58310628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed 58410628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 11797 # Number of memory ordering violations 58510628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 1431300 # Number of stores squashed 5868317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5878317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 58810628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 120407 # Number of loads that were rescheduled 58910628Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 169543 # Number of times an access to memory failed due to the cache being blocked 5908317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 59110628Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 492090 # Number of cycles IEW is squashing 59210628Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 617243 # Number of cycles IEW is blocking 59310628Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 370435 # Number of cycles IEW is unblocking 59410628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 98189662 # Number of instructions dispatched to IQ 59510409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 59610628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 24319642 # Number of dispatched load instructions 59710628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 21987038 # Number of dispatched store instructions 59810628Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 18606 # Number of dispatched non-speculative instructions 59910628Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 1603 # Number of times the IQ has become full, causing a stall 60010628Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 365951 # Number of times the LSQ has become full, causing a stall 60110628Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 11797 # Number of memory order violations 60210628Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 302833 # Number of branches that were predicted taken incorrectly 60310628Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 221503 # Number of branches that were predicted not taken incorrectly 60410628Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 524336 # Number of branch mispredicts detected at execute 60510628Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 93942350 # Number of executed instructions 60610628Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 23727911 # Number of load instructions executed 60710628Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 916601 # Number of squashed instructions skipped in execute 6088317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 60910628Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 9863 # number of nop insts executed 61010628Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 44710370 # number of memory reference insts executed 61110628Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 14251746 # Number of branches executed 61210628Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 20982459 # Number of stores executed 61310628Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.422528 # Inst execution rate 61410628Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 93584307 # cumulative count of insts sent to commit 61510628Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 93463063 # cumulative count of insts written-back 61610628Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 44927637 # num instructions producing a value 61710628Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 76497349 # num instructions consuming a value 6188317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 61910628Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.415271 # insts written-back per cycle 62010628Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.587310 # average fanout of values written-back 6218317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 62210628Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6519180 # The number of squashed insts skipped by commit 6239459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 62410628Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 479062 # The number of times a branch was mispredicted 62510628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 64238392 # Number of insts commited each cycle 62610628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.411744 # Number of insts commited each cycle 62710628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.175817 # Number of insts commited each cycle 6288241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 62910628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 30786432 47.93% 47.93% # Number of insts commited each cycle 63010628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 16709618 26.01% 73.94% # Number of insts commited each cycle 63110628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4274980 6.65% 80.59% # Number of insts commited each cycle 63210628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 4124415 6.42% 87.01% # Number of insts commited each cycle 63310628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1949899 3.04% 90.05% # Number of insts commited each cycle 63410628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 1296449 2.02% 92.07% # Number of insts commited each cycle 63510628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 706597 1.10% 93.17% # Number of insts commited each cycle 63610628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 586126 0.91% 94.08% # Number of insts commited each cycle 63710628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 3803876 5.92% 100.00% # Number of insts commited each cycle 6388241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6398241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6408241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 64110628Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 64238392 # Number of insts commited each cycle 6429459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 70913181 # Number of instructions committed 64310352Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed 6448317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 64510352Sandreas.hansson@arm.comsystem.cpu.commit.refs 43422000 # Number of memory references committed 64610352Sandreas.hansson@arm.comsystem.cpu.commit.loads 22866262 # Number of loads committed 6478317SN/Asystem.cpu.commit.membars 15920 # Number of memory barriers committed 6489575Ssaidi@eecs.umich.edusystem.cpu.commit.branches 13741485 # Number of branches committed 6498241SN/Asystem.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 65010352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 81528487 # Number of committed integer instructions. 6518241SN/Asystem.cpu.commit.function_calls 1679850 # Number of function calls committed. 65210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 65310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 47186010 52.03% 52.03% # Class of committed instruction 65410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 65510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 65610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 65710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 65810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 65910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction 66010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction 66110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction 66210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction 66310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction 66410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction 66510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction 66610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction 66710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction 66810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction 66910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction 67010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction 67110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction 67210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction 67310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction 67410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction 67510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction 67610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction 67710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction 67810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction 67910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 68010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 68110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 68210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 68310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 68410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 68510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 68610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 90688136 # Class of committed instruction 68710628Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 3803876 # number cycles where commit BW limit reached 6888317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 68910628Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 157616533 # The number of ROB reads 69010628Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 195472136 # The number of ROB writes 69110628Sandreas.hansson@arm.comsystem.cpu.timesIdled 23660 # Number of times that the entire CPU went into an idle state and unscheduled itself 69210628Sandreas.hansson@arm.comsystem.cpu.idleCycles 744970 # Total number of cycles that the CPU has spent unscheduled due to idling 6939459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 70907629 # Number of Instructions Simulated 69410352Sandreas.hansson@arm.comsystem.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated 69510628Sandreas.hansson@arm.comsystem.cpu.cpi 0.931339 # CPI: Cycles Per Instruction 69610628Sandreas.hansson@arm.comsystem.cpu.cpi_total 0.931339 # CPI: Total CPI of All Threads 69710628Sandreas.hansson@arm.comsystem.cpu.ipc 1.073723 # IPC: Instructions Per Cycle 69810628Sandreas.hansson@arm.comsystem.cpu.ipc_total 1.073723 # IPC: Total IPC of All Threads 69910628Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 102238235 # number of integer regfile reads 70010628Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 56792997 # number of integer regfile writes 70110409Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 36 # number of floating regfile reads 70210409Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 21 # number of floating regfile writes 70310628Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 345997909 # number of cc regfile reads 70410628Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 38804494 # number of cc regfile writes 70510628Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 44208348 # number of misc regfile reads 7069459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 31840 # number of misc regfile writes 70710628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 485280 # number of replacements 70810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 510.769602 # Cycle average of tags in use 70910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 40441610 # Total number of references to valid blocks. 71010628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 485792 # Sample count of references to valid blocks. 71110628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 83.248818 # Average number of references to valid blocks. 71210628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 148406000 # Cycle when the warmup percentage was hit. 71310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 510.769602 # Average occupied blocks per requestor 71410628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.997597 # Average percentage of cache occupancy 71510628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.997597 # Average percentage of cache occupancy 71610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 71710628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 71810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id 71910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 72010628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 84635072 # Number of tag accesses 72110628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 84635072 # Number of data accesses 72210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 21513403 # number of ReadReq hits 72310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 21513403 # number of ReadReq hits 72410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 18834640 # number of WriteReq hits 72510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 18834640 # number of WriteReq hits 72610628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 62245 # number of SoftPFReq hits 72710628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 62245 # number of SoftPFReq hits 72810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits 72910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits 73010628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 73110628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 73210628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 40348043 # number of demand (read+write) hits 73310628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 40348043 # number of demand (read+write) hits 73410628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 40410288 # number of overall hits 73510628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 40410288 # number of overall hits 73610628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 550665 # number of ReadReq misses 73710628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 550665 # number of ReadReq misses 73810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1015261 # number of WriteReq misses 73910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1015261 # number of WriteReq misses 74010628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 66581 # number of SoftPFReq misses 74110628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 66581 # number of SoftPFReq misses 74210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses 74310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses 74410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1565926 # number of demand (read+write) misses 74510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1565926 # number of demand (read+write) misses 74610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1632507 # number of overall misses 74710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1632507 # number of overall misses 74810628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 8659099753 # number of ReadReq miss cycles 74910628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 8659099753 # number of ReadReq miss cycles 75010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 14372727937 # number of WriteReq miss cycles 75110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 14372727937 # number of WriteReq miss cycles 75210628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4891750 # number of LoadLockedReq miss cycles 75310628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 4891750 # number of LoadLockedReq miss cycles 75410628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 23031827690 # number of demand (read+write) miss cycles 75510628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 23031827690 # number of demand (read+write) miss cycles 75610628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 23031827690 # number of overall miss cycles 75710628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 23031827690 # number of overall miss cycles 75810628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 22064068 # number of ReadReq accesses(hits+misses) 75910628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 22064068 # number of ReadReq accesses(hits+misses) 76010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 76110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 76210628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 128826 # number of SoftPFReq accesses(hits+misses) 76310628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 128826 # number of SoftPFReq accesses(hits+misses) 76410628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) 76510628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) 76610628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 76710628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 76810628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 41913969 # number of demand (read+write) accesses 76910628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 41913969 # number of demand (read+write) accesses 77010628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 42042795 # number of overall (read+write) accesses 77110628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 42042795 # number of overall (read+write) accesses 77210628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024958 # miss rate for ReadReq accesses 77310628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.024958 # miss rate for ReadReq accesses 77410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051147 # miss rate for WriteReq accesses 77510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.051147 # miss rate for WriteReq accesses 77610628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516829 # miss rate for SoftPFReq accesses 77710628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.516829 # miss rate for SoftPFReq accesses 77810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses 77910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses 78010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.037360 # miss rate for demand accesses 78110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.037360 # miss rate for demand accesses 78210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.038830 # miss rate for overall accesses 78310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.038830 # miss rate for overall accesses 78410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15724.805014 # average ReadReq miss latency 78510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 15724.805014 # average ReadReq miss latency 78610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14156.682801 # average WriteReq miss latency 78710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 14156.682801 # average WriteReq miss latency 78810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8942.870201 # average LoadLockedReq miss latency 78910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8942.870201 # average LoadLockedReq miss latency 79010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 14708.120109 # average overall miss latency 79110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 14708.120109 # average overall miss latency 79210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 14108.256620 # average overall miss latency 79310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 14108.256620 # average overall miss latency 79410628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked 79510628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 2883834 # number of cycles access was blocked 79610628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 79710628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 127457 # number of cycles access was blocked 79810628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked 79910628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 22.625937 # average number of cycles each access was blocked 80010628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 80110628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 80210628Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 264417 # number of writebacks 80310628Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 264417 # number of writebacks 80410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 250985 # number of ReadReq MSHR hits 80510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 250985 # number of ReadReq MSHR hits 80610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 866735 # number of WriteReq MSHR hits 80710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 866735 # number of WriteReq MSHR hits 80810628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # number of LoadLockedReq MSHR hits 80910628Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 547 # number of LoadLockedReq MSHR hits 81010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 1117720 # number of demand (read+write) MSHR hits 81110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 1117720 # number of demand (read+write) MSHR hits 81210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 1117720 # number of overall MSHR hits 81310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 1117720 # number of overall MSHR hits 81410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 299680 # number of ReadReq MSHR misses 81510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 299680 # number of ReadReq MSHR misses 81610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 148526 # number of WriteReq MSHR misses 81710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 148526 # number of WriteReq MSHR misses 81810628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses 81910628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses 82010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 448206 # number of demand (read+write) MSHR misses 82110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 448206 # number of demand (read+write) MSHR misses 82210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 485803 # number of overall MSHR misses 82310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 485803 # number of overall MSHR misses 82410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2833367604 # number of ReadReq MSHR miss cycles 82510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 2833367604 # number of ReadReq MSHR miss cycles 82610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2154211948 # number of WriteReq MSHR miss cycles 82710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2154211948 # number of WriteReq MSHR miss cycles 82810628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1934780357 # number of SoftPFReq MSHR miss cycles 82910628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1934780357 # number of SoftPFReq MSHR miss cycles 83010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 4987579552 # number of demand (read+write) MSHR miss cycles 83110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 4987579552 # number of demand (read+write) MSHR miss cycles 83210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 6922359909 # number of overall MSHR miss cycles 83310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 6922359909 # number of overall MSHR miss cycles 83410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013582 # mshr miss rate for ReadReq accesses 83510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013582 # mshr miss rate for ReadReq accesses 83610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses 83710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses 83810628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291843 # mshr miss rate for SoftPFReq accesses 83910628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291843 # mshr miss rate for SoftPFReq accesses 84010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010693 # mshr miss rate for demand accesses 84110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.010693 # mshr miss rate for demand accesses 84210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses 84310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses 84410628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9454.643633 # average ReadReq mshr miss latency 84510628Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9454.643633 # average ReadReq mshr miss latency 84610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14503.938354 # average WriteReq mshr miss latency 84710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14503.938354 # average WriteReq mshr miss latency 84810628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51461.030322 # average SoftPFReq mshr miss latency 84910628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51461.030322 # average SoftPFReq mshr miss latency 85010628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11127.873237 # average overall mshr miss latency 85110628Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 11127.873237 # average overall mshr miss latency 85210628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14249.314864 # average overall mshr miss latency 85310628Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 14249.314864 # average overall mshr miss latency 85410628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 85510628Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 322868 # number of replacements 85610628Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 510.284584 # Cycle average of tags in use 85710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 22426703 # Total number of references to valid blocks. 85810628Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 323380 # Sample count of references to valid blocks. 85910628Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 69.350928 # Average number of references to valid blocks. 86010628Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 1086653000 # Cycle when the warmup percentage was hit. 86110628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 510.284584 # Average occupied blocks per requestor 86210628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.996650 # Average percentage of cache occupancy 86310628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.996650 # Average percentage of cache occupancy 86410628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 86510628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 86610628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id 86710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 86810628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 351 # Occupied blocks per task id 86910628Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 87010628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 87110628Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 45841045 # Number of tag accesses 87210628Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 45841045 # Number of data accesses 87310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 22426703 # number of ReadReq hits 87410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 22426703 # number of ReadReq hits 87510628Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 22426703 # number of demand (read+write) hits 87610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 22426703 # number of demand (read+write) hits 87710628Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 22426703 # number of overall hits 87810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 22426703 # number of overall hits 87910628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 332124 # number of ReadReq misses 88010628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 332124 # number of ReadReq misses 88110628Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 332124 # number of demand (read+write) misses 88210628Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 332124 # number of demand (read+write) misses 88310628Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 332124 # number of overall misses 88410628Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 332124 # number of overall misses 88510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 3299467842 # number of ReadReq miss cycles 88610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 3299467842 # number of ReadReq miss cycles 88710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 3299467842 # number of demand (read+write) miss cycles 88810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 3299467842 # number of demand (read+write) miss cycles 88910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 3299467842 # number of overall miss cycles 89010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 3299467842 # number of overall miss cycles 89110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 22758827 # number of ReadReq accesses(hits+misses) 89210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 22758827 # number of ReadReq accesses(hits+misses) 89310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 22758827 # number of demand (read+write) accesses 89410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 22758827 # number of demand (read+write) accesses 89510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 22758827 # number of overall (read+write) accesses 89610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 22758827 # number of overall (read+write) accesses 89710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014593 # miss rate for ReadReq accesses 89810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.014593 # miss rate for ReadReq accesses 89910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.014593 # miss rate for demand accesses 90010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.014593 # miss rate for demand accesses 90110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.014593 # miss rate for overall accesses 90210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.014593 # miss rate for overall accesses 90310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9934.445695 # average ReadReq miss latency 90410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 9934.445695 # average ReadReq miss latency 90510628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency 90610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 9934.445695 # average overall miss latency 90710628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency 90810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 9934.445695 # average overall miss latency 90910628Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 226617 # number of cycles access was blocked 91010628Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 46 # number of cycles access was blocked 91110628Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 14091 # number of cycles access was blocked 91210628Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked 91310628Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 16.082393 # average number of cycles each access was blocked 91410628Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 23 # average number of cycles each access was blocked 91510628Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 91610628Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 91710628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 8733 # number of ReadReq MSHR hits 91810628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 8733 # number of ReadReq MSHR hits 91910628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 8733 # number of demand (read+write) MSHR hits 92010628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 8733 # number of demand (read+write) MSHR hits 92110628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 8733 # number of overall MSHR hits 92210628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 8733 # number of overall MSHR hits 92310628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 323391 # number of ReadReq MSHR misses 92410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 323391 # number of ReadReq MSHR misses 92510628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 323391 # number of demand (read+write) MSHR misses 92610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 323391 # number of demand (read+write) MSHR misses 92710628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 323391 # number of overall MSHR misses 92810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 323391 # number of overall MSHR misses 92910628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2699093031 # number of ReadReq MSHR miss cycles 93010628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 2699093031 # number of ReadReq MSHR miss cycles 93110628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 2699093031 # number of demand (read+write) MSHR miss cycles 93210628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 2699093031 # number of demand (read+write) MSHR miss cycles 93310628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 2699093031 # number of overall MSHR miss cycles 93410628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 2699093031 # number of overall MSHR miss cycles 93510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for ReadReq accesses 93610628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.014209 # mshr miss rate for ReadReq accesses 93710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for demand accesses 93810628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses 93910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for overall accesses 94010628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.014209 # mshr miss rate for overall accesses 94110628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8346.221852 # average ReadReq mshr miss latency 94210628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8346.221852 # average ReadReq mshr miss latency 94310628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency 94410628Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency 94510628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency 94610628Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency 94710628Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 94810628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 812320 # number of hwpf issued 94910628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 826786 # number of prefetch candidates identified 95010628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 12696 # number of redundant prefetches already in prefetch queue 95110628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 95210628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 95310628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 79190 # number of prefetches not generated due to page crossing 95410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 129572 # number of replacements 95510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 16081.031642 # Cycle average of tags in use 95610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 872493 # Total number of references to valid blocks. 95710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 145853 # Sample count of references to valid blocks. 95810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 5.982002 # Average number of references to valid blocks. 95910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 96010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 12593.782282 # Average occupied blocks per requestor 96110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.951130 # Average occupied blocks per requestor 96210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 1938.685438 # Average occupied blocks per requestor 96310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 114.612791 # Average occupied blocks per requestor 96410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.768663 # Average percentage of cache occupancy 96510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.087521 # Average percentage of cache occupancy 96610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.118328 # Average percentage of cache occupancy 96710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006995 # Average percentage of cache occupancy 96810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.981508 # Average percentage of cache occupancy 96910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 28 # Occupied blocks per task id 97010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 16253 # Occupied blocks per task id 97110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id 97210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id 97310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::3 15 # Occupied blocks per task id 97410628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id 97510628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id 97610628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 2807 # Occupied blocks per task id 97710628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 11875 # Occupied blocks per task id 97810628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 526 # Occupied blocks per task id 97910628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 887 # Occupied blocks per task id 98010628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.001709 # Percentage of cache occupancy per task id 98110628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.992004 # Percentage of cache occupancy per task id 98210628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 17471961 # Number of tag accesses 98310628Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 17471961 # Number of data accesses 98410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 314144 # number of ReadReq hits 98510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 305991 # number of ReadReq hits 98610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 620135 # number of ReadReq hits 98710628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 264417 # number of Writeback hits 98810628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 264417 # number of Writeback hits 98910628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits 99010628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits 99110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 137166 # number of ReadExReq hits 99210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 137166 # number of ReadExReq hits 99310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 314144 # number of demand (read+write) hits 99410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 443157 # number of demand (read+write) hits 99510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 757301 # number of demand (read+write) hits 99610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 314144 # number of overall hits 99710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 443157 # number of overall hits 99810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 757301 # number of overall hits 99910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 9232 # number of ReadReq misses 100010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 31234 # number of ReadReq misses 100110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 40466 # number of ReadReq misses 100210628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 100310628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 100410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 11401 # number of ReadExReq misses 100510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 11401 # number of ReadExReq misses 100610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 9232 # number of demand (read+write) misses 100710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 42635 # number of demand (read+write) misses 100810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 51867 # number of demand (read+write) misses 100910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 9232 # number of overall misses 101010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 42635 # number of overall misses 101110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 51867 # number of overall misses 101210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 649699988 # number of ReadReq miss cycles 101310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 2574698315 # number of ReadReq miss cycles 101410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 3224398303 # number of ReadReq miss cycles 101510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1168450243 # number of ReadExReq miss cycles 101610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1168450243 # number of ReadExReq miss cycles 101710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 649699988 # number of demand (read+write) miss cycles 101810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 3743148558 # number of demand (read+write) miss cycles 101910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 4392848546 # number of demand (read+write) miss cycles 102010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 649699988 # number of overall miss cycles 102110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 3743148558 # number of overall miss cycles 102210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 4392848546 # number of overall miss cycles 102310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 323376 # number of ReadReq accesses(hits+misses) 102410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 337225 # number of ReadReq accesses(hits+misses) 102510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 660601 # number of ReadReq accesses(hits+misses) 102610628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 264417 # number of Writeback accesses(hits+misses) 102710628Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 264417 # number of Writeback accesses(hits+misses) 102810628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 11 # number of UpgradeReq accesses(hits+misses) 102910628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 11 # number of UpgradeReq accesses(hits+misses) 103010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 148567 # number of ReadExReq accesses(hits+misses) 103110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 148567 # number of ReadExReq accesses(hits+misses) 103210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 323376 # number of demand (read+write) accesses 103310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 485792 # number of demand (read+write) accesses 103410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 809168 # number of demand (read+write) accesses 103510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 323376 # number of overall (read+write) accesses 103610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 485792 # number of overall (read+write) accesses 103710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 809168 # number of overall (read+write) accesses 103810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.028549 # miss rate for ReadReq accesses 103910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.092621 # miss rate for ReadReq accesses 104010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.061256 # miss rate for ReadReq accesses 104110628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.545455 # miss rate for UpgradeReq accesses 104210628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.545455 # miss rate for UpgradeReq accesses 104310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076740 # miss rate for ReadExReq accesses 104410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.076740 # miss rate for ReadExReq accesses 104510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.028549 # miss rate for demand accesses 104610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.087764 # miss rate for demand accesses 104710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.064099 # miss rate for demand accesses 104810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.028549 # miss rate for overall accesses 104910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.087764 # miss rate for overall accesses 105010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.064099 # miss rate for overall accesses 105110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70374.782062 # average ReadReq miss latency 105210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82432.551546 # average ReadReq miss latency 105310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 79681.666164 # average ReadReq miss latency 105410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102486.645294 # average ReadExReq miss latency 105510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 102486.645294 # average ReadExReq miss latency 105610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70374.782062 # average overall miss latency 105710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 87795.204832 # average overall miss latency 105810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 84694.479071 # average overall miss latency 105910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70374.782062 # average overall miss latency 106010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 87795.204832 # average overall miss latency 106110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 84694.479071 # average overall miss latency 106210628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106310628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 106410628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 106510628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 106610628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 106710628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 106810628Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 106910628Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 107010628Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 97844 # number of writebacks 107110628Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 97844 # number of writebacks 107210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 33 # number of ReadReq MSHR hits 107310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 152 # number of ReadReq MSHR hits 107410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits 107510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3161 # number of ReadExReq MSHR hits 107610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 3161 # number of ReadExReq MSHR hits 107710628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 33 # number of demand (read+write) MSHR hits 107810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 3313 # number of demand (read+write) MSHR hits 107910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 3346 # number of demand (read+write) MSHR hits 108010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 33 # number of overall MSHR hits 108110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 3313 # number of overall MSHR hits 108210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 3346 # number of overall MSHR hits 108310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9199 # number of ReadReq MSHR misses 108410628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31082 # number of ReadReq MSHR misses 108510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 40281 # number of ReadReq MSHR misses 108610628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112599 # number of HardPFReq MSHR misses 108710628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 112599 # number of HardPFReq MSHR misses 108810628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 108910628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 109010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8240 # number of ReadExReq MSHR misses 109110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 8240 # number of ReadExReq MSHR misses 109210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 9199 # number of demand (read+write) MSHR misses 109310628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 39322 # number of demand (read+write) MSHR misses 109410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 48521 # number of demand (read+write) MSHR misses 109510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 9199 # number of overall MSHR misses 109610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 39322 # number of overall MSHR misses 109710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112599 # number of overall MSHR misses 109810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 161120 # number of overall MSHR misses 109910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 569300762 # number of ReadReq MSHR miss cycles 110010628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2303617903 # number of ReadReq MSHR miss cycles 110110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872918665 # number of ReadReq MSHR miss cycles 110210628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of HardPFReq MSHR miss cycles 110310628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 11396158527 # number of HardPFReq MSHR miss cycles 110410628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39006 # number of UpgradeReq MSHR miss cycles 110510628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39006 # number of UpgradeReq MSHR miss cycles 110610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 539005297 # number of ReadExReq MSHR miss cycles 110710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 539005297 # number of ReadExReq MSHR miss cycles 110810628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 569300762 # number of demand (read+write) MSHR miss cycles 110910628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2842623200 # number of demand (read+write) MSHR miss cycles 111010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 3411923962 # number of demand (read+write) MSHR miss cycles 111110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 569300762 # number of overall MSHR miss cycles 111210628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2842623200 # number of overall MSHR miss cycles 111310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of overall MSHR miss cycles 111410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 14808082489 # number of overall MSHR miss cycles 111510628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for ReadReq accesses 111610628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092170 # mshr miss rate for ReadReq accesses 111710628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.060976 # mshr miss rate for ReadReq accesses 111810628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 111910628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 112010628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses 112110628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses 112210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055463 # mshr miss rate for ReadExReq accesses 112310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055463 # mshr miss rate for ReadExReq accesses 112410628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for demand accesses 112510628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for demand accesses 112610628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.059964 # mshr miss rate for demand accesses 112710628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for overall accesses 112810628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for overall accesses 112910628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 113010628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.199118 # mshr miss rate for overall accesses 113110628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61887.244483 # average ReadReq mshr miss latency 113210628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74114.210894 # average ReadReq mshr miss latency 113310628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71321.930066 # average ReadReq mshr miss latency 113410628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average HardPFReq mshr miss latency 113510628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 101210.121999 # average HardPFReq mshr miss latency 113610628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6501 # average UpgradeReq mshr miss latency 113710628Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6501 # average UpgradeReq mshr miss latency 113810628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65413.264199 # average ReadExReq mshr miss latency 113910628Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65413.264199 # average ReadExReq mshr miss latency 114010628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency 114110628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency 114210628Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 70318.500484 # average overall mshr miss latency 114310628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency 114410628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency 114510628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average overall mshr miss latency 114610628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 91907.165398 # average overall mshr miss latency 114710628Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 114810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 660616 # Transaction distribution 114910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 660616 # Transaction distribution 115010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 264417 # Transaction distribution 115110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 169278 # Transaction distribution 115210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution 115310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution 115410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution 115510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution 115610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646767 # Packet count per connected master and slave (bytes) 115710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1236023 # Packet count per connected master and slave (bytes) 115810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 1882790 # Packet count per connected master and slave (bytes) 115910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20696064 # Cumulative packet size per connected master and slave (bytes) 116010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48013376 # Cumulative packet size per connected master and slave (bytes) 116110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 68709440 # Cumulative packet size per connected master and slave (bytes) 116210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 169293 # Total snoops (count) 116310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 1242889 # Request fanout histogram 116410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 5.136197 # Request fanout histogram 116510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.342998 # Request fanout histogram 116610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 116710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 116810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 116910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 117010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 117110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 117210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::5 1073611 86.38% 86.38% # Request fanout histogram 117310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::6 169278 13.62% 100.00% # Request fanout histogram 117410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 117510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 117610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 117710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 1242889 # Request fanout histogram 117810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 801222500 # Layer occupancy (ticks) 117910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) 118010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 486660171 # Layer occupancy (ticks) 118110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 118210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 734282302 # Layer occupancy (ticks) 118310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) 118410628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 137181 # Transaction distribution 118510628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 137181 # Transaction distribution 118610628Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 97844 # Transaction distribution 118710628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 6 # Transaction distribution 118810628Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 6 # Transaction distribution 118910628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 8252 # Transaction distribution 119010628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 8252 # Transaction distribution 119110628Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388722 # Packet count per connected master and slave (bytes) 119210628Sandreas.hansson@arm.comsystem.membus.pkt_count::total 388722 # Packet count per connected master and slave (bytes) 119310628Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15569728 # Cumulative packet size per connected master and slave (bytes) 119410628Sandreas.hansson@arm.comsystem.membus.pkt_size::total 15569728 # Cumulative packet size per connected master and slave (bytes) 119510628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 119610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 243283 # Request fanout histogram 119710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 119810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 119910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 120010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 243283 100.00% 100.00% # Request fanout histogram 120110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 120210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 120310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 120410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 120510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 243283 # Request fanout histogram 120610628Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 1077095188 # Layer occupancy (ticks) 120710628Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 3.3 # Layer utilization (%) 120810628Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 1335208239 # Layer occupancy (ticks) 120910628Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 4.0 # Layer utilization (%) 12107860SN/A 12117860SN/A---------- End Simulation Statistics ---------- 1212