stats.txt revision 10409
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 310409Sandreas.hansson@arm.comsim_seconds 0.032615 # Number of seconds simulated 410409Sandreas.hansson@arm.comsim_ticks 32615215000 # Number of ticks simulated 510409Sandreas.hansson@arm.comfinal_tick 32615215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710409Sandreas.hansson@arm.comhost_inst_rate 86014 # Simulator instruction rate (inst/s) 810409Sandreas.hansson@arm.comhost_op_rate 110001 # Simulator op (including micro ops) rate (op/s) 910409Sandreas.hansson@arm.comhost_tick_rate 39563517 # Simulator tick rate (ticks/s) 1010409Sandreas.hansson@arm.comhost_mem_usage 333060 # Number of bytes of host memory used 1110409Sandreas.hansson@arm.comhost_seconds 824.38 # Real time elapsed on the host 129459Ssaidi@eecs.umich.edusim_insts 70907629 # Number of instructions simulated 1310352Sandreas.hansson@arm.comsim_ops 90682584 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 133120 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 2337984 # Number of bytes read from this memory 1810409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 7506432 # Number of bytes read from this memory 1910409Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 9977536 # Number of bytes read from this memory 2010409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 133120 # Number of instructions bytes read from this memory 2110409Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 133120 # Number of instructions bytes read from this memory 2210409Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 6303424 # Number of bytes written to this memory 2310409Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 6303424 # Number of bytes written to this memory 2410409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 2080 # Number of read requests responded to by this memory 2510409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 36531 # Number of read requests responded to by this memory 2610409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 117288 # Number of read requests responded to by this memory 2710409Sandreas.hansson@arm.comsystem.physmem.num_reads::total 155899 # Number of read requests responded to by this memory 2810409Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 98491 # Number of write requests responded to by this memory 2910409Sandreas.hansson@arm.comsystem.physmem.num_writes::total 98491 # Number of write requests responded to by this memory 3010409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 4081531 # Total read bandwidth from this memory (bytes/s) 3110409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 71683844 # Total read bandwidth from this memory (bytes/s) 3210409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 230151235 # Total read bandwidth from this memory (bytes/s) 3310409Sandreas.hansson@arm.comsystem.physmem.bw_read::total 305916610 # Total read bandwidth from this memory (bytes/s) 3410409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 4081531 # Instruction read bandwidth from this memory (bytes/s) 3510409Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 4081531 # Instruction read bandwidth from this memory (bytes/s) 3610409Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 193266364 # Write bandwidth from this memory (bytes/s) 3710409Sandreas.hansson@arm.comsystem.physmem.bw_write::total 193266364 # Write bandwidth from this memory (bytes/s) 3810409Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 193266364 # Total bandwidth to/from this memory (bytes/s) 3910409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 4081531 # Total bandwidth to/from this memory (bytes/s) 4010409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 71683844 # Total bandwidth to/from this memory (bytes/s) 4110409Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 230151235 # Total bandwidth to/from this memory (bytes/s) 4210409Sandreas.hansson@arm.comsystem.physmem.bw_total::total 499182973 # Total bandwidth to/from this memory (bytes/s) 4310409Sandreas.hansson@arm.comsystem.physmem.readReqs 155899 # Number of read requests accepted 4410409Sandreas.hansson@arm.comsystem.physmem.writeReqs 98491 # Number of write requests accepted 4510409Sandreas.hansson@arm.comsystem.physmem.readBursts 155899 # Number of DRAM read bursts, including those serviced by the write queue 4610409Sandreas.hansson@arm.comsystem.physmem.writeBursts 98491 # Number of DRAM write bursts, including those merged in the write queue 4710409Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 9968640 # Total number of bytes read from DRAM 4810409Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue 4910409Sandreas.hansson@arm.comsystem.physmem.bytesWritten 6301696 # Total number of bytes written to DRAM 5010409Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 9977536 # Total read bytes from the system interface side 5110409Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 6303424 # Total written bytes from the system interface side 5210409Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue 539978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5410409Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write 5510409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 10106 # Per bank write bursts 5610409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 10077 # Per bank write bursts 5710409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 9750 # Per bank write bursts 5810409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 10345 # Per bank write bursts 5910409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 10619 # Per bank write bursts 6010409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 10733 # Per bank write bursts 6110409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 9548 # Per bank write bursts 6210409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 9567 # Per bank write bursts 6310409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 9971 # Per bank write bursts 6410409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 9445 # Per bank write bursts 6510409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 9639 # Per bank write bursts 6610409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 9476 # Per bank write bursts 6710409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 8930 # Per bank write bursts 6810409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 9084 # Per bank write bursts 6910409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 9062 # Per bank write bursts 7010409Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 9408 # Per bank write bursts 7110409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 6017 # Per bank write bursts 7210409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 6275 # Per bank write bursts 7310409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 6171 # Per bank write bursts 7410409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 6231 # Per bank write bursts 7510409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 6142 # Per bank write bursts 7610409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 6389 # Per bank write bursts 7710409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 6054 # Per bank write bursts 7810409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 6025 # Per bank write bursts 7910409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 6057 # Per bank write bursts 8010409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 6227 # Per bank write bursts 8110409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 6350 # Per bank write bursts 8210409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 5949 # Per bank write bursts 8310409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 6129 # Per bank write bursts 8410409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 6148 # Per bank write bursts 8510409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 6212 # Per bank write bursts 8610409Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 6088 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 889978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8910409Sandreas.hansson@arm.comsystem.physmem.totGap 32615126500 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9610409Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 155899 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10310409Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 98491 # Write request sizes (log2) 10410409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 46242 # What read queue length does an incoming req see 10510409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 51007 # What read queue length does an incoming req see 10610409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 19397 # What read queue length does an incoming req see 10710409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 10907 # What read queue length does an incoming req see 10810409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 7160 # What read queue length does an incoming req see 10910409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 6108 # What read queue length does an incoming req see 11010409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 5351 # What read queue length does an incoming req see 11110409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 4799 # What read queue length does an incoming req see 11210409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 4082 # What read queue length does an incoming req see 11310409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 329 # What read queue length does an incoming req see 11410409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 161 # What read queue length does an incoming req see 11510409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see 11610409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 51 # What read queue length does an incoming req see 11710409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 32 # What read queue length does an incoming req see 11810409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 22 # What read queue length does an incoming req see 11910409Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 12 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1248 # What write queue length does an incoming req see 15210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 1291 # What write queue length does an incoming req see 15310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 1960 # What write queue length does an incoming req see 15410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 2723 # What write queue length does an incoming req see 15510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 3606 # What write queue length does an incoming req see 15610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 4588 # What write queue length does an incoming req see 15710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 5262 # What write queue length does an incoming req see 15810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 5698 # What write queue length does an incoming req see 15910409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 5990 # What write queue length does an incoming req see 16010409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 6308 # What write queue length does an incoming req see 16110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 6755 # What write queue length does an incoming req see 16210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 7385 # What write queue length does an incoming req see 16310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 8090 # What write queue length does an incoming req see 16410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 8877 # What write queue length does an incoming req see 16510409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 7957 # What write queue length does an incoming req see 16610409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 7389 # What write queue length does an incoming req see 16710409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 6799 # What write queue length does an incoming req see 16810409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 6302 # What write queue length does an incoming req see 16910409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 151 # What write queue length does an incoming req see 17010409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 59 # What write queue length does an incoming req see 17110409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see 17210409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see 17310409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see 17410409Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see 17510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 17610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 18010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 18110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 18210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 19010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 19110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 19210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 20010409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 91367 # Bytes accessed per row activation 20110409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 178.055709 # Bytes accessed per row activation 20210409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 111.660605 # Bytes accessed per row activation 20310409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 241.201750 # Bytes accessed per row activation 20410409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 53557 58.62% 58.62% # Bytes accessed per row activation 20510409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 22743 24.89% 83.51% # Bytes accessed per row activation 20610409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4730 5.18% 88.69% # Bytes accessed per row activation 20710409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 1990 2.18% 90.86% # Bytes accessed per row activation 20810409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 1303 1.43% 92.29% # Bytes accessed per row activation 20910409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 874 0.96% 93.25% # Bytes accessed per row activation 21010409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 818 0.90% 94.14% # Bytes accessed per row activation 21110409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 792 0.87% 95.01% # Bytes accessed per row activation 21210409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 4560 4.99% 100.00% # Bytes accessed per row activation 21310409Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 91367 # Bytes accessed per row activation 21410409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5918 # Reads before turning the bus around for writes 21510409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 26.315816 # Reads before turning the bus around for writes 21610409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::gmean 22.639360 # Reads before turning the bus around for writes 21710409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 186.500180 # Reads before turning the bus around for writes 21810409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-511 5917 99.98% 99.98% # Reads before turning the bus around for writes 21910409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes 22010409Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5918 # Reads before turning the bus around for writes 22110409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5918 # Writes before turning the bus around for reads 22210409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 16.638053 # Writes before turning the bus around for reads 22310409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.588323 # Writes before turning the bus around for reads 22410409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 1.367969 # Writes before turning the bus around for reads 22510409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 4586 77.49% 77.49% # Writes before turning the bus around for reads 22610409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::17 35 0.59% 78.08% # Writes before turning the bus around for reads 22710409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 770 13.01% 91.09% # Writes before turning the bus around for reads 22810409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::19 230 3.89% 94.98% # Writes before turning the bus around for reads 22910409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20 141 2.38% 97.36% # Writes before turning the bus around for reads 23010409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::21 69 1.17% 98.53% # Writes before turning the bus around for reads 23110409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::22 46 0.78% 99.31% # Writes before turning the bus around for reads 23210409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::23 20 0.34% 99.65% # Writes before turning the bus around for reads 23310409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24 12 0.20% 99.85% # Writes before turning the bus around for reads 23410409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::25 3 0.05% 99.90% # Writes before turning the bus around for reads 23510409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::26 5 0.08% 99.98% # Writes before turning the bus around for reads 23610409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads 23710409Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5918 # Writes before turning the bus around for reads 23810409Sandreas.hansson@arm.comsystem.physmem.totQLat 7435933847 # Total ticks spent queuing 23910409Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 10356433847 # Total ticks spent from burst creation until serviced by the DRAM 24010409Sandreas.hansson@arm.comsystem.physmem.totBusLat 778800000 # Total ticks spent in databus transfers 24110409Sandreas.hansson@arm.comsystem.physmem.avgQLat 47739.69 # Average queueing delay per DRAM burst 2429978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 24310409Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 66489.69 # Average memory access latency per DRAM burst 24410409Sandreas.hansson@arm.comsystem.physmem.avgRdBW 305.64 # Average DRAM read bandwidth in MiByte/s 24510409Sandreas.hansson@arm.comsystem.physmem.avgWrBW 193.21 # Average achieved write bandwidth in MiByte/s 24610409Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 305.92 # Average system read bandwidth in MiByte/s 24710409Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 193.27 # Average system write bandwidth in MiByte/s 2489978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 24910409Sandreas.hansson@arm.comsystem.physmem.busUtil 3.90 # Data bus utilization in percentage 25010409Sandreas.hansson@arm.comsystem.physmem.busUtilRead 2.39 # Data bus utilization in percentage for reads 25110409Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 1.51 # Data bus utilization in percentage for writes 25210409Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing 25310409Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.56 # Average write queue length when enqueuing 25410409Sandreas.hansson@arm.comsystem.physmem.readRowHits 126861 # Number of row buffer hits during reads 25510409Sandreas.hansson@arm.comsystem.physmem.writeRowHits 35985 # Number of row buffer hits during writes 25610409Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads 25710409Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 36.54 # Row buffer hit rate for writes 25810409Sandreas.hansson@arm.comsystem.physmem.avgGap 128209.15 # Average gap between requests 25910409Sandreas.hansson@arm.comsystem.physmem.pageHitRate 64.05 # Row buffer hit rate, read and write combined 26010409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 11335868113 # Time in different power states 26110409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 1088880000 # Time in different power states 26210220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 26310409Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 20184340637 # Time in different power states 26410220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 26510409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 149976 # Transaction distribution 26610409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 149976 # Transaction distribution 26710409Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 98491 # Transaction distribution 26810409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 6 # Transaction distribution 26910409Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 6 # Transaction distribution 27010409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 5923 # Transaction distribution 27110409Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 5923 # Transaction distribution 27210409Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 410301 # Packet count per connected master and slave (bytes) 27310409Sandreas.hansson@arm.comsystem.membus.pkt_count::total 410301 # Packet count per connected master and slave (bytes) 27410409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16280960 # Cumulative packet size per connected master and slave (bytes) 27510409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 16280960 # Cumulative packet size per connected master and slave (bytes) 27610409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 27710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 254396 # Request fanout histogram 27810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 27910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 28010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 28110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 254396 100.00% 100.00% # Request fanout histogram 28210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 28310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 28410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 28510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 28610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 254396 # Request fanout histogram 28710409Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 1082237025 # Layer occupancy (ticks) 28810409Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 3.3 # Layer utilization (%) 28910409Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 1431940683 # Layer occupancy (ticks) 29010409Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 4.4 # Layer utilization (%) 29110036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 29210409Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 17209876 # Number of BP lookups 29310409Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 11519021 # Number of conditional branches predicted 29410409Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 648079 # Number of conditional branches incorrect 29510409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 9339439 # Number of BTB lookups 29610409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 7675638 # Number of BTB hits 2979481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 29810409Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 82.185215 # BTB Hit Percentage 29910409Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 1872557 # Number of times the RAS was used to get a target. 30010409Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 101558 # Number of incorrect RAS predictions. 30110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 30210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 30310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 30410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 30510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 30610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 30710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 30810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 31210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 31310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 31410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 31510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 31610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 31710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 31810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 31910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 32010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 32110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3228317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3238317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3248317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3258317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3268317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3278317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3288317SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3298317SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3308317SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3318317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3328317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3338317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3348317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3358317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3368317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3378317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3388317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3398317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3408317SN/Asystem.cpu.dtb.hits 0 # DTB hits 3418317SN/Asystem.cpu.dtb.misses 0 # DTB misses 3428317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 34310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 34410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 34510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 35010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 35410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 35510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 35610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 35710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 36010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 36110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 36210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 36310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 3648317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 3658317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 3668317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3678317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3688317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3698317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3708317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 3718317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3728317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3738317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3748317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 3758317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3768317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3778317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3788317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3798317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3808317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3818317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 3828317SN/Asystem.cpu.itb.hits 0 # DTB hits 3838317SN/Asystem.cpu.itb.misses 0 # DTB misses 3848317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 3858317SN/Asystem.cpu.workload.num_syscalls 1946 # Number of system calls 38610409Sandreas.hansson@arm.comsystem.cpu.numCycles 65230431 # number of cpu cycles simulated 3878317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3888317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 38910409Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 4923591 # Number of cycles fetch is stalled on an Icache miss 39010409Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 88199449 # Number of instructions fetch has processed 39110409Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 17209876 # Number of branches that fetch encountered 39210409Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 9548195 # Number of branches that fetch has predicted taken 39310409Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 59293355 # Number of cycles fetch has run and was not squashing or blocked 39410409Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1322460 # Number of cycles fetch has spent squashing 39510409Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 1971 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 39610409Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps 39710409Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 4935 # Number of stall cycles due to full MSHR 39810409Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 22763618 # Number of cache lines fetched 39910409Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 68177 # Number of outstanding Icache misses that were squashed 40010409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 64885124 # Number of instructions fetched each cycle (Total) 40110409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.720232 # Number of instructions fetched each cycle (Total) 40210409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.289546 # Number of instructions fetched each cycle (Total) 4038317SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 40410409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 19096390 29.43% 29.43% # Number of instructions fetched each cycle (Total) 40510409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 8276176 12.76% 42.19% # Number of instructions fetched each cycle (Total) 40610409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 9196383 14.17% 56.36% # Number of instructions fetched each cycle (Total) 40710409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 28316175 43.64% 100.00% # Number of instructions fetched each cycle (Total) 4088317SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4098317SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 41010409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 41110409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 64885124 # Number of instructions fetched each cycle (Total) 41210409Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.263832 # Number of branch fetches per cycle 41310409Sandreas.hansson@arm.comsystem.cpu.fetch.rate 1.352121 # Number of inst fetches per cycle 41410409Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8536355 # Number of cycles decode is idle 41510409Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 18658081 # Number of cycles decode is blocked 41610409Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 31532227 # Number of cycles decode is running 41710409Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 5666329 # Number of cycles decode is unblocking 41810409Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 492132 # Number of cycles decode is squashing 41910409Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 3179364 # Number of times decode resolved a branch 42010409Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 171028 # Number of times decode detected a branch misprediction 42110409Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 101394580 # Number of instructions handled by decode 42210409Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 3046745 # Number of squashed instructions handled by decode 42310409Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 492132 # Number of cycles rename is squashing 42410409Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 13317145 # Number of cycles rename is idle 42510409Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 5269714 # Number of cycles rename is blocking 42610409Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 677558 # count of cycles rename stalled for serializing inst 42710409Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 32193664 # Number of cycles rename is running 42810409Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 12934911 # Number of cycles rename is unblocking 42910409Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 99186097 # Number of instructions processed by rename 43010409Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 982635 # Number of squashed instructions processed by rename 43110409Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 3696460 # Number of times rename has blocked due to ROB full 43210409Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 54484 # Number of times rename has blocked due to IQ full 43310409Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 4041872 # Number of times rename has blocked due to LQ full 43410409Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 4848974 # Number of times rename has blocked due to SQ full 43510409Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 103911408 # Number of destination operands rename has renamed 43610409Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 457625717 # Number of register rename lookups that rename has made 43710409Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 115391737 # Number of integer rename lookups 43810409Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 582 # Number of floating rename lookups 43910352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed 44010409Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 10282182 # Number of HB maps that are undone due to squashing 44110409Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 18671 # count of serializing insts renamed 44210409Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 18658 # count of temporary serializing insts renamed 44310409Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 12776141 # count of insts added to the skid buffer 44410409Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 24320792 # Number of loads inserted to the mem dependence unit. 44510409Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 21987717 # Number of stores inserted to the mem dependence unit. 44610409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1318624 # Number of conflicting loads. 44710409Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 2218270 # Number of conflicting stores. 44810409Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 98150566 # Number of instructions added to the IQ (excludes non-spec) 44910409Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 34524 # Number of non-speculative instructions added to the IQ 45010409Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 94860274 # Number of instructions issued 45110409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 691673 # Number of squashed instructions issued 45210409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 7398751 # Number of squashed instructions iterated over during squash; mainly for profiling 45310409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 20189182 # Number of squashed operands that are examined and possibly removed from graph 45410409Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 738 # Number of squashed non-spec instructions that were removed 45510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 64885124 # Number of insts issued each cycle 45610409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.461973 # Number of insts issued each cycle 45710409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.146315 # Number of insts issued each cycle 4588317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 45910409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 16747153 25.81% 25.81% # Number of insts issued each cycle 46010409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 17200007 26.51% 52.32% # Number of insts issued each cycle 46110409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 17188207 26.49% 78.81% # Number of insts issued each cycle 46210409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 11716155 18.06% 96.87% # Number of insts issued each cycle 46310409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 2032622 3.13% 100.00% # Number of insts issued each cycle 46410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 980 0.00% 100.00% # Number of insts issued each cycle 46510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 46610409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 46710409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 4688317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 4698317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 47010409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 47110409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 64885124 # Number of insts issued each cycle 4728317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 47310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 6675057 22.12% 22.12% # attempts to use FU when none available 47410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 43 0.00% 22.12% # attempts to use FU when none available 47510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 22.12% # attempts to use FU when none available 47610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 22.12% # attempts to use FU when none available 47710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 22.12% # attempts to use FU when none available 47810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 22.12% # attempts to use FU when none available 47910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 22.12% # attempts to use FU when none available 48010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 22.12% # attempts to use FU when none available 48110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.12% # attempts to use FU when none available 48210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 22.12% # attempts to use FU when none available 48310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.12% # attempts to use FU when none available 48410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 22.12% # attempts to use FU when none available 48510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 22.12% # attempts to use FU when none available 48610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 22.12% # attempts to use FU when none available 48710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 22.12% # attempts to use FU when none available 48810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 22.12% # attempts to use FU when none available 48910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.12% # attempts to use FU when none available 49010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 22.12% # attempts to use FU when none available 49110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.12% # attempts to use FU when none available 49210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.12% # attempts to use FU when none available 49310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.12% # attempts to use FU when none available 49410409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.12% # attempts to use FU when none available 49510409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.12% # attempts to use FU when none available 49610409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.12% # attempts to use FU when none available 49710409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.12% # attempts to use FU when none available 49810409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.12% # attempts to use FU when none available 49910409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.12% # attempts to use FU when none available 50010409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.12% # attempts to use FU when none available 50110409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.12% # attempts to use FU when none available 50210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 11293925 37.43% 59.55% # attempts to use FU when none available 50310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 12204027 40.45% 100.00% # attempts to use FU when none available 5048317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5058317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5068317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 50710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 49495845 52.18% 52.18% # Type of FU issued 50810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 89880 0.09% 52.27% # Type of FU issued 50910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued 51010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.27% # Type of FU issued 51110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued 51210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued 51310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued 51410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued 51510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued 51610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued 51710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued 51810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued 51910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued 52010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued 52110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued 52210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued 52310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued 52410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued 52510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued 52610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued 52710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued 52810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued 52910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued 53010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued 53110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued 53210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued 53310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued 53410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued 53510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued 53610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 24035217 25.34% 77.61% # Type of FU issued 53710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 21239293 22.39% 100.00% # Type of FU issued 5388317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5398317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 54010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 94860274 # Type of FU issued 54110409Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.454233 # Inst issue rate 54210409Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 30173052 # FU busy when requested 54310409Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.318079 # FU busy rate (busy events/executed inst) 54410409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 285470188 # Number of integer instruction queue reads 54510409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 105595239 # Number of integer instruction queue writes 54610409Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 93464369 # Number of integer instruction queue wakeup accesses 54710409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads 54810409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 254 # Number of floating instruction queue writes 54910409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses 55010409Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 125033207 # Number of integer alu accesses 55110409Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 119 # Number of floating point alu accesses 55210409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 1351291 # Number of loads that had data forwarded from stores 5538317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 55410409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1454530 # Number of loads squashed 55510409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 2099 # Number of memory responses ignored because the instruction is squashed 55610409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 11910 # Number of memory ordering violations 55710409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 1431979 # Number of stores squashed 5588317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5598317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 56010409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 120662 # Number of loads that were rescheduled 56110409Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 168795 # Number of times an access to memory failed due to the cache being blocked 5628317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 56310409Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 492132 # Number of cycles IEW is squashing 56410409Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 622391 # Number of cycles IEW is blocking 56510409Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 354812 # Number of cycles IEW is unblocking 56610409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 98194956 # Number of instructions dispatched to IQ 56710409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 56810409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 24320792 # Number of dispatched load instructions 56910409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 21987717 # Number of dispatched store instructions 57010409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 18604 # Number of dispatched non-speculative instructions 57110409Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 1618 # Number of times the IQ has become full, causing a stall 57210409Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 350368 # Number of times the LSQ has become full, causing a stall 57310409Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 11910 # Number of memory order violations 57410409Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 302846 # Number of branches that were predicted taken incorrectly 57510409Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 221657 # Number of branches that were predicted not taken incorrectly 57610409Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 524503 # Number of branch mispredicts detected at execute 57710409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 93943274 # Number of executed instructions 57810409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 23727789 # Number of load instructions executed 57910409Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute 5808317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 58110409Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 9866 # number of nop insts executed 58210409Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 44709300 # number of memory reference insts executed 58310409Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 14252629 # Number of branches executed 58410409Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 20981511 # Number of stores executed 58510409Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.440176 # Inst execution rate 58610409Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 93586002 # cumulative count of insts sent to commit 58710409Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 93464426 # cumulative count of insts written-back 58810409Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 44933898 # num instructions producing a value 58910409Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 76510027 # num instructions consuming a value 5908317SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 59110409Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.432835 # insts written-back per cycle 59210409Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.587294 # average fanout of values written-back 5938317SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 59410409Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6524705 # The number of squashed insts skipped by commit 5959459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards 59610409Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 478981 # The number of times a branch was mispredicted 59710409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 63829281 # Number of insts commited each cycle 59810409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.420792 # Number of insts commited each cycle 59910409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 2.179767 # Number of insts commited each cycle 6008241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 60110409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 30376493 47.59% 47.59% # Number of insts commited each cycle 60210409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 16710378 26.18% 73.77% # Number of insts commited each cycle 60310409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4273265 6.69% 80.46% # Number of insts commited each cycle 60410409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 4126779 6.47% 86.93% # Number of insts commited each cycle 60510409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1950134 3.06% 89.99% # Number of insts commited each cycle 60610409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 1295842 2.03% 92.02% # Number of insts commited each cycle 60710409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 707155 1.11% 93.12% # Number of insts commited each cycle 60810409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 585665 0.92% 94.04% # Number of insts commited each cycle 60910409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 3803570 5.96% 100.00% # Number of insts commited each cycle 6108241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6118241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6128241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 61310409Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 63829281 # Number of insts commited each cycle 6149459Ssaidi@eecs.umich.edusystem.cpu.commit.committedInsts 70913181 # Number of instructions committed 61510352Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed 6168317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 61710352Sandreas.hansson@arm.comsystem.cpu.commit.refs 43422000 # Number of memory references committed 61810352Sandreas.hansson@arm.comsystem.cpu.commit.loads 22866262 # Number of loads committed 6198317SN/Asystem.cpu.commit.membars 15920 # Number of memory barriers committed 6209575Ssaidi@eecs.umich.edusystem.cpu.commit.branches 13741485 # Number of branches committed 6218241SN/Asystem.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 62210352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 81528487 # Number of committed integer instructions. 6238241SN/Asystem.cpu.commit.function_calls 1679850 # Number of function calls committed. 62410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 62510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 47186010 52.03% 52.03% # Class of committed instruction 62610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 62710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 62810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 62910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 63010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 63110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction 63210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction 63310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction 63410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction 63510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction 63610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction 63710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction 63810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction 63910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction 64010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction 64110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction 64210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction 64310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction 64410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction 64510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction 64610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction 64710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction 64810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction 64910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction 65010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction 65110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 65210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 65310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 65410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 65510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Class of committed instruction 65610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 65710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 65810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 90688136 # Class of committed instruction 65910409Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 3803570 # number cycles where commit BW limit reached 6608317SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 66110409Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 157213253 # The number of ROB reads 66210409Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 195483387 # The number of ROB writes 66310409Sandreas.hansson@arm.comsystem.cpu.timesIdled 20301 # Number of times that the entire CPU went into an idle state and unscheduled itself 66410409Sandreas.hansson@arm.comsystem.cpu.idleCycles 345307 # Total number of cycles that the CPU has spent unscheduled due to idling 6659459Ssaidi@eecs.umich.edusystem.cpu.committedInsts 70907629 # Number of Instructions Simulated 66610352Sandreas.hansson@arm.comsystem.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated 66710409Sandreas.hansson@arm.comsystem.cpu.cpi 0.919935 # CPI: Cycles Per Instruction 66810409Sandreas.hansson@arm.comsystem.cpu.cpi_total 0.919935 # CPI: Total CPI of All Threads 66910409Sandreas.hansson@arm.comsystem.cpu.ipc 1.087033 # IPC: Instructions Per Cycle 67010409Sandreas.hansson@arm.comsystem.cpu.ipc_total 1.087033 # IPC: Total IPC of All Threads 67110409Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 102236516 # number of integer regfile reads 67210409Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 56794814 # number of integer regfile writes 67310409Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 36 # number of floating regfile reads 67410409Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 21 # number of floating regfile writes 67510409Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 346002142 # number of cc regfile reads 67610409Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 38804540 # number of cc regfile writes 67710409Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 44207937 # number of misc regfile reads 6789459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 31840 # number of misc regfile writes 67910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 661258 # Transaction distribution 68010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 661257 # Transaction distribution 68110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 256573 # Transaction distribution 68210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 261175 # Transaction distribution 68310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution 68410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution 68510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 148561 # Transaction distribution 68610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 148561 # Transaction distribution 68710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 647966 # Packet count per connected master and slave (bytes) 68810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1228253 # Packet count per connected master and slave (bytes) 68910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 1876219 # Packet count per connected master and slave (bytes) 69010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20734528 # Cumulative packet size per connected master and slave (bytes) 69110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47513792 # Cumulative packet size per connected master and slave (bytes) 69210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 68248320 # Cumulative packet size per connected master and slave (bytes) 69310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 261186 # Total snoops (count) 69410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 1327591 # Request fanout histogram 69510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 5.196729 # Request fanout histogram 69610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.397525 # Request fanout histogram 69710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 69810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 69910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 70010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 70110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 70210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 70310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::5 1066416 80.33% 80.33% # Request fanout histogram 70410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::6 261175 19.67% 100.00% # Request fanout histogram 70510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 70610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 70710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 70810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 1327591 # Request fanout histogram 70910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 789786488 # Layer occupancy (ticks) 71010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) 71110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 486428945 # Layer occupancy (ticks) 71210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 71310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 733917689 # Layer occupancy (ticks) 71410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 71510409Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 323466 # number of replacements 71610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 510.438944 # Cycle average of tags in use 71710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 22431935 # Total number of references to valid blocks. 71810409Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 323978 # Sample count of references to valid blocks. 71910409Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 69.239069 # Average number of references to valid blocks. 72010409Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 1054590000 # Cycle when the warmup percentage was hit. 72110409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 510.438944 # Average occupied blocks per requestor 72210409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.996951 # Average percentage of cache occupancy 72310409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.996951 # Average percentage of cache occupancy 72410409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 72510409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 72610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id 72710409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id 72810409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 267 # Occupied blocks per task id 72910409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 73010409Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 73110409Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 45851126 # Number of tag accesses 73210409Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 45851126 # Number of data accesses 73310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 22431935 # number of ReadReq hits 73410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 22431935 # number of ReadReq hits 73510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 22431935 # number of demand (read+write) hits 73610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 22431935 # number of demand (read+write) hits 73710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 22431935 # number of overall hits 73810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 22431935 # number of overall hits 73910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 331634 # number of ReadReq misses 74010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 331634 # number of ReadReq misses 74110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 331634 # number of demand (read+write) misses 74210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 331634 # number of demand (read+write) misses 74310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 331634 # number of overall misses 74410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 331634 # number of overall misses 74510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 2861760504 # number of ReadReq miss cycles 74610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 2861760504 # number of ReadReq miss cycles 74710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 2861760504 # number of demand (read+write) miss cycles 74810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 2861760504 # number of demand (read+write) miss cycles 74910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 2861760504 # number of overall miss cycles 75010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 2861760504 # number of overall miss cycles 75110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 22763569 # number of ReadReq accesses(hits+misses) 75210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 22763569 # number of ReadReq accesses(hits+misses) 75310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 22763569 # number of demand (read+write) accesses 75410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 22763569 # number of demand (read+write) accesses 75510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 22763569 # number of overall (read+write) accesses 75610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 22763569 # number of overall (read+write) accesses 75710409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses 75810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.014569 # miss rate for ReadReq accesses 75910409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses 76010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.014569 # miss rate for demand accesses 76110409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses 76210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.014569 # miss rate for overall accesses 76310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8629.273549 # average ReadReq miss latency 76410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 8629.273549 # average ReadReq miss latency 76510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency 76610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 8629.273549 # average overall miss latency 76710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 8629.273549 # average overall miss latency 76810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 8629.273549 # average overall miss latency 76910409Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 97738 # number of cycles access was blocked 7708317SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 77110409Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 12080 # number of cycles access was blocked 7728317SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 77310409Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 8.090894 # average number of cycles each access was blocked 7748983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7758317SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 7768317SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 77710409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 7645 # number of ReadReq MSHR hits 77810409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 7645 # number of ReadReq MSHR hits 77910409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 7645 # number of demand (read+write) MSHR hits 78010409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 7645 # number of demand (read+write) MSHR hits 78110409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 7645 # number of overall MSHR hits 78210409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 7645 # number of overall MSHR hits 78310409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 323989 # number of ReadReq MSHR misses 78410409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 323989 # number of ReadReq MSHR misses 78510409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 323989 # number of demand (read+write) MSHR misses 78610409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 323989 # number of demand (read+write) MSHR misses 78710409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 323989 # number of overall MSHR misses 78810409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 323989 # number of overall MSHR misses 78910409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2325660123 # number of ReadReq MSHR miss cycles 79010409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 2325660123 # number of ReadReq MSHR miss cycles 79110409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 2325660123 # number of demand (read+write) MSHR miss cycles 79210409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 2325660123 # number of demand (read+write) MSHR miss cycles 79310409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 2325660123 # number of overall MSHR miss cycles 79410409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 2325660123 # number of overall MSHR miss cycles 79510409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for ReadReq accesses 79610409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.014233 # mshr miss rate for ReadReq accesses 79710409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for demand accesses 79810409Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.014233 # mshr miss rate for demand accesses 79910409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014233 # mshr miss rate for overall accesses 80010409Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.014233 # mshr miss rate for overall accesses 80110409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7178.207047 # average ReadReq mshr miss latency 80210409Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7178.207047 # average ReadReq mshr miss latency 80310409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency 80410409Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency 80510409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7178.207047 # average overall mshr miss latency 80610409Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 7178.207047 # average overall mshr miss latency 8078317SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 80810409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 3266027 # number of hwpf identified 80910409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 304781 # number of hwpf that were already in mshr 81010409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2719229 # number of hwpf that were already in the cache 81110409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 25673 # number of hwpf that were already in the prefetch queue 81210409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 81310409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 17215 # number of hwpf removed because MSHR allocated 81410409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 199121 # number of hwpf issued 81510409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 314405 # number of hwpf spanning a virtual page 81610409Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 81710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 140078 # number of replacements 81810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 16107.104250 # Cycle average of tags in use 81910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 874451 # Total number of references to valid blocks. 82010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 156393 # Sample count of references to valid blocks. 82110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 5.591369 # Average number of references to valid blocks. 8229838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 82310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 11482.142430 # Average occupied blocks per requestor 82410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 301.953059 # Average occupied blocks per requestor 82510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 1690.013125 # Average occupied blocks per requestor 82610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2632.995635 # Average occupied blocks per requestor 82710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.700814 # Average percentage of cache occupancy 82810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.018430 # Average percentage of cache occupancy 82910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.103150 # Average percentage of cache occupancy 83010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.160705 # Average percentage of cache occupancy 83110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.983100 # Average percentage of cache occupancy 83210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 869 # Occupied blocks per task id 83310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 15446 # Occupied blocks per task id 83410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::0 223 # Occupied blocks per task id 83510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 244 # Occupied blocks per task id 83610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id 83710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::3 234 # Occupied blocks per task id 83810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 156 # Occupied blocks per task id 83910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 84010409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 2751 # Occupied blocks per task id 84110409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 11585 # Occupied blocks per task id 84210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 388 # Occupied blocks per task id 84310409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 623 # Occupied blocks per task id 84410409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.053040 # Percentage of cache occupancy per task id 84510409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.942749 # Percentage of cache occupancy per task id 84610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 17367214 # Number of tag accesses 84710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 17367214 # Number of data accesses 84810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 320997 # number of ReadReq hits 84910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 306363 # number of ReadReq hits 85010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 627360 # number of ReadReq hits 85110409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 256573 # number of Writeback hits 85210409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 256573 # number of Writeback hits 85310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 85410409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 85510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 139690 # number of ReadExReq hits 85610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 139690 # number of ReadExReq hits 85710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 320997 # number of demand (read+write) hits 85810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 446053 # number of demand (read+write) hits 85910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 767050 # number of demand (read+write) hits 86010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 320997 # number of overall hits 86110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 446053 # number of overall hits 86210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 767050 # number of overall hits 86310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 2981 # number of ReadReq misses 86410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 30906 # number of ReadReq misses 86510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 33887 # number of ReadReq misses 86610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 86710409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 86810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 8871 # number of ReadExReq misses 86910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 8871 # number of ReadExReq misses 87010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2981 # number of demand (read+write) misses 87110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 39777 # number of demand (read+write) misses 87210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 42758 # number of demand (read+write) misses 87310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2981 # number of overall misses 87410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 39777 # number of overall misses 87510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 42758 # number of overall misses 87610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 232061970 # number of ReadReq miss cycles 87710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 2519217993 # number of ReadReq miss cycles 87810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 2751279963 # number of ReadReq miss cycles 87910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950040000 # number of ReadExReq miss cycles 88010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 950040000 # number of ReadExReq miss cycles 88110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 232061970 # number of demand (read+write) miss cycles 88210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 3469257993 # number of demand (read+write) miss cycles 88310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 3701319963 # number of demand (read+write) miss cycles 88410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 232061970 # number of overall miss cycles 88510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 3469257993 # number of overall miss cycles 88610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 3701319963 # number of overall miss cycles 88710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 323978 # number of ReadReq accesses(hits+misses) 88810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 337269 # number of ReadReq accesses(hits+misses) 88910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 661247 # number of ReadReq accesses(hits+misses) 89010409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 256573 # number of Writeback accesses(hits+misses) 89110409Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 256573 # number of Writeback accesses(hits+misses) 89210409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) 89310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) 89410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 148561 # number of ReadExReq accesses(hits+misses) 89510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 148561 # number of ReadExReq accesses(hits+misses) 89610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 323978 # number of demand (read+write) accesses 89710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 485830 # number of demand (read+write) accesses 89810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 809808 # number of demand (read+write) accesses 89910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 323978 # number of overall (read+write) accesses 90010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 485830 # number of overall (read+write) accesses 90110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 809808 # number of overall (read+write) accesses 90210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.009201 # miss rate for ReadReq accesses 90310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.091636 # miss rate for ReadReq accesses 90410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.051247 # miss rate for ReadReq accesses 90510409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for UpgradeReq accesses 90610409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.600000 # miss rate for UpgradeReq accesses 90710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.059713 # miss rate for ReadExReq accesses 90810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.059713 # miss rate for ReadExReq accesses 90910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.009201 # miss rate for demand accesses 91010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.081874 # miss rate for demand accesses 91110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.052800 # miss rate for demand accesses 91210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.009201 # miss rate for overall accesses 91310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.081874 # miss rate for overall accesses 91410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.052800 # miss rate for overall accesses 91510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77847.021134 # average ReadReq miss latency 91610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81512.262765 # average ReadReq miss latency 91710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 81189.835719 # average ReadReq miss latency 91810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 107095.028745 # average ReadExReq miss latency 91910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 107095.028745 # average ReadExReq miss latency 92010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77847.021134 # average overall miss latency 92110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 87217.688438 # average overall miss latency 92210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 86564.384747 # average overall miss latency 92310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77847.021134 # average overall miss latency 92410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 87217.688438 # average overall miss latency 92510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 86564.384747 # average overall miss latency 92610409Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 3458 # number of cycles access was blocked 9278317SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92810409Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 119 # number of cycles access was blocked 9298317SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 93010409Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs 29.058824 # average number of cycles each access was blocked 9318983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9328317SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 9337860SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 93410409Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 98491 # number of writebacks 93510409Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 98491 # number of writebacks 93610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 910 # number of ReadReq MSHR hits 93710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.data 298 # number of ReadReq MSHR hits 93810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1208 # number of ReadReq MSHR hits 93910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2953 # number of ReadExReq MSHR hits 94010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 2953 # number of ReadExReq MSHR hits 94110409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 910 # number of demand (read+write) MSHR hits 94210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 3251 # number of demand (read+write) MSHR hits 94310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 4161 # number of demand (read+write) MSHR hits 94410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 910 # number of overall MSHR hits 94510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 3251 # number of overall MSHR hits 94610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 4161 # number of overall MSHR hits 94710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2071 # number of ReadReq MSHR misses 94810409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30608 # number of ReadReq MSHR misses 94910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 32679 # number of ReadReq MSHR misses 95010409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 199121 # number of HardPFReq MSHR misses 95110409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 199121 # number of HardPFReq MSHR misses 95210409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 95310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 95410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 5918 # number of ReadExReq MSHR misses 95510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 5918 # number of ReadExReq MSHR misses 95610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2071 # number of demand (read+write) MSHR misses 95710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 36526 # number of demand (read+write) MSHR misses 95810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 38597 # number of demand (read+write) MSHR misses 95910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2071 # number of overall MSHR misses 96010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 36526 # number of overall MSHR misses 96110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 199121 # number of overall MSHR misses 96210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 237718 # number of overall MSHR misses 96310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159067500 # number of ReadReq MSHR miss cycles 96410409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2245450503 # number of ReadReq MSHR miss cycles 96510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 2404518003 # number of ReadReq MSHR miss cycles 96610409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of HardPFReq MSHR miss cycles 96710409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 12215795775 # number of HardPFReq MSHR miss cycles 96810409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 36006 # number of UpgradeReq MSHR miss cycles 96910409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 36006 # number of UpgradeReq MSHR miss cycles 97010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 395713000 # number of ReadExReq MSHR miss cycles 97110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 395713000 # number of ReadExReq MSHR miss cycles 97210409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159067500 # number of demand (read+write) MSHR miss cycles 97310409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2641163503 # number of demand (read+write) MSHR miss cycles 97410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 2800231003 # number of demand (read+write) MSHR miss cycles 97510409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159067500 # number of overall MSHR miss cycles 97610409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2641163503 # number of overall MSHR miss cycles 97710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 12215795775 # number of overall MSHR miss cycles 97810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 15016026778 # number of overall MSHR miss cycles 97910409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for ReadReq accesses 98010409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.090752 # mshr miss rate for ReadReq accesses 98110409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.049420 # mshr miss rate for ReadReq accesses 98210409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 98310409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 98410409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for UpgradeReq accesses 98510409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for UpgradeReq accesses 98610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.039835 # mshr miss rate for ReadExReq accesses 98710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.039835 # mshr miss rate for ReadExReq accesses 98810409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for demand accesses 98910409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for demand accesses 99010409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.047662 # mshr miss rate for demand accesses 99110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.006392 # mshr miss rate for overall accesses 99210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075183 # mshr miss rate for overall accesses 99310409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 99410409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.293549 # mshr miss rate for overall accesses 99510409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 76807.098020 # average ReadReq mshr miss latency 99610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73361.555900 # average ReadReq mshr miss latency 99710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 73579.913798 # average ReadReq mshr miss latency 99810409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average HardPFReq mshr miss latency 99910409Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61348.605998 # average HardPFReq mshr miss latency 100010409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency 100110409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency 100210409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66866.002028 # average ReadExReq mshr miss latency 100310409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66866.002028 # average ReadExReq mshr miss latency 100410409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency 100510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency 100610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 72550.483276 # average overall mshr miss latency 100710409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76807.098020 # average overall mshr miss latency 100810409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72309.136040 # average overall mshr miss latency 100910409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61348.605998 # average overall mshr miss latency 101010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 63167.394888 # average overall mshr miss latency 10117860SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 101210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 485318 # number of replacements 101310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 510.841997 # Cycle average of tags in use 101410409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 40443714 # Total number of references to valid blocks. 101510409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 485830 # Sample count of references to valid blocks. 101610409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 83.246638 # Average number of references to valid blocks. 101710409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 139928000 # Cycle when the warmup percentage was hit. 101810409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 510.841997 # Average occupied blocks per requestor 101910409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.997738 # Average percentage of cache occupancy 102010409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.997738 # Average percentage of cache occupancy 102110409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 102210409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 102310409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id 102410036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 102510409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 84640426 # Number of tag accesses 102610409Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 84640426 # Number of data accesses 102710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 21515343 # number of ReadReq hits 102810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 21515343 # number of ReadReq hits 102910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 18834765 # number of WriteReq hits 103010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 18834765 # number of WriteReq hits 103110409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 62288 # number of SoftPFReq hits 103210409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 62288 # number of SoftPFReq hits 103310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 15377 # number of LoadLockedReq hits 103410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 15377 # number of LoadLockedReq hits 10359459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 10369459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 103710409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 40350108 # number of demand (read+write) hits 103810409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 40350108 # number of demand (read+write) hits 103910409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 40412396 # number of overall hits 104010409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 40412396 # number of overall hits 104110409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 551365 # number of ReadReq misses 104210409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 551365 # number of ReadReq misses 104310409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1015136 # number of WriteReq misses 104410409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1015136 # number of WriteReq misses 104510409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 66556 # number of SoftPFReq misses 104610409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 66556 # number of SoftPFReq misses 104710409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 549 # number of LoadLockedReq misses 104810409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 549 # number of LoadLockedReq misses 104910409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1566501 # number of demand (read+write) misses 105010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1566501 # number of demand (read+write) misses 105110409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1633057 # number of overall misses 105210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1633057 # number of overall misses 105310409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 8548612161 # number of ReadReq miss cycles 105410409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 8548612161 # number of ReadReq miss cycles 105510409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 13150540915 # number of WriteReq miss cycles 105610409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 13150540915 # number of WriteReq miss cycles 105710409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5021750 # number of LoadLockedReq miss cycles 105810409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 5021750 # number of LoadLockedReq miss cycles 105910409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 21699153076 # number of demand (read+write) miss cycles 106010409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 21699153076 # number of demand (read+write) miss cycles 106110409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 21699153076 # number of overall miss cycles 106210409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 21699153076 # number of overall miss cycles 106310409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 22066708 # number of ReadReq accesses(hits+misses) 106410409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 22066708 # number of ReadReq accesses(hits+misses) 10659449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 10669449SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 106710409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 128844 # number of SoftPFReq accesses(hits+misses) 106810409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 128844 # number of SoftPFReq accesses(hits+misses) 106910409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) 107010409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) 10719459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 10729459Ssaidi@eecs.umich.edusystem.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 107310409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 41916609 # number of demand (read+write) accesses 107410409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 41916609 # number of demand (read+write) accesses 107510409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 42045453 # number of overall (read+write) accesses 107610409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 42045453 # number of overall (read+write) accesses 107710409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024986 # miss rate for ReadReq accesses 107810409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.024986 # miss rate for ReadReq accesses 107910409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051141 # miss rate for WriteReq accesses 108010409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.051141 # miss rate for WriteReq accesses 108110409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516563 # miss rate for SoftPFReq accesses 108210409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.516563 # miss rate for SoftPFReq accesses 108310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034472 # miss rate for LoadLockedReq accesses 108410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.034472 # miss rate for LoadLockedReq accesses 108510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.037372 # miss rate for demand accesses 108610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.037372 # miss rate for demand accesses 108710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.038840 # miss rate for overall accesses 108810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.038840 # miss rate for overall accesses 108910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15504.451971 # average ReadReq miss latency 109010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 15504.451971 # average ReadReq miss latency 109110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12954.462176 # average WriteReq miss latency 109210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 12954.462176 # average WriteReq miss latency 109310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9147.085610 # average LoadLockedReq miss latency 109410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9147.085610 # average LoadLockedReq miss latency 109510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 13851.988014 # average overall miss latency 109610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 13851.988014 # average overall miss latency 109710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 13287.443779 # average overall miss latency 109810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 13287.443779 # average overall miss latency 109910409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 199 # number of cycles access was blocked 110010409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 2567726 # number of cycles access was blocked 110110409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 14 # number of cycles access was blocked 110210409Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 127351 # number of cycles access was blocked 110310409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 14.214286 # average number of cycles each access was blocked 110410409Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 20.162590 # average number of cycles each access was blocked 11059449SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 11069449SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 110710409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 256573 # number of writebacks 110810409Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 256573 # number of writebacks 110910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 251643 # number of ReadReq MSHR hits 111010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 251643 # number of ReadReq MSHR hits 111110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 866615 # number of WriteReq MSHR hits 111210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 866615 # number of WriteReq MSHR hits 111310409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 549 # number of LoadLockedReq MSHR hits 111410409Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 549 # number of LoadLockedReq MSHR hits 111510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 1118258 # number of demand (read+write) MSHR hits 111610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 1118258 # number of demand (read+write) MSHR hits 111710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 1118258 # number of overall MSHR hits 111810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 1118258 # number of overall MSHR hits 111910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 299722 # number of ReadReq MSHR misses 112010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 299722 # number of ReadReq MSHR misses 112110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 148521 # number of WriteReq MSHR misses 112210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 148521 # number of WriteReq MSHR misses 112310409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses 112410409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses 112510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 448243 # number of demand (read+write) MSHR misses 112610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 448243 # number of demand (read+write) MSHR misses 112710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 485840 # number of overall MSHR misses 112810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 485840 # number of overall MSHR misses 112910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2813681816 # number of ReadReq MSHR miss cycles 113010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 2813681816 # number of ReadReq MSHR miss cycles 113110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1950344957 # number of WriteReq MSHR miss cycles 113210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1950344957 # number of WriteReq MSHR miss cycles 113310409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1901549750 # number of SoftPFReq MSHR miss cycles 113410409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1901549750 # number of SoftPFReq MSHR miss cycles 113510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 4764026773 # number of demand (read+write) MSHR miss cycles 113610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 4764026773 # number of demand (read+write) MSHR miss cycles 113710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 6665576523 # number of overall MSHR miss cycles 113810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 6665576523 # number of overall MSHR miss cycles 113910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013583 # mshr miss rate for ReadReq accesses 114010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013583 # mshr miss rate for ReadReq accesses 114110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses 114210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses 114310409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291802 # mshr miss rate for SoftPFReq accesses 114410409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291802 # mshr miss rate for SoftPFReq accesses 114510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010694 # mshr miss rate for demand accesses 114610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.010694 # mshr miss rate for demand accesses 114710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses 114810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses 114910409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9387.638598 # average ReadReq mshr miss latency 115010409Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9387.638598 # average ReadReq mshr miss latency 115110409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13131.779055 # average WriteReq mshr miss latency 115210409Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 13131.779055 # average WriteReq mshr miss latency 115310409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50577.167061 # average SoftPFReq mshr miss latency 115410409Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50577.167061 # average SoftPFReq mshr miss latency 115510409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10628.223470 # average overall mshr miss latency 115610409Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 10628.223470 # average overall mshr miss latency 115710409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13719.694803 # average overall mshr miss latency 115810409Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 13719.694803 # average overall mshr miss latency 11599449SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 11607860SN/A 11617860SN/A---------- End Simulation Statistics ---------- 1162