xref: /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.023896                       # Number of seconds simulated
sim_ticks                                 23896420500                       # Number of ticks simulated
final_tick                                23896420500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 105740                       # Simulator instruction rate (inst/s)
host_op_rate                                   135229                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               35635051                       # Simulator tick rate (ticks/s)
host_mem_usage                                 262840                       # Number of bytes of host memory used
host_seconds                                   670.59                       # Real time elapsed on the host
sim_insts                                    70907629                       # Number of instructions simulated
sim_ops                                      90682584                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            299392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7936704                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8236096                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       299392                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          299392                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5372800                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5372800                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4678                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             124011                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128689                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83950                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83950                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             12528738                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            332129408                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               344658147                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        12528738                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           12528738                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         224837021                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              224837021                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         224837021                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            12528738                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           332129408                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              569495168                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128689                       # Number of read requests accepted
system.physmem.writeReqs                        83950                       # Number of write requests accepted
system.physmem.readBursts                      128689                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      83950                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  8235648                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       448                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5371072                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   8236096                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5372800                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        7                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            380                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                8141                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8384                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8239                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8150                       # Per bank write bursts
system.physmem.perBankRdBursts::4                8295                       # Per bank write bursts
system.physmem.perBankRdBursts::5                8428                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8074                       # Per bank write bursts
system.physmem.perBankRdBursts::7                7958                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8067                       # Per bank write bursts
system.physmem.perBankRdBursts::9                7598                       # Per bank write bursts
system.physmem.perBankRdBursts::10               7783                       # Per bank write bursts
system.physmem.perBankRdBursts::11               7813                       # Per bank write bursts
system.physmem.perBankRdBursts::12               7877                       # Per bank write bursts
system.physmem.perBankRdBursts::13               7881                       # Per bank write bursts
system.physmem.perBankRdBursts::14               7983                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8011                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5183                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5289                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5157                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5266                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5198                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5051                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5029                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5090                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5246                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5140                       # Per bank write bursts
system.physmem.perBankWrBursts::12               5343                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5452                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5223                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     23896016500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  128689                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  83950                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     68784                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     50927                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      6546                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                      2414                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      628                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      644                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2057                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4948                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5202                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5301                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5438                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5521                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5545                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5656                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6068                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5800                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6220                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6095                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5413                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       91                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                       30                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                       13                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        4                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        37607                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      361.810089                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     217.183531                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     344.455844                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          11970     31.83%     31.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         7877     20.95%     52.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3759     10.00%     62.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2606      6.93%     69.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2473      6.58%     76.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1554      4.13%     80.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1216      3.23%     83.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1043      2.77%     86.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         5109     13.59%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          37607                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5143                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.009139                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      391.762417                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5141     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5143                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5143                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.317908                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.294258                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.943897                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4493     87.36%     87.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 13      0.25%     87.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                424      8.24%     95.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                146      2.84%     98.70% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 43      0.84%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 15      0.29%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  3      0.06%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  1      0.02%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  1      0.02%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  2      0.04%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5143                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2744774250                       # Total ticks spent queuing
system.physmem.totMemAccLat                5157561750                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    643410000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       21329.90                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  40079.90                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         344.64                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         224.76                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      344.66                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      224.84                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           4.45                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.69                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.76                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.39                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.67                       # Average write queue length when enqueuing
system.physmem.readRowHits                     112874                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     62123                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.72                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.00                       # Row buffer hit rate for writes
system.physmem.avgGap                       112378.33                       # Average gap between requests
system.physmem.pageHitRate                      82.30                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE       9567571500                       # Time in different power states
system.physmem.memoryStateTime::REF         797940000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       13530763500                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                    569495168                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               26431                       # Transaction distribution
system.membus.trans_dist::ReadResp              26431                       # Transaction distribution
system.membus.trans_dist::Writeback             83950                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              380                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             380                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102258                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102258                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342088                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 342088                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13608896                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            13608896                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               13608896                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           898146000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.8                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1183170872                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              5.0                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                17877019                       # Number of BP lookups
system.cpu.branchPred.condPredicted          11927811                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            593439                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             11204319                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 8313088                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             74.195388                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1978187                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             104069                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         47792842                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           13399730                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       91818563                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    17877019                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           10291275                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      33374868                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 1293258                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                  460                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles          3119                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           70                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  12485707                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                222370                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           47424876                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.444936                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.221090                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 25840907     54.49%     54.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2398343      5.06%     59.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  2102611      4.43%     63.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2392037      5.04%     69.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1862029      3.93%     72.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1496992      3.16%     76.11% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                  1004992      2.12%     78.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1407650      2.97%     81.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                  8919315     18.81%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             47424876                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.374052                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.921178                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                  9991238                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              18372924                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  15962018                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               2553700                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                 544996                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3514191                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                104008                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              110994138                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                375319                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                 544996                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 11354333                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 2895918                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles        1063087                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  17104266                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles              14462276                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              108881212                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                  1310                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                1983947                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                2643349                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                9691184                       # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands           114456313                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             501643948                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        126478316                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              2998                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              93629226                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 20827087                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              24787                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          25137                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12915604                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             25719384                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            23405570                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           6651489                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          7812944                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  105238243                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               38026                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                  99646497                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            159437                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        14433434                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     35646535                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           4240                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      47424876                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.101144                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        2.177334                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            16924239     35.69%     35.69% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             6535440     13.78%     49.47% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             6148782     12.97%     62.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             5092843     10.74%     73.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             5223877     11.02%     84.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3271997      6.90%     91.09% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             2206801      4.65%     95.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7             1128511      2.38%     98.12% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              892386      1.88%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        47424876                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  215167      9.06%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.06% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1190055     50.09%     59.14% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite                970810     40.86%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              51976863     52.16%     52.16% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                92995      0.09%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 147      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             25513927     25.60%     77.86% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            22062558     22.14%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total               99646497                       # Type of FU issued
system.cpu.iq.rate                           2.084967                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2376032                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023845                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          249252729                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         119771582                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses     97191472                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 610                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                940                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          210                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              102022220                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     309                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          2232705                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2853122                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         4762                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        65666                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      2849832                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads       726205                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked         82286                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                 544996                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1714516                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                834399                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           105286702                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            183365                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              25719384                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             23405570                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              22106                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  17305                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                806226                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          65666                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         396732                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       182672                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               579404                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts              98631248                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              25214590                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1015249                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         10433                       # number of nop insts executed
system.cpu.iew.exec_refs                     46968385                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14905400                       # Number of branches executed
system.cpu.iew.exec_stores                   21753795                       # Number of stores executed
system.cpu.iew.exec_rate                     2.063724                       # Inst execution rate
system.cpu.iew.wb_sent                       97441036                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                      97191682                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  50912103                       # num instructions producing a value
system.cpu.iew.wb_consumers                  98942269                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       2.033603                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.514564                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        14604340                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            491808                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     45293214                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.002246                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.787973                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     20766641     45.85%     45.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1      9214809     20.34%     66.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      2670756      5.90%     72.09% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2400198      5.30%     77.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      2023573      4.47%     81.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5       972100      2.15%     84.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       768345      1.70%     85.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       447977      0.99%     86.69% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6028815     13.31%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     45293214                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
system.cpu.commit.committedOps               90688136                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       43422000                       # Number of memory references committed
system.cpu.commit.loads                      22866262                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741485                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  81528487                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         47186010     52.03%     52.03% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.09%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.12% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        22866262     25.21%     77.33% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555738     22.67%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total          90688136                       # Class of committed instruction
system.cpu.commit.bw_lim_events               6028815                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    144531576                       # The number of ROB reads
system.cpu.rob.rob_writes                   212728591                       # The number of ROB writes
system.cpu.timesIdled                           10876                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          367966                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
system.cpu.committedOps                      90682584                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.674016                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.674016                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.483645                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.483645                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                106842718                       # number of integer regfile reads
system.cpu.int_regfile_writes                59180200                       # number of integer regfile writes
system.cpu.fp_regfile_reads                      1084                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      924                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 361896749                       # number of cc regfile reads
system.cpu.cc_regfile_writes                 40174850                       # number of cc regfile writes
system.cpu.misc_regfile_reads                45647350                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               869793867                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          88682                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         88681                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       129104                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq          425                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          425                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       106980                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       106980                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        66417                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454340                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            520757                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2108672                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18643008                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total       20751680                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus          20751680                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        33280                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      291703993                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      50946473                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     259533576                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.1                       # Layer utilization (%)
system.cpu.icache.tags.replacements             31122                       # number of replacements
system.cpu.icache.tags.tagsinuse          1801.454521                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            12448339                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             33152                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            375.492851                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1801.454521                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.879616                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.879616                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2030                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           92                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           11                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1255                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          672                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.991211                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          25004882                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         25004882                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     12448346                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        12448346                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      12448346                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         12448346                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     12448346                       # number of overall hits
system.cpu.icache.overall_hits::total        12448346                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        37361                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         37361                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        37361                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          37361                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        37361                       # number of overall misses
system.cpu.icache.overall_misses::total         37361                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    833057215                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    833057215                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    833057215                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    833057215                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    833057215                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    833057215                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     12485707                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     12485707                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     12485707                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     12485707                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     12485707                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     12485707                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.002992                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.002992                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.002992                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.002992                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.002992                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.002992                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22297.508498                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22297.508498                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22297.508498                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22297.508498                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22297.508498                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22297.508498                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1054                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    40.538462                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3892                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3892                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3892                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3892                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3892                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3892                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        33469                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        33469                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        33469                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        33469                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        33469                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        33469                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    671681027                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    671681027                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    671681027                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    671681027                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    671681027                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    671681027                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002681                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002681                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002681                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.002681                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002681                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.002681                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20068.750993                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20068.750993                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20068.750993                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20068.750993                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20068.750993                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20068.750993                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            95567                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29785.869326                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              90467                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           126676                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.714161                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26681.247493                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1364.251232                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1740.370601                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.814247                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041634                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.053112                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.908993                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31109                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          155                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         2594                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        24318                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3666                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          376                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949371                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          2831071                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         2831071                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        28249                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        33410                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          61659                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       129104                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       129104                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           45                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           45                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4722                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4722                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        28249                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        38132                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           66381                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        28249                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        38132                       # number of overall hits
system.cpu.l2cache.overall_hits::total          66381                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         4700                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21803                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26503                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          380                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          380                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102258                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102258                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4700                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       124061                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128761                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4700                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       124061                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128761                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    354760000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   2021590000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2376350000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        46498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        46498                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8476574750                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8476574750                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    354760000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10498164750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10852924750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    354760000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10498164750                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10852924750                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        32949                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        55213                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        88162                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       129104                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       129104                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          425                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          425                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       106980                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       106980                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        32949                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       162193                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       195142                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        32949                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       162193                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       195142                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.142645                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.394889                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.300617                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.894118                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.894118                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955861                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955861                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.142645                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.764897                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.659832                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.142645                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.764897                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.659832                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75480.851064                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 92720.726506                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 89663.434328                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   122.363158                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   122.363158                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82894.000958                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82894.000958                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75480.851064                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84620.990884                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 84287.359915                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75480.851064                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84620.990884                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 84287.359915                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83950                       # number of writebacks
system.cpu.l2cache.writebacks::total            83950                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           21                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           50                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           71                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           21                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           50                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           71                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           21                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           50                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           71                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4679                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21753                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26432                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          380                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          380                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102258                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102258                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4679                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       124011                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128690                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4679                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       124011                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128690                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    294843250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1751098750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2045942000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3814378                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3814378                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7217032750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7217032750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    294843250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8968131500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9262974750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    294843250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8968131500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9262974750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.142007                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.393983                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.299812                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.894118                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.894118                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955861                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955861                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.142007                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764589                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.659468                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.142007                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764589                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.659468                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63014.159008                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 80499.184021                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77403.980024                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10037.836842                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10037.836842                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70576.705490                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70576.705490                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63014.159008                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72317.225891                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71978.978553                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63014.159008                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72317.225891                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71978.978553                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            158097                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4066.697393                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            40254845                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            162193                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            248.191013                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         349035000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4066.697393                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.992846                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.992846                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           75                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         2487                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         1534                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          84282165                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         84282165                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     21874674                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21874674                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18263658                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18263658                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        83481                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         83481                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15983                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15983                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40138332                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40138332                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40221813                       # number of overall hits
system.cpu.dcache.overall_hits::total        40221813                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       172724                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        172724                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1586243                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1586243                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data        47266                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total        47266                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           38                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           38                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1758967                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1758967                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1806233                       # number of overall misses
system.cpu.dcache.overall_misses::total       1806233                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5001907368                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5001907368                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 128651444042                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 128651444042                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      1064000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      1064000                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 133653351410                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 133653351410                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 133653351410                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 133653351410                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     22047398                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     22047398                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       130747                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       130747                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16021                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        16021                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41897299                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41897299                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     42028046                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     42028046                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.007834                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.007834                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079912                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.079912                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.361507                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.361507                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002372                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002372                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.041983                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.041983                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.042977                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.042977                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28958.959774                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 28958.959774                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81104.499148                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 81104.499148                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        28000                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total        28000                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75984.001638                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75984.001638                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73995.631466                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73995.631466                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs       911565                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1622                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs             13218                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              15                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    68.963913                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets   108.133333                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       129104                       # number of writebacks
system.cpu.dcache.writebacks::total            129104                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data       141550                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total       141550                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1478910                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1478910                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           38                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           38                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1620460                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1620460                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1620460                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1620460                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        31174                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        31174                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107333                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107333                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data        24111                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total        24111                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       138507                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       138507                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       162618                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       162618                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    566566801                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    566566801                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8639740111                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8639740111                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data   1848458500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total   1848458500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9206306912                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   9206306912                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11054765412                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  11054765412                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001414                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001414                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005407                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005407                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.184410                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.184410                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003306                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003306                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003869                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003869                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18174.337621                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18174.337621                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80494.723067                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80494.723067                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 76664.530712                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 76664.530712                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66468.170648                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 66468.170648                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67979.961702                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67979.961702                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------