xref: /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.026655                       # Number of seconds simulated
sim_ticks                                 26655046000                       # Number of ticks simulated
final_tick                                26655046000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 108502                       # Simulator instruction rate (inst/s)
host_op_rate                                   153979                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               40787374                       # Simulator tick rate (ticks/s)
host_mem_usage                                 322284                       # Number of bytes of host memory used
host_seconds                                   653.51                       # Real time elapsed on the host
sim_insts                                    70907629                       # Number of instructions simulated
sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            298176                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7943424                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8241600                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       298176                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          298176                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5372544                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5372544                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4659                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             124116                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128775                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83946                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83946                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             11186475                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            298008265                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               309194739                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        11186475                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           11186475                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         201558234                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              201558234                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         201558234                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            11186475                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           298008265                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              510752973                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128776                       # Number of read requests accepted
system.physmem.writeReqs                        83946                       # Number of write requests accepted
system.physmem.readBursts                      128776                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      83946                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  8241344                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5371328                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   8241664                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5372544                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            320                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                8145                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8395                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8248                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8167                       # Per bank write bursts
system.physmem.perBankRdBursts::4                8288                       # Per bank write bursts
system.physmem.perBankRdBursts::5                8447                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8087                       # Per bank write bursts
system.physmem.perBankRdBursts::7                7963                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8065                       # Per bank write bursts
system.physmem.perBankRdBursts::9                7608                       # Per bank write bursts
system.physmem.perBankRdBursts::10               7787                       # Per bank write bursts
system.physmem.perBankRdBursts::11               7815                       # Per bank write bursts
system.physmem.perBankRdBursts::12               7882                       # Per bank write bursts
system.physmem.perBankRdBursts::13               7885                       # Per bank write bursts
system.physmem.perBankRdBursts::14               7978                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8011                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5180                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5377                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5291                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5157                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5199                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5049                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5030                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5091                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5246                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5144                       # Per bank write bursts
system.physmem.perBankWrBursts::12               5342                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5225                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     26655030500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  128776                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  83946                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     74138                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     53140                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1433                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        52                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         8                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      643                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      655                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     2224                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4090                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4895                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     5167                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5187                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5237                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5353                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5362                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5346                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5604                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     5798                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     5633                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     6233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     6000                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5239                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                       32                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        2                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        37804                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      360.014390                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     216.175335                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     343.156707                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          12089     31.98%     31.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         7874     20.83%     52.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3781     10.00%     62.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2728      7.22%     70.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2397      6.34%     76.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1617      4.28%     80.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1220      3.23%     83.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1066      2.82%     86.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         5032     13.31%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          37804                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5144                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.030132                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      392.032521                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5142     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5144                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5144                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.315513                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.292869                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.917660                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4492     87.33%     87.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                  6      0.12%     87.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                431      8.38%     95.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                161      3.13%     98.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                 33      0.64%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 11      0.21%     99.81% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                  6      0.12%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                  1      0.02%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  1      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5144                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2471536000                       # Total ticks spent queuing
system.physmem.totMemAccLat                4885992250                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    643855000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       19193.27                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  37943.27                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         309.19                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         201.51                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      309.20                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      201.56                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.99                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.42                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.57                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.35                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        23.52                       # Average write queue length when enqueuing
system.physmem.readRowHits                     112800                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     62083                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.60                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.96                       # Row buffer hit rate for writes
system.physmem.avgGap                       125304.53                       # Average gap between requests
system.physmem.pageHitRate                      82.21                       # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE      11333884750                       # Time in different power states
system.physmem.memoryStateTime::REF         889980000                       # Time in different power states
system.physmem.memoryStateTime::PRE_PDN             0                       # Time in different power states
system.physmem.memoryStateTime::ACT       14428773750                       # Time in different power states
system.physmem.memoryStateTime::ACT_PDN             0                       # Time in different power states
system.membus.throughput                    510752973                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               26520                       # Transaction distribution
system.membus.trans_dist::ReadResp              26519                       # Transaction distribution
system.membus.trans_dist::Writeback             83946                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              320                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             320                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102256                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102256                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342137                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 342137                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13614144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            13614144                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               13614144                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           932451500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1211794930                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              4.5                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                16636502                       # Number of BP lookups
system.cpu.branchPred.condPredicted          12767541                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            605249                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             10577266                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7776939                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             73.525039                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1824082                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             113194                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         53310093                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           12544266                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       85245132                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16636502                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9601021                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21203621                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2373453                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               10826846                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   66                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           346                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           55                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11685368                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                181941                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           46316681                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.577051                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.331362                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 25133357     54.26%     54.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2139356      4.62%     58.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1964088      4.24%     63.12% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2042720      4.41%     67.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1470632      3.18%     70.71% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1380684      2.98%     73.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   958438      2.07%     75.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1191046      2.57%     78.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 10036360     21.67%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             46316681                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.312070                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.599043                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 14641724                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9163742                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19491129                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1382035                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1638051                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3333190                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                105248                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              116897409                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                363517                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1638051                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 16359930                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 2678860                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles        1013546                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  19105164                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5521130                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              115000815                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   184                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  16720                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4660350                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              282                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           115331621                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             529914525                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        476510410                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              2776                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 16198949                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              20436                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          20434                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13095384                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             29625138                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            22434042                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3869725                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          4362550                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  111565619                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               36058                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 107262004                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            275498                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        10829281                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     25946611                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           2272                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      46316681                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.315840                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.990470                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            11030019     23.81%     23.81% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             8138803     17.57%     41.39% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7430883     16.04%     57.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7110857     15.35%     72.78% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             5417654     11.70%     84.48% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3891349      8.40%     92.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1848302      3.99%     96.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              878821      1.90%     98.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              569993      1.23%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        46316681                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  113827      4.59%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.59% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1360293     54.84%     59.43% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               1006288     40.57%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              56646184     52.81%     52.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                91539      0.09%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 222      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             28903042     26.95%     79.84% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21621010     20.16%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              107262004                       # Type of FU issued
system.cpu.iq.rate                           2.012039                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2480410                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023125                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          263595997                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         122458930                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    105571537                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 600                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                932                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          176                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              109742111                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     303                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          2179776                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2318030                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6495                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        30041                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1878304                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads           30                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           708                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1638051                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1126663                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 45667                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           111611483                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            295320                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              29625138                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             22434042                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              20138                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   6203                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  5120                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          30041                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         394287                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       181285                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               575572                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             106232062                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              28604336                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1029942                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9806                       # number of nop insts executed
system.cpu.iew.exec_refs                     49939736                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14601830                       # Number of branches executed
system.cpu.iew.exec_stores                   21335400                       # Number of stores executed
system.cpu.iew.exec_rate                     1.992720                       # Inst execution rate
system.cpu.iew.wb_sent                      105794271                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     105571713                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  53289529                       # num instructions producing a value
system.cpu.iew.wb_consumers                 103696689                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.980333                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.513898                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        10980049                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            501819                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     44678630                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.252362                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.761359                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     15558775     34.82%     34.82% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11701818     26.19%     61.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3471869      7.77%     68.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2879306      6.44%     75.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1869514      4.18%     79.41% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1922443      4.30%     83.72% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       688922      1.54%     85.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       562713      1.26%     86.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6023270     13.48%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     44678630                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       47862846                       # Number of memory references committed
system.cpu.commit.loads                      27307108                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741485                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu         52689456     52.36%     52.36% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult           80119      0.08%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc            7      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     52.44% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        27307108     27.14%     79.57% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       20555738     20.43%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         100632428                       # Class of committed instruction
system.cpu.commit.bw_lim_events               6023270                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    150242538                       # The number of ROB reads
system.cpu.rob.rob_writes                   224871982                       # The number of ROB writes
system.cpu.timesIdled                           79510                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         6993412                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              70907629                       # Number of Instructions Simulated
system.cpu.cpi                               0.751825                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.751825                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.330098                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.330098                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                511631717                       # number of integer regfile reads
system.cpu.int_regfile_writes               103353872                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       846                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      710                       # number of floating regfile writes
system.cpu.misc_regfile_reads                49341635                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               775139386                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          86625                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         86624                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       129165                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq          335                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          335                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       107045                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       107045                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        62039                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454624                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            516663                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1968896                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18659776                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total       20628672                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus          20628672                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        32704                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      290752497                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      47657477                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     267144007                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements             28917                       # number of replacements
system.cpu.icache.tags.tagsinuse          1807.865134                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            11650266                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             30950                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            376.422165                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1807.865134                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.882747                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.882747                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2033                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1259                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          672                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.992676                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          23402009                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         23402009                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     11650274                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11650274                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11650274                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11650274                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11650274                       # number of overall hits
system.cpu.icache.overall_hits::total        11650274                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        35093                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         35093                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        35093                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          35093                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        35093                       # number of overall misses
system.cpu.icache.overall_misses::total         35093                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    796173972                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    796173972                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    796173972                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    796173972                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    796173972                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    796173972                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11685367                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11685367                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11685367                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11685367                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11685367                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11685367                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003003                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.003003                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.003003                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.003003                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.003003                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.003003                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22687.543727                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22687.543727                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22687.543727                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22687.543727                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22687.543727                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22687.543727                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1584                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                26                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    60.923077                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3818                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3818                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3818                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3818                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3818                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3818                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31275                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        31275                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        31275                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        31275                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        31275                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        31275                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    647196022                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    647196022                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    647196022                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    647196022                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    647196022                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    647196022                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002676                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002676                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002676                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.002676                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002676                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.002676                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.717730                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.717730                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.717730                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.717730                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.717730                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.717730                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            95645                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29867.639929                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              88414                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           126758                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.697502                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26665.630532                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1369.813019                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1832.196377                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.813770                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041803                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.055914                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.911488                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31113                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          140                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1847                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20513                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8219                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          394                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949493                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          2815092                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         2815092                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        26089                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        33429                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          59518                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       129165                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       129165                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           16                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           16                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4788                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4788                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        26089                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        38217                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           64306                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        26089                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        38217                       # number of overall hits
system.cpu.l2cache.overall_hits::total          64306                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         4675                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21921                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26596                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          319                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          319                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102257                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102257                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4675                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       124178                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128853                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4675                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       124178                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128853                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    354274500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1813961250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2168235750                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        22999                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        22999                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8348408999                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8348408999                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    354274500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10162370249                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10516644749                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    354274500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10162370249                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10516644749                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        30764                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        55350                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        86114                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       129165                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       129165                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          335                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          335                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107045                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107045                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        30764                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       162395                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       193159                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        30764                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       162395                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       193159                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.151963                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.396043                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.308846                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.952239                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.952239                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955271                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955271                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.151963                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.764666                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.667083                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.151963                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.764666                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.667083                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75780.641711                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82749.931572                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 81524.881561                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    72.097179                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    72.097179                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81641.442630                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81641.442630                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75780.641711                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81837.122912                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81617.383755                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75780.641711                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81837.122912                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81617.383755                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83946                       # number of writebacks
system.cpu.l2cache.writebacks::total            83946                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           16                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           60                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           76                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           16                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           60                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           76                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           16                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           60                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           76                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4659                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21861                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26520                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          319                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          319                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102257                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102257                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4659                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       124118                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128777                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4659                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       124118                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128777                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    294952000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1536285750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1831237750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3196819                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3196819                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7058409501                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7058409501                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    294952000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8594695251                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8889647251                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    294952000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8594695251                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8889647251                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.151443                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394959                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.307964                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.952239                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.952239                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955271                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955271                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.151443                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764297                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.666689                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.151443                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764297                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.666689                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63308.006010                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70275.181831                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69051.197210                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10021.376176                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10021.376176                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69026.174257                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69026.174257                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63308.006010                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69246.162934                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69031.327419                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63308.006010                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69246.162934                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69031.327419                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            158298                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4068.579596                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            44367951                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            162394                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            273.211763                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         366659250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4068.579596                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993306                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993306                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           69                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1762                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2265                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          92310952                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         92310952                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     26067775                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        26067775                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18267649                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18267649                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15993                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15993                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      44335424                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         44335424                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     44335424                       # number of overall hits
system.cpu.dcache.overall_hits::total        44335424                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       124650                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        124650                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1582252                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1582252                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           41                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           41                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1706902                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1706902                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1706902                       # number of overall misses
system.cpu.dcache.overall_misses::total       1706902                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5082447470                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5082447470                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 124553146004                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 124553146004                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       917250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       917250                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 129635593474                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 129635593474                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 129635593474                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 129635593474                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     26192425                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     26192425                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16034                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        16034                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     46042326                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     46042326                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     46042326                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     46042326                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004759                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004759                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079711                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.079711                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002557                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002557                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037072                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037072                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037072                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037072                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40773.746249                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40773.746249                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78718.905714                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 78718.905714                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22371.951220                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 22371.951220                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75947.883050                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75947.883050                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75947.883050                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 75947.883050                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         3831                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1303                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               134                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              16                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    28.589552                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    81.437500                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       129165                       # number of writebacks
system.cpu.dcache.writebacks::total            129165                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69269                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        69269                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1474904                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1474904                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           40                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           40                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1544173                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1544173                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1544173                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1544173                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55381                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        55381                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107348                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107348                       # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       162729                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       162729                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       162729                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       162729                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2206437312                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2206437312                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8512084920                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8512084920                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        11500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        11500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10718522232                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  10718522232                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10718522232                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10718522232                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002114                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002114                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005408                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005408                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.000062                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.000062                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003534                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003534                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003534                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003534                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39841.052202                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39841.052202                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79294.303760                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79294.303760                       # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        11500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        11500                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65867.314566                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65867.314566                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65867.314566                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 65867.314566                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------