xref: /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.026596                       # Number of seconds simulated
sim_ticks                                 26596403000                       # Number of ticks simulated
final_tick                                26596403000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 110554                       # Simulator instruction rate (inst/s)
host_op_rate                                   156889                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               41466984                       # Simulator tick rate (ticks/s)
host_mem_usage                                 321816                       # Number of bytes of host memory used
host_seconds                                   641.39                       # Real time elapsed on the host
sim_insts                                    70907629                       # Number of instructions simulated
sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            297984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7942976                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8240960                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       297984                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          297984                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5372480                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5372480                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4656                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             124109                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128765                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83945                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83945                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             11203921                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            298648505                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               309852426                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        11203921                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           11203921                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         202000248                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              202000248                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         202000248                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            11203921                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           298648505                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              511852674                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128766                       # Number of read requests accepted
system.physmem.writeReqs                        83945                       # Number of write requests accepted
system.physmem.readBursts                      128766                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      83945                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  8240704                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       320                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5371136                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   8241024                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5372480                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        5                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            300                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                8143                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8388                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8255                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8165                       # Per bank write bursts
system.physmem.perBankRdBursts::4                8298                       # Per bank write bursts
system.physmem.perBankRdBursts::5                8451                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8084                       # Per bank write bursts
system.physmem.perBankRdBursts::7                7964                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8055                       # Per bank write bursts
system.physmem.perBankRdBursts::9                7611                       # Per bank write bursts
system.physmem.perBankRdBursts::10               7782                       # Per bank write bursts
system.physmem.perBankRdBursts::11               7815                       # Per bank write bursts
system.physmem.perBankRdBursts::12               7881                       # Per bank write bursts
system.physmem.perBankRdBursts::13               7884                       # Per bank write bursts
system.physmem.perBankRdBursts::14               7976                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8009                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5177                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5376                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5289                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5157                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5267                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5201                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5049                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5030                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5089                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5246                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5144                       # Per bank write bursts
system.physmem.perBankWrBursts::12               5342                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5452                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5225                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     26596386500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  128766                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  83945                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     71874                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     54925                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1900                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        55                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      478                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      495                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                      840                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     2288                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3768                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4393                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4872                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     5100                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     5159                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     5216                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     5492                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     5691                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     5740                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     6272                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     6389                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     5693                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     5625                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     5394                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2900                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      953                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      409                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      107                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                       92                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                       49                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                       50                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                       43                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                       37                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                       36                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                       31                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                       34                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                       26                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                       24                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                       22                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                       20                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                       19                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        29627                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      410.695649                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     253.351666                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     359.831379                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           7793     26.30%     26.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         6034     20.37%     46.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         3130     10.56%     57.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         2203      7.44%     64.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639         2053      6.93%     71.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         1365      4.61%     76.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         1045      3.53%     79.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         1191      4.02%     83.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         4813     16.25%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          29627                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          5084                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        25.322974                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      394.325536                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           5082     99.96%     99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::27648-28671            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            5084                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          5084                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.507474                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.421096                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        2.063173                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               4555     89.59%     89.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17                 21      0.41%     90.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                 58      1.14%     91.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19                170      3.34%     94.49% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20                125      2.46%     96.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21                 57      1.12%     98.07% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22                 23      0.45%     98.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23                 15      0.30%     98.82% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24                 10      0.20%     99.02% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25                  6      0.12%     99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26                  5      0.10%     99.23% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::27                  5      0.10%     99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28                  4      0.08%     99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29                  2      0.04%     99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30                  4      0.08%     99.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31                  2      0.04%     99.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::33                  1      0.02%     99.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35                  1      0.02%     99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36                  1      0.02%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::37                  1      0.02%     99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::39                 13      0.26%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40                  3      0.06%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::42                  1      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48                  1      0.02%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            5084                       # Writes before turning the bus around for reads
system.physmem.totQLat                     2537399000                       # Total ticks spent queuing
system.physmem.totMemAccLat                4590111500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    643805000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  1408907500                       # Total ticks spent accessing banks
system.physmem.avgQLat                       19706.27                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    10942.04                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  35648.31                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         309.84                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         201.95                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      309.85                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      202.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           4.00                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.42                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.58                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.36                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        25.09                       # Average write queue length when enqueuing
system.physmem.readRowHits                     112537                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     62593                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   87.40                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  74.56                       # Row buffer hit rate for writes
system.physmem.avgGap                       125035.31                       # Average gap between requests
system.physmem.pageHitRate                      82.33                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent              11.63                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                    511852674                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               26511                       # Transaction distribution
system.membus.trans_dist::ReadResp              26510                       # Transaction distribution
system.membus.trans_dist::Writeback             83945                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              300                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             300                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102255                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102255                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342076                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 342076                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13613440                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            13613440                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               13613440                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           934794000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1201882201                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              4.5                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                16626299                       # Number of BP lookups
system.cpu.branchPred.condPredicted          12761376                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            603542                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             10553987                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7772041                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             73.640805                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1823891                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             112970                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         53192807                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           12548027                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       85225985                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16626299                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9595932                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21195811                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2371567                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               10764095                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                  172                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           524                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           23                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11679981                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                179230                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           46249849                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.580108                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.332376                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 25074842     54.22%     54.22% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2134843      4.62%     58.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1965334      4.25%     63.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2045724      4.42%     67.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1467866      3.17%     70.68% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1377638      2.98%     73.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   956719      2.07%     75.73% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1188096      2.57%     78.29% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 10038787     21.71%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             46249849                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.312567                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.602209                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 14635842                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9109376                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19493309                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1372783                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1638539                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3331010                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                104505                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              116880506                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                361697                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1638539                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 16346771                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 2652791                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles        1020533                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  19105290                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5485925                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              114999580                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   152                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  17445                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4623062                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              183                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           115318587                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             529932404                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        476522297                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              2751                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 16185915                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              20374                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          20369                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13024660                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             29615928                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            22451967                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3877153                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          4417845                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  111572377                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               35991                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 107273861                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            274045                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        10831021                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     25918238                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           2205                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      46249849                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.319442                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.990414                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            10978806     23.74%     23.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             8116860     17.55%     41.29% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7434269     16.07%     57.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7097763     15.35%     72.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             5421519     11.72%     84.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3913580      8.46%     92.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1842525      3.98%     96.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              870168      1.88%     98.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              574359      1.24%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        46249849                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  113368      4.58%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.58% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1353818     54.73%     59.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               1006223     40.68%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              56655592     52.81%     52.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                91505      0.09%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 217      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             28893939     26.93%     79.83% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21632601     20.17%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              107273861                       # Type of FU issued
system.cpu.iq.rate                           2.016699                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2473411                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023057                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          263544444                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         122467509                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    105589962                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 583                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                918                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          177                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              109746981                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     291                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          2178933                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2308820                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6717                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        29962                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1896229                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads           29                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           670                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1638539                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1135526                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 46796                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           111618146                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            297287                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              29615928                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             22451967                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              20071                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   6522                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  5186                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          29962                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         392730                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       181164                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               573894                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             106245086                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              28594669                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1028775                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9778                       # number of nop insts executed
system.cpu.iew.exec_refs                     49940992                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14602318                       # Number of branches executed
system.cpu.iew.exec_stores                   21346323                       # Number of stores executed
system.cpu.iew.exec_rate                     1.997358                       # Inst execution rate
system.cpu.iew.wb_sent                      105809508                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     105590139                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  53305824                       # num instructions producing a value
system.cpu.iew.wb_consumers                 103866304                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.985045                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.513216                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        10986690                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            500884                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     44611310                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.255760                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.762475                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     15517142     34.78%     34.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11686207     26.20%     60.98% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3450926      7.74%     68.71% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2867812      6.43%     75.14% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1872959      4.20%     79.34% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1945129      4.36%     83.70% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       689747      1.55%     85.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       566134      1.27%     86.52% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6015254     13.48%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     44611310                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       47862846                       # Number of memory references committed
system.cpu.commit.loads                      27307108                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741485                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6015254                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    150189875                       # The number of ROB reads
system.cpu.rob.rob_writes                   224886049                       # The number of ROB writes
system.cpu.timesIdled                           80066                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         6942958                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              70907629                       # Number of Instructions Simulated
system.cpu.cpi                               0.750170                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.750170                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.333030                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.333030                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                511686083                       # number of integer regfile reads
system.cpu.int_regfile_writes               103364033                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       870                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      762                       # number of floating regfile writes
system.cpu.misc_regfile_reads                49348247                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               778162370                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          87191                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         87190                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       129156                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq          314                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          314                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       107034                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       107034                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        63123                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454609                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            517732                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2003904                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18660352                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total       20664256                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus          20664256                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        32064                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      291006496                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      48441979                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     259878236                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements             29471                       # number of replacements
system.cpu.icache.tags.tagsinuse          1806.055358                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            11644351                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             31508                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            369.568078                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1806.055358                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.881863                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.881863                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2037                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           84                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           19                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1253                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          681                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.994629                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          23391772                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         23391772                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     11644361                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11644361                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11644361                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11644361                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11644361                       # number of overall hits
system.cpu.icache.overall_hits::total        11644361                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        35619                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         35619                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        35619                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          35619                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        35619                       # number of overall misses
system.cpu.icache.overall_misses::total         35619                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    813918226                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    813918226                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    813918226                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    813918226                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    813918226                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    813918226                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11679980                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11679980                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11679980                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11679980                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11679980                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11679980                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003050                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.003050                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.003050                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.003050                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.003050                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.003050                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22850.675931                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 22850.675931                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22850.675931                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 22850.675931                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22850.675931                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 22850.675931                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs         1148                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                22                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    52.181818                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3807                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3807                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3807                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3807                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3807                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3807                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31812                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        31812                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        31812                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        31812                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        31812                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        31812                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    661574021                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    661574021                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    661574021                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    661574021                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    661574021                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    661574021                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002724                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002724                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002724                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.002724                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002724                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.002724                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20796.366811                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20796.366811                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20796.366811                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20796.366811                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20796.366811                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20796.366811                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            95635                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29857.974256                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              88990                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           126748                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.702102                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26666.144476                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1368.316766                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1823.513014                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.813786                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041758                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.055649                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.911193                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31113                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          137                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1837                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20828                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         7917                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          394                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949493                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          2819349                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         2819349                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        26638                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        33464                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          60102                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       129156                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       129156                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           14                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           14                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4779                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4779                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        26638                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        38243                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           64881                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        26638                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        38243                       # number of overall hits
system.cpu.l2cache.overall_hits::total          64881                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         4673                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21915                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26588                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          300                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          300                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102255                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102255                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4673                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       124170                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128843                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4673                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       124170                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128843                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    362632500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1783611000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2146243500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        23499                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        23499                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8210815250                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8210815250                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    362632500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data   9994426250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10357058750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    362632500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data   9994426250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10357058750                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        31311                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        55379                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        86690                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       129156                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       129156                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          314                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          314                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107034                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107034                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        31311                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       162413                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       193724                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        31311                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       162413                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       193724                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.149245                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.395728                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.306702                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.955414                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.955414                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955351                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955351                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.149245                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.764532                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.665085                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.149245                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.764532                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.665085                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77601.647764                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81387.679671                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80722.261923                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    78.330000                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    78.330000                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80297.445113                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80297.445113                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77601.647764                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80489.862688                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80385.110173                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77601.647764                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80489.862688                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80385.110173                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83945                       # number of writebacks
system.cpu.l2cache.writebacks::total            83945                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           60                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           77                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           60                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           77                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           17                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           60                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           77                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4656                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21855                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26511                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          300                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          300                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102255                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102255                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4656                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       124110                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128766                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4656                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       124110                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128766                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    303015250                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1507731500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1810746750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3014299                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3014299                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6936413750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6936413750                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    303015250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8444145250                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   8747160500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    303015250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8444145250                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   8747160500                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.148702                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394644                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.305814                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.955414                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.955414                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955351                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955351                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.148702                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764163                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.664688                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.148702                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764163                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.664688                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65080.594931                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68987.943262                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68301.714383                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10047.663333                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10047.663333                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67834.470197                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67834.470197                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65080.594931                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68037.589638                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67930.668810                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65080.594931                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68037.589638                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67930.668810                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            158316                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4068.473281                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            44361466                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            162412                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            273.141554                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         367394250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4068.473281                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993280                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993280                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1757                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2276                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          92298894                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         92298894                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     26061245                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        26061245                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18267715                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18267715                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15989                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15989                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      44328960                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         44328960                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     44328960                       # number of overall hits
system.cpu.dcache.overall_hits::total        44328960                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       125143                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        125143                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1582186                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1582186                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           44                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           44                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1707329                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1707329                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1707329                       # number of overall misses
system.cpu.dcache.overall_misses::total       1707329                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5010352449                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5010352449                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 122380602729                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 122380602729                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       944750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       944750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 127390955178                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 127390955178                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 127390955178                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 127390955178                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     26186388                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     26186388                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16033                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        16033                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     46036289                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     46036289                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     46036289                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     46036289                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004779                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004779                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079708                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.079708                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002744                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002744                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037087                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037087                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037087                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037087                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40037.017244                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40037.017244                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77349.061823                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77349.061823                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21471.590909                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21471.590909                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 74614.181085                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 74614.181085                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 74614.181085                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 74614.181085                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         4179                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1300                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               140                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              15                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    29.850000                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    86.666667                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       129156                       # number of writebacks
system.cpu.dcache.writebacks::total            129156                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69730                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        69730                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1474872                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1474872                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           44                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           44                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1544602                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1544602                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1544602                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1544602                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55413                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        55413                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107314                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107314                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       162727                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       162727                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       162727                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       162727                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2176479313                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2176479313                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8375757941                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8375757941                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10552237254                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  10552237254                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10552237254                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10552237254                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002116                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002116                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005406                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005406                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003535                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003535                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003535                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003535                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39277.413477                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39277.413477                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78049.070401                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78049.070401                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64846.259404                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 64846.259404                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64846.259404                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 64846.259404                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------