xref: /gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.026790                       # Number of seconds simulated
sim_ticks                                 26790388000                       # Number of ticks simulated
final_tick                                26790388000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 134448                       # Simulator instruction rate (inst/s)
host_op_rate                                   190799                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               50797444                       # Simulator tick rate (ticks/s)
host_mem_usage                                 278572                       # Number of bytes of host memory used
host_seconds                                   527.40                       # Real time elapsed on the host
sim_insts                                    70907629                       # Number of instructions simulated
sim_ops                                     100626876                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            297344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data           7942912                       # Number of bytes read from this memory
system.physmem.bytes_read::total              8240256                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       297344                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          297344                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      5371968                       # Number of bytes written to this memory
system.physmem.bytes_written::total           5371968                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               4646                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             124108                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                128754                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           83937                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83937                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst             11098906                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            296483649                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total               307582555                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst        11098906                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total           11098906                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks         200518484                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total              200518484                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks         200518484                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst            11098906                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           296483649                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              508101040                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        128754                       # Number of read requests accepted
system.physmem.writeReqs                        83937                       # Number of write requests accepted
system.physmem.readBursts                      128754                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      83937                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                  8240128                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                       128                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   5371648                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                   8240256                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                5371968                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        2                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs            308                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                8131                       # Per bank write bursts
system.physmem.perBankRdBursts::1                8390                       # Per bank write bursts
system.physmem.perBankRdBursts::2                8247                       # Per bank write bursts
system.physmem.perBankRdBursts::3                8163                       # Per bank write bursts
system.physmem.perBankRdBursts::4                8302                       # Per bank write bursts
system.physmem.perBankRdBursts::5                8446                       # Per bank write bursts
system.physmem.perBankRdBursts::6                8088                       # Per bank write bursts
system.physmem.perBankRdBursts::7                7962                       # Per bank write bursts
system.physmem.perBankRdBursts::8                8060                       # Per bank write bursts
system.physmem.perBankRdBursts::9                7613                       # Per bank write bursts
system.physmem.perBankRdBursts::10               7786                       # Per bank write bursts
system.physmem.perBankRdBursts::11               7812                       # Per bank write bursts
system.physmem.perBankRdBursts::12               7879                       # Per bank write bursts
system.physmem.perBankRdBursts::13               7885                       # Per bank write bursts
system.physmem.perBankRdBursts::14               7978                       # Per bank write bursts
system.physmem.perBankRdBursts::15               8010                       # Per bank write bursts
system.physmem.perBankWrBursts::0                5179                       # Per bank write bursts
system.physmem.perBankWrBursts::1                5375                       # Per bank write bursts
system.physmem.perBankWrBursts::2                5289                       # Per bank write bursts
system.physmem.perBankWrBursts::3                5157                       # Per bank write bursts
system.physmem.perBankWrBursts::4                5265                       # Per bank write bursts
system.physmem.perBankWrBursts::5                5517                       # Per bank write bursts
system.physmem.perBankWrBursts::6                5207                       # Per bank write bursts
system.physmem.perBankWrBursts::7                5048                       # Per bank write bursts
system.physmem.perBankWrBursts::8                5029                       # Per bank write bursts
system.physmem.perBankWrBursts::9                5089                       # Per bank write bursts
system.physmem.perBankWrBursts::10               5251                       # Per bank write bursts
system.physmem.perBankWrBursts::11               5144                       # Per bank write bursts
system.physmem.perBankWrBursts::12               5342                       # Per bank write bursts
system.physmem.perBankWrBursts::13               5363                       # Per bank write bursts
system.physmem.perBankWrBursts::14               5451                       # Per bank write bursts
system.physmem.perBankWrBursts::15               5226                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     26790282500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  128754                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  83937                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     73147                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     54223                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                      1319                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        57                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         6                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                      3672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                      3689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                      3689                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                      3683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                      3681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                      3683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                      3687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                      3686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                      3681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                      3678                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                     3681                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                     3680                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                     3686                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                     3683                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                     3698                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                     3772                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                     3751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     3941                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     3889                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     3936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4300                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     5019                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                       63                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        8                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples        37879                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      359.276222                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     174.215706                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     692.456870                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65          15075     39.80%     39.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129         5750     15.18%     54.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193         3421      9.03%     64.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257         2320      6.12%     70.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321         1668      4.40%     74.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385         1547      4.08%     78.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449         1100      2.90%     81.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513          895      2.36%     83.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577          687      1.81%     85.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641          539      1.42%     87.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705          385      1.02%     88.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769          594      1.57%     89.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833          272      0.72%     90.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897          354      0.93%     91.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961          173      0.46%     91.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025          239      0.63%     92.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089          118      0.31%     92.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153          247      0.65%     93.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217          108      0.29%     93.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281          279      0.74%     94.43% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345          118      0.31%     94.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409          446      1.18%     95.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473          106      0.28%     96.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537          237      0.63%     96.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601           43      0.11%     96.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665          118      0.31%     97.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1729           42      0.11%     97.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1793           85      0.22%     97.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857           20      0.05%     97.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1921           62      0.16%     97.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985           22      0.06%     97.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049           44      0.12%     97.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113           19      0.05%     98.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177           33      0.09%     98.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241           16      0.04%     98.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305           33      0.09%     98.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369            8      0.02%     98.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433           24      0.06%     98.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497           13      0.03%     98.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2561           33      0.09%     98.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625           14      0.04%     98.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689           23      0.06%     98.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753           10      0.03%     98.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817           16      0.04%     98.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2881            9      0.02%     98.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2945           18      0.05%     98.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009            4      0.01%     98.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073           17      0.04%     98.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137           11      0.03%     98.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3201           19      0.05%     98.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3265           11      0.03%     98.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3329           26      0.07%     98.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3393            4      0.01%     98.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457            7      0.02%     98.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3521           10      0.03%     98.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3585            5      0.01%     98.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649            7      0.02%     99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3713           10      0.03%     99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777            5      0.01%     99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3841            9      0.02%     99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3905            4      0.01%     99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969           16      0.04%     99.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4033            7      0.02%     99.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4097            9      0.02%     99.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161            5      0.01%     99.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225           10      0.03%     99.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289           10      0.03%     99.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353           11      0.03%     99.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4417            6      0.02%     99.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4481           10      0.03%     99.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4545            7      0.02%     99.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4609            6      0.02%     99.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4673            5      0.01%     99.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4737            5      0.01%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4801            2      0.01%     99.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865           12      0.03%     99.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4929            4      0.01%     99.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4993            8      0.02%     99.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5057            5      0.01%     99.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121            9      0.02%     99.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5185            2      0.01%     99.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5249            7      0.02%     99.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5313            4      0.01%     99.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377            6      0.02%     99.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5441            5      0.01%     99.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5505            7      0.02%     99.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5569            7      0.02%     99.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5633           10      0.03%     99.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5697            4      0.01%     99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5761            3      0.01%     99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5825            5      0.01%     99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5889            2      0.01%     99.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-5953            4      0.01%     99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6017            1      0.00%     99.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6081            5      0.01%     99.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6145            6      0.02%     99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6209            6      0.02%     99.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6273            3      0.01%     99.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6337            5      0.01%     99.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6401            4      0.01%     99.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6465            5      0.01%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6529            1      0.00%     99.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6593            4      0.01%     99.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6657            4      0.01%     99.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6721            5      0.01%     99.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6785            5      0.01%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6849            1      0.00%     99.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6913            4      0.01%     99.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6977            4      0.01%     99.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7041            5      0.01%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7105            1      0.00%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7169            1      0.00%     99.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7233            2      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7297            3      0.01%     99.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7425            3      0.01%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7553            1      0.00%     99.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7681            3      0.01%     99.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7745            3      0.01%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7873            1      0.00%     99.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7937            1      0.00%     99.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8065            4      0.01%     99.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8129            6      0.02%     99.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193           37      0.10%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total          37879                       # Bytes accessed per row activation
system.physmem.totQLat                     3022726750                       # Total ticks spent queuing
system.physmem.totMemAccLat                4971045500                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                    643760000                       # Total ticks spent in databus transfers
system.physmem.totBankLat                  1304558750                       # Total ticks spent accessing banks
system.physmem.avgQLat                       23477.12                       # Average queueing delay per DRAM burst
system.physmem.avgBankLat                    10132.34                       # Average bank access latency per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  38609.46                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                         307.58                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                         200.51                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                      307.58                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                      200.52                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           3.97                       # Data bus utilization in percentage
system.physmem.busUtilRead                       2.40                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      1.57                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         0.19                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         9.70                       # Average write queue length when enqueuing
system.physmem.readRowHits                     117872                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     56933                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   91.55                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  67.83                       # Row buffer hit rate for writes
system.physmem.avgGap                       125958.70                       # Average gap between requests
system.physmem.pageHitRate                      82.19                       # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent              11.78                       # Percentage of time for which DRAM has all the banks in precharge state
system.membus.throughput                    508101040                       # Throughput (bytes/s)
system.membus.trans_dist::ReadReq               26500                       # Transaction distribution
system.membus.trans_dist::ReadResp              26500                       # Transaction distribution
system.membus.trans_dist::Writeback             83937                       # Transaction distribution
system.membus.trans_dist::UpgradeReq              308                       # Transaction distribution
system.membus.trans_dist::UpgradeResp             308                       # Transaction distribution
system.membus.trans_dist::ReadExReq            102254                       # Transaction distribution
system.membus.trans_dist::ReadExResp           102254                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       342061                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 342061                       # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     13612224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total            13612224                       # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus               13612224                       # Total data (bytes)
system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
system.membus.reqLayer0.occupancy           934459500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               3.5                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1203485442                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              4.5                       # Layer utilization (%)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.branchPred.lookups                16615535                       # Number of BP lookups
system.cpu.branchPred.condPredicted          12754556                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect            602333                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             10795457                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                 7770077                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             71.975434                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 1823925                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             112966                       # Number of incorrect RAS predictions.
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                 1946                       # Number of system calls
system.cpu.numCycles                         53580777                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles           12546836                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                       85170403                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    16615535                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches            9594002                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                      21183792                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                 2362024                       # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles               10685029                       # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles                   63                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles           557                       # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles           20                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  11675856                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                179932                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples           46149323                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.583841                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             3.333163                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 24986446     54.14%     54.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                  2137638      4.63%     58.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                  1962079      4.25%     63.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                  2043997      4.43%     67.46% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4                  1466310      3.18%     70.63% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5                  1377582      2.99%     73.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6                   960310      2.08%     75.70% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7                  1185958      2.57%     78.27% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8                 10029003     21.73%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total             46149323                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.310103                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        1.589570                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 14635353                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles               9029918                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                  19485051                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               1368887                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                1630114                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved              3325603                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                104819                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              116788167                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts                363460                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                1630114                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 16340014                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 2585458                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles        1028005                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                  19100045                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               5465687                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              114914880                       # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents                   172                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                  17272                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents               4606354                       # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents              316                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           115243032                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups             529540867                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        476170049                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups              2600                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps              99132672                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 16110360                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              20388                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          20384                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  12995984                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             29602749                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            22439249                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           3932152                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          4401403                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  111507434                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               36062                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 107242523                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued            272405                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        10768427                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     25739903                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved           2276                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples      46149323                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         2.323816                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.990206                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            10919279     23.66%     23.66% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1             8079518     17.51%     41.17% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2             7423472     16.09%     57.25% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3             7094481     15.37%     72.63% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             5420902     11.75%     84.37% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5             3930329      8.52%     92.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6             1841974      3.99%     96.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7              869423      1.88%     98.76% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8              569945      1.24%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total        46149323                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                  112279      4.53%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     2      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      4.53% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead                1361817     54.98%     59.52% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               1002641     40.48%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu              56635396     52.81%     52.81% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult                91455      0.09%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 208      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc              7      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     52.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             28883502     26.93%     79.83% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            21631955     20.17%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              107242523                       # Type of FU issued
system.cpu.iq.rate                           2.001511                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                     2476739                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.023095                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          263382945                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         122340040                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    105564996                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads                 568                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes                856                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses          168                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              109718975                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                     287                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          2181751                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      2295641                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         6455                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation        29983                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1883511                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads           31                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           679                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                1630114                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 1093825                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 45147                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           111553302                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts            294819                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              29602749                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             22439249                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              20142                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   6322                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                  5200                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents          29983                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect         391827                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect       180696                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts               572523                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             106211851                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              28585179                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           1030672                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                          9806                       # number of nop insts executed
system.cpu.iew.exec_refs                     49926975                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 14599283                       # Number of branches executed
system.cpu.iew.exec_stores                   21341796                       # Number of stores executed
system.cpu.iew.exec_rate                     1.982275                       # Inst execution rate
system.cpu.iew.wb_sent                      105782073                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     105565164                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                  53316718                       # num instructions producing a value
system.cpu.iew.wb_consumers                 103963305                       # num instructions consuming a value
system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate                       1.970206                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.512842                       # average fanout of values written-back
system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts        10921742                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           33786                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts            499421                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples     44519209                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     2.260427                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     2.765009                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     15470185     34.75%     34.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     11634994     26.13%     60.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2      3452010      7.75%     68.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      2868846      6.44%     75.08% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      1865323      4.19%     79.27% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      1954753      4.39%     83.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6       686748      1.54%     85.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7       559469      1.26%     86.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      6026881     13.54%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total     44519209                       # Number of insts commited each cycle
system.cpu.commit.committedInsts             70913181                       # Number of instructions committed
system.cpu.commit.committedOps              100632428                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       47862846                       # Number of memory references committed
system.cpu.commit.loads                      27307108                       # Number of loads committed
system.cpu.commit.membars                       15920                       # Number of memory barriers committed
system.cpu.commit.branches                   13741485                       # Number of branches committed
system.cpu.commit.fp_insts                         56                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                  91472779                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1679850                       # Number of function calls committed.
system.cpu.commit.bw_lim_events               6026881                       # number cycles where commit BW limit reached
system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
system.cpu.rob.rob_reads                    150021199                       # The number of ROB reads
system.cpu.rob.rob_writes                   224747411                       # The number of ROB writes
system.cpu.timesIdled                           76674                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                         7431454                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                    70907629                       # Number of Instructions Simulated
system.cpu.committedOps                     100626876                       # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total              70907629                       # Number of Instructions Simulated
system.cpu.cpi                               0.755642                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.755642                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.323378                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.323378                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                511545132                       # number of integer regfile reads
system.cpu.int_regfile_writes               103340839                       # number of integer regfile writes
system.cpu.fp_regfile_reads                       806                       # number of floating regfile reads
system.cpu.fp_regfile_writes                      694                       # number of floating regfile writes
system.cpu.misc_regfile_reads                49339612                       # number of misc regfile reads
system.cpu.misc_regfile_writes                  31840                       # number of misc regfile writes
system.cpu.toL2Bus.throughput               773036658                       # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq          87363                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp         87363                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback       129182                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq          325                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp          325                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       107048                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       107048                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        63452                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       454686                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            518138                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      2013952                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     18662976                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total       20676928                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus          20676928                       # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus        33024                       # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy      291143497                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          1.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      48712731                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     260354993                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          1.0                       # Layer utilization (%)
system.cpu.icache.tags.replacements             29638                       # number of replacements
system.cpu.icache.tags.tagsinuse          1806.211071                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            11640103                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             31672                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            367.520302                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1806.211071                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.881939                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.881939                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         2034                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           89                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3         1251                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          676                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.993164                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          23383696                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         23383696                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     11640118                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        11640118                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      11640118                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         11640118                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     11640118                       # number of overall hits
system.cpu.icache.overall_hits::total        11640118                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        35738                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         35738                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        35738                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          35738                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        35738                       # number of overall misses
system.cpu.icache.overall_misses::total         35738                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    828271479                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    828271479                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    828271479                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    828271479                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    828271479                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    828271479                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     11675856                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     11675856                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     11675856                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     11675856                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     11675856                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     11675856                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003061                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.003061                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.003061                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.003061                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.003061                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.003061                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23176.212407                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 23176.212407                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23176.212407                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 23176.212407                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23176.212407                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 23176.212407                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs          856                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                20                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    42.800000                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3754                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3754                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3754                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3754                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3754                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3754                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        31984                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        31984                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        31984                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        31984                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        31984                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        31984                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    671357769                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    671357769                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    671357769                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    671357769                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    671357769                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    671357769                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002739                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.002739                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002739                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.002739                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002739                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.002739                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20990.425494                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20990.425494                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20990.425494                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 20990.425494                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20990.425494                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 20990.425494                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements            95620                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        29882.992791                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs              89182                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           126734                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             0.703694                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 26677.610156                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  1366.039955                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data  1839.342681                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.814136                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.041688                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.056132                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.911957                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        31114                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          144                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1         1849                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2        20244                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         8486                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4          391                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949524                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          2821016                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         2821016                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst        26805                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data        33463                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total          60268                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks       129182                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total       129182                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           17                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           17                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         4794                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         4794                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst        26805                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        38257                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total           65062                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        26805                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        38257                       # number of overall hits
system.cpu.l2cache.overall_hits::total          65062                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         4663                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        21916                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        26579                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data          308                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total          308                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       102254                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       102254                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         4663                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       124170                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        128833                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         4663                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       124170                       # number of overall misses
system.cpu.l2cache.overall_misses::total       128833                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    370582250                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1870540500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total   2241122750                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data        22999                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total        22999                       # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8514187000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   8514187000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    370582250                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  10384727500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  10755309750                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    370582250                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  10384727500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  10755309750                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst        31468                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data        55379                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total        86847                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks       129182                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total       129182                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data          325                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total          325                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       107048                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       107048                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        31468                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       162427                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       193895                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        31468                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       162427                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       193895                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.148182                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.395746                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.306044                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.947692                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.947692                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.955216                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.955216                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.148182                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.764466                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.664447                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.148182                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.764466                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.664447                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79472.925155                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85350.451725                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84319.302833                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    74.672078                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    74.672078                       # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83265.075205                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83265.075205                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79472.925155                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83633.144077                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 83482.568519                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79472.925155                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83633.144077                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 83482.568519                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        83937                       # number of writebacks
system.cpu.l2cache.writebacks::total            83937                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           17                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           62                       # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total           79                       # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst           17                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           62                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           79                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst           17                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           62                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           79                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4646                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        21854                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total        26500                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          308                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total          308                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102254                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       102254                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         4646                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       124108                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       128754                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         4646                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       124108                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       128754                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    311360750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1593475000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1904835750                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3080308                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3080308                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7238548000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7238548000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    311360750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8832023000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total   9143383750                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    311360750                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8832023000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total   9143383750                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.147642                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.394626                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.305134                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.947692                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.947692                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.955216                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.955216                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.147642                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.764085                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.664040                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.147642                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.764085                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.664040                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67016.950065                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72914.569415                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71880.594340                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        10001                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70789.876191                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70789.876191                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67016.950065                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71164.010378                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71014.366544                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67016.950065                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71164.010378                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71014.366544                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements            158331                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4068.839586                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            44347897                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            162427                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            273.032790                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         363282250                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4068.839586                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.993369                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.993369                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           66                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1         1776                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2         2254                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          92273995                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         92273995                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     26048802                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        26048802                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     18266579                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       18266579                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        15981                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        15981                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      44315381                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         44315381                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     44315381                       # number of overall hits
system.cpu.dcache.overall_hits::total        44315381                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       125140                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        125140                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1583322                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1583322                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data           41                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total           41                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data      1708462                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1708462                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1708462                       # number of overall misses
system.cpu.dcache.overall_misses::total       1708462                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   5205484954                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   5205484954                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 127036653749                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 127036653749                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       856750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total       856750                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 132242138703                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 132242138703                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 132242138703                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 132242138703                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     26173942                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     26173942                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        16022                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        16022                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     46023843                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     46023843                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     46023843                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     46023843                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004781                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004781                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.079765                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.079765                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.002559                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.002559                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.037121                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.037121                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.037121                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.037121                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41597.290666                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 41597.290666                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80234.250360                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 80234.250360                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20896.341463                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20896.341463                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 77404.202554                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 77404.202554                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 77404.202554                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 77404.202554                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs         4865                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets         1223                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs               137                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              14                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    35.510949                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    87.357143                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       129182                       # number of writebacks
system.cpu.dcache.writebacks::total            129182                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        69727                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        69727                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1475983                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      1475983                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           41                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total           41                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data      1545710                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total      1545710                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data      1545710                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total      1545710                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55413                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        55413                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107339                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       107339                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       162752                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       162752                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       162752                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       162752                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2263243564                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total   2263243564                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8680214182                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   8680214182                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10943457746                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  10943457746                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10943457746                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  10943457746                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002117                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002117                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005408                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005408                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.003536                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003536                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.003536                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40843.187772                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40843.187772                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80867.291311                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80867.291311                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 67240.081511                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67240.081511                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67240.081511                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67240.081511                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------