stats.txt revision 11308
17860SN/A 27860SN/A---------- Begin Simulation Statistics ---------- 311201Sandreas.hansson@arm.comsim_seconds 0.234001 # Number of seconds simulated 411201Sandreas.hansson@arm.comsim_ticks 234001297000 # Number of ticks simulated 511201Sandreas.hansson@arm.comfinal_tick 234001297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67860SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711201Sandreas.hansson@arm.comhost_inst_rate 134504 # Simulator instruction rate (inst/s) 811201Sandreas.hansson@arm.comhost_op_rate 145716 # Simulator op (including micro ops) rate (op/s) 911201Sandreas.hansson@arm.comhost_tick_rate 62295833 # Simulator tick rate (ticks/s) 1011201Sandreas.hansson@arm.comhost_mem_usage 343376 # Number of bytes of host memory used 1111201Sandreas.hansson@arm.comhost_seconds 3756.29 # Real time elapsed on the host 1210812Snilay@cs.wisc.edusim_insts 505237724 # Number of instructions simulated 1310812Snilay@cs.wisc.edusim_ops 547350945 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 517504 # Number of bytes read from this memory 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10131008 # Number of bytes read from this memory 1811201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 16480064 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 27128576 # Number of bytes read from this memory 2011201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 517504 # Number of instructions bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 517504 # Number of instructions bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 18730688 # Number of bytes written to this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 18730688 # Number of bytes written to this memory 2411201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 8086 # Number of read requests responded to by this memory 2511201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 158297 # Number of read requests responded to by this memory 2611201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 257501 # Number of read requests responded to by this memory 2711201Sandreas.hansson@arm.comsystem.physmem.num_reads::total 423884 # Number of read requests responded to by this memory 2811201Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 292667 # Number of write requests responded to by this memory 2911201Sandreas.hansson@arm.comsystem.physmem.num_writes::total 292667 # Number of write requests responded to by this memory 3011201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 2211543 # Total read bandwidth from this memory (bytes/s) 3111201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 43294666 # Total read bandwidth from this memory (bytes/s) 3211201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 70427234 # Total read bandwidth from this memory (bytes/s) 3311201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 115933443 # Total read bandwidth from this memory (bytes/s) 3411201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 2211543 # Instruction read bandwidth from this memory (bytes/s) 3511201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 2211543 # Instruction read bandwidth from this memory (bytes/s) 3611201Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 80045232 # Write bandwidth from this memory (bytes/s) 3711201Sandreas.hansson@arm.comsystem.physmem.bw_write::total 80045232 # Write bandwidth from this memory (bytes/s) 3811201Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 80045232 # Total bandwidth to/from this memory (bytes/s) 3911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 2211543 # Total bandwidth to/from this memory (bytes/s) 4011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 43294666 # Total bandwidth to/from this memory (bytes/s) 4111201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 70427234 # Total bandwidth to/from this memory (bytes/s) 4211201Sandreas.hansson@arm.comsystem.physmem.bw_total::total 195978674 # Total bandwidth to/from this memory (bytes/s) 4311201Sandreas.hansson@arm.comsystem.physmem.readReqs 423884 # Number of read requests accepted 4411201Sandreas.hansson@arm.comsystem.physmem.writeReqs 292667 # Number of write requests accepted 4511201Sandreas.hansson@arm.comsystem.physmem.readBursts 423884 # Number of DRAM read bursts, including those serviced by the write queue 4611201Sandreas.hansson@arm.comsystem.physmem.writeBursts 292667 # Number of DRAM write bursts, including those merged in the write queue 4711201Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 26972992 # Total number of bytes read from DRAM 4811201Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 155584 # Total number of bytes read from write queue 4911201Sandreas.hansson@arm.comsystem.physmem.bytesWritten 18728832 # Total number of bytes written to DRAM 5011201Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 27128576 # Total read bytes from the system interface side 5111201Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 18730688 # Total written bytes from the system interface side 5211201Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 2431 # Number of DRAM read bursts serviced by the write queue 5311201Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one 5411201Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 98651 # Number of requests that are neither read nor write 5511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 26584 # Per bank write bursts 5611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 25337 # Per bank write bursts 5711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 25274 # Per bank write bursts 5811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 32197 # Per bank write bursts 5911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 27335 # Per bank write bursts 6011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 28299 # Per bank write bursts 6111201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 25126 # Per bank write bursts 6211201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 24198 # Per bank write bursts 6311201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 25368 # Per bank write bursts 6411201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 25926 # Per bank write bursts 6511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25318 # Per bank write bursts 6611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 26278 # Per bank write bursts 6711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 27572 # Per bank write bursts 6811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25872 # Per bank write bursts 6911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 25056 # Per bank write bursts 7011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25713 # Per bank write bursts 7111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 18662 # Per bank write bursts 7211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 18231 # Per bank write bursts 7311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 18003 # Per bank write bursts 7411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 17875 # Per bank write bursts 7511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 18721 # Per bank write bursts 7611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 18310 # Per bank write bursts 7711201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 17836 # Per bank write bursts 7811201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 17744 # Per bank write bursts 7911201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 17983 # Per bank write bursts 8011201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 17940 # Per bank write bursts 8111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 18239 # Per bank write bursts 8211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 18938 # Per bank write bursts 8311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 18976 # Per bank write bursts 8411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 18211 # Per bank write bursts 8511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 18390 # Per bank write bursts 8611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 18579 # Per bank write bursts 879978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 889978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8911201Sandreas.hansson@arm.comsystem.physmem.totGap 234001244500 # Total gap between requests 909978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 949978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 959978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9611201Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 423884 # Read request sizes (log2) 979978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 989978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 999978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1009978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1019978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10311201Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 292667 # Write request sizes (log2) 10411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 323806 # What read queue length does an incoming req see 10511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 49376 # What read queue length does an incoming req see 10611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 12876 # What read queue length does an incoming req see 10711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 8979 # What read queue length does an incoming req see 10811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see 10911201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see 11011201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 5227 # What read queue length does an incoming req see 11111201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 4284 # What read queue length does an incoming req see 11211201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 3341 # What read queue length does an incoming req see 11311201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see 11411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 11511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see 11611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see 11711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see 11810726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11910628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 7238 # What write queue length does an incoming req see 15211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 7730 # What write queue length does an incoming req see 15311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 12413 # What write queue length does an incoming req see 15411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 15049 # What write queue length does an incoming req see 15511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 16333 # What write queue length does an incoming req see 15611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 16979 # What write queue length does an incoming req see 15711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 17275 # What write queue length does an incoming req see 15811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 17603 # What write queue length does an incoming req see 15911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 17899 # What write queue length does an incoming req see 16011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 18115 # What write queue length does an incoming req see 16111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 18307 # What write queue length does an incoming req see 16211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 18692 # What write queue length does an incoming req see 16311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 18718 # What write queue length does an incoming req see 16411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 18910 # What write queue length does an incoming req see 16511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 19072 # What write queue length does an incoming req see 16611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 17647 # What write queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 17263 # What write queue length does an incoming req see 16811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 17149 # What write queue length does an incoming req see 16911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 141 # What write queue length does an incoming req see 17011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see 17111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see 17211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see 17311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see 17411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see 17511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see 17611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see 17711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see 17811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 17911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 18010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 18110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 18210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18310220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18410220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18510220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18610220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18710220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18810220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18910220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 19010220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 19110220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 19210220Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 20011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 322061 # Bytes accessed per row activation 20111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 141.901068 # Bytes accessed per row activation 20211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 99.764285 # Bytes accessed per row activation 20311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 180.057081 # Bytes accessed per row activation 20411201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 202493 62.87% 62.87% # Bytes accessed per row activation 20511201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 79759 24.77% 87.64% # Bytes accessed per row activation 20611201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 15144 4.70% 92.34% # Bytes accessed per row activation 20711201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 7279 2.26% 94.60% # Bytes accessed per row activation 20811201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 4961 1.54% 96.14% # Bytes accessed per row activation 20911201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 2580 0.80% 96.94% # Bytes accessed per row activation 21011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1828 0.57% 97.51% # Bytes accessed per row activation 21111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1538 0.48% 97.99% # Bytes accessed per row activation 21211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 6479 2.01% 100.00% # Bytes accessed per row activation 21311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 322061 # Bytes accessed per row activation 21411201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 17076 # Reads before turning the bus around for writes 21511201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 24.676095 # Reads before turning the bus around for writes 21611201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 143.384257 # Reads before turning the bus around for writes 21711201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 17074 99.99% 99.99% # Reads before turning the bus around for writes 21811201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes 21911201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes 22011201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 17076 # Reads before turning the bus around for writes 22111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 17076 # Writes before turning the bus around for reads 22211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.137386 # Writes before turning the bus around for reads 22311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.076722 # Writes before turning the bus around for reads 22411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 1.519222 # Writes before turning the bus around for reads 22511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 9254 54.19% 54.19% # Writes before turning the bus around for reads 22611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::17 359 2.10% 56.30% # Writes before turning the bus around for reads 22711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 5270 30.86% 87.16% # Writes before turning the bus around for reads 22811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::19 1365 7.99% 95.15% # Writes before turning the bus around for reads 22911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20 405 2.37% 97.52% # Writes before turning the bus around for reads 23011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::21 163 0.95% 98.48% # Writes before turning the bus around for reads 23111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::22 106 0.62% 99.10% # Writes before turning the bus around for reads 23211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::23 62 0.36% 99.46% # Writes before turning the bus around for reads 23311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24 41 0.24% 99.70% # Writes before turning the bus around for reads 23411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::25 19 0.11% 99.81% # Writes before turning the bus around for reads 23511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::26 11 0.06% 99.88% # Writes before turning the bus around for reads 23611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads 23711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads 23811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::29 3 0.02% 99.94% # Writes before turning the bus around for reads 23911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::30 3 0.02% 99.96% # Writes before turning the bus around for reads 24011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32 2 0.01% 99.97% # Writes before turning the bus around for reads 24111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads 24211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads 24311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads 24411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::39 1 0.01% 99.99% # Writes before turning the bus around for reads 24511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads 24611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 17076 # Writes before turning the bus around for reads 24711201Sandreas.hansson@arm.comsystem.physmem.totQLat 8693371575 # Total ticks spent queuing 24811201Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 16595615325 # Total ticks spent from burst creation until serviced by the DRAM 24911201Sandreas.hansson@arm.comsystem.physmem.totBusLat 2107265000 # Total ticks spent in databus transfers 25011201Sandreas.hansson@arm.comsystem.physmem.avgQLat 20627.14 # Average queueing delay per DRAM burst 2519978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 25211201Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 39377.14 # Average memory access latency per DRAM burst 25311201Sandreas.hansson@arm.comsystem.physmem.avgRdBW 115.27 # Average DRAM read bandwidth in MiByte/s 25411201Sandreas.hansson@arm.comsystem.physmem.avgWrBW 80.04 # Average achieved write bandwidth in MiByte/s 25511201Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 115.93 # Average system read bandwidth in MiByte/s 25611201Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 80.05 # Average system write bandwidth in MiByte/s 2579978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 25811201Sandreas.hansson@arm.comsystem.physmem.busUtil 1.53 # Data bus utilization in percentage 25911201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads 26010628Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes 26111201Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing 26211201Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 21.60 # Average write queue length when enqueuing 26311201Sandreas.hansson@arm.comsystem.physmem.readRowHits 306420 # Number of row buffer hits during reads 26411201Sandreas.hansson@arm.comsystem.physmem.writeRowHits 85606 # Number of row buffer hits during writes 26511201Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 72.71 # Row buffer hit rate for reads 26611201Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 29.25 # Row buffer hit rate for writes 26711201Sandreas.hansson@arm.comsystem.physmem.avgGap 326566.07 # Average gap between requests 26811201Sandreas.hansson@arm.comsystem.physmem.pageHitRate 54.90 # Row buffer hit rate, read and write combined 26911201Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 1224553680 # Energy for activate commands per rank (pJ) 27011201Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 668159250 # Energy for precharge commands per rank (pJ) 27111201Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1671883200 # Energy for read commands per rank (pJ) 27211201Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 942075360 # Energy for write commands per rank (pJ) 27311201Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) 27411201Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 82043634285 # Energy for active background per rank (pJ) 27511201Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 68432158500 # Energy for precharge background per rank (pJ) 27611201Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 170266217955 # Total energy per rank (pJ) 27711201Sandreas.hansson@arm.comsystem.physmem_0.averagePower 727.632069 # Core power per rank (mW) 27811201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 113312610225 # Time in different power states 27911201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 7813780000 # Time in different power states 28010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 28111201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 112874154775 # Time in different power states 28210628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 28311201Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 1210227480 # Energy for activate commands per rank (pJ) 28411201Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 660342375 # Energy for precharge commands per rank (pJ) 28511201Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1615325400 # Energy for read commands per rank (pJ) 28611201Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 954218880 # Energy for write commands per rank (pJ) 28711201Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) 28811201Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 79914700530 # Energy for active background per rank (pJ) 28911201Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 70299646500 # Energy for precharge background per rank (pJ) 29011201Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 169938214845 # Total energy per rank (pJ) 29111201Sandreas.hansson@arm.comsystem.physmem_1.averagePower 726.230337 # Core power per rank (mW) 29211201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 116426727240 # Time in different power states 29311201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 7813780000 # Time in different power states 29410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 29511201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 109759940510 # Time in different power states 29610628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 29711201Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 175128597 # Number of BP lookups 29811201Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 131371974 # Number of conditional branches predicted 29911201Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 7444955 # Number of conditional branches incorrect 30011201Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 90537565 # Number of BTB lookups 30111201Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 83893856 # Number of BTB hits 30210628Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 30311201Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 92.661931 # BTB Hit Percentage 30411201Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 12111370 # Number of times the RAS was used to get a target. 30511201Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 104180 # Number of incorrect RAS predictions. 30610036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 30710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 30810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 31210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 31310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 31410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 31510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 31610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 31710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 31810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 31910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 32010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 32110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 32210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 32610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 32710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 32810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 32910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 33110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 33210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 33310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 33410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 33510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 33610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 33710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 33810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 34310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 3448317SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 3458317SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 3468317SN/Asystem.cpu.dtb.read_hits 0 # DTB read hits 3478317SN/Asystem.cpu.dtb.read_misses 0 # DTB read misses 3488317SN/Asystem.cpu.dtb.write_hits 0 # DTB write hits 3498317SN/Asystem.cpu.dtb.write_misses 0 # DTB write misses 3508317SN/Asystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 3518317SN/Asystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3528317SN/Asystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 3538317SN/Asystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 3548317SN/Asystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 3558317SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 3568317SN/Asystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 3578317SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 3588317SN/Asystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3598317SN/Asystem.cpu.dtb.read_accesses 0 # DTB read accesses 3608317SN/Asystem.cpu.dtb.write_accesses 0 # DTB write accesses 3618317SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 3628317SN/Asystem.cpu.dtb.hits 0 # DTB hits 3638317SN/Asystem.cpu.dtb.misses 0 # DTB misses 3648317SN/Asystem.cpu.dtb.accesses 0 # DTB accesses 36510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 36610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 37210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 37410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 37510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 37610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 37710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 37810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 37910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 38010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 38210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 38410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 38510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 38610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 38710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 38910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 39010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 39110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 39210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 39310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 39410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 39510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 4028317SN/Asystem.cpu.itb.inst_hits 0 # ITB inst hits 4038317SN/Asystem.cpu.itb.inst_misses 0 # ITB inst misses 4048317SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 4058317SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 4068317SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 4078317SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 4088317SN/Asystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 4098317SN/Asystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4108317SN/Asystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 4118317SN/Asystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 4128317SN/Asystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 4138317SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4148317SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4158317SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4168317SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4178317SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 4188317SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 4198317SN/Asystem.cpu.itb.inst_accesses 0 # ITB inst accesses 4208317SN/Asystem.cpu.itb.hits 0 # DTB hits 4218317SN/Asystem.cpu.itb.misses 0 # DTB misses 4228317SN/Asystem.cpu.itb.accesses 0 # DTB accesses 4238317SN/Asystem.cpu.workload.num_syscalls 548 # Number of system calls 42411201Sandreas.hansson@arm.comsystem.cpu.numCycles 468002595 # number of cpu cycles simulated 4258317SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 4268317SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 42711201Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 7807530 # Number of cycles fetch is stalled on an Icache miss 42811201Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 731939592 # Number of instructions fetch has processed 42911201Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 175128597 # Number of branches that fetch encountered 43011201Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 96005226 # Number of branches that fetch has predicted taken 43111201Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 452073756 # Number of cycles fetch has run and was not squashing or blocked 43211201Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 14942657 # Number of cycles fetch has spent squashing 43311201Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 4553 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 43411201Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 179 # Number of stall cycles due to pending traps 43511201Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 11657 # Number of stall cycles due to full MSHR 43611201Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 236761982 # Number of cache lines fetched 43711201Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 33954 # Number of outstanding Icache misses that were squashed 43811201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 467369003 # Number of instructions fetched each cycle (Total) 43911201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.696062 # Number of instructions fetched each cycle (Total) 44011201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 1.181505 # Number of instructions fetched each cycle (Total) 4418317SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 44211201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 95368751 20.41% 20.41% # Number of instructions fetched each cycle (Total) 44311201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 132719598 28.40% 48.80% # Number of instructions fetched each cycle (Total) 44411201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 57874720 12.38% 61.19% # Number of instructions fetched each cycle (Total) 44511201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 181405934 38.81% 100.00% # Number of instructions fetched each cycle (Total) 4468317SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 4478317SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 44810409Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 44911201Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 467369003 # Number of instructions fetched each cycle (Total) 45011201Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.374204 # Number of branch fetches per cycle 45111201Sandreas.hansson@arm.comsystem.cpu.fetch.rate 1.563965 # Number of inst fetches per cycle 45211201Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 32359971 # Number of cycles decode is idle 45311201Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 118993599 # Number of cycles decode is blocked 45411201Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 286955454 # Number of cycles decode is running 45511201Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 22077159 # Number of cycles decode is unblocking 45611201Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 6982820 # Number of cycles decode is squashing 45711201Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 24051378 # Number of times decode resolved a branch 45811201Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 496211 # Number of times decode detected a branch misprediction 45911201Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 715838012 # Number of instructions handled by decode 46011201Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 30014698 # Number of squashed instructions handled by decode 46111201Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 6982820 # Number of cycles rename is squashing 46211201Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 63444256 # Number of cycles rename is idle 46311201Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 55810223 # Number of cycles rename is blocking 46411201Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 40372652 # count of cycles rename stalled for serializing inst 46511201Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 276569326 # Number of cycles rename is running 46611201Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 24189726 # Number of cycles rename is unblocking 46711201Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 686622974 # Number of instructions processed by rename 46811201Sandreas.hansson@arm.comsystem.cpu.rename.SquashedInsts 13340540 # Number of squashed instructions processed by rename 46911201Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 9445783 # Number of times rename has blocked due to ROB full 47011201Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 2386683 # Number of times rename has blocked due to IQ full 47111201Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 1668073 # Number of times rename has blocked due to LQ full 47211201Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 1901045 # Number of times rename has blocked due to SQ full 47311201Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 831058832 # Number of destination operands rename has renamed 47411201Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 3019300335 # Number of register rename lookups that rename has made 47511201Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 723953090 # Number of integer rename lookups 47610409Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 47710352Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed 47811201Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 176935081 # Number of HB maps that are undone due to squashing 47911201Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1544712 # count of serializing insts renamed 48011201Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 1535132 # count of temporary serializing insts renamed 48111201Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 42423418 # count of insts added to the skid buffer 48211201Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 143529755 # Number of loads inserted to the mem dependence unit. 48311201Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 67982396 # Number of stores inserted to the mem dependence unit. 48411201Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 12868793 # Number of conflicting loads. 48511201Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 11217167 # Number of conflicting stores. 48611201Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 668185878 # Number of instructions added to the IQ (excludes non-spec) 48711201Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2978339 # Number of non-speculative instructions added to the IQ 48811201Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 610253474 # Number of instructions issued 48911201Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 5862945 # Number of squashed instructions issued 49011201Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 123813272 # Number of squashed instructions iterated over during squash; mainly for profiling 49111201Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 319307246 # Number of squashed operands that are examined and possibly removed from graph 49211201Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 707 # Number of squashed non-spec instructions that were removed 49311201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 467369003 # Number of insts issued each cycle 49411201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 1.305721 # Number of insts issued each cycle 49511201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.102066 # Number of insts issued each cycle 4968317SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 49711201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 150209828 32.14% 32.14% # Number of insts issued each cycle 49811201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 101164226 21.65% 53.78% # Number of insts issued each cycle 49911201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 145806231 31.20% 84.98% # Number of insts issued each cycle 50011201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 63278562 13.54% 98.52% # Number of insts issued each cycle 50111201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 6909680 1.48% 100.00% # Number of insts issued each cycle 50211201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 476 0.00% 100.00% # Number of insts issued each cycle 50310409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 50410409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 50510409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 5068317SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5078317SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 50810409Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 50911201Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 467369003 # Number of insts issued each cycle 5108317SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 51111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 71905667 52.96% 52.96% # attempts to use FU when none available 51211201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available 51311201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available 51411201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available 51511201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available 51611201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available 51711201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available 51811201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available 51911201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available 52011201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available 52111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available 52211201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available 52311201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available 52411201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available 52511201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available 52611201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available 52711201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available 52811201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available 52911201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available 53011201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available 53111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available 53211201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available 53311201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available 53411201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available 53511201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available 53611201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available 53711201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available 53811201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available 53911201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available 54011201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 44557603 32.82% 85.78% # attempts to use FU when none available 54111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 19305643 14.22% 100.00% # attempts to use FU when none available 5428317SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 5438317SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 5448317SN/Asystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 54511201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 413150420 67.70% 67.70% # Type of FU issued 54611201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued 54710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued 54810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued 54910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 55010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 55110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 55210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 55310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 55410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 55510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 55610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 55710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 55810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 55910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 56010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 56110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 56210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 56310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 56410409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 56510409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 56610409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 56710409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 56810409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 56910409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 57010409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued 57110409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 57210409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 57310409Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 57411201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 134216313 21.99% 89.75% # Type of FU issued 57511201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 62534943 10.25% 100.00% # Type of FU issued 5768317SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 5778317SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 57811201Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 610253474 # Type of FU issued 57911201Sandreas.hansson@arm.comsystem.cpu.iq.rate 1.303953 # Inst issue rate 58011201Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 135768943 # FU busy when requested 58111201Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.222480 # FU busy rate (busy events/executed inst) 58211201Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 1829507546 # Number of integer instruction queue reads 58311201Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 795005708 # Number of integer instruction queue writes 58411201Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 594983942 # Number of integer instruction queue wakeup accesses 58510409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads 58610409Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes 5878317SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 58811201Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 746022240 # Number of integer alu accesses 58910409Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses 59011201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 7274295 # Number of loads that had data forwarded from stores 5918317SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 59211201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 27644999 # Number of loads squashed 59311201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 25509 # Number of memory responses ignored because the instruction is squashed 59411201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 28969 # Number of memory ordering violations 59511201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 11121919 # Number of stores squashed 5968317SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 5978317SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 59811201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 225058 # Number of loads that were rescheduled 59911201Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 22341 # Number of times an access to memory failed due to the cache being blocked 6008317SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 60111201Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 6982820 # Number of cycles IEW is squashing 60211201Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 22939909 # Number of cycles IEW is blocking 60311201Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 921157 # Number of cycles IEW is unblocking 60411201Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 672651686 # Number of instructions dispatched to IQ 60510409Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 60611201Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 143529755 # Number of dispatched load instructions 60711201Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 67982396 # Number of dispatched store instructions 60811201Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1489797 # Number of dispatched non-speculative instructions 60911201Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 258383 # Number of times the IQ has become full, causing a stall 61011201Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 526747 # Number of times the LSQ has become full, causing a stall 61111201Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 28969 # Number of memory order violations 61211201Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 3822799 # Number of branches that were predicted taken incorrectly 61311201Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 3731713 # Number of branches that were predicted not taken incorrectly 61411201Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 7554512 # Number of branch mispredicts detected at execute 61511201Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 599398028 # Number of executed instructions 61611201Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 129575309 # Number of load instructions executed 61711201Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 10855446 # Number of squashed instructions skipped in execute 6188317SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 61911201Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 1487469 # number of nop insts executed 62011201Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 190532110 # number of memory reference insts executed 62111201Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 131373386 # Number of branches executed 62211201Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 60956801 # Number of stores executed 62311201Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 1.280758 # Inst execution rate 62411201Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 596278477 # cumulative count of insts sent to commit 62511201Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 594983958 # cumulative count of insts written-back 62611201Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 349895185 # num instructions producing a value 62711201Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 570621697 # num instructions consuming a value 62811201Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 1.271326 # insts written-back per cycle 62911201Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.613182 # average fanout of values written-back 63011201Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 110038028 # The number of squashed insts skipped by commit 6319459Ssaidi@eecs.umich.edusystem.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 63211201Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 6956447 # The number of times a branch was mispredicted 63311201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 450252376 # Number of insts commited each cycle 63411201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 1.218638 # Number of insts commited each cycle 63511201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.886273 # Number of insts commited each cycle 6368241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 63711201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 221217275 49.13% 49.13% # Number of insts commited each cycle 63811201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 116327442 25.84% 74.97% # Number of insts commited each cycle 63911201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 43752953 9.72% 84.69% # Number of insts commited each cycle 64011201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 23318372 5.18% 89.86% # Number of insts commited each cycle 64111201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 11527046 2.56% 92.42% # Number of insts commited each cycle 64211201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 7779334 1.73% 94.15% # Number of insts commited each cycle 64311201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 8252081 1.83% 95.98% # Number of insts commited each cycle 64411201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 4233959 0.94% 96.93% # Number of insts commited each cycle 64511201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 13843914 3.07% 100.00% # Number of insts commited each cycle 6468241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 6478241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 6488241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 64911201Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 450252376 # Number of insts commited each cycle 65010812Snilay@cs.wisc.edusystem.cpu.commit.committedInsts 506581608 # Number of instructions committed 65110812Snilay@cs.wisc.edusystem.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed 6528317SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 65310352Sandreas.hansson@arm.comsystem.cpu.commit.refs 172745233 # Number of memory references committed 65410352Sandreas.hansson@arm.comsystem.cpu.commit.loads 115884756 # Number of loads committed 6558317SN/Asystem.cpu.commit.membars 1488542 # Number of memory barriers committed 65610812Snilay@cs.wisc.edusystem.cpu.commit.branches 121548302 # Number of branches committed 6578241SN/Asystem.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 65810352Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 448454354 # Number of committed integer instructions. 6598241SN/Asystem.cpu.commit.function_calls 9757362 # Number of function calls committed. 66010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 66110812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::IntAlu 375610374 68.46% 68.46% # Class of committed instruction 66210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 66310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 66410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 66510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 66610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 66710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 66810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 66910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 67010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 67110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 67210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 67310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 67410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 67510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 67610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 67710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 67810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 67910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 68010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 68110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 68210352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 68310352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 68410352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 68510352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 68610352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 68710352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 68810352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 68910352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 69010352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 69110352Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 69210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 69310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 69410812Snilay@cs.wisc.edusystem.cpu.commit.op_class_0::total 548694829 # Class of committed instruction 69511201Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 13843914 # number cycles where commit BW limit reached 69611201Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 1095134181 # The number of ROB reads 69711201Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 1334612111 # The number of ROB writes 69811201Sandreas.hansson@arm.comsystem.cpu.timesIdled 12504 # Number of times that the entire CPU went into an idle state and unscheduled itself 69911201Sandreas.hansson@arm.comsystem.cpu.idleCycles 633592 # Total number of cycles that the CPU has spent unscheduled due to idling 70010812Snilay@cs.wisc.edusystem.cpu.committedInsts 505237724 # Number of Instructions Simulated 70110812Snilay@cs.wisc.edusystem.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated 70211201Sandreas.hansson@arm.comsystem.cpu.cpi 0.926302 # CPI: Cycles Per Instruction 70311201Sandreas.hansson@arm.comsystem.cpu.cpi_total 0.926302 # CPI: Total CPI of All Threads 70411201Sandreas.hansson@arm.comsystem.cpu.ipc 1.079562 # IPC: Instructions Per Cycle 70511201Sandreas.hansson@arm.comsystem.cpu.ipc_total 1.079562 # IPC: Total IPC of All Threads 70611201Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 611088799 # number of integer regfile reads 70711201Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 328120173 # number of integer regfile writes 7088317SN/Asystem.cpu.fp_regfile_reads 16 # number of floating regfile reads 70911201Sandreas.hansson@arm.comsystem.cpu.cc_regfile_reads 2170182732 # number of cc regfile reads 71011201Sandreas.hansson@arm.comsystem.cpu.cc_regfile_writes 376542810 # number of cc regfile writes 71111201Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 217972310 # number of misc regfile reads 7129459Ssaidi@eecs.umich.edusystem.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 71311201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 2820726 # number of replacements 71411201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.629844 # Cycle average of tags in use 71511201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 169352944 # Total number of references to valid blocks. 71611201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 2821238 # Sample count of references to valid blocks. 71711201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 60.027883 # Average number of references to valid blocks. 71811201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. 71911201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.629844 # Average occupied blocks per requestor 72011201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy 72111201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy 72210628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 72311201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id 72411201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id 72510726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 72610628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 72711201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 356245422 # Number of tag accesses 72811201Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 356245422 # Number of data accesses 72911201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 114648159 # number of ReadReq hits 73011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 114648159 # number of ReadReq hits 73111201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 51724842 # number of WriteReq hits 73211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 51724842 # number of WriteReq hits 73311201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits 73411201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits 73511201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits 73611201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits 73710628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 73810628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 73911201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 166373001 # number of demand (read+write) hits 74011201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 166373001 # number of demand (read+write) hits 74111201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 166375784 # number of overall hits 74211201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 166375784 # number of overall hits 74311201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 4844666 # number of ReadReq misses 74411201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 4844666 # number of ReadReq misses 74511201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 2514464 # number of WriteReq misses 74611201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 2514464 # number of WriteReq misses 74711138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses 74811138Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses 74911201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses 75011201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses 75111201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 7359130 # number of demand (read+write) misses 75211201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 7359130 # number of demand (read+write) misses 75311201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 7359142 # number of overall misses 75411201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 7359142 # number of overall misses 75511201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 57569719500 # number of ReadReq miss cycles 75611201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 57569719500 # number of ReadReq miss cycles 75711201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 18925127941 # number of WriteReq miss cycles 75811201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 18925127941 # number of WriteReq miss cycles 75911201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles 76011201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles 76111201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 76494847441 # number of demand (read+write) miss cycles 76211201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 76494847441 # number of demand (read+write) miss cycles 76311201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 76494847441 # number of overall miss cycles 76411201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 76494847441 # number of overall miss cycles 76511201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 119492825 # number of ReadReq accesses(hits+misses) 76611201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 119492825 # number of ReadReq accesses(hits+misses) 76710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 76810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 76911201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) 77011201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses) 77111201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) 77211201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) 77310628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 77410628Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 77511201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 173732131 # number of demand (read+write) accesses 77611201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 173732131 # number of demand (read+write) accesses 77711201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 173734926 # number of overall (read+write) accesses 77811201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 173734926 # number of overall (read+write) accesses 77911201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040544 # miss rate for ReadReq accesses 78011201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.040544 # miss rate for ReadReq accesses 78111201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046359 # miss rate for WriteReq accesses 78211201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.046359 # miss rate for WriteReq accesses 78311201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses 78411201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses 78511201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses 78611201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses 78711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.042359 # miss rate for demand accesses 78811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.042359 # miss rate for demand accesses 78911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.042358 # miss rate for overall accesses 79011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.042358 # miss rate for overall accesses 79111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11883.114233 # average ReadReq miss latency 79211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 11883.114233 # average ReadReq miss latency 79311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7526.505824 # average WriteReq miss latency 79411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 7526.505824 # average WriteReq miss latency 79511201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency 79611201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency 79711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 10394.550367 # average overall miss latency 79811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 10394.550367 # average overall miss latency 79911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 10394.533417 # average overall miss latency 80011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 10394.533417 # average overall miss latency 80111201Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked 80211201Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 905651 # number of cycles access was blocked 80311201Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 80411201Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 221227 # number of cycles access was blocked 80511201Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked 80611201Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 4.093763 # average number of cycles each access was blocked 80710628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 80810628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 80911201Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 2820726 # number of writebacks 81011201Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 2820726 # number of writebacks 81111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542974 # number of ReadReq MSHR hits 81211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 2542974 # number of ReadReq MSHR hits 81311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994900 # number of WriteReq MSHR hits 81411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1994900 # number of WriteReq MSHR hits 81511201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits 81611201Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits 81711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 4537874 # number of demand (read+write) MSHR hits 81811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 4537874 # number of demand (read+write) MSHR hits 81911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 4537874 # number of overall MSHR hits 82011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 4537874 # number of overall MSHR hits 82111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301692 # number of ReadReq MSHR misses 82211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 2301692 # number of ReadReq MSHR misses 82311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 519564 # number of WriteReq MSHR misses 82411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 519564 # number of WriteReq MSHR misses 82510628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 82610628Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 82711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 2821256 # number of demand (read+write) MSHR misses 82811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 2821256 # number of demand (read+write) MSHR misses 82911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 2821266 # number of overall MSHR misses 83011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 2821266 # number of overall MSHR misses 83111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29568664500 # number of ReadReq MSHR miss cycles 83211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 29568664500 # number of ReadReq MSHR miss cycles 83311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603651495 # number of WriteReq MSHR miss cycles 83411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 4603651495 # number of WriteReq MSHR miss cycles 83511201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 644000 # number of SoftPFReq MSHR miss cycles 83611201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 644000 # number of SoftPFReq MSHR miss cycles 83711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 34172315995 # number of demand (read+write) MSHR miss cycles 83811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 34172315995 # number of demand (read+write) MSHR miss cycles 83911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 34172959995 # number of overall MSHR miss cycles 84011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 34172959995 # number of overall MSHR miss cycles 84111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019262 # mshr miss rate for ReadReq accesses 84211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019262 # mshr miss rate for ReadReq accesses 84311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009579 # mshr miss rate for WriteReq accesses 84411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009579 # mshr miss rate for WriteReq accesses 84511201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses 84611201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses 84711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for demand accesses 84811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.016239 # mshr miss rate for demand accesses 84911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for overall accesses 85011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.016239 # mshr miss rate for overall accesses 85111201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12846.490538 # average ReadReq mshr miss latency 85211201Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12846.490538 # average ReadReq mshr miss latency 85311201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8860.605229 # average WriteReq mshr miss latency 85411201Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8860.605229 # average WriteReq mshr miss latency 85511201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64400 # average SoftPFReq mshr miss latency 85611201Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64400 # average SoftPFReq mshr miss latency 85711201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.447787 # average overall mshr miss latency 85811201Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.447787 # average overall mshr miss latency 85911201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.633121 # average overall mshr miss latency 86011201Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.633121 # average overall mshr miss latency 86110628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 86211201Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 73505 # number of replacements 86311201Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 466.324466 # Cycle average of tags in use 86411201Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 236680067 # Total number of references to valid blocks. 86511201Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 74017 # Sample count of references to valid blocks. 86611201Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 3197.644690 # Average number of references to valid blocks. 86711201Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 115567558500 # Cycle when the warmup percentage was hit. 86811201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 466.324466 # Average occupied blocks per requestor 86911201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.910790 # Average percentage of cache occupancy 87011201Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.910790 # Average percentage of cache occupancy 87110628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 87211201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 87311201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 87411201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id 87511201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id 87611201Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id 87710628Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 87811201Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 473597840 # Number of tag accesses 87911201Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 473597840 # Number of data accesses 88011201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 236680067 # number of ReadReq hits 88111201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 236680067 # number of ReadReq hits 88211201Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 236680067 # number of demand (read+write) hits 88311201Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 236680067 # number of demand (read+write) hits 88411201Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 236680067 # number of overall hits 88511201Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 236680067 # number of overall hits 88611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 81831 # number of ReadReq misses 88711201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 81831 # number of ReadReq misses 88811201Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 81831 # number of demand (read+write) misses 88911201Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 81831 # number of demand (read+write) misses 89011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 81831 # number of overall misses 89111201Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 81831 # number of overall misses 89211201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 1321953198 # number of ReadReq miss cycles 89311201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 1321953198 # number of ReadReq miss cycles 89411201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 1321953198 # number of demand (read+write) miss cycles 89511201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 1321953198 # number of demand (read+write) miss cycles 89611201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 1321953198 # number of overall miss cycles 89711201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 1321953198 # number of overall miss cycles 89811201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 236761898 # number of ReadReq accesses(hits+misses) 89911201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 236761898 # number of ReadReq accesses(hits+misses) 90011201Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 236761898 # number of demand (read+write) accesses 90111201Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 236761898 # number of demand (read+write) accesses 90211201Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 236761898 # number of overall (read+write) accesses 90311201Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 236761898 # number of overall (read+write) accesses 90411201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses 90511201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses 90611201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses 90711201Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses 90811201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses 90911201Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses 91011201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16154.674854 # average ReadReq miss latency 91111201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 16154.674854 # average ReadReq miss latency 91211201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 16154.674854 # average overall miss latency 91311201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 16154.674854 # average overall miss latency 91411201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 16154.674854 # average overall miss latency 91511201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 16154.674854 # average overall miss latency 91611201Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 160057 # number of cycles access was blocked 91711201Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 121 # number of cycles access was blocked 91811201Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 6454 # number of cycles access was blocked 91911201Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 92011201Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 24.799659 # average number of cycles each access was blocked 92111201Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 24.200000 # average number of cycles each access was blocked 92210628Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 92310628Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 92411201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 73505 # number of writebacks 92511201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 73505 # number of writebacks 92611201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 7785 # number of ReadReq MSHR hits 92711201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 7785 # number of ReadReq MSHR hits 92811201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 7785 # number of demand (read+write) MSHR hits 92911201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 7785 # number of demand (read+write) MSHR hits 93011201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 7785 # number of overall MSHR hits 93111201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 7785 # number of overall MSHR hits 93211201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 74046 # number of ReadReq MSHR misses 93311201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 74046 # number of ReadReq MSHR misses 93411201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 74046 # number of demand (read+write) MSHR misses 93511201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 74046 # number of demand (read+write) MSHR misses 93611201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 74046 # number of overall MSHR misses 93711201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 74046 # number of overall MSHR misses 93811201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1096634301 # number of ReadReq MSHR miss cycles 93911201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 1096634301 # number of ReadReq MSHR miss cycles 94011201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 1096634301 # number of demand (read+write) MSHR miss cycles 94111201Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 1096634301 # number of demand (read+write) MSHR miss cycles 94211201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 1096634301 # number of overall MSHR miss cycles 94311201Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 1096634301 # number of overall MSHR miss cycles 94410628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 94510628Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 94610628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 94710628Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 94810628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 94910628Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses 95011201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14810.176120 # average ReadReq mshr miss latency 95111201Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14810.176120 # average ReadReq mshr miss latency 95211201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14810.176120 # average overall mshr miss latency 95311201Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 14810.176120 # average overall mshr miss latency 95411201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14810.176120 # average overall mshr miss latency 95511201Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 14810.176120 # average overall mshr miss latency 95610628Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 95711201Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 8513868 # number of hwpf issued 95811201Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 8515266 # number of prefetch candidates identified 95911201Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 405 # number of redundant prefetches already in prefetch queue 96010628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 96110628Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 96211201Sandreas.hansson@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 743582 # number of prefetches not generated due to page crossing 96311201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 395654 # number of replacements 96411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 15130.862056 # Cycle average of tags in use 96511201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3181572 # Total number of references to valid blocks. 96611201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 411591 # Sample count of references to valid blocks. 96711201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 7.729936 # Average number of references to valid blocks. 96811201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 170394344500 # Cycle when the warmup percentage was hit. 96911201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 13787.674482 # Average occupied blocks per requestor 97011201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 0.001651 # Average occupied blocks per requestor 97111201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1343.185923 # Average occupied blocks per requestor 97211201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.841533 # Average percentage of cache occupancy 97311201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy 97411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.081982 # Average percentage of cache occupancy 97511201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.923515 # Average percentage of cache occupancy 97611201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 1035 # Occupied blocks per task id 97711201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 14902 # Occupied blocks per task id 97811201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 39 # Occupied blocks per task id 97911201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::3 218 # Occupied blocks per task id 98011201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 778 # Occupied blocks per task id 98111201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 98211201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id 98311201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id 98411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 6295 # Occupied blocks per task id 98511201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 3370 # Occupied blocks per task id 98611201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.063171 # Percentage of cache occupancy per task id 98711201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id 98811201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 94911547 # Number of tag accesses 98911201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 94911547 # Number of data accesses 99011201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 2356600 # number of WritebackDirty hits 99111201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 2356600 # number of WritebackDirty hits 99211201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 513929 # number of WritebackClean hits 99311201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 513929 # number of WritebackClean hits 99411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 516839 # number of ReadExReq hits 99511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 516839 # number of ReadExReq hits 99611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 65920 # number of ReadCleanReq hits 99711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 65920 # number of ReadCleanReq hits 99811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 2140480 # number of ReadSharedReq hits 99911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 2140480 # number of ReadSharedReq hits 100011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 65920 # number of demand (read+write) hits 100111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 2657319 # number of demand (read+write) hits 100211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2723239 # number of demand (read+write) hits 100311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 65920 # number of overall hits 100411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 2657319 # number of overall hits 100511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2723239 # number of overall hits 100611201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 28 # number of UpgradeReq misses 100711201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 28 # number of UpgradeReq misses 100811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 5118 # number of ReadExReq misses 100911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 5118 # number of ReadExReq misses 101011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8094 # number of ReadCleanReq misses 101111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 8094 # number of ReadCleanReq misses 101211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 158801 # number of ReadSharedReq misses 101311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 158801 # number of ReadSharedReq misses 101411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 8094 # number of demand (read+write) misses 101511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 163919 # number of demand (read+write) misses 101611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 172013 # number of demand (read+write) misses 101711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 8094 # number of overall misses 101811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 163919 # number of overall misses 101911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 172013 # number of overall misses 102011201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69500 # number of UpgradeReq miss cycles 102111201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 69500 # number of UpgradeReq miss cycles 102211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 486926500 # number of ReadExReq miss cycles 102311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 486926500 # number of ReadExReq miss cycles 102411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 587769500 # number of ReadCleanReq miss cycles 102511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 587769500 # number of ReadCleanReq miss cycles 102611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12091050000 # number of ReadSharedReq miss cycles 102711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 12091050000 # number of ReadSharedReq miss cycles 102811201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 587769500 # number of demand (read+write) miss cycles 102911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 12577976500 # number of demand (read+write) miss cycles 103011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 13165746000 # number of demand (read+write) miss cycles 103111201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 587769500 # number of overall miss cycles 103211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 12577976500 # number of overall miss cycles 103311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 13165746000 # number of overall miss cycles 103411201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 2356600 # number of WritebackDirty accesses(hits+misses) 103511201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 2356600 # number of WritebackDirty accesses(hits+misses) 103611201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 513929 # number of WritebackClean accesses(hits+misses) 103711201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 513929 # number of WritebackClean accesses(hits+misses) 103811201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses) 103911201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) 104011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 521957 # number of ReadExReq accesses(hits+misses) 104111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 521957 # number of ReadExReq accesses(hits+misses) 104211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 74014 # number of ReadCleanReq accesses(hits+misses) 104311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 74014 # number of ReadCleanReq accesses(hits+misses) 104411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299281 # number of ReadSharedReq accesses(hits+misses) 104511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 2299281 # number of ReadSharedReq accesses(hits+misses) 104611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 74014 # number of demand (read+write) accesses 104711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2821238 # number of demand (read+write) accesses 104811201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2895252 # number of demand (read+write) accesses 104911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 74014 # number of overall (read+write) accesses 105011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2821238 # number of overall (read+write) accesses 105111201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2895252 # number of overall (read+write) accesses 105211201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 105311201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 105411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009805 # miss rate for ReadExReq accesses 105511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.009805 # miss rate for ReadExReq accesses 105611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.109358 # miss rate for ReadCleanReq accesses 105711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.109358 # miss rate for ReadCleanReq accesses 105811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.069066 # miss rate for ReadSharedReq accesses 105911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.069066 # miss rate for ReadSharedReq accesses 106011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.109358 # miss rate for demand accesses 106111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.058102 # miss rate for demand accesses 106211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.059412 # miss rate for demand accesses 106311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.109358 # miss rate for overall accesses 106411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.058102 # miss rate for overall accesses 106511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.059412 # miss rate for overall accesses 106611201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2482.142857 # average UpgradeReq miss latency 106711201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2482.142857 # average UpgradeReq miss latency 106811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95139.996092 # average ReadExReq miss latency 106911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 95139.996092 # average ReadExReq miss latency 107011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72617.926859 # average ReadCleanReq miss latency 107111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72617.926859 # average ReadCleanReq miss latency 107211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76139.633881 # average ReadSharedReq miss latency 107311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76139.633881 # average ReadSharedReq miss latency 107411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72617.926859 # average overall miss latency 107511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76732.877214 # average overall miss latency 107611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 76539.249940 # average overall miss latency 107711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72617.926859 # average overall miss latency 107811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76732.877214 # average overall miss latency 107911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 76539.249940 # average overall miss latency 108010628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 108110628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 108210628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 108310628Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 108410628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 108510628Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 108610628Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 108710628Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 108811201Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 292667 # number of writebacks 108911201Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 292667 # number of writebacks 109011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1428 # number of ReadExReq MSHR hits 109111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 1428 # number of ReadExReq MSHR hits 109211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 7 # number of ReadCleanReq MSHR hits 109311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 109411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4193 # number of ReadSharedReq MSHR hits 109511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 4193 # number of ReadSharedReq MSHR hits 109611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits 109711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 5621 # number of demand (read+write) MSHR hits 109811201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 5628 # number of demand (read+write) MSHR hits 109911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits 110011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 5621 # number of overall MSHR hits 110111201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 5628 # number of overall MSHR hits 110211201Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 350851 # number of HardPFReq MSHR misses 110311201Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 350851 # number of HardPFReq MSHR misses 110411201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 28 # number of UpgradeReq MSHR misses 110511201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses 110611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3690 # number of ReadExReq MSHR misses 110711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 3690 # number of ReadExReq MSHR misses 110811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8087 # number of ReadCleanReq MSHR misses 110911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 8087 # number of ReadCleanReq MSHR misses 111011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154608 # number of ReadSharedReq MSHR misses 111111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 154608 # number of ReadSharedReq MSHR misses 111211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 8087 # number of demand (read+write) MSHR misses 111311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 158298 # number of demand (read+write) MSHR misses 111411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 166385 # number of demand (read+write) MSHR misses 111511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 8087 # number of overall MSHR misses 111611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 158298 # number of overall MSHR misses 111711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 350851 # number of overall MSHR misses 111811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 517236 # number of overall MSHR misses 111911201Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18662693863 # number of HardPFReq MSHR miss cycles 112011201Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18662693863 # number of HardPFReq MSHR miss cycles 112111201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 481000 # number of UpgradeReq MSHR miss cycles 112211201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 481000 # number of UpgradeReq MSHR miss cycles 112311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 335947000 # number of ReadExReq MSHR miss cycles 112411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 335947000 # number of ReadExReq MSHR miss cycles 112511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 538896500 # number of ReadCleanReq MSHR miss cycles 112611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 538896500 # number of ReadCleanReq MSHR miss cycles 112711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10864639500 # number of ReadSharedReq MSHR miss cycles 112811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10864639500 # number of ReadSharedReq MSHR miss cycles 112911201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538896500 # number of demand (read+write) MSHR miss cycles 113011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11200586500 # number of demand (read+write) MSHR miss cycles 113111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 11739483000 # number of demand (read+write) MSHR miss cycles 113211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538896500 # number of overall MSHR miss cycles 113311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11200586500 # number of overall MSHR miss cycles 113411201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18662693863 # number of overall MSHR miss cycles 113511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 30402176863 # number of overall MSHR miss cycles 113610628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 113710628Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 113811201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 113911201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 114011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007070 # mshr miss rate for ReadExReq accesses 114111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007070 # mshr miss rate for ReadExReq accesses 114211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for ReadCleanReq accesses 114311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109263 # mshr miss rate for ReadCleanReq accesses 114411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067242 # mshr miss rate for ReadSharedReq accesses 114511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067242 # mshr miss rate for ReadSharedReq accesses 114611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for demand accesses 114711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for demand accesses 114811201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.057468 # mshr miss rate for demand accesses 114911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for overall accesses 115011201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for overall accesses 115110628Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 115211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.178650 # mshr miss rate for overall accesses 115311201Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average HardPFReq mshr miss latency 115411201Sandreas.hansson@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53192.648341 # average HardPFReq mshr miss latency 115511201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17178.571429 # average UpgradeReq mshr miss latency 115611201Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17178.571429 # average UpgradeReq mshr miss latency 115711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91042.547425 # average ReadExReq mshr miss latency 115811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91042.547425 # average ReadExReq mshr miss latency 115911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66637.380982 # average ReadCleanReq mshr miss latency 116011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66637.380982 # average ReadCleanReq mshr miss latency 116111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70272.168969 # average ReadSharedReq mshr miss latency 116211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70272.168969 # average ReadSharedReq mshr miss latency 116311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency 116411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency 116511201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 70556.137873 # average overall mshr miss latency 116611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency 116711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency 116811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average overall mshr miss latency 116911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 58778.153228 # average overall mshr miss latency 117010628Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 117111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 5789543 # Total number of requests made to the snoop filter. 117211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2894272 # Number of requests hitting in the snoop filter with a single holder of the requested data. 117311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 23735 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 117411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 260412 # Total number of snoops made to the snoop filter. 117511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 244232 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 117611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 117711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2373325 # Transaction distribution 117811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 2649267 # Transaction distribution 117911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 513929 # Transaction distribution 118011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 265680 # Transaction distribution 118111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 392283 # Transaction distribution 118211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 118311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution 118411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution 118511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 521957 # Transaction distribution 118611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 521957 # Transaction distribution 118711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 74046 # Transaction distribution 118811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 2299281 # Transaction distribution 118911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220710 # Packet count per connected master and slave (bytes) 119011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440410 # Packet count per connected master and slave (bytes) 119111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 8661120 # Packet count per connected master and slave (bytes) 119211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9386496 # Cumulative packet size per connected master and slave (bytes) 119311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359623424 # Cumulative packet size per connected master and slave (bytes) 119411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 369009920 # Cumulative packet size per connected master and slave (bytes) 119511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 950663 # Total snoops (count) 119611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 3845942 # Request fanout histogram 119711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.078099 # Request fanout histogram 119811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.283574 # Request fanout histogram 119910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 120011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 3561756 92.61% 92.61% # Request fanout histogram 120111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 268006 6.97% 99.58% # Request fanout histogram 120211201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 16180 0.42% 100.00% # Request fanout histogram 120310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 120411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 120510827Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 120611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 3845942 # Request fanout histogram 120711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 5789002505 # Layer occupancy (ticks) 120811201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) 120911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) 121011201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 121111201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 111143345 # Layer occupancy (ticks) 12129729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 121311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 4231890461 # Layer occupancy (ticks) 121410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 121511201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 420198 # Transaction distribution 121611201Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 292667 # Transaction distribution 121711201Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 98618 # Transaction distribution 121811201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 33 # Transaction distribution 121911201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 33 # Transaction distribution 122011201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 3685 # Transaction distribution 122111201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 3685 # Transaction distribution 122211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 420199 # Transaction distribution 122311201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239118 # Packet count per connected master and slave (bytes) 122411201Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1239118 # Packet count per connected master and slave (bytes) 122511201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45859200 # Cumulative packet size per connected master and slave (bytes) 122611201Sandreas.hansson@arm.comsystem.membus.pkt_size::total 45859200 # Cumulative packet size per connected master and slave (bytes) 122710628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 122811201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 815202 # Request fanout histogram 122910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 123010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 123110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 123211201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 815202 100.00% 100.00% # Request fanout histogram 123310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 123410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 123510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 123610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 123711201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 815202 # Request fanout histogram 123811201Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 2212929834 # Layer occupancy (ticks) 123910726Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 124011201Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2242544064 # Layer occupancy (ticks) 124111201Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 1.0 # Layer utilization (%) 12427860SN/A 12437860SN/A---------- End Simulation Statistics ---------- 1244