stats.txt revision 11308
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.234001 # Number of seconds simulated 4sim_ticks 234001297000 # Number of ticks simulated 5final_tick 234001297000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 134504 # Simulator instruction rate (inst/s) 8host_op_rate 145716 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 62295833 # Simulator tick rate (ticks/s) 10host_mem_usage 343376 # Number of bytes of host memory used 11host_seconds 3756.29 # Real time elapsed on the host 12sim_insts 505237724 # Number of instructions simulated 13sim_ops 547350945 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 517504 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10131008 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 16480064 # Number of bytes read from this memory 19system.physmem.bytes_read::total 27128576 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 517504 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 517504 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 18730688 # Number of bytes written to this memory 23system.physmem.bytes_written::total 18730688 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 8086 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 158297 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 257501 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 423884 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 292667 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 292667 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 2211543 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 43294666 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 70427234 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 115933443 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 2211543 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 2211543 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 80045232 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 80045232 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 80045232 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 2211543 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 43294666 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 70427234 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 195978674 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 423884 # Number of read requests accepted 44system.physmem.writeReqs 292667 # Number of write requests accepted 45system.physmem.readBursts 423884 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 292667 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 26972992 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 155584 # Total number of bytes read from write queue 49system.physmem.bytesWritten 18728832 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 27128576 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 18730688 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 2431 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 5 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 98651 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 26584 # Per bank write bursts 56system.physmem.perBankRdBursts::1 25337 # Per bank write bursts 57system.physmem.perBankRdBursts::2 25274 # Per bank write bursts 58system.physmem.perBankRdBursts::3 32197 # Per bank write bursts 59system.physmem.perBankRdBursts::4 27335 # Per bank write bursts 60system.physmem.perBankRdBursts::5 28299 # Per bank write bursts 61system.physmem.perBankRdBursts::6 25126 # Per bank write bursts 62system.physmem.perBankRdBursts::7 24198 # Per bank write bursts 63system.physmem.perBankRdBursts::8 25368 # Per bank write bursts 64system.physmem.perBankRdBursts::9 25926 # Per bank write bursts 65system.physmem.perBankRdBursts::10 25318 # Per bank write bursts 66system.physmem.perBankRdBursts::11 26278 # Per bank write bursts 67system.physmem.perBankRdBursts::12 27572 # Per bank write bursts 68system.physmem.perBankRdBursts::13 25872 # Per bank write bursts 69system.physmem.perBankRdBursts::14 25056 # Per bank write bursts 70system.physmem.perBankRdBursts::15 25713 # Per bank write bursts 71system.physmem.perBankWrBursts::0 18662 # Per bank write bursts 72system.physmem.perBankWrBursts::1 18231 # Per bank write bursts 73system.physmem.perBankWrBursts::2 18003 # Per bank write bursts 74system.physmem.perBankWrBursts::3 17875 # Per bank write bursts 75system.physmem.perBankWrBursts::4 18721 # Per bank write bursts 76system.physmem.perBankWrBursts::5 18310 # Per bank write bursts 77system.physmem.perBankWrBursts::6 17836 # Per bank write bursts 78system.physmem.perBankWrBursts::7 17744 # Per bank write bursts 79system.physmem.perBankWrBursts::8 17983 # Per bank write bursts 80system.physmem.perBankWrBursts::9 17940 # Per bank write bursts 81system.physmem.perBankWrBursts::10 18239 # Per bank write bursts 82system.physmem.perBankWrBursts::11 18938 # Per bank write bursts 83system.physmem.perBankWrBursts::12 18976 # Per bank write bursts 84system.physmem.perBankWrBursts::13 18211 # Per bank write bursts 85system.physmem.perBankWrBursts::14 18390 # Per bank write bursts 86system.physmem.perBankWrBursts::15 18579 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 234001244500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 423884 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 292667 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 323806 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 49376 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 12876 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 8979 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 6144 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 5227 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 4284 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 3341 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 7 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 7238 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 7730 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 12413 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 15049 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 16333 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 16979 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 17275 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 17603 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 17899 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 18115 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 18307 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 18692 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 18718 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 18910 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 19072 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 17647 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 17263 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 17149 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 141 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 19 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 14 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 11 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 11 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 322061 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 141.901068 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 99.764285 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 180.057081 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 202493 62.87% 62.87% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 79759 24.77% 87.64% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 15144 4.70% 92.34% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 7279 2.26% 94.60% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 4961 1.54% 96.14% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 2580 0.80% 96.94% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 1828 0.57% 97.51% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 1538 0.48% 97.99% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 6479 2.01% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 322061 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 17076 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 24.676095 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 143.384257 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-1023 17074 99.99% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 17076 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 17076 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 17.137386 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 17.076722 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::stdev 1.519222 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::16 9254 54.19% 54.19% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::17 359 2.10% 56.30% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::18 5270 30.86% 87.16% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::19 1365 7.99% 95.15% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::20 405 2.37% 97.52% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::21 163 0.95% 98.48% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::22 106 0.62% 99.10% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::23 62 0.36% 99.46% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::24 41 0.24% 99.70% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::25 19 0.11% 99.81% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::26 11 0.06% 99.88% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::29 3 0.02% 99.94% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::30 3 0.02% 99.96% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::32 2 0.01% 99.97% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::39 1 0.01% 99.99% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::43 1 0.01% 100.00% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::total 17076 # Writes before turning the bus around for reads 247system.physmem.totQLat 8693371575 # Total ticks spent queuing 248system.physmem.totMemAccLat 16595615325 # Total ticks spent from burst creation until serviced by the DRAM 249system.physmem.totBusLat 2107265000 # Total ticks spent in databus transfers 250system.physmem.avgQLat 20627.14 # Average queueing delay per DRAM burst 251system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 252system.physmem.avgMemAccLat 39377.14 # Average memory access latency per DRAM burst 253system.physmem.avgRdBW 115.27 # Average DRAM read bandwidth in MiByte/s 254system.physmem.avgWrBW 80.04 # Average achieved write bandwidth in MiByte/s 255system.physmem.avgRdBWSys 115.93 # Average system read bandwidth in MiByte/s 256system.physmem.avgWrBWSys 80.05 # Average system write bandwidth in MiByte/s 257system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 258system.physmem.busUtil 1.53 # Data bus utilization in percentage 259system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads 260system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes 261system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing 262system.physmem.avgWrQLen 21.60 # Average write queue length when enqueuing 263system.physmem.readRowHits 306420 # Number of row buffer hits during reads 264system.physmem.writeRowHits 85606 # Number of row buffer hits during writes 265system.physmem.readRowHitRate 72.71 # Row buffer hit rate for reads 266system.physmem.writeRowHitRate 29.25 # Row buffer hit rate for writes 267system.physmem.avgGap 326566.07 # Average gap between requests 268system.physmem.pageHitRate 54.90 # Row buffer hit rate, read and write combined 269system.physmem_0.actEnergy 1224553680 # Energy for activate commands per rank (pJ) 270system.physmem_0.preEnergy 668159250 # Energy for precharge commands per rank (pJ) 271system.physmem_0.readEnergy 1671883200 # Energy for read commands per rank (pJ) 272system.physmem_0.writeEnergy 942075360 # Energy for write commands per rank (pJ) 273system.physmem_0.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) 274system.physmem_0.actBackEnergy 82043634285 # Energy for active background per rank (pJ) 275system.physmem_0.preBackEnergy 68432158500 # Energy for precharge background per rank (pJ) 276system.physmem_0.totalEnergy 170266217955 # Total energy per rank (pJ) 277system.physmem_0.averagePower 727.632069 # Core power per rank (mW) 278system.physmem_0.memoryStateTime::IDLE 113312610225 # Time in different power states 279system.physmem_0.memoryStateTime::REF 7813780000 # Time in different power states 280system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 281system.physmem_0.memoryStateTime::ACT 112874154775 # Time in different power states 282system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 283system.physmem_1.actEnergy 1210227480 # Energy for activate commands per rank (pJ) 284system.physmem_1.preEnergy 660342375 # Energy for precharge commands per rank (pJ) 285system.physmem_1.readEnergy 1615325400 # Energy for read commands per rank (pJ) 286system.physmem_1.writeEnergy 954218880 # Energy for write commands per rank (pJ) 287system.physmem_1.refreshEnergy 15283753680 # Energy for refresh commands per rank (pJ) 288system.physmem_1.actBackEnergy 79914700530 # Energy for active background per rank (pJ) 289system.physmem_1.preBackEnergy 70299646500 # Energy for precharge background per rank (pJ) 290system.physmem_1.totalEnergy 169938214845 # Total energy per rank (pJ) 291system.physmem_1.averagePower 726.230337 # Core power per rank (mW) 292system.physmem_1.memoryStateTime::IDLE 116426727240 # Time in different power states 293system.physmem_1.memoryStateTime::REF 7813780000 # Time in different power states 294system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 295system.physmem_1.memoryStateTime::ACT 109759940510 # Time in different power states 296system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 297system.cpu.branchPred.lookups 175128597 # Number of BP lookups 298system.cpu.branchPred.condPredicted 131371974 # Number of conditional branches predicted 299system.cpu.branchPred.condIncorrect 7444955 # Number of conditional branches incorrect 300system.cpu.branchPred.BTBLookups 90537565 # Number of BTB lookups 301system.cpu.branchPred.BTBHits 83893856 # Number of BTB hits 302system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 303system.cpu.branchPred.BTBHitPct 92.661931 # BTB Hit Percentage 304system.cpu.branchPred.usedRAS 12111370 # Number of times the RAS was used to get a target. 305system.cpu.branchPred.RASInCorrect 104180 # Number of incorrect RAS predictions. 306system.cpu_clk_domain.clock 500 # Clock period in ticks 307system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 316system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 317system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 318system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 319system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 320system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 321system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 322system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 323system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 324system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 325system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 326system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 327system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 328system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 329system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 330system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 331system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 332system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 333system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 334system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 335system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 336system.cpu.dtb.walker.walks 0 # Table walker walks requested 337system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.inst_hits 0 # ITB inst hits 345system.cpu.dtb.inst_misses 0 # ITB inst misses 346system.cpu.dtb.read_hits 0 # DTB read hits 347system.cpu.dtb.read_misses 0 # DTB read misses 348system.cpu.dtb.write_hits 0 # DTB write hits 349system.cpu.dtb.write_misses 0 # DTB write misses 350system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 351system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 352system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 353system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 354system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 355system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 356system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 357system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 358system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 359system.cpu.dtb.read_accesses 0 # DTB read accesses 360system.cpu.dtb.write_accesses 0 # DTB write accesses 361system.cpu.dtb.inst_accesses 0 # ITB inst accesses 362system.cpu.dtb.hits 0 # DTB hits 363system.cpu.dtb.misses 0 # DTB misses 364system.cpu.dtb.accesses 0 # DTB accesses 365system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 374system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 375system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 376system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 377system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 378system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 379system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 380system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 381system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 382system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 383system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 384system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 385system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 386system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 387system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 388system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 389system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 390system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 391system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 392system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 393system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 394system.cpu.itb.walker.walks 0 # Table walker walks requested 395system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.inst_hits 0 # ITB inst hits 403system.cpu.itb.inst_misses 0 # ITB inst misses 404system.cpu.itb.read_hits 0 # DTB read hits 405system.cpu.itb.read_misses 0 # DTB read misses 406system.cpu.itb.write_hits 0 # DTB write hits 407system.cpu.itb.write_misses 0 # DTB write misses 408system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 409system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 410system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 411system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 412system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 413system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 414system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 415system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 416system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu.itb.read_accesses 0 # DTB read accesses 418system.cpu.itb.write_accesses 0 # DTB write accesses 419system.cpu.itb.inst_accesses 0 # ITB inst accesses 420system.cpu.itb.hits 0 # DTB hits 421system.cpu.itb.misses 0 # DTB misses 422system.cpu.itb.accesses 0 # DTB accesses 423system.cpu.workload.num_syscalls 548 # Number of system calls 424system.cpu.numCycles 468002595 # number of cpu cycles simulated 425system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 426system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 427system.cpu.fetch.icacheStallCycles 7807530 # Number of cycles fetch is stalled on an Icache miss 428system.cpu.fetch.Insts 731939592 # Number of instructions fetch has processed 429system.cpu.fetch.Branches 175128597 # Number of branches that fetch encountered 430system.cpu.fetch.predictedBranches 96005226 # Number of branches that fetch has predicted taken 431system.cpu.fetch.Cycles 452073756 # Number of cycles fetch has run and was not squashing or blocked 432system.cpu.fetch.SquashCycles 14942657 # Number of cycles fetch has spent squashing 433system.cpu.fetch.MiscStallCycles 4553 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 434system.cpu.fetch.PendingTrapStallCycles 179 # Number of stall cycles due to pending traps 435system.cpu.fetch.IcacheWaitRetryStallCycles 11657 # Number of stall cycles due to full MSHR 436system.cpu.fetch.CacheLines 236761982 # Number of cache lines fetched 437system.cpu.fetch.IcacheSquashes 33954 # Number of outstanding Icache misses that were squashed 438system.cpu.fetch.rateDist::samples 467369003 # Number of instructions fetched each cycle (Total) 439system.cpu.fetch.rateDist::mean 1.696062 # Number of instructions fetched each cycle (Total) 440system.cpu.fetch.rateDist::stdev 1.181505 # Number of instructions fetched each cycle (Total) 441system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 442system.cpu.fetch.rateDist::0 95368751 20.41% 20.41% # Number of instructions fetched each cycle (Total) 443system.cpu.fetch.rateDist::1 132719598 28.40% 48.80% # Number of instructions fetched each cycle (Total) 444system.cpu.fetch.rateDist::2 57874720 12.38% 61.19% # Number of instructions fetched each cycle (Total) 445system.cpu.fetch.rateDist::3 181405934 38.81% 100.00% # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::total 467369003 # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.branchRate 0.374204 # Number of branch fetches per cycle 451system.cpu.fetch.rate 1.563965 # Number of inst fetches per cycle 452system.cpu.decode.IdleCycles 32359971 # Number of cycles decode is idle 453system.cpu.decode.BlockedCycles 118993599 # Number of cycles decode is blocked 454system.cpu.decode.RunCycles 286955454 # Number of cycles decode is running 455system.cpu.decode.UnblockCycles 22077159 # Number of cycles decode is unblocking 456system.cpu.decode.SquashCycles 6982820 # Number of cycles decode is squashing 457system.cpu.decode.BranchResolved 24051378 # Number of times decode resolved a branch 458system.cpu.decode.BranchMispred 496211 # Number of times decode detected a branch misprediction 459system.cpu.decode.DecodedInsts 715838012 # Number of instructions handled by decode 460system.cpu.decode.SquashedInsts 30014698 # Number of squashed instructions handled by decode 461system.cpu.rename.SquashCycles 6982820 # Number of cycles rename is squashing 462system.cpu.rename.IdleCycles 63444256 # Number of cycles rename is idle 463system.cpu.rename.BlockCycles 55810223 # Number of cycles rename is blocking 464system.cpu.rename.serializeStallCycles 40372652 # count of cycles rename stalled for serializing inst 465system.cpu.rename.RunCycles 276569326 # Number of cycles rename is running 466system.cpu.rename.UnblockCycles 24189726 # Number of cycles rename is unblocking 467system.cpu.rename.RenamedInsts 686622974 # Number of instructions processed by rename 468system.cpu.rename.SquashedInsts 13340540 # Number of squashed instructions processed by rename 469system.cpu.rename.ROBFullEvents 9445783 # Number of times rename has blocked due to ROB full 470system.cpu.rename.IQFullEvents 2386683 # Number of times rename has blocked due to IQ full 471system.cpu.rename.LQFullEvents 1668073 # Number of times rename has blocked due to LQ full 472system.cpu.rename.SQFullEvents 1901045 # Number of times rename has blocked due to SQ full 473system.cpu.rename.RenamedOperands 831058832 # Number of destination operands rename has renamed 474system.cpu.rename.RenameLookups 3019300335 # Number of register rename lookups that rename has made 475system.cpu.rename.int_rename_lookups 723953090 # Number of integer rename lookups 476system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups 477system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed 478system.cpu.rename.UndoneMaps 176935081 # Number of HB maps that are undone due to squashing 479system.cpu.rename.serializingInsts 1544712 # count of serializing insts renamed 480system.cpu.rename.tempSerializingInsts 1535132 # count of temporary serializing insts renamed 481system.cpu.rename.skidInsts 42423418 # count of insts added to the skid buffer 482system.cpu.memDep0.insertedLoads 143529755 # Number of loads inserted to the mem dependence unit. 483system.cpu.memDep0.insertedStores 67982396 # Number of stores inserted to the mem dependence unit. 484system.cpu.memDep0.conflictingLoads 12868793 # Number of conflicting loads. 485system.cpu.memDep0.conflictingStores 11217167 # Number of conflicting stores. 486system.cpu.iq.iqInstsAdded 668185878 # Number of instructions added to the IQ (excludes non-spec) 487system.cpu.iq.iqNonSpecInstsAdded 2978339 # Number of non-speculative instructions added to the IQ 488system.cpu.iq.iqInstsIssued 610253474 # Number of instructions issued 489system.cpu.iq.iqSquashedInstsIssued 5862945 # Number of squashed instructions issued 490system.cpu.iq.iqSquashedInstsExamined 123813272 # Number of squashed instructions iterated over during squash; mainly for profiling 491system.cpu.iq.iqSquashedOperandsExamined 319307246 # Number of squashed operands that are examined and possibly removed from graph 492system.cpu.iq.iqSquashedNonSpecRemoved 707 # Number of squashed non-spec instructions that were removed 493system.cpu.iq.issued_per_cycle::samples 467369003 # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::mean 1.305721 # Number of insts issued each cycle 495system.cpu.iq.issued_per_cycle::stdev 1.102066 # Number of insts issued each cycle 496system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 497system.cpu.iq.issued_per_cycle::0 150209828 32.14% 32.14% # Number of insts issued each cycle 498system.cpu.iq.issued_per_cycle::1 101164226 21.65% 53.78% # Number of insts issued each cycle 499system.cpu.iq.issued_per_cycle::2 145806231 31.20% 84.98% # Number of insts issued each cycle 500system.cpu.iq.issued_per_cycle::3 63278562 13.54% 98.52% # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::4 6909680 1.48% 100.00% # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::5 476 0.00% 100.00% # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::total 467369003 # Number of insts issued each cycle 510system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 511system.cpu.iq.fu_full::IntAlu 71905667 52.96% 52.96% # attempts to use FU when none available 512system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available 513system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available 514system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available 515system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available 516system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available 517system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available 518system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available 519system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available 525system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available 526system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available 540system.cpu.iq.fu_full::MemRead 44557603 32.82% 85.78% # attempts to use FU when none available 541system.cpu.iq.fu_full::MemWrite 19305643 14.22% 100.00% # attempts to use FU when none available 542system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 543system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 544system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 545system.cpu.iq.FU_type_0::IntAlu 413150420 67.70% 67.70% # Type of FU issued 546system.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued 547system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued 548system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued 549system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 550system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 551system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 552system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 553system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 574system.cpu.iq.FU_type_0::MemRead 134216313 21.99% 89.75% # Type of FU issued 575system.cpu.iq.FU_type_0::MemWrite 62534943 10.25% 100.00% # Type of FU issued 576system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 577system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 578system.cpu.iq.FU_type_0::total 610253474 # Type of FU issued 579system.cpu.iq.rate 1.303953 # Inst issue rate 580system.cpu.iq.fu_busy_cnt 135768943 # FU busy when requested 581system.cpu.iq.fu_busy_rate 0.222480 # FU busy rate (busy events/executed inst) 582system.cpu.iq.int_inst_queue_reads 1829507546 # Number of integer instruction queue reads 583system.cpu.iq.int_inst_queue_writes 795005708 # Number of integer instruction queue writes 584system.cpu.iq.int_inst_queue_wakeup_accesses 594983942 # Number of integer instruction queue wakeup accesses 585system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads 586system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes 587system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 588system.cpu.iq.int_alu_accesses 746022240 # Number of integer alu accesses 589system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses 590system.cpu.iew.lsq.thread0.forwLoads 7274295 # Number of loads that had data forwarded from stores 591system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 592system.cpu.iew.lsq.thread0.squashedLoads 27644999 # Number of loads squashed 593system.cpu.iew.lsq.thread0.ignoredResponses 25509 # Number of memory responses ignored because the instruction is squashed 594system.cpu.iew.lsq.thread0.memOrderViolation 28969 # Number of memory ordering violations 595system.cpu.iew.lsq.thread0.squashedStores 11121919 # Number of stores squashed 596system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 597system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 598system.cpu.iew.lsq.thread0.rescheduledLoads 225058 # Number of loads that were rescheduled 599system.cpu.iew.lsq.thread0.cacheBlocked 22341 # Number of times an access to memory failed due to the cache being blocked 600system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 601system.cpu.iew.iewSquashCycles 6982820 # Number of cycles IEW is squashing 602system.cpu.iew.iewBlockCycles 22939909 # Number of cycles IEW is blocking 603system.cpu.iew.iewUnblockCycles 921157 # Number of cycles IEW is unblocking 604system.cpu.iew.iewDispatchedInsts 672651686 # Number of instructions dispatched to IQ 605system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 606system.cpu.iew.iewDispLoadInsts 143529755 # Number of dispatched load instructions 607system.cpu.iew.iewDispStoreInsts 67982396 # Number of dispatched store instructions 608system.cpu.iew.iewDispNonSpecInsts 1489797 # Number of dispatched non-speculative instructions 609system.cpu.iew.iewIQFullEvents 258383 # Number of times the IQ has become full, causing a stall 610system.cpu.iew.iewLSQFullEvents 526747 # Number of times the LSQ has become full, causing a stall 611system.cpu.iew.memOrderViolationEvents 28969 # Number of memory order violations 612system.cpu.iew.predictedTakenIncorrect 3822799 # Number of branches that were predicted taken incorrectly 613system.cpu.iew.predictedNotTakenIncorrect 3731713 # Number of branches that were predicted not taken incorrectly 614system.cpu.iew.branchMispredicts 7554512 # Number of branch mispredicts detected at execute 615system.cpu.iew.iewExecutedInsts 599398028 # Number of executed instructions 616system.cpu.iew.iewExecLoadInsts 129575309 # Number of load instructions executed 617system.cpu.iew.iewExecSquashedInsts 10855446 # Number of squashed instructions skipped in execute 618system.cpu.iew.exec_swp 0 # number of swp insts executed 619system.cpu.iew.exec_nop 1487469 # number of nop insts executed 620system.cpu.iew.exec_refs 190532110 # number of memory reference insts executed 621system.cpu.iew.exec_branches 131373386 # Number of branches executed 622system.cpu.iew.exec_stores 60956801 # Number of stores executed 623system.cpu.iew.exec_rate 1.280758 # Inst execution rate 624system.cpu.iew.wb_sent 596278477 # cumulative count of insts sent to commit 625system.cpu.iew.wb_count 594983958 # cumulative count of insts written-back 626system.cpu.iew.wb_producers 349895185 # num instructions producing a value 627system.cpu.iew.wb_consumers 570621697 # num instructions consuming a value 628system.cpu.iew.wb_rate 1.271326 # insts written-back per cycle 629system.cpu.iew.wb_fanout 0.613182 # average fanout of values written-back 630system.cpu.commit.commitSquashedInsts 110038028 # The number of squashed insts skipped by commit 631system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards 632system.cpu.commit.branchMispredicts 6956447 # The number of times a branch was mispredicted 633system.cpu.commit.committed_per_cycle::samples 450252376 # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::mean 1.218638 # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::stdev 1.886273 # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::0 221217275 49.13% 49.13% # Number of insts commited each cycle 638system.cpu.commit.committed_per_cycle::1 116327442 25.84% 74.97% # Number of insts commited each cycle 639system.cpu.commit.committed_per_cycle::2 43752953 9.72% 84.69% # Number of insts commited each cycle 640system.cpu.commit.committed_per_cycle::3 23318372 5.18% 89.86% # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::4 11527046 2.56% 92.42% # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::5 7779334 1.73% 94.15% # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::6 8252081 1.83% 95.98% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::7 4233959 0.94% 96.93% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::8 13843914 3.07% 100.00% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::total 450252376 # Number of insts commited each cycle 650system.cpu.commit.committedInsts 506581608 # Number of instructions committed 651system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed 652system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 653system.cpu.commit.refs 172745233 # Number of memory references committed 654system.cpu.commit.loads 115884756 # Number of loads committed 655system.cpu.commit.membars 1488542 # Number of memory barriers committed 656system.cpu.commit.branches 121548302 # Number of branches committed 657system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 658system.cpu.commit.int_insts 448454354 # Number of committed integer instructions. 659system.cpu.commit.function_calls 9757362 # Number of function calls committed. 660system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 661system.cpu.commit.op_class_0::IntAlu 375610374 68.46% 68.46% # Class of committed instruction 662system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 663system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 664system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 665system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 666system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 667system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 668system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 669system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 672system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 673system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 690system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction 691system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction 692system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 693system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 694system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction 695system.cpu.commit.bw_lim_events 13843914 # number cycles where commit BW limit reached 696system.cpu.rob.rob_reads 1095134181 # The number of ROB reads 697system.cpu.rob.rob_writes 1334612111 # The number of ROB writes 698system.cpu.timesIdled 12504 # Number of times that the entire CPU went into an idle state and unscheduled itself 699system.cpu.idleCycles 633592 # Total number of cycles that the CPU has spent unscheduled due to idling 700system.cpu.committedInsts 505237724 # Number of Instructions Simulated 701system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated 702system.cpu.cpi 0.926302 # CPI: Cycles Per Instruction 703system.cpu.cpi_total 0.926302 # CPI: Total CPI of All Threads 704system.cpu.ipc 1.079562 # IPC: Instructions Per Cycle 705system.cpu.ipc_total 1.079562 # IPC: Total IPC of All Threads 706system.cpu.int_regfile_reads 611088799 # number of integer regfile reads 707system.cpu.int_regfile_writes 328120173 # number of integer regfile writes 708system.cpu.fp_regfile_reads 16 # number of floating regfile reads 709system.cpu.cc_regfile_reads 2170182732 # number of cc regfile reads 710system.cpu.cc_regfile_writes 376542810 # number of cc regfile writes 711system.cpu.misc_regfile_reads 217972310 # number of misc regfile reads 712system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes 713system.cpu.dcache.tags.replacements 2820726 # number of replacements 714system.cpu.dcache.tags.tagsinuse 511.629844 # Cycle average of tags in use 715system.cpu.dcache.tags.total_refs 169352944 # Total number of references to valid blocks. 716system.cpu.dcache.tags.sampled_refs 2821238 # Sample count of references to valid blocks. 717system.cpu.dcache.tags.avg_refs 60.027883 # Average number of references to valid blocks. 718system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit. 719system.cpu.dcache.tags.occ_blocks::cpu.data 511.629844 # Average occupied blocks per requestor 720system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy 721system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy 722system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 723system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id 724system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id 725system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 726system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 727system.cpu.dcache.tags.tag_accesses 356245422 # Number of tag accesses 728system.cpu.dcache.tags.data_accesses 356245422 # Number of data accesses 729system.cpu.dcache.ReadReq_hits::cpu.data 114648159 # number of ReadReq hits 730system.cpu.dcache.ReadReq_hits::total 114648159 # number of ReadReq hits 731system.cpu.dcache.WriteReq_hits::cpu.data 51724842 # number of WriteReq hits 732system.cpu.dcache.WriteReq_hits::total 51724842 # number of WriteReq hits 733system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits 734system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits 735system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits 736system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits 737system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 738system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 739system.cpu.dcache.demand_hits::cpu.data 166373001 # number of demand (read+write) hits 740system.cpu.dcache.demand_hits::total 166373001 # number of demand (read+write) hits 741system.cpu.dcache.overall_hits::cpu.data 166375784 # number of overall hits 742system.cpu.dcache.overall_hits::total 166375784 # number of overall hits 743system.cpu.dcache.ReadReq_misses::cpu.data 4844666 # number of ReadReq misses 744system.cpu.dcache.ReadReq_misses::total 4844666 # number of ReadReq misses 745system.cpu.dcache.WriteReq_misses::cpu.data 2514464 # number of WriteReq misses 746system.cpu.dcache.WriteReq_misses::total 2514464 # number of WriteReq misses 747system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses 748system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses 749system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses 750system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses 751system.cpu.dcache.demand_misses::cpu.data 7359130 # number of demand (read+write) misses 752system.cpu.dcache.demand_misses::total 7359130 # number of demand (read+write) misses 753system.cpu.dcache.overall_misses::cpu.data 7359142 # number of overall misses 754system.cpu.dcache.overall_misses::total 7359142 # number of overall misses 755system.cpu.dcache.ReadReq_miss_latency::cpu.data 57569719500 # number of ReadReq miss cycles 756system.cpu.dcache.ReadReq_miss_latency::total 57569719500 # number of ReadReq miss cycles 757system.cpu.dcache.WriteReq_miss_latency::cpu.data 18925127941 # number of WriteReq miss cycles 758system.cpu.dcache.WriteReq_miss_latency::total 18925127941 # number of WriteReq miss cycles 759system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles 760system.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles 761system.cpu.dcache.demand_miss_latency::cpu.data 76494847441 # number of demand (read+write) miss cycles 762system.cpu.dcache.demand_miss_latency::total 76494847441 # number of demand (read+write) miss cycles 763system.cpu.dcache.overall_miss_latency::cpu.data 76494847441 # number of overall miss cycles 764system.cpu.dcache.overall_miss_latency::total 76494847441 # number of overall miss cycles 765system.cpu.dcache.ReadReq_accesses::cpu.data 119492825 # number of ReadReq accesses(hits+misses) 766system.cpu.dcache.ReadReq_accesses::total 119492825 # number of ReadReq accesses(hits+misses) 767system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) 768system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) 769system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses) 770system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses) 771system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) 772system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) 773system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 774system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 775system.cpu.dcache.demand_accesses::cpu.data 173732131 # number of demand (read+write) accesses 776system.cpu.dcache.demand_accesses::total 173732131 # number of demand (read+write) accesses 777system.cpu.dcache.overall_accesses::cpu.data 173734926 # number of overall (read+write) accesses 778system.cpu.dcache.overall_accesses::total 173734926 # number of overall (read+write) accesses 779system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040544 # miss rate for ReadReq accesses 780system.cpu.dcache.ReadReq_miss_rate::total 0.040544 # miss rate for ReadReq accesses 781system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046359 # miss rate for WriteReq accesses 782system.cpu.dcache.WriteReq_miss_rate::total 0.046359 # miss rate for WriteReq accesses 783system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses 784system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses 785system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses 786system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses 787system.cpu.dcache.demand_miss_rate::cpu.data 0.042359 # miss rate for demand accesses 788system.cpu.dcache.demand_miss_rate::total 0.042359 # miss rate for demand accesses 789system.cpu.dcache.overall_miss_rate::cpu.data 0.042358 # miss rate for overall accesses 790system.cpu.dcache.overall_miss_rate::total 0.042358 # miss rate for overall accesses 791system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11883.114233 # average ReadReq miss latency 792system.cpu.dcache.ReadReq_avg_miss_latency::total 11883.114233 # average ReadReq miss latency 793system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7526.505824 # average WriteReq miss latency 794system.cpu.dcache.WriteReq_avg_miss_latency::total 7526.505824 # average WriteReq miss latency 795system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency 796system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency 797system.cpu.dcache.demand_avg_miss_latency::cpu.data 10394.550367 # average overall miss latency 798system.cpu.dcache.demand_avg_miss_latency::total 10394.550367 # average overall miss latency 799system.cpu.dcache.overall_avg_miss_latency::cpu.data 10394.533417 # average overall miss latency 800system.cpu.dcache.overall_avg_miss_latency::total 10394.533417 # average overall miss latency 801system.cpu.dcache.blocked_cycles::no_mshrs 17 # number of cycles access was blocked 802system.cpu.dcache.blocked_cycles::no_targets 905651 # number of cycles access was blocked 803system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 804system.cpu.dcache.blocked::no_targets 221227 # number of cycles access was blocked 805system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.500000 # average number of cycles each access was blocked 806system.cpu.dcache.avg_blocked_cycles::no_targets 4.093763 # average number of cycles each access was blocked 807system.cpu.dcache.fast_writes 0 # number of fast writes performed 808system.cpu.dcache.cache_copies 0 # number of cache copies performed 809system.cpu.dcache.writebacks::writebacks 2820726 # number of writebacks 810system.cpu.dcache.writebacks::total 2820726 # number of writebacks 811system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542974 # number of ReadReq MSHR hits 812system.cpu.dcache.ReadReq_mshr_hits::total 2542974 # number of ReadReq MSHR hits 813system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994900 # number of WriteReq MSHR hits 814system.cpu.dcache.WriteReq_mshr_hits::total 1994900 # number of WriteReq MSHR hits 815system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits 816system.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits 817system.cpu.dcache.demand_mshr_hits::cpu.data 4537874 # number of demand (read+write) MSHR hits 818system.cpu.dcache.demand_mshr_hits::total 4537874 # number of demand (read+write) MSHR hits 819system.cpu.dcache.overall_mshr_hits::cpu.data 4537874 # number of overall MSHR hits 820system.cpu.dcache.overall_mshr_hits::total 4537874 # number of overall MSHR hits 821system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301692 # number of ReadReq MSHR misses 822system.cpu.dcache.ReadReq_mshr_misses::total 2301692 # number of ReadReq MSHR misses 823system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519564 # number of WriteReq MSHR misses 824system.cpu.dcache.WriteReq_mshr_misses::total 519564 # number of WriteReq MSHR misses 825system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses 826system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses 827system.cpu.dcache.demand_mshr_misses::cpu.data 2821256 # number of demand (read+write) MSHR misses 828system.cpu.dcache.demand_mshr_misses::total 2821256 # number of demand (read+write) MSHR misses 829system.cpu.dcache.overall_mshr_misses::cpu.data 2821266 # number of overall MSHR misses 830system.cpu.dcache.overall_mshr_misses::total 2821266 # number of overall MSHR misses 831system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29568664500 # number of ReadReq MSHR miss cycles 832system.cpu.dcache.ReadReq_mshr_miss_latency::total 29568664500 # number of ReadReq MSHR miss cycles 833system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603651495 # number of WriteReq MSHR miss cycles 834system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603651495 # number of WriteReq MSHR miss cycles 835system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 644000 # number of SoftPFReq MSHR miss cycles 836system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 644000 # number of SoftPFReq MSHR miss cycles 837system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34172315995 # number of demand (read+write) MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::total 34172315995 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34172959995 # number of overall MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::total 34172959995 # number of overall MSHR miss cycles 841system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019262 # mshr miss rate for ReadReq accesses 842system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019262 # mshr miss rate for ReadReq accesses 843system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009579 # mshr miss rate for WriteReq accesses 844system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009579 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses 846system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses 847system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for demand accesses 848system.cpu.dcache.demand_mshr_miss_rate::total 0.016239 # mshr miss rate for demand accesses 849system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for overall accesses 850system.cpu.dcache.overall_mshr_miss_rate::total 0.016239 # mshr miss rate for overall accesses 851system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12846.490538 # average ReadReq mshr miss latency 852system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12846.490538 # average ReadReq mshr miss latency 853system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8860.605229 # average WriteReq mshr miss latency 854system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8860.605229 # average WriteReq mshr miss latency 855system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 64400 # average SoftPFReq mshr miss latency 856system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 64400 # average SoftPFReq mshr miss latency 857system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.447787 # average overall mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.447787 # average overall mshr miss latency 859system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.633121 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.633121 # average overall mshr miss latency 861system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 862system.cpu.icache.tags.replacements 73505 # number of replacements 863system.cpu.icache.tags.tagsinuse 466.324466 # Cycle average of tags in use 864system.cpu.icache.tags.total_refs 236680067 # Total number of references to valid blocks. 865system.cpu.icache.tags.sampled_refs 74017 # Sample count of references to valid blocks. 866system.cpu.icache.tags.avg_refs 3197.644690 # Average number of references to valid blocks. 867system.cpu.icache.tags.warmup_cycle 115567558500 # Cycle when the warmup percentage was hit. 868system.cpu.icache.tags.occ_blocks::cpu.inst 466.324466 # Average occupied blocks per requestor 869system.cpu.icache.tags.occ_percent::cpu.inst 0.910790 # Average percentage of cache occupancy 870system.cpu.icache.tags.occ_percent::total 0.910790 # Average percentage of cache occupancy 871system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 872system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 873system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 874system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id 875system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id 876system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id 877system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 878system.cpu.icache.tags.tag_accesses 473597840 # Number of tag accesses 879system.cpu.icache.tags.data_accesses 473597840 # Number of data accesses 880system.cpu.icache.ReadReq_hits::cpu.inst 236680067 # number of ReadReq hits 881system.cpu.icache.ReadReq_hits::total 236680067 # number of ReadReq hits 882system.cpu.icache.demand_hits::cpu.inst 236680067 # number of demand (read+write) hits 883system.cpu.icache.demand_hits::total 236680067 # number of demand (read+write) hits 884system.cpu.icache.overall_hits::cpu.inst 236680067 # number of overall hits 885system.cpu.icache.overall_hits::total 236680067 # number of overall hits 886system.cpu.icache.ReadReq_misses::cpu.inst 81831 # number of ReadReq misses 887system.cpu.icache.ReadReq_misses::total 81831 # number of ReadReq misses 888system.cpu.icache.demand_misses::cpu.inst 81831 # number of demand (read+write) misses 889system.cpu.icache.demand_misses::total 81831 # number of demand (read+write) misses 890system.cpu.icache.overall_misses::cpu.inst 81831 # number of overall misses 891system.cpu.icache.overall_misses::total 81831 # number of overall misses 892system.cpu.icache.ReadReq_miss_latency::cpu.inst 1321953198 # number of ReadReq miss cycles 893system.cpu.icache.ReadReq_miss_latency::total 1321953198 # number of ReadReq miss cycles 894system.cpu.icache.demand_miss_latency::cpu.inst 1321953198 # number of demand (read+write) miss cycles 895system.cpu.icache.demand_miss_latency::total 1321953198 # number of demand (read+write) miss cycles 896system.cpu.icache.overall_miss_latency::cpu.inst 1321953198 # number of overall miss cycles 897system.cpu.icache.overall_miss_latency::total 1321953198 # number of overall miss cycles 898system.cpu.icache.ReadReq_accesses::cpu.inst 236761898 # number of ReadReq accesses(hits+misses) 899system.cpu.icache.ReadReq_accesses::total 236761898 # number of ReadReq accesses(hits+misses) 900system.cpu.icache.demand_accesses::cpu.inst 236761898 # number of demand (read+write) accesses 901system.cpu.icache.demand_accesses::total 236761898 # number of demand (read+write) accesses 902system.cpu.icache.overall_accesses::cpu.inst 236761898 # number of overall (read+write) accesses 903system.cpu.icache.overall_accesses::total 236761898 # number of overall (read+write) accesses 904system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses 905system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses 906system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses 907system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses 908system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses 909system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses 910system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16154.674854 # average ReadReq miss latency 911system.cpu.icache.ReadReq_avg_miss_latency::total 16154.674854 # average ReadReq miss latency 912system.cpu.icache.demand_avg_miss_latency::cpu.inst 16154.674854 # average overall miss latency 913system.cpu.icache.demand_avg_miss_latency::total 16154.674854 # average overall miss latency 914system.cpu.icache.overall_avg_miss_latency::cpu.inst 16154.674854 # average overall miss latency 915system.cpu.icache.overall_avg_miss_latency::total 16154.674854 # average overall miss latency 916system.cpu.icache.blocked_cycles::no_mshrs 160057 # number of cycles access was blocked 917system.cpu.icache.blocked_cycles::no_targets 121 # number of cycles access was blocked 918system.cpu.icache.blocked::no_mshrs 6454 # number of cycles access was blocked 919system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 920system.cpu.icache.avg_blocked_cycles::no_mshrs 24.799659 # average number of cycles each access was blocked 921system.cpu.icache.avg_blocked_cycles::no_targets 24.200000 # average number of cycles each access was blocked 922system.cpu.icache.fast_writes 0 # number of fast writes performed 923system.cpu.icache.cache_copies 0 # number of cache copies performed 924system.cpu.icache.writebacks::writebacks 73505 # number of writebacks 925system.cpu.icache.writebacks::total 73505 # number of writebacks 926system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7785 # number of ReadReq MSHR hits 927system.cpu.icache.ReadReq_mshr_hits::total 7785 # number of ReadReq MSHR hits 928system.cpu.icache.demand_mshr_hits::cpu.inst 7785 # number of demand (read+write) MSHR hits 929system.cpu.icache.demand_mshr_hits::total 7785 # number of demand (read+write) MSHR hits 930system.cpu.icache.overall_mshr_hits::cpu.inst 7785 # number of overall MSHR hits 931system.cpu.icache.overall_mshr_hits::total 7785 # number of overall MSHR hits 932system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74046 # number of ReadReq MSHR misses 933system.cpu.icache.ReadReq_mshr_misses::total 74046 # number of ReadReq MSHR misses 934system.cpu.icache.demand_mshr_misses::cpu.inst 74046 # number of demand (read+write) MSHR misses 935system.cpu.icache.demand_mshr_misses::total 74046 # number of demand (read+write) MSHR misses 936system.cpu.icache.overall_mshr_misses::cpu.inst 74046 # number of overall MSHR misses 937system.cpu.icache.overall_mshr_misses::total 74046 # number of overall MSHR misses 938system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1096634301 # number of ReadReq MSHR miss cycles 939system.cpu.icache.ReadReq_mshr_miss_latency::total 1096634301 # number of ReadReq MSHR miss cycles 940system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1096634301 # number of demand (read+write) MSHR miss cycles 941system.cpu.icache.demand_mshr_miss_latency::total 1096634301 # number of demand (read+write) MSHR miss cycles 942system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1096634301 # number of overall MSHR miss cycles 943system.cpu.icache.overall_mshr_miss_latency::total 1096634301 # number of overall MSHR miss cycles 944system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses 945system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses 946system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses 947system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses 948system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses 949system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses 950system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14810.176120 # average ReadReq mshr miss latency 951system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14810.176120 # average ReadReq mshr miss latency 952system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14810.176120 # average overall mshr miss latency 953system.cpu.icache.demand_avg_mshr_miss_latency::total 14810.176120 # average overall mshr miss latency 954system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14810.176120 # average overall mshr miss latency 955system.cpu.icache.overall_avg_mshr_miss_latency::total 14810.176120 # average overall mshr miss latency 956system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 957system.cpu.l2cache.prefetcher.num_hwpf_issued 8513868 # number of hwpf issued 958system.cpu.l2cache.prefetcher.pfIdentified 8515266 # number of prefetch candidates identified 959system.cpu.l2cache.prefetcher.pfBufferHit 405 # number of redundant prefetches already in prefetch queue 960system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 961system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 962system.cpu.l2cache.prefetcher.pfSpanPage 743582 # number of prefetches not generated due to page crossing 963system.cpu.l2cache.tags.replacements 395654 # number of replacements 964system.cpu.l2cache.tags.tagsinuse 15130.862056 # Cycle average of tags in use 965system.cpu.l2cache.tags.total_refs 3181572 # Total number of references to valid blocks. 966system.cpu.l2cache.tags.sampled_refs 411591 # Sample count of references to valid blocks. 967system.cpu.l2cache.tags.avg_refs 7.729936 # Average number of references to valid blocks. 968system.cpu.l2cache.tags.warmup_cycle 170394344500 # Cycle when the warmup percentage was hit. 969system.cpu.l2cache.tags.occ_blocks::writebacks 13787.674482 # Average occupied blocks per requestor 970system.cpu.l2cache.tags.occ_blocks::cpu.data 0.001651 # Average occupied blocks per requestor 971system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1343.185923 # Average occupied blocks per requestor 972system.cpu.l2cache.tags.occ_percent::writebacks 0.841533 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy 974system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.081982 # Average percentage of cache occupancy 975system.cpu.l2cache.tags.occ_percent::total 0.923515 # Average percentage of cache occupancy 976system.cpu.l2cache.tags.occ_task_id_blocks::1022 1035 # Occupied blocks per task id 977system.cpu.l2cache.tags.occ_task_id_blocks::1024 14902 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1022::2 39 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1022::3 218 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1022::4 778 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::1 211 # Occupied blocks per task id 983system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id 984system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6295 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3370 # Occupied blocks per task id 986system.cpu.l2cache.tags.occ_task_id_percent::1022 0.063171 # Percentage of cache occupancy per task id 987system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id 988system.cpu.l2cache.tags.tag_accesses 94911547 # Number of tag accesses 989system.cpu.l2cache.tags.data_accesses 94911547 # Number of data accesses 990system.cpu.l2cache.WritebackDirty_hits::writebacks 2356600 # number of WritebackDirty hits 991system.cpu.l2cache.WritebackDirty_hits::total 2356600 # number of WritebackDirty hits 992system.cpu.l2cache.WritebackClean_hits::writebacks 513929 # number of WritebackClean hits 993system.cpu.l2cache.WritebackClean_hits::total 513929 # number of WritebackClean hits 994system.cpu.l2cache.ReadExReq_hits::cpu.data 516839 # number of ReadExReq hits 995system.cpu.l2cache.ReadExReq_hits::total 516839 # number of ReadExReq hits 996system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 65920 # number of ReadCleanReq hits 997system.cpu.l2cache.ReadCleanReq_hits::total 65920 # number of ReadCleanReq hits 998system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2140480 # number of ReadSharedReq hits 999system.cpu.l2cache.ReadSharedReq_hits::total 2140480 # number of ReadSharedReq hits 1000system.cpu.l2cache.demand_hits::cpu.inst 65920 # number of demand (read+write) hits 1001system.cpu.l2cache.demand_hits::cpu.data 2657319 # number of demand (read+write) hits 1002system.cpu.l2cache.demand_hits::total 2723239 # number of demand (read+write) hits 1003system.cpu.l2cache.overall_hits::cpu.inst 65920 # number of overall hits 1004system.cpu.l2cache.overall_hits::cpu.data 2657319 # number of overall hits 1005system.cpu.l2cache.overall_hits::total 2723239 # number of overall hits 1006system.cpu.l2cache.UpgradeReq_misses::cpu.data 28 # number of UpgradeReq misses 1007system.cpu.l2cache.UpgradeReq_misses::total 28 # number of UpgradeReq misses 1008system.cpu.l2cache.ReadExReq_misses::cpu.data 5118 # number of ReadExReq misses 1009system.cpu.l2cache.ReadExReq_misses::total 5118 # number of ReadExReq misses 1010system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8094 # number of ReadCleanReq misses 1011system.cpu.l2cache.ReadCleanReq_misses::total 8094 # number of ReadCleanReq misses 1012system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158801 # number of ReadSharedReq misses 1013system.cpu.l2cache.ReadSharedReq_misses::total 158801 # number of ReadSharedReq misses 1014system.cpu.l2cache.demand_misses::cpu.inst 8094 # number of demand (read+write) misses 1015system.cpu.l2cache.demand_misses::cpu.data 163919 # number of demand (read+write) misses 1016system.cpu.l2cache.demand_misses::total 172013 # number of demand (read+write) misses 1017system.cpu.l2cache.overall_misses::cpu.inst 8094 # number of overall misses 1018system.cpu.l2cache.overall_misses::cpu.data 163919 # number of overall misses 1019system.cpu.l2cache.overall_misses::total 172013 # number of overall misses 1020system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69500 # number of UpgradeReq miss cycles 1021system.cpu.l2cache.UpgradeReq_miss_latency::total 69500 # number of UpgradeReq miss cycles 1022system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 486926500 # number of ReadExReq miss cycles 1023system.cpu.l2cache.ReadExReq_miss_latency::total 486926500 # number of ReadExReq miss cycles 1024system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 587769500 # number of ReadCleanReq miss cycles 1025system.cpu.l2cache.ReadCleanReq_miss_latency::total 587769500 # number of ReadCleanReq miss cycles 1026system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12091050000 # number of ReadSharedReq miss cycles 1027system.cpu.l2cache.ReadSharedReq_miss_latency::total 12091050000 # number of ReadSharedReq miss cycles 1028system.cpu.l2cache.demand_miss_latency::cpu.inst 587769500 # number of demand (read+write) miss cycles 1029system.cpu.l2cache.demand_miss_latency::cpu.data 12577976500 # number of demand (read+write) miss cycles 1030system.cpu.l2cache.demand_miss_latency::total 13165746000 # number of demand (read+write) miss cycles 1031system.cpu.l2cache.overall_miss_latency::cpu.inst 587769500 # number of overall miss cycles 1032system.cpu.l2cache.overall_miss_latency::cpu.data 12577976500 # number of overall miss cycles 1033system.cpu.l2cache.overall_miss_latency::total 13165746000 # number of overall miss cycles 1034system.cpu.l2cache.WritebackDirty_accesses::writebacks 2356600 # number of WritebackDirty accesses(hits+misses) 1035system.cpu.l2cache.WritebackDirty_accesses::total 2356600 # number of WritebackDirty accesses(hits+misses) 1036system.cpu.l2cache.WritebackClean_accesses::writebacks 513929 # number of WritebackClean accesses(hits+misses) 1037system.cpu.l2cache.WritebackClean_accesses::total 513929 # number of WritebackClean accesses(hits+misses) 1038system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses) 1039system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) 1040system.cpu.l2cache.ReadExReq_accesses::cpu.data 521957 # number of ReadExReq accesses(hits+misses) 1041system.cpu.l2cache.ReadExReq_accesses::total 521957 # number of ReadExReq accesses(hits+misses) 1042system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 74014 # number of ReadCleanReq accesses(hits+misses) 1043system.cpu.l2cache.ReadCleanReq_accesses::total 74014 # number of ReadCleanReq accesses(hits+misses) 1044system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299281 # number of ReadSharedReq accesses(hits+misses) 1045system.cpu.l2cache.ReadSharedReq_accesses::total 2299281 # number of ReadSharedReq accesses(hits+misses) 1046system.cpu.l2cache.demand_accesses::cpu.inst 74014 # number of demand (read+write) accesses 1047system.cpu.l2cache.demand_accesses::cpu.data 2821238 # number of demand (read+write) accesses 1048system.cpu.l2cache.demand_accesses::total 2895252 # number of demand (read+write) accesses 1049system.cpu.l2cache.overall_accesses::cpu.inst 74014 # number of overall (read+write) accesses 1050system.cpu.l2cache.overall_accesses::cpu.data 2821238 # number of overall (read+write) accesses 1051system.cpu.l2cache.overall_accesses::total 2895252 # number of overall (read+write) accesses 1052system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1053system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1054system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009805 # miss rate for ReadExReq accesses 1055system.cpu.l2cache.ReadExReq_miss_rate::total 0.009805 # miss rate for ReadExReq accesses 1056system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.109358 # miss rate for ReadCleanReq accesses 1057system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.109358 # miss rate for ReadCleanReq accesses 1058system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.069066 # miss rate for ReadSharedReq accesses 1059system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.069066 # miss rate for ReadSharedReq accesses 1060system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109358 # miss rate for demand accesses 1061system.cpu.l2cache.demand_miss_rate::cpu.data 0.058102 # miss rate for demand accesses 1062system.cpu.l2cache.demand_miss_rate::total 0.059412 # miss rate for demand accesses 1063system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109358 # miss rate for overall accesses 1064system.cpu.l2cache.overall_miss_rate::cpu.data 0.058102 # miss rate for overall accesses 1065system.cpu.l2cache.overall_miss_rate::total 0.059412 # miss rate for overall accesses 1066system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2482.142857 # average UpgradeReq miss latency 1067system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2482.142857 # average UpgradeReq miss latency 1068system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95139.996092 # average ReadExReq miss latency 1069system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95139.996092 # average ReadExReq miss latency 1070system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72617.926859 # average ReadCleanReq miss latency 1071system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72617.926859 # average ReadCleanReq miss latency 1072system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76139.633881 # average ReadSharedReq miss latency 1073system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76139.633881 # average ReadSharedReq miss latency 1074system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72617.926859 # average overall miss latency 1075system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76732.877214 # average overall miss latency 1076system.cpu.l2cache.demand_avg_miss_latency::total 76539.249940 # average overall miss latency 1077system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72617.926859 # average overall miss latency 1078system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76732.877214 # average overall miss latency 1079system.cpu.l2cache.overall_avg_miss_latency::total 76539.249940 # average overall miss latency 1080system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1081system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1082system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1083system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1084system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1085system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1086system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1087system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1088system.cpu.l2cache.writebacks::writebacks 292667 # number of writebacks 1089system.cpu.l2cache.writebacks::total 292667 # number of writebacks 1090system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1428 # number of ReadExReq MSHR hits 1091system.cpu.l2cache.ReadExReq_mshr_hits::total 1428 # number of ReadExReq MSHR hits 1092system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 7 # number of ReadCleanReq MSHR hits 1093system.cpu.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 1094system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4193 # number of ReadSharedReq MSHR hits 1095system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4193 # number of ReadSharedReq MSHR hits 1096system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits 1097system.cpu.l2cache.demand_mshr_hits::cpu.data 5621 # number of demand (read+write) MSHR hits 1098system.cpu.l2cache.demand_mshr_hits::total 5628 # number of demand (read+write) MSHR hits 1099system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits 1100system.cpu.l2cache.overall_mshr_hits::cpu.data 5621 # number of overall MSHR hits 1101system.cpu.l2cache.overall_mshr_hits::total 5628 # number of overall MSHR hits 1102system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 350851 # number of HardPFReq MSHR misses 1103system.cpu.l2cache.HardPFReq_mshr_misses::total 350851 # number of HardPFReq MSHR misses 1104system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 28 # number of UpgradeReq MSHR misses 1105system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses 1106system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3690 # number of ReadExReq MSHR misses 1107system.cpu.l2cache.ReadExReq_mshr_misses::total 3690 # number of ReadExReq MSHR misses 1108system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8087 # number of ReadCleanReq MSHR misses 1109system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8087 # number of ReadCleanReq MSHR misses 1110system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154608 # number of ReadSharedReq MSHR misses 1111system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154608 # number of ReadSharedReq MSHR misses 1112system.cpu.l2cache.demand_mshr_misses::cpu.inst 8087 # number of demand (read+write) MSHR misses 1113system.cpu.l2cache.demand_mshr_misses::cpu.data 158298 # number of demand (read+write) MSHR misses 1114system.cpu.l2cache.demand_mshr_misses::total 166385 # number of demand (read+write) MSHR misses 1115system.cpu.l2cache.overall_mshr_misses::cpu.inst 8087 # number of overall MSHR misses 1116system.cpu.l2cache.overall_mshr_misses::cpu.data 158298 # number of overall MSHR misses 1117system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 350851 # number of overall MSHR misses 1118system.cpu.l2cache.overall_mshr_misses::total 517236 # number of overall MSHR misses 1119system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18662693863 # number of HardPFReq MSHR miss cycles 1120system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18662693863 # number of HardPFReq MSHR miss cycles 1121system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 481000 # number of UpgradeReq MSHR miss cycles 1122system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 481000 # number of UpgradeReq MSHR miss cycles 1123system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 335947000 # number of ReadExReq MSHR miss cycles 1124system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 335947000 # number of ReadExReq MSHR miss cycles 1125system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 538896500 # number of ReadCleanReq MSHR miss cycles 1126system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 538896500 # number of ReadCleanReq MSHR miss cycles 1127system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10864639500 # number of ReadSharedReq MSHR miss cycles 1128system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10864639500 # number of ReadSharedReq MSHR miss cycles 1129system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538896500 # number of demand (read+write) MSHR miss cycles 1130system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11200586500 # number of demand (read+write) MSHR miss cycles 1131system.cpu.l2cache.demand_mshr_miss_latency::total 11739483000 # number of demand (read+write) MSHR miss cycles 1132system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538896500 # number of overall MSHR miss cycles 1133system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11200586500 # number of overall MSHR miss cycles 1134system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18662693863 # number of overall MSHR miss cycles 1135system.cpu.l2cache.overall_mshr_miss_latency::total 30402176863 # number of overall MSHR miss cycles 1136system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1137system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1138system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1139system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1140system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007070 # mshr miss rate for ReadExReq accesses 1141system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007070 # mshr miss rate for ReadExReq accesses 1142system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for ReadCleanReq accesses 1143system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109263 # mshr miss rate for ReadCleanReq accesses 1144system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067242 # mshr miss rate for ReadSharedReq accesses 1145system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067242 # mshr miss rate for ReadSharedReq accesses 1146system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for demand accesses 1147system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for demand accesses 1148system.cpu.l2cache.demand_mshr_miss_rate::total 0.057468 # mshr miss rate for demand accesses 1149system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109263 # mshr miss rate for overall accesses 1150system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056109 # mshr miss rate for overall accesses 1151system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1152system.cpu.l2cache.overall_mshr_miss_rate::total 0.178650 # mshr miss rate for overall accesses 1153system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average HardPFReq mshr miss latency 1154system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53192.648341 # average HardPFReq mshr miss latency 1155system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17178.571429 # average UpgradeReq mshr miss latency 1156system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17178.571429 # average UpgradeReq mshr miss latency 1157system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91042.547425 # average ReadExReq mshr miss latency 1158system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91042.547425 # average ReadExReq mshr miss latency 1159system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66637.380982 # average ReadCleanReq mshr miss latency 1160system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66637.380982 # average ReadCleanReq mshr miss latency 1161system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70272.168969 # average ReadSharedReq mshr miss latency 1162system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70272.168969 # average ReadSharedReq mshr miss latency 1163system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency 1164system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency 1165system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70556.137873 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66637.380982 # average overall mshr miss latency 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70756.336151 # average overall mshr miss latency 1168system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53192.648341 # average overall mshr miss latency 1169system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58778.153228 # average overall mshr miss latency 1170system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1171system.cpu.toL2Bus.snoop_filter.tot_requests 5789543 # Total number of requests made to the snoop filter. 1172system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894272 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1173system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23735 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1174system.cpu.toL2Bus.snoop_filter.tot_snoops 260412 # Total number of snoops made to the snoop filter. 1175system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244232 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1176system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16180 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1177system.cpu.toL2Bus.trans_dist::ReadResp 2373325 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::WritebackDirty 2649267 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::WritebackClean 513929 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::CleanEvict 265680 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::HardPFReq 392283 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution 1185system.cpu.toL2Bus.trans_dist::ReadExReq 521957 # Transaction distribution 1186system.cpu.toL2Bus.trans_dist::ReadExResp 521957 # Transaction distribution 1187system.cpu.toL2Bus.trans_dist::ReadCleanReq 74046 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299281 # Transaction distribution 1189system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220710 # Packet count per connected master and slave (bytes) 1190system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8440410 # Packet count per connected master and slave (bytes) 1191system.cpu.toL2Bus.pkt_count::total 8661120 # Packet count per connected master and slave (bytes) 1192system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9386496 # Cumulative packet size per connected master and slave (bytes) 1193system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 359623424 # Cumulative packet size per connected master and slave (bytes) 1194system.cpu.toL2Bus.pkt_size::total 369009920 # Cumulative packet size per connected master and slave (bytes) 1195system.cpu.toL2Bus.snoops 950663 # Total snoops (count) 1196system.cpu.toL2Bus.snoop_fanout::samples 3845942 # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::mean 0.078099 # Request fanout histogram 1198system.cpu.toL2Bus.snoop_fanout::stdev 0.283574 # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1200system.cpu.toL2Bus.snoop_fanout::0 3561756 92.61% 92.61% # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::1 268006 6.97% 99.58% # Request fanout histogram 1202system.cpu.toL2Bus.snoop_fanout::2 16180 0.42% 100.00% # Request fanout histogram 1203system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1204system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1205system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1206system.cpu.toL2Bus.snoop_fanout::total 3845942 # Request fanout histogram 1207system.cpu.toL2Bus.reqLayer0.occupancy 5789002505 # Layer occupancy (ticks) 1208system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) 1209system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) 1210system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1211system.cpu.toL2Bus.respLayer0.occupancy 111143345 # Layer occupancy (ticks) 1212system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1213system.cpu.toL2Bus.respLayer1.occupancy 4231890461 # Layer occupancy (ticks) 1214system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) 1215system.membus.trans_dist::ReadResp 420198 # Transaction distribution 1216system.membus.trans_dist::WritebackDirty 292667 # Transaction distribution 1217system.membus.trans_dist::CleanEvict 98618 # Transaction distribution 1218system.membus.trans_dist::UpgradeReq 33 # Transaction distribution 1219system.membus.trans_dist::UpgradeResp 33 # Transaction distribution 1220system.membus.trans_dist::ReadExReq 3685 # Transaction distribution 1221system.membus.trans_dist::ReadExResp 3685 # Transaction distribution 1222system.membus.trans_dist::ReadSharedReq 420199 # Transaction distribution 1223system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239118 # Packet count per connected master and slave (bytes) 1224system.membus.pkt_count::total 1239118 # Packet count per connected master and slave (bytes) 1225system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45859200 # Cumulative packet size per connected master and slave (bytes) 1226system.membus.pkt_size::total 45859200 # Cumulative packet size per connected master and slave (bytes) 1227system.membus.snoops 0 # Total snoops (count) 1228system.membus.snoop_fanout::samples 815202 # Request fanout histogram 1229system.membus.snoop_fanout::mean 0 # Request fanout histogram 1230system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1231system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1232system.membus.snoop_fanout::0 815202 100.00% 100.00% # Request fanout histogram 1233system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1234system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1235system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1236system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1237system.membus.snoop_fanout::total 815202 # Request fanout histogram 1238system.membus.reqLayer0.occupancy 2212929834 # Layer occupancy (ticks) 1239system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) 1240system.membus.respLayer1.occupancy 2242544064 # Layer occupancy (ticks) 1241system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 1242 1243---------- End Simulation Statistics ---------- 1244