stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.058199 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 58199030500 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 101249 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 101754 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 65047265 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 487144 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 894.72 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 90589799 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 91041030 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 1057024 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 11200 # Number of bytes written to this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 16516 # Number of read requests responded to by this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory 2911507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 175 # Number of write requests responded to by this memory 3011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s) 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s) 3311507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s) 3411507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s) 3511507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s) 3611507SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s) 3711507SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s) 3811507SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s) 3911507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s) 4011507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s) 4111507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s) 4211507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s) 4311507SCurtis.Dunham@arm.comsystem.physmem.readReqs 16517 # Number of read requests accepted 4411507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 175 # Number of write requests accepted 4511507SCurtis.Dunham@arm.comsystem.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue 4611507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue 4711507SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM 4811507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue 4911507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 9216 # Total number of bytes written to DRAM 5011507SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side 5111507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side 5211507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue 5311507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 5411507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 1166 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 920 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 953 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 1031 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 1061 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 1122 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 1094 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 1089 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 1025 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 962 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 933 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 900 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 903 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 900 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 1411 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 910 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 2 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 6 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 1 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 3 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 16 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 40 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 7 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 2 # Per bank write bursts 8011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 8111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 2 # Per bank write bursts 8211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 2 # Per bank write bursts 8311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 2 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 17 # Per bank write bursts 8511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 37 # Per bank write bursts 8611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 7 # Per bank write bursts 8711507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8811507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8911507SCurtis.Dunham@arm.comsystem.physmem.totGap 58199022000 # Total gap between requests 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 16517 # Read request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 10011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 10111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 10211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 175 # Write request sizes (log2) 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 20011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation 20111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation 20211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation 20311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation 20411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation 20511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation 20611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation 20711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation 20811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation 20911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation 21011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation 21111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation 21211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation 21311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation 21411507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes 21511507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes 21811507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes 21911507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes 22011507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes 22111507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads 22211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads 22311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads 22411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads 22511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads 22611507SCurtis.Dunham@arm.comsystem.physmem.totQLat 175730624 # Total ticks spent queuing 22711507SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM 22811507SCurtis.Dunham@arm.comsystem.physmem.totBusLat 81900000 # Total ticks spent in databus transfers 22911507SCurtis.Dunham@arm.comsystem.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst 23011507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 23111507SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst 23211507SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s 23311507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s 23411507SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s 23511507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s 23611507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 23711507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.14 # Data bus utilization in percentage 23811507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads 23911507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 24011507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 24111507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing 24211507SCurtis.Dunham@arm.comsystem.physmem.readRowHits 14651 # Number of row buffer hits during reads 24311507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 51 # Number of row buffer hits during writes 24411507SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads 24511507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes 24611507SCurtis.Dunham@arm.comsystem.physmem.avgGap 3486641.62 # Average gap between requests 24711507SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined 24811507SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) 24911507SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) 25011507SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ) 25111507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ) 25211507SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) 25311507SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ) 25411507SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ) 25511507SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ) 25611507SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 672.381118 # Core power per rank (mW) 25711507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states 25811507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states 25911507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 26011507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states 26111507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 26211507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ) 26311507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ) 26411507SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ) 26511507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ) 26611507SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) 26711507SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ) 26811507SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) 26911507SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) 27011507SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 671.780705 # Core power per rank (mW) 27111507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states 27211507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states 27311507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 27411507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states 27511507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 27611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 28233538 # Number of BP lookups 27711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted 27811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect 27911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups 28011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 11747655 # Number of BTB hits 28111507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 28211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage 28311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. 28411507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. 28511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. 28611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. 28711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. 28811507SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. 28911507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 29011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 29111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 29311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 29411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 29511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 29611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 29711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 29811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 29911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 30011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 30111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 30211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 30311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 30411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 30511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 30711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 30811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 30911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 31011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 31111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 31211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 31911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 32011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 32211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 32311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 32411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 32511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 32611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 32711507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 32811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 32911507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 33011507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 33111507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 33211507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 33311507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 33411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 33511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 33611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 33711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 33811507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 33911507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 34011507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 34111507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34211507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 34811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 35511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 35611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 35711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 35811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 35911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 36111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 36211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 36311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 36411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 36511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 36611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 36711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 36811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 36911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 37211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 37711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 37811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 38511507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 38611507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 38711507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 38811507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 38911507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 39011507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 39111507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 39211507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39311507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 39511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 39611507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 39711507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 39811507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 39911507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 40111507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 40611507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 442 # Number of system calls 40711507SCurtis.Dunham@arm.comsystem.cpu.numCycles 116398062 # number of cpu cycles simulated 40811507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 40911507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41011507SCurtis.Dunham@arm.comsystem.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss 41111507SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed 41211507SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered 41311507SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken 41411507SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked 41511507SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing 41611507SCurtis.Dunham@arm.comsystem.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 41711507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR 41811507SCurtis.Dunham@arm.comsystem.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched 41911507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed 42011507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total) 42111507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total) 42211507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total) 42311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 42411507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total) 42511507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total) 42611507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total) 42711507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total) 42811507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 42911507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 43011507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 43111507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total) 43211507SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle 43311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle 43411507SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle 43511507SCurtis.Dunham@arm.comsystem.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked 43611507SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 33013656 # Number of cycles decode is running 43711507SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking 43811507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing 43911507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch 44011507SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction 44111507SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode 44211507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode 44311507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing 44411507SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle 44511507SCurtis.Dunham@arm.comsystem.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking 44611507SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst 44711507SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 35410349 # Number of cycles rename is running 44811507SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking 44911507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename 45011507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename 45111507SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full 45211507SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full 45311507SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full 45411507SCurtis.Dunham@arm.comsystem.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full 45511507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed 45611507SCurtis.Dunham@arm.comsystem.cpu.rename.RenameLookups 483153288 # Number of register rename lookups that rename has made 45711507SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups 45811507SCurtis.Dunham@arm.comsystem.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups 45911507SCurtis.Dunham@arm.comsystem.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed 46011507SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing 46111507SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 4409 # count of serializing insts renamed 46211507SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed 46311507SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer 46411507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit. 46511507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit. 46611507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads. 46711507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores. 46811507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec) 46911507SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ 47011507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued 47111507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued 47211507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling 47311507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 41667299 # Number of squashed operands that are examined and possibly removed from graph 47411507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed 47511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle 47611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle 47711507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle 47811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 47911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle 48011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle 48111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle 48211507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle 48311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle 48411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle 48511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 48611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 48711507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 48811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 48911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 49011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 49111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle 49211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 49311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available 49411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available 49511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available 49611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available 49711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available 49811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available 49911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available 50011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available 50111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available 50211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available 50311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available 50411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available 50511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available 50611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available 50711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available 50811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available 50911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available 51011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available 51111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available 51211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available 51311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available 51411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available 51511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available 51611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available 51711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available 51811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available 51911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available 52011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available 52111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available 52211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available 52311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available 52411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 52511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 52611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 52711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued 52811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued 52911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued 53011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued 53111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued 53211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued 53311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued 53411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued 53511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued 53611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued 53711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued 53811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued 53911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued 54011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued 54111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued 54211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued 54311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued 54411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued 54511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued 54611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued 54711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued 54811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued 54911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued 55011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued 55111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued 55211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued 55311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued 55411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued 55511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued 55611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued 55711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued 55811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 55911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 56011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::total 101366848 # Type of FU issued 56111507SCurtis.Dunham@arm.comsystem.cpu.iq.rate 0.870864 # Inst issue rate 56211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested 56311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst) 56411507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads 56511507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes 56611507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses 56711507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads 56811507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes 56911507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses 57011507SCurtis.Dunham@arm.comsystem.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses 57111507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses 57211507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores 57311507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 57411507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed 57511507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed 57611507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations 57711507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed 57811507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 57911507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 58011507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled 58111507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked 58211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 58311507SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing 58411507SCurtis.Dunham@arm.comsystem.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking 58511507SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking 58611507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ 58711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 58811507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions 58911507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions 59011507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions 59111507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall 59211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall 59311507SCurtis.Dunham@arm.comsystem.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations 59411507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly 59511507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly 59611507SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute 59711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions 59811507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed 59911507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute 60011507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 60111507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 12822 # number of nop insts executed 60211507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 28718921 # number of memory reference insts executed 60311507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 20621209 # Number of branches executed 60411507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 4915850 # Number of stores executed 60511507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_rate 0.860065 # Inst execution rate 60611507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit 60711507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_count 99608605 # cumulative count of insts written-back 60811507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 59691637 # num instructions producing a value 60911507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 95527463 # num instructions consuming a value 61011507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_rate 0.855758 # insts written-back per cycle 61111507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back 61211507SCurtis.Dunham@arm.comsystem.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit 61311507SCurtis.Dunham@arm.comsystem.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 61411507SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted 61511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle 61611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle 61711507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle 61811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 61911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle 62011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle 62111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle 62211507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle 62311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle 62411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle 62511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle 62611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle 62711507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle 62811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 62911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 63011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 63111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle 63211507SCurtis.Dunham@arm.comsystem.cpu.commit.committedInsts 90602408 # Number of instructions committed 63311507SCurtis.Dunham@arm.comsystem.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed 63411507SCurtis.Dunham@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 63511507SCurtis.Dunham@arm.comsystem.cpu.commit.refs 27220755 # Number of memory references committed 63611507SCurtis.Dunham@arm.comsystem.cpu.commit.loads 22475911 # Number of loads committed 63711507SCurtis.Dunham@arm.comsystem.cpu.commit.membars 3888 # Number of memory barriers committed 63811507SCurtis.Dunham@arm.comsystem.cpu.commit.branches 18732305 # Number of branches committed 63911507SCurtis.Dunham@arm.comsystem.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 64011507SCurtis.Dunham@arm.comsystem.cpu.commit.int_insts 72326352 # Number of committed integer instructions. 64111507SCurtis.Dunham@arm.comsystem.cpu.commit.function_calls 56148 # Number of function calls committed. 64211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 64311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction 64411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 64511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 64611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 64711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 64811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 64911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 65011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 65111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 65211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 65311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 65411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 65511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 65611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 65711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 65811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 65911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 66011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 66111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 66211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 66311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 66411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 66511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 66611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 66711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 66811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 66911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 67011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 67111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 67211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 67311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 67411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 67511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 67611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::total 91053639 # Class of committed instruction 67711507SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached 67811507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_reads 217947492 # The number of ROB reads 67911507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_writes 219521309 # The number of ROB writes 68011507SCurtis.Dunham@arm.comsystem.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself 68111507SCurtis.Dunham@arm.comsystem.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling 68211507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 90589799 # Number of Instructions Simulated 68311507SCurtis.Dunham@arm.comsystem.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated 68411507SCurtis.Dunham@arm.comsystem.cpu.cpi 1.284891 # CPI: Cycles Per Instruction 68511507SCurtis.Dunham@arm.comsystem.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads 68611507SCurtis.Dunham@arm.comsystem.cpu.ipc 0.778276 # IPC: Instructions Per Cycle 68711507SCurtis.Dunham@arm.comsystem.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads 68811507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_reads 108097873 # number of integer regfile reads 68911507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 58692304 # number of integer regfile writes 69011507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_reads 59 # number of floating regfile reads 69111507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_writes 96 # number of floating regfile writes 69211507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_reads 369004699 # number of cc regfile reads 69311507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_writes 58686555 # number of cc regfile writes 69411507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_reads 28410220 # number of misc regfile reads 69511507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_writes 7784 # number of misc regfile writes 69611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 5470634 # number of replacements 69711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use 69811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. 69911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. 70011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. 70111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. 70211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor 70311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy 70411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy 70511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 70611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id 70711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id 70811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 70911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses 71011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses 71111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits 71211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits 71311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits 71411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits 71511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 71611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 71711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits 71811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits 71911507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 72011507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 72111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits 72211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits 72311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits 72411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 18241600 # number of overall hits 72511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses 72611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses 72711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses 72811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses 72911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 73011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 73111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses 73211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses 73311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses 73411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses 73511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses 73611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 9968505 # number of overall misses 73711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles 73811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles 73911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles 74011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles 74111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles 74211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles 74311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles 74411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles 74511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles 74611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles 74711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses) 74811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses) 74911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 75011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 75111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 75211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 75311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 75411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 75511507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 75611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 75711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses 75811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses 75911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses 76011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses 76111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses 76211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses 76311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses 76411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses 76511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 76611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 76711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses 76811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses 76911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses 77011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses 77111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses 77211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses 77311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency 77411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency 77511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency 77611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency 77711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency 77811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency 77911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency 78011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency 78111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency 78211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency 78311507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked 78411507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked 78511507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked 78611507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked 78711507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked 78811507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked 78911507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks 79011507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 5470634 # number of writebacks 79111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits 79211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits 79311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits 79411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits 79511507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits 79611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits 79711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits 79811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits 79911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits 80011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits 80111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses 80211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses 80311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses 80411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses 80511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 80611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses 80711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses 80811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses 80911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses 81011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses 81111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles 81211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles 81311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles 81411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles 81511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles 81611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles 81711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles 81811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles 81911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles 82011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles 82111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses 82211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses 82311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses 82411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses 82511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 82611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses 82711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses 82811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses 82911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses 83011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses 83111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency 83211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency 83311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency 83411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency 83511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency 83611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency 83711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency 83811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency 83911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency 84011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency 84111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 447 # number of replacements 84211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use 84311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. 84411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. 84511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. 84611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 84711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor 84811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy 84911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy 85011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id 85111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 85211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 85311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 85411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id 85511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id 85611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses 85711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 64550990 # Number of data accesses 85811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits 85911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits 86011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits 86111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits 86211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits 86311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 32273898 # number of overall hits 86411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses 86511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses 86611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses 86711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses 86811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses 86911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 1145 # number of overall misses 87011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles 87111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles 87211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles 87311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles 87411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles 87511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles 87611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses) 87711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses) 87811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses 87911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses 88011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses 88111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses 88211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses 88311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses 88411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses 88511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses 88611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses 88711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses 88811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency 88911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency 89011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency 89111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency 89211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency 89311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency 89411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked 89511507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked 89611507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked 89711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 89811507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked 89911507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked 90011507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 447 # number of writebacks 90111507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 447 # number of writebacks 90211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits 90311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits 90411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits 90511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits 90611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits 90711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits 90811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses 90911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses 91011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses 91111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses 91211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses 91311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses 91411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles 91511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles 91611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles 91711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles 91811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles 91911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles 92011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 92111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 92211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 92311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 92411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 92511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 92611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency 92711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency 92811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 92911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency 93011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 93111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency 93211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued 93311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified 93411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue 93511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 93611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 93711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing 93811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 248 # number of replacements 93911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use 94011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. 94111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks. 94211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks. 94311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 94411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor 94511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor 94611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy 94711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy 94811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy 94911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id 95011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id 95111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 95211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id 95311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id 95411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id 95511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id 95611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id 95711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id 95811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id 95911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id 96011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id 96111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id 96211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses 96311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses 96411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits 96511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits 96611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits 96711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits 96811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits 96911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits 97011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits 97111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits 97211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits 97311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits 97411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits 97511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 5469581 # number of demand (read+write) hits 97611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 5469791 # number of demand (read+write) hits 97711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits 97811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits 97911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 5469791 # number of overall hits 98011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 98111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses 98211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 500 # number of ReadExReq misses 98311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 500 # number of ReadExReq misses 98411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 695 # number of ReadCleanReq misses 98511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 695 # number of ReadCleanReq misses 98611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 1065 # number of ReadSharedReq misses 98711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 1065 # number of ReadSharedReq misses 98811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses 98911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 1565 # number of demand (read+write) misses 99011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 2260 # number of demand (read+write) misses 99111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses 99211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 1565 # number of overall misses 99311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 2260 # number of overall misses 99411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 59500 # number of UpgradeReq miss cycles 99511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 59500 # number of UpgradeReq miss cycles 99611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41259500 # number of ReadExReq miss cycles 99711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 41259500 # number of ReadExReq miss cycles 99811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47414000 # number of ReadCleanReq miss cycles 99911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 47414000 # number of ReadCleanReq miss cycles 100011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71274500 # number of ReadSharedReq miss cycles 100111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 71274500 # number of ReadSharedReq miss cycles 100211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 47414000 # number of demand (read+write) miss cycles 100311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 112534000 # number of demand (read+write) miss cycles 100411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 159948000 # number of demand (read+write) miss cycles 100511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 47414000 # number of overall miss cycles 100611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 112534000 # number of overall miss cycles 100711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 159948000 # number of overall miss cycles 100811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 5451171 # number of WritebackDirty accesses(hits+misses) 100911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 5451171 # number of WritebackDirty accesses(hits+misses) 101011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 17033 # number of WritebackClean accesses(hits+misses) 101111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 17033 # number of WritebackClean accesses(hits+misses) 101211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 101311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) 101411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses) 101511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses) 101611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 905 # number of ReadCleanReq accesses(hits+misses) 101711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 905 # number of ReadCleanReq accesses(hits+misses) 101811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244627 # number of ReadSharedReq accesses(hits+misses) 101911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 5244627 # number of ReadSharedReq accesses(hits+misses) 102011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 905 # number of demand (read+write) accesses 102111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 5471146 # number of demand (read+write) accesses 102211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses 102311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 905 # number of overall (read+write) accesses 102411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 5471146 # number of overall (read+write) accesses 102511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses 102611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 102711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 102811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002207 # miss rate for ReadExReq accesses 102911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.002207 # miss rate for ReadExReq accesses 103011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.767956 # miss rate for ReadCleanReq accesses 103111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.767956 # miss rate for ReadCleanReq accesses 103211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000203 # miss rate for ReadSharedReq accesses 103311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000203 # miss rate for ReadSharedReq accesses 103411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.767956 # miss rate for demand accesses 103511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.000286 # miss rate for demand accesses 103611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.000413 # miss rate for demand accesses 103711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.767956 # miss rate for overall accesses 103811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.000286 # miss rate for overall accesses 103911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.000413 # miss rate for overall accesses 104011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333 # average UpgradeReq miss latency 104111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333 # average UpgradeReq miss latency 104211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82519 # average ReadExReq miss latency 104311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 82519 # average ReadExReq miss latency 104411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734 # average ReadCleanReq miss latency 104511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734 # average ReadCleanReq miss latency 104611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146 # average ReadSharedReq miss latency 104711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146 # average ReadSharedReq miss latency 104811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency 104911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency 105011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 70773.451327 # average overall miss latency 105111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency 105211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency 105311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency 105411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 105511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 105611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 105711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 105811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 105911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 106011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference 106111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 175 # number of writebacks 106211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 175 # number of writebacks 106311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits 106411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits 106511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 106611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 106711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits 106811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 37 # number of ReadSharedReq MSHR hits 106911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 107011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 195 # number of demand (read+write) MSHR hits 107111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 196 # number of demand (read+write) MSHR hits 107211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 107311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 195 # number of overall MSHR hits 107411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 196 # number of overall MSHR hits 107511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316084 # number of HardPFReq MSHR misses 107611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_misses::total 316084 # number of HardPFReq MSHR misses 107711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 107811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses 107911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses 108011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses 108111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 694 # number of ReadCleanReq MSHR misses 108211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 694 # number of ReadCleanReq MSHR misses 108311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1028 # number of ReadSharedReq MSHR misses 108411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 1028 # number of ReadSharedReq MSHR misses 108511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses 108611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 1370 # number of demand (read+write) MSHR misses 108711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 2064 # number of demand (read+write) MSHR misses 108811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses 108911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 1370 # number of overall MSHR misses 109011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316084 # number of overall MSHR misses 109111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 318148 # number of overall MSHR misses 109211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of HardPFReq MSHR miss cycles 109311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852614747 # number of HardPFReq MSHR miss cycles 109411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 41500 # number of UpgradeReq MSHR miss cycles 109511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 41500 # number of UpgradeReq MSHR miss cycles 109611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32745000 # number of ReadExReq MSHR miss cycles 109711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32745000 # number of ReadExReq MSHR miss cycles 109811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43196500 # number of ReadCleanReq MSHR miss cycles 109911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43196500 # number of ReadCleanReq MSHR miss cycles 110011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63614500 # number of ReadSharedReq MSHR miss cycles 110111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63614500 # number of ReadSharedReq MSHR miss cycles 110211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43196500 # number of demand (read+write) MSHR miss cycles 110311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96359500 # number of demand (read+write) MSHR miss cycles 110411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 139556000 # number of demand (read+write) MSHR miss cycles 110511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43196500 # number of overall MSHR miss cycles 110611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96359500 # number of overall MSHR miss cycles 110711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of overall MSHR miss cycles 110811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 992170747 # number of overall MSHR miss cycles 110911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 111011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 111111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 111211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 111311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses 111411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses 111511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses 111611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses 111711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses 111811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses 111911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses 112011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses 112111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses 112211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses 112311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses 112411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 112511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses 112611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency 112711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency 112811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency 112911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency 113011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency 113111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency 113211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency 113311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency 113411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency 113511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency 113611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency 113711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency 113811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency 113911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency 114011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency 114111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency 114211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency 114311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. 114411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. 114511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 114611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. 114711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 114811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 114911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution 115011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution 115111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution 115211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution 115311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution 115411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 115511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 115611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution 115711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution 115811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution 115911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution 116011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution 116111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) 116211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) 116311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes) 116411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) 116511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes) 116611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes) 116711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 319939 # Total snoops (count) 116811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram 116911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram 117011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram 117111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 117211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram 117311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram 117411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram 117511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 117611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 117711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 117811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram 117911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) 118011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) 118111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) 118211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 118311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) 118411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 118511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) 118611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) 118711507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 16175 # Transaction distribution 118811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 175 # Transaction distribution 118911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 63 # Transaction distribution 119011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 4 # Transaction distribution 119111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 341 # Transaction distribution 119211507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 341 # Transaction distribution 119311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution 119411507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) 119511507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes) 119611507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes) 119711507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes) 119811507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 119911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 16759 # Request fanout histogram 120011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 120111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 120211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 120311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram 120411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 120511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 120611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 120711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 120811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 16759 # Request fanout histogram 120911507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks) 121011507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 121111507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks) 121211507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 121311507SCurtis.Dunham@arm.com 121411507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 1215