stats.txt revision 11507
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.058199 # Number of seconds simulated 4sim_ticks 58199030500 # Number of ticks simulated 5final_tick 58199030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 101249 # Simulator instruction rate (inst/s) 8host_op_rate 101754 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 65047265 # Simulator tick rate (ticks/s) 10host_mem_usage 487144 # Number of bytes of host memory used 11host_seconds 894.72 # Real time elapsed on the host 12sim_insts 90589799 # Number of instructions simulated 13sim_ops 91041030 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 44352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 87616 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 925056 # Number of bytes read from this memory 19system.physmem.bytes_read::total 1057024 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 44352 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 44352 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 11200 # Number of bytes written to this memory 23system.physmem.bytes_written::total 11200 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 693 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 1369 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 14454 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 16516 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 175 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 175 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 762075 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 1505455 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 15894698 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 18162227 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 762075 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 762075 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 192443 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 192443 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 192443 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 762075 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 1505455 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 15894698 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 18354670 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 16517 # Number of read requests accepted 44system.physmem.writeReqs 175 # Number of write requests accepted 45system.physmem.readBursts 16517 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 175 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 1048320 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue 49system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 1057088 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 11200 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 1166 # Per bank write bursts 56system.physmem.perBankRdBursts::1 920 # Per bank write bursts 57system.physmem.perBankRdBursts::2 953 # Per bank write bursts 58system.physmem.perBankRdBursts::3 1031 # Per bank write bursts 59system.physmem.perBankRdBursts::4 1061 # Per bank write bursts 60system.physmem.perBankRdBursts::5 1122 # Per bank write bursts 61system.physmem.perBankRdBursts::6 1094 # Per bank write bursts 62system.physmem.perBankRdBursts::7 1089 # Per bank write bursts 63system.physmem.perBankRdBursts::8 1025 # Per bank write bursts 64system.physmem.perBankRdBursts::9 962 # Per bank write bursts 65system.physmem.perBankRdBursts::10 933 # Per bank write bursts 66system.physmem.perBankRdBursts::11 900 # Per bank write bursts 67system.physmem.perBankRdBursts::12 903 # Per bank write bursts 68system.physmem.perBankRdBursts::13 900 # Per bank write bursts 69system.physmem.perBankRdBursts::14 1411 # Per bank write bursts 70system.physmem.perBankRdBursts::15 910 # Per bank write bursts 71system.physmem.perBankWrBursts::0 2 # Per bank write bursts 72system.physmem.perBankWrBursts::1 0 # Per bank write bursts 73system.physmem.perBankWrBursts::2 6 # Per bank write bursts 74system.physmem.perBankWrBursts::3 1 # Per bank write bursts 75system.physmem.perBankWrBursts::4 3 # Per bank write bursts 76system.physmem.perBankWrBursts::5 16 # Per bank write bursts 77system.physmem.perBankWrBursts::6 40 # Per bank write bursts 78system.physmem.perBankWrBursts::7 7 # Per bank write bursts 79system.physmem.perBankWrBursts::8 2 # Per bank write bursts 80system.physmem.perBankWrBursts::9 0 # Per bank write bursts 81system.physmem.perBankWrBursts::10 2 # Per bank write bursts 82system.physmem.perBankWrBursts::11 2 # Per bank write bursts 83system.physmem.perBankWrBursts::12 2 # Per bank write bursts 84system.physmem.perBankWrBursts::13 17 # Per bank write bursts 85system.physmem.perBankWrBursts::14 37 # Per bank write bursts 86system.physmem.perBankWrBursts::15 7 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 58199022000 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 16517 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 175 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 11454 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 2521 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 462 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 397 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 296 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 296 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 316 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 292 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 292 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 54 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 9 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 9 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 1812 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 582.746137 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 353.648277 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 424.722034 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 448 24.72% 24.72% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 213 11.75% 36.48% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 96 5.30% 41.78% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 72 3.97% 45.75% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 56 3.09% 48.84% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 67 3.70% 52.54% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 61 3.37% 55.91% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 48 2.65% 58.55% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 751 41.45% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 1812 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 2016.250000 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 98.342741 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 5441.040729 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-511 7 87.50% 87.50% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::15360-15871 1 12.50% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes 221system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads 226system.physmem.totQLat 175730624 # Total ticks spent queuing 227system.physmem.totMemAccLat 482855624 # Total ticks spent from burst creation until serviced by the DRAM 228system.physmem.totBusLat 81900000 # Total ticks spent in databus transfers 229system.physmem.avgQLat 10728.37 # Average queueing delay per DRAM burst 230system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 231system.physmem.avgMemAccLat 29478.37 # Average memory access latency per DRAM burst 232system.physmem.avgRdBW 18.01 # Average DRAM read bandwidth in MiByte/s 233system.physmem.avgWrBW 0.16 # Average achieved write bandwidth in MiByte/s 234system.physmem.avgRdBWSys 18.16 # Average system read bandwidth in MiByte/s 235system.physmem.avgWrBWSys 0.19 # Average system write bandwidth in MiByte/s 236system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 237system.physmem.busUtil 0.14 # Data bus utilization in percentage 238system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads 239system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 240system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 241system.physmem.avgWrQLen 14.75 # Average write queue length when enqueuing 242system.physmem.readRowHits 14651 # Number of row buffer hits during reads 243system.physmem.writeRowHits 51 # Number of row buffer hits during writes 244system.physmem.readRowHitRate 89.44 # Row buffer hit rate for reads 245system.physmem.writeRowHitRate 29.82 # Row buffer hit rate for writes 246system.physmem.avgGap 3486641.62 # Average gap between requests 247system.physmem.pageHitRate 88.83 # Row buffer hit rate, read and write combined 248system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) 249system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) 250system.physmem_0.readEnergy 65512200 # Energy for read commands per rank (pJ) 251system.physmem_0.writeEnergy 486000 # Energy for write commands per rank (pJ) 252system.physmem_0.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) 253system.physmem_0.actBackEnergy 2714701095 # Energy for active background per rank (pJ) 254system.physmem_0.preBackEnergy 32535498750 # Energy for precharge background per rank (pJ) 255system.physmem_0.totalEnergy 39129012390 # Total energy per rank (pJ) 256system.physmem_0.averagePower 672.381118 # Core power per rank (mW) 257system.physmem_0.memoryStateTime::IDLE 54114607553 # Time in different power states 258system.physmem_0.memoryStateTime::REF 1943240000 # Time in different power states 259system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 260system.physmem_0.memoryStateTime::ACT 2137743447 # Time in different power states 261system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 262system.physmem_1.actEnergy 6017760 # Energy for activate commands per rank (pJ) 263system.physmem_1.preEnergy 3283500 # Energy for precharge commands per rank (pJ) 264system.physmem_1.readEnergy 61916400 # Energy for read commands per rank (pJ) 265system.physmem_1.writeEnergy 447120 # Energy for write commands per rank (pJ) 266system.physmem_1.refreshEnergy 3800977440 # Energy for refresh commands per rank (pJ) 267system.physmem_1.actBackEnergy 2480426820 # Energy for active background per rank (pJ) 268system.physmem_1.preBackEnergy 32741002500 # Energy for precharge background per rank (pJ) 269system.physmem_1.totalEnergy 39094071540 # Total energy per rank (pJ) 270system.physmem_1.averagePower 671.780705 # Core power per rank (mW) 271system.physmem_1.memoryStateTime::IDLE 54458056984 # Time in different power states 272system.physmem_1.memoryStateTime::REF 1943240000 # Time in different power states 273system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 274system.physmem_1.memoryStateTime::ACT 1793992016 # Time in different power states 275system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 276system.cpu.branchPred.lookups 28233538 # Number of BP lookups 277system.cpu.branchPred.condPredicted 23266052 # Number of conditional branches predicted 278system.cpu.branchPred.condIncorrect 835390 # Number of conditional branches incorrect 279system.cpu.branchPred.BTBLookups 11829354 # Number of BTB lookups 280system.cpu.branchPred.BTBHits 11747655 # Number of BTB hits 281system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 282system.cpu.branchPred.BTBHitPct 99.309354 # BTB Hit Percentage 283system.cpu.branchPred.usedRAS 74541 # Number of times the RAS was used to get a target. 284system.cpu.branchPred.RASInCorrect 92 # Number of incorrect RAS predictions. 285system.cpu.branchPred.indirectLookups 27216 # Number of indirect predictor lookups. 286system.cpu.branchPred.indirectHits 25478 # Number of indirect target hits. 287system.cpu.branchPred.indirectMisses 1738 # Number of indirect misses. 288system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. 289system.cpu_clk_domain.clock 500 # Clock period in ticks 290system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 292system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 299system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 300system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 301system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 302system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 303system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 304system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 305system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 306system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 307system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 308system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 309system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 310system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 311system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 312system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 313system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 314system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 315system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 316system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 317system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 318system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 319system.cpu.dtb.walker.walks 0 # Table walker walks requested 320system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 322system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.inst_hits 0 # ITB inst hits 328system.cpu.dtb.inst_misses 0 # ITB inst misses 329system.cpu.dtb.read_hits 0 # DTB read hits 330system.cpu.dtb.read_misses 0 # DTB read misses 331system.cpu.dtb.write_hits 0 # DTB write hits 332system.cpu.dtb.write_misses 0 # DTB write misses 333system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 334system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 335system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 336system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 337system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 338system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 339system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 340system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 341system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 342system.cpu.dtb.read_accesses 0 # DTB read accesses 343system.cpu.dtb.write_accesses 0 # DTB write accesses 344system.cpu.dtb.inst_accesses 0 # ITB inst accesses 345system.cpu.dtb.hits 0 # DTB hits 346system.cpu.dtb.misses 0 # DTB misses 347system.cpu.dtb.accesses 0 # DTB accesses 348system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 357system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 358system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 359system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 360system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 361system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 362system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 363system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 364system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 365system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 366system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 367system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 368system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 369system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 370system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 371system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 372system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 373system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 374system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 375system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 376system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 377system.cpu.itb.walker.walks 0 # Table walker walks requested 378system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.inst_hits 0 # ITB inst hits 386system.cpu.itb.inst_misses 0 # ITB inst misses 387system.cpu.itb.read_hits 0 # DTB read hits 388system.cpu.itb.read_misses 0 # DTB read misses 389system.cpu.itb.write_hits 0 # DTB write hits 390system.cpu.itb.write_misses 0 # DTB write misses 391system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 392system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 393system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 394system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 395system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 396system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 397system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 398system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 399system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 400system.cpu.itb.read_accesses 0 # DTB read accesses 401system.cpu.itb.write_accesses 0 # DTB write accesses 402system.cpu.itb.inst_accesses 0 # ITB inst accesses 403system.cpu.itb.hits 0 # DTB hits 404system.cpu.itb.misses 0 # DTB misses 405system.cpu.itb.accesses 0 # DTB accesses 406system.cpu.workload.num_syscalls 442 # Number of system calls 407system.cpu.numCycles 116398062 # number of cpu cycles simulated 408system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 409system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 410system.cpu.fetch.icacheStallCycles 746143 # Number of cycles fetch is stalled on an Icache miss 411system.cpu.fetch.Insts 134906479 # Number of instructions fetch has processed 412system.cpu.fetch.Branches 28233538 # Number of branches that fetch encountered 413system.cpu.fetch.predictedBranches 11847674 # Number of branches that fetch has predicted taken 414system.cpu.fetch.Cycles 114760827 # Number of cycles fetch has run and was not squashing or blocked 415system.cpu.fetch.SquashCycles 1674187 # Number of cycles fetch has spent squashing 416system.cpu.fetch.MiscStallCycles 911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 417system.cpu.fetch.IcacheWaitRetryStallCycles 805 # Number of stall cycles due to full MSHR 418system.cpu.fetch.CacheLines 32275055 # Number of cache lines fetched 419system.cpu.fetch.IcacheSquashes 562 # Number of outstanding Icache misses that were squashed 420system.cpu.fetch.rateDist::samples 116345779 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::mean 1.164712 # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::stdev 1.318875 # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::0 58810972 50.55% 50.55% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::1 13933527 11.98% 62.52% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::2 9228064 7.93% 70.46% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::3 34373216 29.54% 100.00% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::total 116345779 # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.branchRate 0.242560 # Number of branch fetches per cycle 433system.cpu.fetch.rate 1.159010 # Number of inst fetches per cycle 434system.cpu.decode.IdleCycles 8834252 # Number of cycles decode is idle 435system.cpu.decode.BlockedCycles 64111694 # Number of cycles decode is blocked 436system.cpu.decode.RunCycles 33013656 # Number of cycles decode is running 437system.cpu.decode.UnblockCycles 9560800 # Number of cycles decode is unblocking 438system.cpu.decode.SquashCycles 825377 # Number of cycles decode is squashing 439system.cpu.decode.BranchResolved 4097950 # Number of times decode resolved a branch 440system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction 441system.cpu.decode.DecodedInsts 114395383 # Number of instructions handled by decode 442system.cpu.decode.SquashedInsts 1985420 # Number of squashed instructions handled by decode 443system.cpu.rename.SquashCycles 825377 # Number of cycles rename is squashing 444system.cpu.rename.IdleCycles 15270485 # Number of cycles rename is idle 445system.cpu.rename.BlockCycles 49952350 # Number of cycles rename is blocking 446system.cpu.rename.serializeStallCycles 109536 # count of cycles rename stalled for serializing inst 447system.cpu.rename.RunCycles 35410349 # Number of cycles rename is running 448system.cpu.rename.UnblockCycles 14777682 # Number of cycles rename is unblocking 449system.cpu.rename.RenamedInsts 110872417 # Number of instructions processed by rename 450system.cpu.rename.SquashedInsts 1412237 # Number of squashed instructions processed by rename 451system.cpu.rename.ROBFullEvents 11132933 # Number of times rename has blocked due to ROB full 452system.cpu.rename.IQFullEvents 1144918 # Number of times rename has blocked due to IQ full 453system.cpu.rename.LQFullEvents 1526969 # Number of times rename has blocked due to LQ full 454system.cpu.rename.SQFullEvents 486977 # Number of times rename has blocked due to SQ full 455system.cpu.rename.RenamedOperands 129945519 # Number of destination operands rename has renamed 456system.cpu.rename.RenameLookups 483153288 # Number of register rename lookups that rename has made 457system.cpu.rename.int_rename_lookups 119447216 # Number of integer rename lookups 458system.cpu.rename.fp_rename_lookups 432 # Number of floating rename lookups 459system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed 460system.cpu.rename.UndoneMaps 22632600 # Number of HB maps that are undone due to squashing 461system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed 462system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed 463system.cpu.rename.skidInsts 21510749 # count of insts added to the skid buffer 464system.cpu.memDep0.insertedLoads 26805153 # Number of loads inserted to the mem dependence unit. 465system.cpu.memDep0.insertedStores 5347343 # Number of stores inserted to the mem dependence unit. 466system.cpu.memDep0.conflictingLoads 519410 # Number of conflicting loads. 467system.cpu.memDep0.conflictingStores 254099 # Number of conflicting stores. 468system.cpu.iq.iqInstsAdded 109667150 # Number of instructions added to the IQ (excludes non-spec) 469system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ 470system.cpu.iq.iqInstsIssued 101366848 # Number of instructions issued 471system.cpu.iq.iqSquashedInstsIssued 1074801 # Number of squashed instructions issued 472system.cpu.iq.iqSquashedInstsExamined 18634403 # Number of squashed instructions iterated over during squash; mainly for profiling 473system.cpu.iq.iqSquashedOperandsExamined 41667299 # Number of squashed operands that are examined and possibly removed from graph 474system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed 475system.cpu.iq.issued_per_cycle::samples 116345779 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::mean 0.871255 # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::stdev 0.989200 # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::0 54714850 47.03% 47.03% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::1 31358235 26.95% 73.98% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::2 22007860 18.92% 92.90% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::3 7066756 6.07% 98.97% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::4 1197765 1.03% 100.00% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::5 313 0.00% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::total 116345779 # Number of insts issued each cycle 492system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 493system.cpu.iq.fu_full::IntAlu 9784213 48.67% 48.67% # attempts to use FU when none available 494system.cpu.iq.fu_full::IntMult 50 0.00% 48.67% # attempts to use FU when none available 495system.cpu.iq.fu_full::IntDiv 0 0.00% 48.67% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.67% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.67% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.67% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatMult 0 0.00% 48.67% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.67% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.67% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.67% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.67% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.67% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.67% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.67% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.67% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdMult 0 0.00% 48.67% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.67% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdShift 0 0.00% 48.67% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.67% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.67% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.67% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.67% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.67% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.67% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.67% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.67% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.67% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.67% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.67% # attempts to use FU when none available 522system.cpu.iq.fu_full::MemRead 9614548 47.83% 96.50% # attempts to use FU when none available 523system.cpu.iq.fu_full::MemWrite 702998 3.50% 100.00% # attempts to use FU when none available 524system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 525system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 526system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 527system.cpu.iq.FU_type_0::IntAlu 71970791 71.00% 71.00% # Type of FU issued 528system.cpu.iq.FU_type_0::IntMult 10698 0.01% 71.01% # Type of FU issued 529system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued 530system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued 531system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued 532system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued 535system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatCvt 54 0.00% 71.01% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued 556system.cpu.iq.FU_type_0::MemRead 24337715 24.01% 95.02% # Type of FU issued 557system.cpu.iq.FU_type_0::MemWrite 5047462 4.98% 100.00% # Type of FU issued 558system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 559system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 560system.cpu.iq.FU_type_0::total 101366848 # Type of FU issued 561system.cpu.iq.rate 0.870864 # Inst issue rate 562system.cpu.iq.fu_busy_cnt 20101822 # FU busy when requested 563system.cpu.iq.fu_busy_rate 0.198308 # FU busy rate (busy events/executed inst) 564system.cpu.iq.int_inst_queue_reads 340255638 # Number of integer instruction queue reads 565system.cpu.iq.int_inst_queue_writes 128310520 # Number of integer instruction queue writes 566system.cpu.iq.int_inst_queue_wakeup_accesses 99608490 # Number of integer instruction queue wakeup accesses 567system.cpu.iq.fp_inst_queue_reads 460 # Number of floating instruction queue reads 568system.cpu.iq.fp_inst_queue_writes 624 # Number of floating instruction queue writes 569system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses 570system.cpu.iq.int_alu_accesses 121468430 # Number of integer alu accesses 571system.cpu.iq.fp_alu_accesses 240 # Number of floating point alu accesses 572system.cpu.iew.lsq.thread0.forwLoads 288068 # Number of loads that had data forwarded from stores 573system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 574system.cpu.iew.lsq.thread0.squashedLoads 4329242 # Number of loads squashed 575system.cpu.iew.lsq.thread0.ignoredResponses 1500 # Number of memory responses ignored because the instruction is squashed 576system.cpu.iew.lsq.thread0.memOrderViolation 1342 # Number of memory ordering violations 577system.cpu.iew.lsq.thread0.squashedStores 602499 # Number of stores squashed 578system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 579system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 580system.cpu.iew.lsq.thread0.rescheduledLoads 7579 # Number of loads that were rescheduled 581system.cpu.iew.lsq.thread0.cacheBlocked 130663 # Number of times an access to memory failed due to the cache being blocked 582system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 583system.cpu.iew.iewSquashCycles 825377 # Number of cycles IEW is squashing 584system.cpu.iew.iewBlockCycles 8119454 # Number of cycles IEW is blocking 585system.cpu.iew.iewUnblockCycles 685980 # Number of cycles IEW is unblocking 586system.cpu.iew.iewDispatchedInsts 109688255 # Number of instructions dispatched to IQ 587system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 588system.cpu.iew.iewDispLoadInsts 26805153 # Number of dispatched load instructions 589system.cpu.iew.iewDispStoreInsts 5347343 # Number of dispatched store instructions 590system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions 591system.cpu.iew.iewIQFullEvents 180270 # Number of times the IQ has become full, causing a stall 592system.cpu.iew.iewLSQFullEvents 342292 # Number of times the LSQ has become full, causing a stall 593system.cpu.iew.memOrderViolationEvents 1342 # Number of memory order violations 594system.cpu.iew.predictedTakenIncorrect 435059 # Number of branches that were predicted taken incorrectly 595system.cpu.iew.predictedNotTakenIncorrect 412404 # Number of branches that were predicted not taken incorrectly 596system.cpu.iew.branchMispredicts 847463 # Number of branch mispredicts detected at execute 597system.cpu.iew.iewExecutedInsts 100109842 # Number of executed instructions 598system.cpu.iew.iewExecLoadInsts 23803071 # Number of load instructions executed 599system.cpu.iew.iewExecSquashedInsts 1257006 # Number of squashed instructions skipped in execute 600system.cpu.iew.exec_swp 0 # number of swp insts executed 601system.cpu.iew.exec_nop 12822 # number of nop insts executed 602system.cpu.iew.exec_refs 28718921 # number of memory reference insts executed 603system.cpu.iew.exec_branches 20621209 # Number of branches executed 604system.cpu.iew.exec_stores 4915850 # Number of stores executed 605system.cpu.iew.exec_rate 0.860065 # Inst execution rate 606system.cpu.iew.wb_sent 99693752 # cumulative count of insts sent to commit 607system.cpu.iew.wb_count 99608605 # cumulative count of insts written-back 608system.cpu.iew.wb_producers 59691637 # num instructions producing a value 609system.cpu.iew.wb_consumers 95527463 # num instructions consuming a value 610system.cpu.iew.wb_rate 0.855758 # insts written-back per cycle 611system.cpu.iew.wb_fanout 0.624864 # average fanout of values written-back 612system.cpu.commit.commitSquashedInsts 17362842 # The number of squashed insts skipped by commit 613system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards 614system.cpu.commit.branchMispredicts 823674 # The number of times a branch was mispredicted 615system.cpu.commit.committed_per_cycle::samples 113658017 # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::mean 0.801119 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::stdev 1.737711 # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::0 77235221 67.95% 67.95% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::1 18611593 16.38% 84.33% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::2 7151823 6.29% 90.62% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::3 3469408 3.05% 93.67% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::4 1644636 1.45% 95.12% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::5 541902 0.48% 95.60% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::6 703188 0.62% 96.22% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::7 178974 0.16% 96.37% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::8 4121272 3.63% 100.00% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::total 113658017 # Number of insts commited each cycle 632system.cpu.commit.committedInsts 90602408 # Number of instructions committed 633system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed 634system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 635system.cpu.commit.refs 27220755 # Number of memory references committed 636system.cpu.commit.loads 22475911 # Number of loads committed 637system.cpu.commit.membars 3888 # Number of memory barriers committed 638system.cpu.commit.branches 18732305 # Number of branches committed 639system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 640system.cpu.commit.int_insts 72326352 # Number of committed integer instructions. 641system.cpu.commit.function_calls 56148 # Number of function calls committed. 642system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 643system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction 644system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 645system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 646system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 647system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 648system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 649system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 650system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 651system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 652system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 653system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 654system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 655system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 656system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 657system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 658system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 659system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 661system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 662system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 663system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 664system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 665system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 666system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 667system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 668system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 669system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 670system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 671system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 672system.cpu.commit.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 673system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 674system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 675system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 676system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction 677system.cpu.commit.bw_lim_events 4121272 # number cycles where commit BW limit reached 678system.cpu.rob.rob_reads 217947492 # The number of ROB reads 679system.cpu.rob.rob_writes 219521309 # The number of ROB writes 680system.cpu.timesIdled 570 # Number of times that the entire CPU went into an idle state and unscheduled itself 681system.cpu.idleCycles 52283 # Total number of cycles that the CPU has spent unscheduled due to idling 682system.cpu.committedInsts 90589799 # Number of Instructions Simulated 683system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated 684system.cpu.cpi 1.284891 # CPI: Cycles Per Instruction 685system.cpu.cpi_total 1.284891 # CPI: Total CPI of All Threads 686system.cpu.ipc 0.778276 # IPC: Instructions Per Cycle 687system.cpu.ipc_total 0.778276 # IPC: Total IPC of All Threads 688system.cpu.int_regfile_reads 108097873 # number of integer regfile reads 689system.cpu.int_regfile_writes 58692304 # number of integer regfile writes 690system.cpu.fp_regfile_reads 59 # number of floating regfile reads 691system.cpu.fp_regfile_writes 96 # number of floating regfile writes 692system.cpu.cc_regfile_reads 369004699 # number of cc regfile reads 693system.cpu.cc_regfile_writes 58686555 # number of cc regfile writes 694system.cpu.misc_regfile_reads 28410220 # number of misc regfile reads 695system.cpu.misc_regfile_writes 7784 # number of misc regfile writes 696system.cpu.dcache.tags.replacements 5470634 # number of replacements 697system.cpu.dcache.tags.tagsinuse 511.784091 # Cycle average of tags in use 698system.cpu.dcache.tags.total_refs 18249365 # Total number of references to valid blocks. 699system.cpu.dcache.tags.sampled_refs 5471146 # Sample count of references to valid blocks. 700system.cpu.dcache.tags.avg_refs 3.335565 # Average number of references to valid blocks. 701system.cpu.dcache.tags.warmup_cycle 35796500 # Cycle when the warmup percentage was hit. 702system.cpu.dcache.tags.occ_blocks::cpu.data 511.784091 # Average occupied blocks per requestor 703system.cpu.dcache.tags.occ_percent::cpu.data 0.999578 # Average percentage of cache occupancy 704system.cpu.dcache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy 705system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 706system.cpu.dcache.tags.age_task_id_blocks_1024::0 344 # Occupied blocks per task id 707system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id 708system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 709system.cpu.dcache.tags.tag_accesses 61906904 # Number of tag accesses 710system.cpu.dcache.tags.data_accesses 61906904 # Number of data accesses 711system.cpu.dcache.ReadReq_hits::cpu.data 13887331 # number of ReadReq hits 712system.cpu.dcache.ReadReq_hits::total 13887331 # number of ReadReq hits 713system.cpu.dcache.WriteReq_hits::cpu.data 4353747 # number of WriteReq hits 714system.cpu.dcache.WriteReq_hits::total 4353747 # number of WriteReq hits 715system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits 716system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits 717system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits 718system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits 719system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 720system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 721system.cpu.dcache.demand_hits::cpu.data 18241078 # number of demand (read+write) hits 722system.cpu.dcache.demand_hits::total 18241078 # number of demand (read+write) hits 723system.cpu.dcache.overall_hits::cpu.data 18241600 # number of overall hits 724system.cpu.dcache.overall_hits::total 18241600 # number of overall hits 725system.cpu.dcache.ReadReq_misses::cpu.data 9587264 # number of ReadReq misses 726system.cpu.dcache.ReadReq_misses::total 9587264 # number of ReadReq misses 727system.cpu.dcache.WriteReq_misses::cpu.data 381234 # number of WriteReq misses 728system.cpu.dcache.WriteReq_misses::total 381234 # number of WriteReq misses 729system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses 730system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses 731system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses 732system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses 733system.cpu.dcache.demand_misses::cpu.data 9968498 # number of demand (read+write) misses 734system.cpu.dcache.demand_misses::total 9968498 # number of demand (read+write) misses 735system.cpu.dcache.overall_misses::cpu.data 9968505 # number of overall misses 736system.cpu.dcache.overall_misses::total 9968505 # number of overall misses 737system.cpu.dcache.ReadReq_miss_latency::cpu.data 88773272500 # number of ReadReq miss cycles 738system.cpu.dcache.ReadReq_miss_latency::total 88773272500 # number of ReadReq miss cycles 739system.cpu.dcache.WriteReq_miss_latency::cpu.data 4000795875 # number of WriteReq miss cycles 740system.cpu.dcache.WriteReq_miss_latency::total 4000795875 # number of WriteReq miss cycles 741system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 291000 # number of LoadLockedReq miss cycles 742system.cpu.dcache.LoadLockedReq_miss_latency::total 291000 # number of LoadLockedReq miss cycles 743system.cpu.dcache.demand_miss_latency::cpu.data 92774068375 # number of demand (read+write) miss cycles 744system.cpu.dcache.demand_miss_latency::total 92774068375 # number of demand (read+write) miss cycles 745system.cpu.dcache.overall_miss_latency::cpu.data 92774068375 # number of overall miss cycles 746system.cpu.dcache.overall_miss_latency::total 92774068375 # number of overall miss cycles 747system.cpu.dcache.ReadReq_accesses::cpu.data 23474595 # number of ReadReq accesses(hits+misses) 748system.cpu.dcache.ReadReq_accesses::total 23474595 # number of ReadReq accesses(hits+misses) 749system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 750system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 751system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) 752system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) 753system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 754system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 755system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 756system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 757system.cpu.dcache.demand_accesses::cpu.data 28209576 # number of demand (read+write) accesses 758system.cpu.dcache.demand_accesses::total 28209576 # number of demand (read+write) accesses 759system.cpu.dcache.overall_accesses::cpu.data 28210105 # number of overall (read+write) accesses 760system.cpu.dcache.overall_accesses::total 28210105 # number of overall (read+write) accesses 761system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses 762system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses 763system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080514 # miss rate for WriteReq accesses 764system.cpu.dcache.WriteReq_miss_rate::total 0.080514 # miss rate for WriteReq accesses 765system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses 766system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses 767system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses 768system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses 769system.cpu.dcache.demand_miss_rate::cpu.data 0.353373 # miss rate for demand accesses 770system.cpu.dcache.demand_miss_rate::total 0.353373 # miss rate for demand accesses 771system.cpu.dcache.overall_miss_rate::cpu.data 0.353366 # miss rate for overall accesses 772system.cpu.dcache.overall_miss_rate::total 0.353366 # miss rate for overall accesses 773system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9259.500156 # average ReadReq miss latency 774system.cpu.dcache.ReadReq_avg_miss_latency::total 9259.500156 # average ReadReq miss latency 775system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10494.331238 # average WriteReq miss latency 776system.cpu.dcache.WriteReq_avg_miss_latency::total 10494.331238 # average WriteReq miss latency 777system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19400 # average LoadLockedReq miss latency 778system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19400 # average LoadLockedReq miss latency 779system.cpu.dcache.demand_avg_miss_latency::cpu.data 9306.724882 # average overall miss latency 780system.cpu.dcache.demand_avg_miss_latency::total 9306.724882 # average overall miss latency 781system.cpu.dcache.overall_avg_miss_latency::cpu.data 9306.718347 # average overall miss latency 782system.cpu.dcache.overall_avg_miss_latency::total 9306.718347 # average overall miss latency 783system.cpu.dcache.blocked_cycles::no_mshrs 329915 # number of cycles access was blocked 784system.cpu.dcache.blocked_cycles::no_targets 108865 # number of cycles access was blocked 785system.cpu.dcache.blocked::no_mshrs 121409 # number of cycles access was blocked 786system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked 787system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.717385 # average number of cycles each access was blocked 788system.cpu.dcache.avg_blocked_cycles::no_targets 8.479903 # average number of cycles each access was blocked 789system.cpu.dcache.writebacks::writebacks 5470634 # number of writebacks 790system.cpu.dcache.writebacks::total 5470634 # number of writebacks 791system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338603 # number of ReadReq MSHR hits 792system.cpu.dcache.ReadReq_mshr_hits::total 4338603 # number of ReadReq MSHR hits 793system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158750 # number of WriteReq MSHR hits 794system.cpu.dcache.WriteReq_mshr_hits::total 158750 # number of WriteReq MSHR hits 795system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits 796system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits 797system.cpu.dcache.demand_mshr_hits::cpu.data 4497353 # number of demand (read+write) MSHR hits 798system.cpu.dcache.demand_mshr_hits::total 4497353 # number of demand (read+write) MSHR hits 799system.cpu.dcache.overall_mshr_hits::cpu.data 4497353 # number of overall MSHR hits 800system.cpu.dcache.overall_mshr_hits::total 4497353 # number of overall MSHR hits 801system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248661 # number of ReadReq MSHR misses 802system.cpu.dcache.ReadReq_mshr_misses::total 5248661 # number of ReadReq MSHR misses 803system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222484 # number of WriteReq MSHR misses 804system.cpu.dcache.WriteReq_mshr_misses::total 222484 # number of WriteReq MSHR misses 805system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses 806system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses 807system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses 808system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses 809system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses 810system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses 811system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43288788000 # number of ReadReq MSHR miss cycles 812system.cpu.dcache.ReadReq_mshr_miss_latency::total 43288788000 # number of ReadReq MSHR miss cycles 813system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285573254 # number of WriteReq MSHR miss cycles 814system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285573254 # number of WriteReq MSHR miss cycles 815system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 214500 # number of SoftPFReq MSHR miss cycles 816system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 214500 # number of SoftPFReq MSHR miss cycles 817system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45574361254 # number of demand (read+write) MSHR miss cycles 818system.cpu.dcache.demand_mshr_miss_latency::total 45574361254 # number of demand (read+write) MSHR miss cycles 819system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45574575754 # number of overall MSHR miss cycles 820system.cpu.dcache.overall_mshr_miss_latency::total 45574575754 # number of overall MSHR miss cycles 821system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223589 # mshr miss rate for ReadReq accesses 822system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223589 # mshr miss rate for ReadReq accesses 823system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046987 # mshr miss rate for WriteReq accesses 824system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046987 # mshr miss rate for WriteReq accesses 825system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses 826system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses 827system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses 828system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses 829system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses 830system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses 831system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8247.586956 # average ReadReq mshr miss latency 832system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8247.586956 # average ReadReq mshr miss latency 833system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10272.978075 # average WriteReq mshr miss latency 834system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10272.978075 # average WriteReq mshr miss latency 835system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53625 # average SoftPFReq mshr miss latency 836system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53625 # average SoftPFReq mshr miss latency 837system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8329.949445 # average overall mshr miss latency 838system.cpu.dcache.demand_avg_mshr_miss_latency::total 8329.949445 # average overall mshr miss latency 839system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8329.982560 # average overall mshr miss latency 840system.cpu.dcache.overall_avg_mshr_miss_latency::total 8329.982560 # average overall mshr miss latency 841system.cpu.icache.tags.replacements 447 # number of replacements 842system.cpu.icache.tags.tagsinuse 427.448157 # Cycle average of tags in use 843system.cpu.icache.tags.total_refs 32273898 # Total number of references to valid blocks. 844system.cpu.icache.tags.sampled_refs 904 # Sample count of references to valid blocks. 845system.cpu.icache.tags.avg_refs 35701.214602 # Average number of references to valid blocks. 846system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 847system.cpu.icache.tags.occ_blocks::cpu.inst 427.448157 # Average occupied blocks per requestor 848system.cpu.icache.tags.occ_percent::cpu.inst 0.834860 # Average percentage of cache occupancy 849system.cpu.icache.tags.occ_percent::total 0.834860 # Average percentage of cache occupancy 850system.cpu.icache.tags.occ_task_id_blocks::1024 457 # Occupied blocks per task id 851system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 852system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 853system.cpu.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id 854system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id 855system.cpu.icache.tags.occ_task_id_percent::1024 0.892578 # Percentage of cache occupancy per task id 856system.cpu.icache.tags.tag_accesses 64550990 # Number of tag accesses 857system.cpu.icache.tags.data_accesses 64550990 # Number of data accesses 858system.cpu.icache.ReadReq_hits::cpu.inst 32273898 # number of ReadReq hits 859system.cpu.icache.ReadReq_hits::total 32273898 # number of ReadReq hits 860system.cpu.icache.demand_hits::cpu.inst 32273898 # number of demand (read+write) hits 861system.cpu.icache.demand_hits::total 32273898 # number of demand (read+write) hits 862system.cpu.icache.overall_hits::cpu.inst 32273898 # number of overall hits 863system.cpu.icache.overall_hits::total 32273898 # number of overall hits 864system.cpu.icache.ReadReq_misses::cpu.inst 1145 # number of ReadReq misses 865system.cpu.icache.ReadReq_misses::total 1145 # number of ReadReq misses 866system.cpu.icache.demand_misses::cpu.inst 1145 # number of demand (read+write) misses 867system.cpu.icache.demand_misses::total 1145 # number of demand (read+write) misses 868system.cpu.icache.overall_misses::cpu.inst 1145 # number of overall misses 869system.cpu.icache.overall_misses::total 1145 # number of overall misses 870system.cpu.icache.ReadReq_miss_latency::cpu.inst 60302481 # number of ReadReq miss cycles 871system.cpu.icache.ReadReq_miss_latency::total 60302481 # number of ReadReq miss cycles 872system.cpu.icache.demand_miss_latency::cpu.inst 60302481 # number of demand (read+write) miss cycles 873system.cpu.icache.demand_miss_latency::total 60302481 # number of demand (read+write) miss cycles 874system.cpu.icache.overall_miss_latency::cpu.inst 60302481 # number of overall miss cycles 875system.cpu.icache.overall_miss_latency::total 60302481 # number of overall miss cycles 876system.cpu.icache.ReadReq_accesses::cpu.inst 32275043 # number of ReadReq accesses(hits+misses) 877system.cpu.icache.ReadReq_accesses::total 32275043 # number of ReadReq accesses(hits+misses) 878system.cpu.icache.demand_accesses::cpu.inst 32275043 # number of demand (read+write) accesses 879system.cpu.icache.demand_accesses::total 32275043 # number of demand (read+write) accesses 880system.cpu.icache.overall_accesses::cpu.inst 32275043 # number of overall (read+write) accesses 881system.cpu.icache.overall_accesses::total 32275043 # number of overall (read+write) accesses 882system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses 883system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses 884system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses 885system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses 886system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses 887system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses 888system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52665.922271 # average ReadReq miss latency 889system.cpu.icache.ReadReq_avg_miss_latency::total 52665.922271 # average ReadReq miss latency 890system.cpu.icache.demand_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency 891system.cpu.icache.demand_avg_miss_latency::total 52665.922271 # average overall miss latency 892system.cpu.icache.overall_avg_miss_latency::cpu.inst 52665.922271 # average overall miss latency 893system.cpu.icache.overall_avg_miss_latency::total 52665.922271 # average overall miss latency 894system.cpu.icache.blocked_cycles::no_mshrs 18953 # number of cycles access was blocked 895system.cpu.icache.blocked_cycles::no_targets 107 # number of cycles access was blocked 896system.cpu.icache.blocked::no_mshrs 219 # number of cycles access was blocked 897system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked 898system.cpu.icache.avg_blocked_cycles::no_mshrs 86.543379 # average number of cycles each access was blocked 899system.cpu.icache.avg_blocked_cycles::no_targets 21.400000 # average number of cycles each access was blocked 900system.cpu.icache.writebacks::writebacks 447 # number of writebacks 901system.cpu.icache.writebacks::total 447 # number of writebacks 902system.cpu.icache.ReadReq_mshr_hits::cpu.inst 240 # number of ReadReq MSHR hits 903system.cpu.icache.ReadReq_mshr_hits::total 240 # number of ReadReq MSHR hits 904system.cpu.icache.demand_mshr_hits::cpu.inst 240 # number of demand (read+write) MSHR hits 905system.cpu.icache.demand_mshr_hits::total 240 # number of demand (read+write) MSHR hits 906system.cpu.icache.overall_mshr_hits::cpu.inst 240 # number of overall MSHR hits 907system.cpu.icache.overall_mshr_hits::total 240 # number of overall MSHR hits 908system.cpu.icache.ReadReq_mshr_misses::cpu.inst 905 # number of ReadReq MSHR misses 909system.cpu.icache.ReadReq_mshr_misses::total 905 # number of ReadReq MSHR misses 910system.cpu.icache.demand_mshr_misses::cpu.inst 905 # number of demand (read+write) MSHR misses 911system.cpu.icache.demand_mshr_misses::total 905 # number of demand (read+write) MSHR misses 912system.cpu.icache.overall_mshr_misses::cpu.inst 905 # number of overall MSHR misses 913system.cpu.icache.overall_mshr_misses::total 905 # number of overall MSHR misses 914system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49734485 # number of ReadReq MSHR miss cycles 915system.cpu.icache.ReadReq_mshr_miss_latency::total 49734485 # number of ReadReq MSHR miss cycles 916system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49734485 # number of demand (read+write) MSHR miss cycles 917system.cpu.icache.demand_mshr_miss_latency::total 49734485 # number of demand (read+write) MSHR miss cycles 918system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49734485 # number of overall MSHR miss cycles 919system.cpu.icache.overall_mshr_miss_latency::total 49734485 # number of overall MSHR miss cycles 920system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses 921system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses 922system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses 923system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses 924system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses 925system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses 926system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54955.232044 # average ReadReq mshr miss latency 927system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54955.232044 # average ReadReq mshr miss latency 928system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 929system.cpu.icache.demand_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency 930system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54955.232044 # average overall mshr miss latency 931system.cpu.icache.overall_avg_mshr_miss_latency::total 54955.232044 # average overall mshr miss latency 932system.cpu.l2cache.prefetcher.num_hwpf_issued 4981065 # number of hwpf issued 933system.cpu.l2cache.prefetcher.pfIdentified 5296247 # number of prefetch candidates identified 934system.cpu.l2cache.prefetcher.pfBufferHit 274020 # number of redundant prefetches already in prefetch queue 935system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 936system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 937system.cpu.l2cache.prefetcher.pfSpanPage 14074841 # number of prefetches not generated due to page crossing 938system.cpu.l2cache.tags.replacements 248 # number of replacements 939system.cpu.l2cache.tags.tagsinuse 11235.818499 # Cycle average of tags in use 940system.cpu.l2cache.tags.total_refs 5318374 # Total number of references to valid blocks. 941system.cpu.l2cache.tags.sampled_refs 14915 # Sample count of references to valid blocks. 942system.cpu.l2cache.tags.avg_refs 356.578880 # Average number of references to valid blocks. 943system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 944system.cpu.l2cache.tags.occ_blocks::writebacks 11061.516911 # Average occupied blocks per requestor 945system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 174.301588 # Average occupied blocks per requestor 946system.cpu.l2cache.tags.occ_percent::writebacks 0.675141 # Average percentage of cache occupancy 947system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010639 # Average percentage of cache occupancy 948system.cpu.l2cache.tags.occ_percent::total 0.685780 # Average percentage of cache occupancy 949system.cpu.l2cache.tags.occ_task_id_blocks::1022 181 # Occupied blocks per task id 950system.cpu.l2cache.tags.occ_task_id_blocks::1024 14486 # Occupied blocks per task id 951system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 952system.cpu.l2cache.tags.age_task_id_blocks_1022::2 3 # Occupied blocks per task id 953system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id 954system.cpu.l2cache.tags.age_task_id_blocks_1022::4 168 # Occupied blocks per task id 955system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id 956system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3489 # Occupied blocks per task id 957system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9544 # Occupied blocks per task id 958system.cpu.l2cache.tags.age_task_id_blocks_1024::3 100 # Occupied blocks per task id 959system.cpu.l2cache.tags.age_task_id_blocks_1024::4 884 # Occupied blocks per task id 960system.cpu.l2cache.tags.occ_task_id_percent::1022 0.011047 # Percentage of cache occupancy per task id 961system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884155 # Percentage of cache occupancy per task id 962system.cpu.l2cache.tags.tag_accesses 180510207 # Number of tag accesses 963system.cpu.l2cache.tags.data_accesses 180510207 # Number of data accesses 964system.cpu.l2cache.WritebackDirty_hits::writebacks 5451171 # number of WritebackDirty hits 965system.cpu.l2cache.WritebackDirty_hits::total 5451171 # number of WritebackDirty hits 966system.cpu.l2cache.WritebackClean_hits::writebacks 17033 # number of WritebackClean hits 967system.cpu.l2cache.WritebackClean_hits::total 17033 # number of WritebackClean hits 968system.cpu.l2cache.ReadExReq_hits::cpu.data 226019 # number of ReadExReq hits 969system.cpu.l2cache.ReadExReq_hits::total 226019 # number of ReadExReq hits 970system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 210 # number of ReadCleanReq hits 971system.cpu.l2cache.ReadCleanReq_hits::total 210 # number of ReadCleanReq hits 972system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5243562 # number of ReadSharedReq hits 973system.cpu.l2cache.ReadSharedReq_hits::total 5243562 # number of ReadSharedReq hits 974system.cpu.l2cache.demand_hits::cpu.inst 210 # number of demand (read+write) hits 975system.cpu.l2cache.demand_hits::cpu.data 5469581 # number of demand (read+write) hits 976system.cpu.l2cache.demand_hits::total 5469791 # number of demand (read+write) hits 977system.cpu.l2cache.overall_hits::cpu.inst 210 # number of overall hits 978system.cpu.l2cache.overall_hits::cpu.data 5469581 # number of overall hits 979system.cpu.l2cache.overall_hits::total 5469791 # number of overall hits 980system.cpu.l2cache.UpgradeReq_misses::cpu.data 3 # number of UpgradeReq misses 981system.cpu.l2cache.UpgradeReq_misses::total 3 # number of UpgradeReq misses 982system.cpu.l2cache.ReadExReq_misses::cpu.data 500 # number of ReadExReq misses 983system.cpu.l2cache.ReadExReq_misses::total 500 # number of ReadExReq misses 984system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 695 # number of ReadCleanReq misses 985system.cpu.l2cache.ReadCleanReq_misses::total 695 # number of ReadCleanReq misses 986system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1065 # number of ReadSharedReq misses 987system.cpu.l2cache.ReadSharedReq_misses::total 1065 # number of ReadSharedReq misses 988system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses 989system.cpu.l2cache.demand_misses::cpu.data 1565 # number of demand (read+write) misses 990system.cpu.l2cache.demand_misses::total 2260 # number of demand (read+write) misses 991system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses 992system.cpu.l2cache.overall_misses::cpu.data 1565 # number of overall misses 993system.cpu.l2cache.overall_misses::total 2260 # number of overall misses 994system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 59500 # number of UpgradeReq miss cycles 995system.cpu.l2cache.UpgradeReq_miss_latency::total 59500 # number of UpgradeReq miss cycles 996system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41259500 # number of ReadExReq miss cycles 997system.cpu.l2cache.ReadExReq_miss_latency::total 41259500 # number of ReadExReq miss cycles 998system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 47414000 # number of ReadCleanReq miss cycles 999system.cpu.l2cache.ReadCleanReq_miss_latency::total 47414000 # number of ReadCleanReq miss cycles 1000system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71274500 # number of ReadSharedReq miss cycles 1001system.cpu.l2cache.ReadSharedReq_miss_latency::total 71274500 # number of ReadSharedReq miss cycles 1002system.cpu.l2cache.demand_miss_latency::cpu.inst 47414000 # number of demand (read+write) miss cycles 1003system.cpu.l2cache.demand_miss_latency::cpu.data 112534000 # number of demand (read+write) miss cycles 1004system.cpu.l2cache.demand_miss_latency::total 159948000 # number of demand (read+write) miss cycles 1005system.cpu.l2cache.overall_miss_latency::cpu.inst 47414000 # number of overall miss cycles 1006system.cpu.l2cache.overall_miss_latency::cpu.data 112534000 # number of overall miss cycles 1007system.cpu.l2cache.overall_miss_latency::total 159948000 # number of overall miss cycles 1008system.cpu.l2cache.WritebackDirty_accesses::writebacks 5451171 # number of WritebackDirty accesses(hits+misses) 1009system.cpu.l2cache.WritebackDirty_accesses::total 5451171 # number of WritebackDirty accesses(hits+misses) 1010system.cpu.l2cache.WritebackClean_accesses::writebacks 17033 # number of WritebackClean accesses(hits+misses) 1011system.cpu.l2cache.WritebackClean_accesses::total 17033 # number of WritebackClean accesses(hits+misses) 1012system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3 # number of UpgradeReq accesses(hits+misses) 1013system.cpu.l2cache.UpgradeReq_accesses::total 3 # number of UpgradeReq accesses(hits+misses) 1014system.cpu.l2cache.ReadExReq_accesses::cpu.data 226519 # number of ReadExReq accesses(hits+misses) 1015system.cpu.l2cache.ReadExReq_accesses::total 226519 # number of ReadExReq accesses(hits+misses) 1016system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 905 # number of ReadCleanReq accesses(hits+misses) 1017system.cpu.l2cache.ReadCleanReq_accesses::total 905 # number of ReadCleanReq accesses(hits+misses) 1018system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 5244627 # number of ReadSharedReq accesses(hits+misses) 1019system.cpu.l2cache.ReadSharedReq_accesses::total 5244627 # number of ReadSharedReq accesses(hits+misses) 1020system.cpu.l2cache.demand_accesses::cpu.inst 905 # number of demand (read+write) accesses 1021system.cpu.l2cache.demand_accesses::cpu.data 5471146 # number of demand (read+write) accesses 1022system.cpu.l2cache.demand_accesses::total 5472051 # number of demand (read+write) accesses 1023system.cpu.l2cache.overall_accesses::cpu.inst 905 # number of overall (read+write) accesses 1024system.cpu.l2cache.overall_accesses::cpu.data 5471146 # number of overall (read+write) accesses 1025system.cpu.l2cache.overall_accesses::total 5472051 # number of overall (read+write) accesses 1026system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1027system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1028system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002207 # miss rate for ReadExReq accesses 1029system.cpu.l2cache.ReadExReq_miss_rate::total 0.002207 # miss rate for ReadExReq accesses 1030system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.767956 # miss rate for ReadCleanReq accesses 1031system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.767956 # miss rate for ReadCleanReq accesses 1032system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000203 # miss rate for ReadSharedReq accesses 1033system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000203 # miss rate for ReadSharedReq accesses 1034system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767956 # miss rate for demand accesses 1035system.cpu.l2cache.demand_miss_rate::cpu.data 0.000286 # miss rate for demand accesses 1036system.cpu.l2cache.demand_miss_rate::total 0.000413 # miss rate for demand accesses 1037system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767956 # miss rate for overall accesses 1038system.cpu.l2cache.overall_miss_rate::cpu.data 0.000286 # miss rate for overall accesses 1039system.cpu.l2cache.overall_miss_rate::total 0.000413 # miss rate for overall accesses 1040system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 19833.333333 # average UpgradeReq miss latency 1041system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 19833.333333 # average UpgradeReq miss latency 1042system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82519 # average ReadExReq miss latency 1043system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82519 # average ReadExReq miss latency 1044system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 68221.582734 # average ReadCleanReq miss latency 1045system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 68221.582734 # average ReadCleanReq miss latency 1046system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66924.413146 # average ReadSharedReq miss latency 1047system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66924.413146 # average ReadSharedReq miss latency 1048system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency 1049system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency 1050system.cpu.l2cache.demand_avg_miss_latency::total 70773.451327 # average overall miss latency 1051system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68221.582734 # average overall miss latency 1052system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71906.709265 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::total 70773.451327 # average overall miss latency 1054system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1055system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1056system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1057system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1058system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1059system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1060system.cpu.l2cache.unused_prefetches 7 # number of HardPF blocks evicted w/o reference 1061system.cpu.l2cache.writebacks::writebacks 175 # number of writebacks 1062system.cpu.l2cache.writebacks::total 175 # number of writebacks 1063system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits 1064system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits 1065system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1066system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1067system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 37 # number of ReadSharedReq MSHR hits 1068system.cpu.l2cache.ReadSharedReq_mshr_hits::total 37 # number of ReadSharedReq MSHR hits 1069system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1070system.cpu.l2cache.demand_mshr_hits::cpu.data 195 # number of demand (read+write) MSHR hits 1071system.cpu.l2cache.demand_mshr_hits::total 196 # number of demand (read+write) MSHR hits 1072system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1073system.cpu.l2cache.overall_mshr_hits::cpu.data 195 # number of overall MSHR hits 1074system.cpu.l2cache.overall_mshr_hits::total 196 # number of overall MSHR hits 1075system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316084 # number of HardPFReq MSHR misses 1076system.cpu.l2cache.HardPFReq_mshr_misses::total 316084 # number of HardPFReq MSHR misses 1077system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3 # number of UpgradeReq MSHR misses 1078system.cpu.l2cache.UpgradeReq_mshr_misses::total 3 # number of UpgradeReq MSHR misses 1079system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 342 # number of ReadExReq MSHR misses 1080system.cpu.l2cache.ReadExReq_mshr_misses::total 342 # number of ReadExReq MSHR misses 1081system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 694 # number of ReadCleanReq MSHR misses 1082system.cpu.l2cache.ReadCleanReq_mshr_misses::total 694 # number of ReadCleanReq MSHR misses 1083system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1028 # number of ReadSharedReq MSHR misses 1084system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1028 # number of ReadSharedReq MSHR misses 1085system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses 1086system.cpu.l2cache.demand_mshr_misses::cpu.data 1370 # number of demand (read+write) MSHR misses 1087system.cpu.l2cache.demand_mshr_misses::total 2064 # number of demand (read+write) MSHR misses 1088system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses 1089system.cpu.l2cache.overall_mshr_misses::cpu.data 1370 # number of overall MSHR misses 1090system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316084 # number of overall MSHR misses 1091system.cpu.l2cache.overall_mshr_misses::total 318148 # number of overall MSHR misses 1092system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of HardPFReq MSHR miss cycles 1093system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 852614747 # number of HardPFReq MSHR miss cycles 1094system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 41500 # number of UpgradeReq MSHR miss cycles 1095system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 41500 # number of UpgradeReq MSHR miss cycles 1096system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32745000 # number of ReadExReq MSHR miss cycles 1097system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32745000 # number of ReadExReq MSHR miss cycles 1098system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43196500 # number of ReadCleanReq MSHR miss cycles 1099system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43196500 # number of ReadCleanReq MSHR miss cycles 1100system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63614500 # number of ReadSharedReq MSHR miss cycles 1101system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63614500 # number of ReadSharedReq MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43196500 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 96359500 # number of demand (read+write) MSHR miss cycles 1104system.cpu.l2cache.demand_mshr_miss_latency::total 139556000 # number of demand (read+write) MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43196500 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 96359500 # number of overall MSHR miss cycles 1107system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 852614747 # number of overall MSHR miss cycles 1108system.cpu.l2cache.overall_mshr_miss_latency::total 992170747 # number of overall MSHR miss cycles 1109system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1110system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1111system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1112system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1113system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001510 # mshr miss rate for ReadExReq accesses 1114system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001510 # mshr miss rate for ReadExReq accesses 1115system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for ReadCleanReq accesses 1116system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.766851 # mshr miss rate for ReadCleanReq accesses 1117system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000196 # mshr miss rate for ReadSharedReq accesses 1118system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000196 # mshr miss rate for ReadSharedReq accesses 1119system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for demand accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for demand accesses 1121system.cpu.l2cache.demand_mshr_miss_rate::total 0.000377 # mshr miss rate for demand accesses 1122system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766851 # mshr miss rate for overall accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000250 # mshr miss rate for overall accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1125system.cpu.l2cache.overall_mshr_miss_rate::total 0.058141 # mshr miss rate for overall accesses 1126system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average HardPFReq mshr miss latency 1127system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 2697.430895 # average HardPFReq mshr miss latency 1128system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13833.333333 # average UpgradeReq mshr miss latency 1129system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13833.333333 # average UpgradeReq mshr miss latency 1130system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95745.614035 # average ReadExReq mshr miss latency 1131system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95745.614035 # average ReadExReq mshr miss latency 1132system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 62242.795389 # average ReadCleanReq mshr miss latency 1133system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62242.795389 # average ReadCleanReq mshr miss latency 1134system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61881.809339 # average ReadSharedReq mshr miss latency 1135system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61881.809339 # average ReadSharedReq mshr miss latency 1136system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency 1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency 1138system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67614.341085 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62242.795389 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70335.401460 # average overall mshr miss latency 1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 2697.430895 # average overall mshr miss latency 1142system.cpu.l2cache.overall_avg_mshr_miss_latency::total 3118.582380 # average overall mshr miss latency 1143system.cpu.toL2Bus.snoop_filter.tot_requests 10943135 # Total number of requests made to the snoop filter. 1144system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471097 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1145system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2877 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1146system.cpu.toL2Bus.snoop_filter.tot_snoops 303361 # Total number of snoops made to the snoop filter. 1147system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302576 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1148system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 785 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1149system.cpu.toL2Bus.trans_dist::ReadResp 5245531 # Transaction distribution 1150system.cpu.toL2Bus.trans_dist::WritebackDirty 5451346 # Transaction distribution 1151system.cpu.toL2Bus.trans_dist::WritebackClean 19910 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::CleanEvict 1794 # Transaction distribution 1153system.cpu.toL2Bus.trans_dist::HardPFReq 317966 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1155system.cpu.toL2Bus.trans_dist::UpgradeReq 3 # Transaction distribution 1156system.cpu.toL2Bus.trans_dist::UpgradeResp 3 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::ReadExReq 226519 # Transaction distribution 1158system.cpu.toL2Bus.trans_dist::ReadExResp 226519 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::ReadCleanReq 905 # Transaction distribution 1160system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244627 # Transaction distribution 1161system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2256 # Packet count per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) 1163system.cpu.toL2Bus.pkt_count::total 16415192 # Packet count per connected master and slave (bytes) 1164system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86464 # Cumulative packet size per connected master and slave (bytes) 1165system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274176 # Cumulative packet size per connected master and slave (bytes) 1166system.cpu.toL2Bus.pkt_size::total 700360640 # Cumulative packet size per connected master and slave (bytes) 1167system.cpu.toL2Bus.snoops 319939 # Total snoops (count) 1168system.cpu.toL2Bus.snoop_fanout::samples 5791989 # Request fanout histogram 1169system.cpu.toL2Bus.snoop_fanout::mean 0.053010 # Request fanout histogram 1170system.cpu.toL2Bus.snoop_fanout::stdev 0.224658 # Request fanout histogram 1171system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1172system.cpu.toL2Bus.snoop_fanout::0 5485738 94.71% 94.71% # Request fanout histogram 1173system.cpu.toL2Bus.snoop_fanout::1 305466 5.27% 99.99% # Request fanout histogram 1174system.cpu.toL2Bus.snoop_fanout::2 785 0.01% 100.00% # Request fanout histogram 1175system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1176system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1177system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1178system.cpu.toL2Bus.snoop_fanout::total 5791989 # Request fanout histogram 1179system.cpu.toL2Bus.reqLayer0.occupancy 10942648515 # Layer occupancy (ticks) 1180system.cpu.toL2Bus.reqLayer0.utilization 18.8 # Layer utilization (%) 1181system.cpu.toL2Bus.snoopLayer0.occupancy 6019 # Layer occupancy (ticks) 1182system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1183system.cpu.toL2Bus.respLayer0.occupancy 1357497 # Layer occupancy (ticks) 1184system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1185system.cpu.toL2Bus.respLayer1.occupancy 8206724991 # Layer occupancy (ticks) 1186system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) 1187system.membus.trans_dist::ReadResp 16175 # Transaction distribution 1188system.membus.trans_dist::WritebackDirty 175 # Transaction distribution 1189system.membus.trans_dist::CleanEvict 63 # Transaction distribution 1190system.membus.trans_dist::UpgradeReq 4 # Transaction distribution 1191system.membus.trans_dist::ReadExReq 341 # Transaction distribution 1192system.membus.trans_dist::ReadExResp 341 # Transaction distribution 1193system.membus.trans_dist::ReadSharedReq 16176 # Transaction distribution 1194system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 33275 # Packet count per connected master and slave (bytes) 1195system.membus.pkt_count::total 33275 # Packet count per connected master and slave (bytes) 1196system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1068224 # Cumulative packet size per connected master and slave (bytes) 1197system.membus.pkt_size::total 1068224 # Cumulative packet size per connected master and slave (bytes) 1198system.membus.snoops 0 # Total snoops (count) 1199system.membus.snoop_fanout::samples 16759 # Request fanout histogram 1200system.membus.snoop_fanout::mean 0 # Request fanout histogram 1201system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1202system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1203system.membus.snoop_fanout::0 16759 100.00% 100.00% # Request fanout histogram 1204system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1205system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1206system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1207system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1208system.membus.snoop_fanout::total 16759 # Request fanout histogram 1209system.membus.reqLayer0.occupancy 27529285 # Layer occupancy (ticks) 1210system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1211system.membus.respLayer1.occupancy 86434816 # Layer occupancy (ticks) 1212system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 1213 1214---------- End Simulation Statistics ---------- 1215