stats.txt revision 11680
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 47.405013 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 47405012960500 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 47405012960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711680SCurtis.Dunham@arm.comhost_inst_rate 480061 # Simulator instruction rate (inst/s) 811680SCurtis.Dunham@arm.comhost_op_rate 564722 # Simulator op (including micro ops) rate (op/s) 911680SCurtis.Dunham@arm.comhost_tick_rate 25874318289 # Simulator tick rate (ticks/s) 1011680SCurtis.Dunham@arm.comhost_mem_usage 758156 # Number of bytes of host memory used 1111680SCurtis.Dunham@arm.comhost_seconds 1832.13 # Real time elapsed on the host 1211680SCurtis.Dunham@arm.comsim_insts 879531552 # Number of instructions simulated 1311680SCurtis.Dunham@arm.comsim_ops 1034641707 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1711680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 107584 # Number of bytes read from this memory 1811680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 111616 # Number of bytes read from this memory 1911680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 3269620 # Number of bytes read from this memory 2011680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 13856200 # Number of bytes read from this memory 2111680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 15427200 # Number of bytes read from this memory 2211680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 122176 # Number of bytes read from this memory 2311680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 126272 # Number of bytes read from this memory 2411680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 2852024 # Number of bytes read from this memory 2511680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 9626320 # Number of bytes read from this memory 2611680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 10834112 # Number of bytes read from this memory 2711680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::realview.ide 432576 # Number of bytes read from this memory 2811680SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 56765700 # Number of bytes read from this memory 2911680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3269620 # Number of instructions bytes read from this memory 3011680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2852024 # Number of instructions bytes read from this memory 3111680SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 6121644 # Number of instructions bytes read from this memory 3211680SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 74832256 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3410585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3511680SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 74852840 # Number of bytes written to this memory 3611680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1681 # Number of read requests responded to by this memory 3711680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1744 # Number of read requests responded to by this memory 3811680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 91495 # Number of read requests responded to by this memory 3911680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 216516 # Number of read requests responded to by this memory 4011680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 241050 # Number of read requests responded to by this memory 4111680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1909 # Number of read requests responded to by this memory 4211680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1973 # Number of read requests responded to by this memory 4311680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 44651 # Number of read requests responded to by this memory 4411680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 150424 # Number of read requests responded to by this memory 4511680SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 169283 # Number of read requests responded to by this memory 4611680SCurtis.Dunham@arm.comsystem.physmem.num_reads::realview.ide 6759 # Number of read requests responded to by this memory 4711680SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 927485 # Number of read requests responded to by this memory 4811680SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 1169254 # Number of write requests responded to by this memory 4910827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 5010585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5111680SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 1171828 # Number of write requests responded to by this memory 5211680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2269 # Total read bandwidth from this memory (bytes/s) 5311680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2355 # Total read bandwidth from this memory (bytes/s) 5411680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 68972 # Total read bandwidth from this memory (bytes/s) 5511680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 292294 # Total read bandwidth from this memory (bytes/s) 5611680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 325434 # Total read bandwidth from this memory (bytes/s) 5711680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2577 # Total read bandwidth from this memory (bytes/s) 5811680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2664 # Total read bandwidth from this memory (bytes/s) 5911680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 60163 # Total read bandwidth from this memory (bytes/s) 6011680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 203065 # Total read bandwidth from this memory (bytes/s) 6111680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 228544 # Total read bandwidth from this memory (bytes/s) 6211680SCurtis.Dunham@arm.comsystem.physmem.bw_read::realview.ide 9125 # Total read bandwidth from this memory (bytes/s) 6311680SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 1197462 # Total read bandwidth from this memory (bytes/s) 6411680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 68972 # Instruction read bandwidth from this memory (bytes/s) 6511680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 60163 # Instruction read bandwidth from this memory (bytes/s) 6611680SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 129135 # Instruction read bandwidth from this memory (bytes/s) 6711680SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 1578573 # Write bandwidth from this memory (bytes/s) 6811570SCurtis.Dunham@arm.comsystem.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 6910585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 7011680SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 1579007 # Write bandwidth from this memory (bytes/s) 7111680SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 1578573 # Total bandwidth to/from this memory (bytes/s) 7211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2269 # Total bandwidth to/from this memory (bytes/s) 7311680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2355 # Total bandwidth to/from this memory (bytes/s) 7411680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 68972 # Total bandwidth to/from this memory (bytes/s) 7511680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 292728 # Total bandwidth to/from this memory (bytes/s) 7611680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 325434 # Total bandwidth to/from this memory (bytes/s) 7711680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2577 # Total bandwidth to/from this memory (bytes/s) 7811680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2664 # Total bandwidth to/from this memory (bytes/s) 7911680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 60163 # Total bandwidth to/from this memory (bytes/s) 8011680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 203066 # Total bandwidth to/from this memory (bytes/s) 8111680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 228544 # Total bandwidth to/from this memory (bytes/s) 8211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::realview.ide 9125 # Total bandwidth to/from this memory (bytes/s) 8311680SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 2776469 # Total bandwidth to/from this memory (bytes/s) 8411680SCurtis.Dunham@arm.comsystem.physmem.readReqs 927485 # Number of read requests accepted 8511680SCurtis.Dunham@arm.comsystem.physmem.writeReqs 1171828 # Number of write requests accepted 8611680SCurtis.Dunham@arm.comsystem.physmem.readBursts 927485 # Number of DRAM read bursts, including those serviced by the write queue 8711680SCurtis.Dunham@arm.comsystem.physmem.writeBursts 1171828 # Number of DRAM write bursts, including those merged in the write queue 8811680SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 59337472 # Total number of bytes read from DRAM 8911680SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 21568 # Total number of bytes read from write queue 9011680SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 74850880 # Total number of bytes written to DRAM 9111680SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 56765700 # Total read bytes from the system interface side 9211680SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 74852840 # Total written bytes from the system interface side 9311680SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 337 # Number of DRAM read bursts serviced by the write queue 9411680SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one 9511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 9611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 53188 # Per bank write bursts 9711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 58555 # Per bank write bursts 9811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 49548 # Per bank write bursts 9911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 58849 # Per bank write bursts 10011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 61060 # Per bank write bursts 10111680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 64213 # Per bank write bursts 10211680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 58593 # Per bank write bursts 10311680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 62574 # Per bank write bursts 10411680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 53530 # Per bank write bursts 10511680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 96457 # Per bank write bursts 10611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 50033 # Per bank write bursts 10711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 57571 # Per bank write bursts 10811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 47029 # Per bank write bursts 10911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 51615 # Per bank write bursts 11011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 49510 # Per bank write bursts 11111680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 54823 # Per bank write bursts 11211680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 69378 # Per bank write bursts 11311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 74382 # Per bank write bursts 11411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 69427 # Per bank write bursts 11511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 75087 # Per bank write bursts 11611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 76532 # Per bank write bursts 11711680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 78990 # Per bank write bursts 11811680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 75385 # Per bank write bursts 11911680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 77589 # Per bank write bursts 12011680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 70916 # Per bank write bursts 12111680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 76207 # Per bank write bursts 12211680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 70858 # Per bank write bursts 12311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 75862 # Per bank write bursts 12411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 66596 # Per bank write bursts 12511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 70423 # Per bank write bursts 12611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 68869 # Per bank write bursts 12711680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 73044 # Per bank write bursts 12810515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12911680SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 516 # Number of times write queue was full causing retry 13011680SCurtis.Dunham@arm.comsystem.physmem.totGap 47405009605000 # Total gap between requests 13110515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13310515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13410827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13610515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13711680SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 884260 # Read request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 14010515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14110827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14310515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14411680SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 1169254 # Write request sizes (log2) 14511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 645919 # What read queue length does an incoming req see 14611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 88942 # What read queue length does an incoming req see 14711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 42222 # What read queue length does an incoming req see 14811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 33520 # What read queue length does an incoming req see 14911680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 28634 # What read queue length does an incoming req see 15011680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 25074 # What read queue length does an incoming req see 15111680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 21962 # What read queue length does an incoming req see 15211680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 18312 # What read queue length does an incoming req see 15311680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 15502 # What read queue length does an incoming req see 15411680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 2962 # What read queue length does an incoming req see 15511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 1110 # What read queue length does an incoming req see 15611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 816 # What read queue length does an incoming req see 15711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 608 # What read queue length does an incoming req see 15811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 446 # What read queue length does an incoming req see 15911680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see 16011680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 249 # What read queue length does an incoming req see 16111680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 195 # What read queue length does an incoming req see 16211680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see 16311680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see 16411680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see 16511680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 16611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 17010628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19110515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 28620 # What write queue length does an incoming req see 19311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 36458 # What write queue length does an incoming req see 19411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 48218 # What write queue length does an incoming req see 19511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 54653 # What write queue length does an incoming req see 19611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 60726 # What write queue length does an incoming req see 19711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 63711 # What write queue length does an incoming req see 19811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 65994 # What write queue length does an incoming req see 19911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 67665 # What write queue length does an incoming req see 20011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 70176 # What write queue length does an incoming req see 20111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 70363 # What write queue length does an incoming req see 20211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 73600 # What write queue length does an incoming req see 20311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 75174 # What write queue length does an incoming req see 20411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 72029 # What write queue length does an incoming req see 20511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 70698 # What write queue length does an incoming req see 20611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 71278 # What write queue length does an incoming req see 20711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 75021 # What write queue length does an incoming req see 20811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 68576 # What write queue length does an incoming req see 20911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 65669 # What write queue length does an incoming req see 21011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 3787 # What write queue length does an incoming req see 21111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 2027 # What write queue length does an incoming req see 21211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 1477 # What write queue length does an incoming req see 21311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 1239 # What write queue length does an incoming req see 21411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see 21511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 975 # What write queue length does an incoming req see 21611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 1013 # What write queue length does an incoming req see 21711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 865 # What write queue length does an incoming req see 21811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 814 # What write queue length does an incoming req see 21911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 739 # What write queue length does an incoming req see 22011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 756 # What write queue length does an incoming req see 22111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 763 # What write queue length does an incoming req see 22211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 668 # What write queue length does an incoming req see 22311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 705 # What write queue length does an incoming req see 22411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 695 # What write queue length does an incoming req see 22511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 747 # What write queue length does an incoming req see 22611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 666 # What write queue length does an incoming req see 22711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 760 # What write queue length does an incoming req see 22811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 682 # What write queue length does an incoming req see 22911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 648 # What write queue length does an incoming req see 23011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 743 # What write queue length does an incoming req see 23111680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 716 # What write queue length does an incoming req see 23211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 785 # What write queue length does an incoming req see 23311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 937 # What write queue length does an incoming req see 23411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see 23511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 551 # What write queue length does an incoming req see 23611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 928 # What write queue length does an incoming req see 23711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 1380 # What write queue length does an incoming req see 23811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 1236 # What write queue length does an incoming req see 23911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 535 # What write queue length does an incoming req see 24011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 1170 # What write queue length does an incoming req see 24111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 929017 # Bytes accessed per row activation 24211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 144.440810 # Bytes accessed per row activation 24311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 98.331936 # Bytes accessed per row activation 24411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 191.352121 # Bytes accessed per row activation 24511680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 617371 66.45% 66.45% # Bytes accessed per row activation 24611680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 189527 20.40% 86.86% # Bytes accessed per row activation 24711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 44674 4.81% 91.66% # Bytes accessed per row activation 24811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 20356 2.19% 93.85% # Bytes accessed per row activation 24911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 14838 1.60% 95.45% # Bytes accessed per row activation 25011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 9142 0.98% 96.44% # Bytes accessed per row activation 25111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 6196 0.67% 97.10% # Bytes accessed per row activation 25211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 5371 0.58% 97.68% # Bytes accessed per row activation 25311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 21542 2.32% 100.00% # Bytes accessed per row activation 25411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 929017 # Bytes accessed per row activation 25511680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 60832 # Reads before turning the bus around for writes 25611680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 15.240992 # Reads before turning the bus around for writes 25711680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 130.606668 # Reads before turning the bus around for writes 25811680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 60830 100.00% 100.00% # Reads before turning the bus around for writes 25911353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 26011353Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 26111680SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 60832 # Reads before turning the bus around for writes 26211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 60832 # Writes before turning the bus around for reads 26311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 19.225819 # Writes before turning the bus around for reads 26411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 18.418138 # Writes before turning the bus around for reads 26511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 8.471341 # Writes before turning the bus around for reads 26611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-19 49295 81.03% 81.03% # Writes before turning the bus around for reads 26711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20-23 4521 7.43% 88.47% # Writes before turning the bus around for reads 26811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-27 2878 4.73% 93.20% # Writes before turning the bus around for reads 26911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28-31 1749 2.88% 96.07% # Writes before turning the bus around for reads 27011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-35 1023 1.68% 97.75% # Writes before turning the bus around for reads 27111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::36-39 226 0.37% 98.13% # Writes before turning the bus around for reads 27211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-43 91 0.15% 98.28% # Writes before turning the bus around for reads 27311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::44-47 113 0.19% 98.46% # Writes before turning the bus around for reads 27411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::48-51 47 0.08% 98.54% # Writes before turning the bus around for reads 27511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::52-55 23 0.04% 98.58% # Writes before turning the bus around for reads 27611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::56-59 10 0.02% 98.59% # Writes before turning the bus around for reads 27711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::60-63 42 0.07% 98.66% # Writes before turning the bus around for reads 27811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::64-67 494 0.81% 99.47% # Writes before turning the bus around for reads 27911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::68-71 82 0.13% 99.61% # Writes before turning the bus around for reads 28011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-75 51 0.08% 99.69% # Writes before turning the bus around for reads 28111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::76-79 57 0.09% 99.79% # Writes before turning the bus around for reads 28211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::80-83 26 0.04% 99.83% # Writes before turning the bus around for reads 28311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::84-87 3 0.00% 99.83% # Writes before turning the bus around for reads 28411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::88-91 1 0.00% 99.84% # Writes before turning the bus around for reads 28511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::92-95 4 0.01% 99.84% # Writes before turning the bus around for reads 28611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::96-99 2 0.00% 99.85% # Writes before turning the bus around for reads 28711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::100-103 5 0.01% 99.85% # Writes before turning the bus around for reads 28811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::104-107 4 0.01% 99.86% # Writes before turning the bus around for reads 28911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::108-111 14 0.02% 99.88% # Writes before turning the bus around for reads 29011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::116-119 2 0.00% 99.89% # Writes before turning the bus around for reads 29111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::124-127 3 0.00% 99.89% # Writes before turning the bus around for reads 29211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::128-131 21 0.03% 99.93% # Writes before turning the bus around for reads 29311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::132-135 3 0.00% 99.93% # Writes before turning the bus around for reads 29411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-139 2 0.00% 99.93% # Writes before turning the bus around for reads 29511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::140-143 13 0.02% 99.96% # Writes before turning the bus around for reads 29611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads 29711680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads 29811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::156-159 2 0.00% 99.97% # Writes before turning the bus around for reads 29911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads 30011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads 30111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads 30211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::180-183 3 0.00% 99.98% # Writes before turning the bus around for reads 30311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads 30411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::192-195 2 0.00% 99.99% # Writes before turning the bus around for reads 30511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads 30611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads 30711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads 30811680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 60832 # Writes before turning the bus around for reads 30911680SCurtis.Dunham@arm.comsystem.physmem.totQLat 46218732203 # Total ticks spent queuing 31011680SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 63602757203 # Total ticks spent from burst creation until serviced by the DRAM 31111680SCurtis.Dunham@arm.comsystem.physmem.totBusLat 4635740000 # Total ticks spent in databus transfers 31211680SCurtis.Dunham@arm.comsystem.physmem.avgQLat 49850.44 # Average queueing delay per DRAM burst 31310515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31411680SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 68600.44 # Average memory access latency per DRAM burst 31511502SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s 31611606Sandreas.sandberg@arm.comsystem.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 31711680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s 31811606Sandreas.sandberg@arm.comsystem.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 31910515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 32011374Ssteve.reinhardt@amd.comsystem.physmem.busUtil 0.02 # Data bus utilization in percentage 32111201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 32210892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 32311680SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 32411680SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing 32511680SCurtis.Dunham@arm.comsystem.physmem.readRowHits 685692 # Number of row buffer hits during reads 32611680SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 481982 # Number of row buffer hits during writes 32711680SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads 32811680SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes 32911680SCurtis.Dunham@arm.comsystem.physmem.avgGap 22581201.38 # Average gap between requests 33011680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined 33111680SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 3446827860 # Energy for activate commands per rank (pJ) 33211680SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 1832028660 # Energy for precharge commands per rank (pJ) 33311680SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 3331381200 # Energy for read commands per rank (pJ) 33411680SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 3115139400 # Energy for write commands per rank (pJ) 33511680SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 41510941680.000008 # Energy for refresh commands per rank (pJ) 33611680SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 46501533090 # Energy for active background per rank (pJ) 33711680SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 2234866560 # Energy for precharge background per rank (pJ) 33811680SCurtis.Dunham@arm.comsystem.physmem_0.actPowerDownEnergy 80625696300 # Energy for active power-down per rank (pJ) 33911680SCurtis.Dunham@arm.comsystem.physmem_0.prePowerDownEnergy 57761558880 # Energy for precharge power-down per rank (pJ) 34011680SCurtis.Dunham@arm.comsystem.physmem_0.selfRefreshEnergy 11279719224960 # Energy for self refresh per rank (pJ) 34111680SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 11520096687780 # Total energy per rank (pJ) 34211680SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 243.014314 # Core power per rank (mW) 34311680SCurtis.Dunham@arm.comsystem.physmem_0.totalIdleTime 47297174723637 # Total Idle time Per DRAM Rank 34411680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 3911587994 # Time in different power states 34511680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 17636282000 # Time in different power states 34611680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::SREF 46969945639000 # Time in different power states 34711680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 150420602883 # Time in different power states 34811680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 86288423369 # Time in different power states 34911680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 176810425254 # Time in different power states 35011680SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 3186367800 # Energy for activate commands per rank (pJ) 35111680SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 1693590855 # Energy for precharge commands per rank (pJ) 35211680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 3288455520 # Energy for read commands per rank (pJ) 35311680SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 2989885500 # Energy for write commands per rank (pJ) 35411680SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 39461117280.000008 # Energy for refresh commands per rank (pJ) 35511680SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 47361781080 # Energy for active background per rank (pJ) 35611680SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 2153404320 # Energy for precharge background per rank (pJ) 35711680SCurtis.Dunham@arm.comsystem.physmem_1.actPowerDownEnergy 72224847060 # Energy for active power-down per rank (pJ) 35811680SCurtis.Dunham@arm.comsystem.physmem_1.prePowerDownEnergy 55366694400 # Energy for precharge power-down per rank (pJ) 35911680SCurtis.Dunham@arm.comsystem.physmem_1.selfRefreshEnergy 11285008491285 # Energy for self refresh per rank (pJ) 36011680SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 11512750460370 # Total energy per rank (pJ) 36111680SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 242.859346 # Core power per rank (mW) 36211680SCurtis.Dunham@arm.comsystem.physmem_1.totalIdleTime 47295506898407 # Total Idle time Per DRAM Rank 36311680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 3731843770 # Time in different power states 36411680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 16766470000 # Time in different power states 36511680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::SREF 46992934432500 # Time in different power states 36611680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 144184093324 # Time in different power states 36711680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 89007700573 # Time in different power states 36811680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 158388420333 # Time in different power states 36911680SCurtis.Dunham@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 37010515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 37110515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 37210515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 37310515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 37410515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 37510515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 37610515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 37710515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 37810515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 37910515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 38010515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 38110515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 38210515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 38310515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 38410515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 38510515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 38610515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 38710515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 38810515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 38910515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 39010515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 39110515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 39210515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 39310515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 39410515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 39510515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 39611680SCurtis.Dunham@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 39711680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 39811680SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 39910535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 40010535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 40110535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 40211680SCurtis.Dunham@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 40311680SCurtis.Dunham@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 40411680SCurtis.Dunham@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 40510515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 40611680SCurtis.Dunham@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 40710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 40910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 41010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 41110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 41310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 41410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 41610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 41710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 41810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 41910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 42010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 42110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 42210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 42310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 42410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 42510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 42610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 42710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 42810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 42910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 43010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 43110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 43210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 43310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 43410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 43510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 43611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 43711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walks 110745 # Table walker walks requested 43811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLong 110745 # Table walker walks initiated with long descriptors 43911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10295 # Level at which table walker walks with long descriptors terminate 44011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84545 # Level at which table walker walks with long descriptors terminate 44111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting 44211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 110723 # Table walker wait (enqueue to first request) latency 44311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.234820 # Table walker wait (enqueue to first request) latency 44411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 78.136585 # Table walker wait (enqueue to first request) latency 44511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-2047 110722 100.00% 100.00% # Table walker wait (enqueue to first request) latency 44611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 44711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 110723 # Table walker wait (enqueue to first request) latency 44811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 94862 # Table walker service (enqueue to completion) latency 44911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 23879.314162 # Table walker service (enqueue to completion) latency 45011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 22054.085361 # Table walker service (enqueue to completion) latency 45111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 16759.177694 # Table walker service (enqueue to completion) latency 45211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 93763 98.84% 98.84% # Table walker service (enqueue to completion) latency 45311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 840 0.89% 99.73% # Table walker service (enqueue to completion) latency 45411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 113 0.12% 99.85% # Table walker service (enqueue to completion) latency 45511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency 45611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.96% # Table walker service (enqueue to completion) latency 45711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.98% # Table walker service (enqueue to completion) latency 45811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency 45911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 46011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 46111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.01% 100.00% # Table walker service (enqueue to completion) latency 46211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 94862 # Table walker service (enqueue to completion) latency 46311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::samples -2682325288 # Table walker pending requests distribution 46411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::mean 2.121047 # Table walker pending requests distribution 46511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution 46611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::0 3007013124 -112.10% -112.10% # Table walker pending requests distribution 46711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::1 -5689338412 212.10% 100.00% # Table walker pending requests distribution 46811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walksPending::total -2682325288 # Table walker pending requests distribution 46911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 84546 89.14% 89.14% # Table walker page sizes translated 47011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10295 10.86% 100.00% # Table walker page sizes translated 47111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 94841 # Table walker page sizes translated 47211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 110745 # Table walker requests started/completed, data/inst 47310628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 110745 # Table walker requests started/completed, data/inst 47511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94841 # Table walker requests started/completed, data/inst 47610628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94841 # Table walker requests started/completed, data/inst 47811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 205586 # Table walker requests started/completed, data/inst 47910535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 48010535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 48111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 86849149 # DTB read hits 48211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 83538 # DTB read misses 48311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 78785461 # DTB write hits 48411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 27207 # DTB write misses 48510535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 48610535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID 48811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 48911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.flush_entries 37555 # Number of entries that have been flushed from TLB 49010535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 49111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.prefetch_faults 4746 # Number of TLB faults due to prefetch 49210535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 49311680SCurtis.Dunham@arm.comsystem.cpu0.dtb.perms_faults 9443 # Number of TLB faults due to permissions restrictions 49411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 86932687 # DTB read accesses 49511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 78812668 # DTB write accesses 49610535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 49711680SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 165634610 # DTB hits 49811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.misses 110745 # DTB misses 49911680SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 165745355 # DTB accesses 50011680SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 50110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 50210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 50310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 50410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 50510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 50610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 50710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 50810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 51110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 51310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 51410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 51510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 51710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 52110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 52210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 52310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 52510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 52610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 52710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 52810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 52910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 53011680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 53111680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walks 57780 # Table walker walks requested 53211680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLong 57780 # Table walker walks initiated with long descriptors 53311680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 572 # Level at which table walker walks with long descriptors terminate 53411680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 51544 # Level at which table walker walks with long descriptors terminate 53511680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 57780 # Table walker wait (enqueue to first request) latency 53611680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 57780 100.00% 100.00% # Table walker wait (enqueue to first request) latency 53711680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 57780 # Table walker wait (enqueue to first request) latency 53811680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 52116 # Table walker service (enqueue to completion) latency 53911680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 25803.102694 # Table walker service (enqueue to completion) latency 54011680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23425.328726 # Table walker service (enqueue to completion) latency 54111680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 22386.426518 # Table walker service (enqueue to completion) latency 54211680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 51056 97.97% 97.97% # Table walker service (enqueue to completion) latency 54311680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 692 1.33% 99.29% # Table walker service (enqueue to completion) latency 54411680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 219 0.42% 99.71% # Table walker service (enqueue to completion) latency 54511680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 60 0.12% 99.83% # Table walker service (enqueue to completion) latency 54611680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.10% 99.93% # Table walker service (enqueue to completion) latency 54711680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.95% # Table walker service (enqueue to completion) latency 54811680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.96% # Table walker service (enqueue to completion) latency 54911680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.96% # Table walker service (enqueue to completion) latency 55011680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency 55111680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 14 0.03% 99.99% # Table walker service (enqueue to completion) latency 55211680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 55311680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 52116 # Table walker service (enqueue to completion) latency 55411680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution 55511680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution 55611680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution 55711680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 51544 98.90% 98.90% # Table walker page sizes translated 55811680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 572 1.10% 100.00% # Table walker page sizes translated 55911680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 52116 # Table walker page sizes translated 56010628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 56111680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57780 # Table walker requests started/completed, data/inst 56211680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 57780 # Table walker requests started/completed, data/inst 56310628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 56411680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52116 # Table walker requests started/completed, data/inst 56511680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 52116 # Table walker requests started/completed, data/inst 56611680SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 109896 # Table walker requests started/completed, data/inst 56711680SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 463942995 # ITB inst hits 56811680SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_misses 57780 # ITB inst misses 56910535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 57010535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 57110535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 57210535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 57310535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 57410535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 57511680SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID 57611680SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 57711680SCurtis.Dunham@arm.comsystem.cpu0.itb.flush_entries 26477 # Number of entries that have been flushed from TLB 57810535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 57910535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 58010535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 58110535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 58210535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 58310535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 58411680SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 464000775 # ITB inst accesses 58511680SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 463942995 # DTB hits 58611680SCurtis.Dunham@arm.comsystem.cpu0.itb.misses 57780 # DTB misses 58711680SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 464000775 # DTB accesses 58811680SCurtis.Dunham@arm.comsystem.cpu0.numPwrStateTransitions 8984 # Number of power state transitions 58911680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::samples 4492 # Distribution of time spent in the clock gated state 59011680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::mean 10426010818.709705 # Distribution of time spent in the clock gated state 59111680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 169261679723.888153 # Distribution of time spent in the clock gated state 59211680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3260 72.57% 72.57% # Distribution of time spent in the clock gated state 59311680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 1205 26.83% 99.40% # Distribution of time spent in the clock gated state 59411680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 8 0.18% 99.58% # Distribution of time spent in the clock gated state 59511680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.60% # Distribution of time spent in the clock gated state 59611680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state 59711680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state 59811680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state 59911680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state 60011680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 12 0.27% 100.00% # Distribution of time spent in the clock gated state 60111570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 60211680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7033293863000 # Distribution of time spent in the clock gated state 60311680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::total 4492 # Distribution of time spent in the clock gated state 60411680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 571372362856 # Cumulative time (in ticks) in various power states 60511680SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46833640597644 # Cumulative time (in ticks) in various power states 60611680SCurtis.Dunham@arm.comsystem.cpu0.numCycles 94810025915 # number of cpu cycles simulated 60710535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 60810535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 60911167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 61011680SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 4492 # number of quiesce instructions executed 61111680SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 463690677 # Number of instructions committed 61211680SCurtis.Dunham@arm.comsystem.cpu0.committedOps 544305781 # Number of ops (including micro ops) committed 61311680SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 499985272 # Number of integer alu accesses 61411680SCurtis.Dunham@arm.comsystem.cpu0.num_fp_alu_accesses 430429 # Number of float alu accesses 61511680SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 27825312 # number of times a function call or return occured 61611680SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 70353837 # number of instructions that are conditional controls 61711680SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 499985272 # number of integer instructions 61811680SCurtis.Dunham@arm.comsystem.cpu0.num_fp_insts 430429 # number of float instructions 61911680SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 725660016 # number of times the integer registers were read 62011680SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 396645033 # number of times the integer registers were written 62111680SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_reads 713342 # number of times the floating registers were read 62211680SCurtis.Dunham@arm.comsystem.cpu0.num_fp_register_writes 322808 # number of times the floating registers were written 62311680SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_reads 121489824 # number of times the CC registers were read 62411680SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_writes 121106505 # number of times the CC registers were written 62511680SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 165624912 # number of memory refs 62611680SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 86844124 # Number of load instructions 62711680SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 78780788 # Number of store instructions 62811680SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 93667281189.358337 # Number of idle cycles 62911680SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 1142744725.641658 # Number of busy cycles 63011680SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 0.012053 # Percentage of non-idle cycles 63111680SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.987947 # Percentage of idle cycles 63211680SCurtis.Dunham@arm.comsystem.cpu0.Branches 103560532 # Number of branches fetched 63311680SCurtis.Dunham@arm.comsystem.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 63411680SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 377679680 69.35% 69.35% # Class of executed instruction 63511680SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 1190205 0.22% 69.57% # Class of executed instruction 63611680SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntDiv 61578 0.01% 69.58% # Class of executed instruction 63711680SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction 63811680SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction 63911680SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction 64011680SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction 64111680SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction 64211680SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction 64311680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction 64411680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction 64511680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction 64611680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction 64711680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction 64811680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction 64911680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction 65011680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction 65111680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction 65211680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction 65311680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction 65411680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction 65511680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction 65611680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction 65711680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction 65811680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction 65911680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMisc 44848 0.01% 69.59% # Class of executed instruction 66011680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction 66111680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction 66211680SCurtis.Dunham@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction 66311680SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemRead 86844124 15.95% 85.53% # Class of executed instruction 66411680SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemWrite 78780788 14.47% 100.00% # Class of executed instruction 66510535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 66610535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 66711680SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 544601223 # Class of executed instruction 66811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 66911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 5731745 # number of replacements 67011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 479.859189 # Cycle average of tags in use 67111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 159669170 # Total number of references to valid blocks. 67211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 5732255 # Sample count of references to valid blocks. 67311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 27.854513 # Average number of references to valid blocks. 67411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. 67511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 479.859189 # Average occupied blocks per requestor 67611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.937225 # Average percentage of cache occupancy 67711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.937225 # Average percentage of cache occupancy 67811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 67911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 68011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 68111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 452 # Occupied blocks per task id 68211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 68311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 337018109 # Number of tag accesses 68411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 337018109 # Number of data accesses 68511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 68611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 80850678 # number of ReadReq hits 68711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 80850678 # number of ReadReq hits 68811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 74290365 # number of WriteReq hits 68911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 74290365 # number of WriteReq hits 69011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 206988 # number of SoftPFReq hits 69111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 206988 # number of SoftPFReq hits 69211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 237888 # number of WriteLineReq hits 69311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 237888 # number of WriteLineReq hits 69411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1848102 # number of LoadLockedReq hits 69511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1848102 # number of LoadLockedReq hits 69611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1813975 # number of StoreCondReq hits 69711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1813975 # number of StoreCondReq hits 69811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 155378931 # number of demand (read+write) hits 69911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 155378931 # number of demand (read+write) hits 70011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 155585919 # number of overall hits 70111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 155585919 # number of overall hits 70211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3109712 # number of ReadReq misses 70311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3109712 # number of ReadReq misses 70411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1421405 # number of WriteReq misses 70511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1421405 # number of WriteReq misses 70611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 649654 # number of SoftPFReq misses 70711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 649654 # number of SoftPFReq misses 70811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 796576 # number of WriteLineReq misses 70911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 796576 # number of WriteLineReq misses 71011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167654 # number of LoadLockedReq misses 71111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 167654 # number of LoadLockedReq misses 71211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 200528 # number of StoreCondReq misses 71311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 200528 # number of StoreCondReq misses 71411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5327693 # number of demand (read+write) misses 71511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 5327693 # number of demand (read+write) misses 71611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5977347 # number of overall misses 71711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 5977347 # number of overall misses 71811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 48841831500 # number of ReadReq miss cycles 71911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 48841831500 # number of ReadReq miss cycles 72011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 30112535000 # number of WriteReq miss cycles 72111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 30112535000 # number of WriteReq miss cycles 72211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25700725500 # number of WriteLineReq miss cycles 72311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 25700725500 # number of WriteLineReq miss cycles 72411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2575322000 # number of LoadLockedReq miss cycles 72511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2575322000 # number of LoadLockedReq miss cycles 72611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4758884500 # number of StoreCondReq miss cycles 72711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4758884500 # number of StoreCondReq miss cycles 72811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2246000 # number of StoreCondFailReq miss cycles 72911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles 73011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 104655092000 # number of demand (read+write) miss cycles 73111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_latency::total 104655092000 # number of demand (read+write) miss cycles 73211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 104655092000 # number of overall miss cycles 73311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_latency::total 104655092000 # number of overall miss cycles 73411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 83960390 # number of ReadReq accesses(hits+misses) 73511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 83960390 # number of ReadReq accesses(hits+misses) 73611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 75711770 # number of WriteReq accesses(hits+misses) 73711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 75711770 # number of WriteReq accesses(hits+misses) 73811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 856642 # number of SoftPFReq accesses(hits+misses) 73911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 856642 # number of SoftPFReq accesses(hits+misses) 74011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1034464 # number of WriteLineReq accesses(hits+misses) 74111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1034464 # number of WriteLineReq accesses(hits+misses) 74211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015756 # number of LoadLockedReq accesses(hits+misses) 74311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2015756 # number of LoadLockedReq accesses(hits+misses) 74411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014503 # number of StoreCondReq accesses(hits+misses) 74511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2014503 # number of StoreCondReq accesses(hits+misses) 74611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 160706624 # number of demand (read+write) accesses 74711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 160706624 # number of demand (read+write) accesses 74811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 161563266 # number of overall (read+write) accesses 74911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 161563266 # number of overall (read+write) accesses 75011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037038 # miss rate for ReadReq accesses 75111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.037038 # miss rate for ReadReq accesses 75211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018774 # miss rate for WriteReq accesses 75311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018774 # miss rate for WriteReq accesses 75411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758373 # miss rate for SoftPFReq accesses 75511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.758373 # miss rate for SoftPFReq accesses 75611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.770037 # miss rate for WriteLineReq accesses 75711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.770037 # miss rate for WriteLineReq accesses 75811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083172 # miss rate for LoadLockedReq accesses 75911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083172 # miss rate for LoadLockedReq accesses 76011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses 76111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses 76211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.033152 # miss rate for demand accesses 76311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.033152 # miss rate for demand accesses 76411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.036997 # miss rate for overall accesses 76511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.036997 # miss rate for overall accesses 76611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15706.223438 # average ReadReq miss latency 76711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 15706.223438 # average ReadReq miss latency 76811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21185.049300 # average WriteReq miss latency 76911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 21185.049300 # average WriteReq miss latency 77011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32263.996781 # average WriteLineReq miss latency 77111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32263.996781 # average WriteLineReq miss latency 77211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.933828 # average LoadLockedReq miss latency 77311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.933828 # average LoadLockedReq miss latency 77411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23731.770626 # average StoreCondReq miss latency 77511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23731.770626 # average StoreCondReq miss latency 77610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 77710535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 77811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19643.604089 # average overall miss latency 77911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19643.604089 # average overall miss latency 78011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17508.619125 # average overall miss latency 78111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 17508.619125 # average overall miss latency 78210535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 78310535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78410535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 78510535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 78610535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 78710535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 78811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 5731745 # number of writebacks 78911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 5731745 # number of writebacks 79011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26385 # number of ReadReq MSHR hits 79111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 26385 # number of ReadReq MSHR hits 79211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21245 # number of WriteReq MSHR hits 79311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21245 # number of WriteReq MSHR hits 79411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44162 # number of LoadLockedReq MSHR hits 79511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 44162 # number of LoadLockedReq MSHR hits 79611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 47630 # number of demand (read+write) MSHR hits 79711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 47630 # number of demand (read+write) MSHR hits 79811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 47630 # number of overall MSHR hits 79911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 47630 # number of overall MSHR hits 80011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3083327 # number of ReadReq MSHR misses 80111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3083327 # number of ReadReq MSHR misses 80211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1400160 # number of WriteReq MSHR misses 80311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1400160 # number of WriteReq MSHR misses 80411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648080 # number of SoftPFReq MSHR misses 80511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 648080 # number of SoftPFReq MSHR misses 80611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796576 # number of WriteLineReq MSHR misses 80711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 796576 # number of WriteLineReq MSHR misses 80811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123492 # number of LoadLockedReq MSHR misses 80911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 123492 # number of LoadLockedReq MSHR misses 81011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200528 # number of StoreCondReq MSHR misses 81111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 200528 # number of StoreCondReq MSHR misses 81211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 5280063 # number of demand (read+write) MSHR misses 81311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 5280063 # number of demand (read+write) MSHR misses 81411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5928143 # number of overall MSHR misses 81511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5928143 # number of overall MSHR misses 81611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable 81711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 16381 # number of ReadReq MSHR uncacheable 81811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable 81911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable 82011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses 82111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 34075 # number of overall MSHR uncacheable misses 82211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44323294000 # number of ReadReq MSHR miss cycles 82311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 44323294000 # number of ReadReq MSHR miss cycles 82411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28148510000 # number of WriteReq MSHR miss cycles 82511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 28148510000 # number of WriteReq MSHR miss cycles 82611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14944693500 # number of SoftPFReq MSHR miss cycles 82711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14944693500 # number of SoftPFReq MSHR miss cycles 82811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24904149500 # number of WriteLineReq MSHR miss cycles 82911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24904149500 # number of WriteLineReq MSHR miss cycles 83011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1681387500 # number of LoadLockedReq MSHR miss cycles 83111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1681387500 # number of LoadLockedReq MSHR miss cycles 83211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4558410500 # number of StoreCondReq MSHR miss cycles 83311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4558410500 # number of StoreCondReq MSHR miss cycles 83411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2192000 # number of StoreCondFailReq MSHR miss cycles 83511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2192000 # number of StoreCondFailReq MSHR miss cycles 83611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 97375953500 # number of demand (read+write) MSHR miss cycles 83711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 97375953500 # number of demand (read+write) MSHR miss cycles 83811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112320647000 # number of overall MSHR miss cycles 83911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 112320647000 # number of overall MSHR miss cycles 84011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3040589500 # number of ReadReq MSHR uncacheable cycles 84111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3040589500 # number of ReadReq MSHR uncacheable cycles 84211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3040589500 # number of overall MSHR uncacheable cycles 84311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 3040589500 # number of overall MSHR uncacheable cycles 84411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036724 # mshr miss rate for ReadReq accesses 84511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036724 # mshr miss rate for ReadReq accesses 84611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018493 # mshr miss rate for WriteReq accesses 84711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018493 # mshr miss rate for WriteReq accesses 84811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756535 # mshr miss rate for SoftPFReq accesses 84911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756535 # mshr miss rate for SoftPFReq accesses 85011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.770037 # mshr miss rate for WriteLineReq accesses 85111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.770037 # mshr miss rate for WriteLineReq accesses 85211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061263 # mshr miss rate for LoadLockedReq accesses 85311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061263 # mshr miss rate for LoadLockedReq accesses 85411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099542 # mshr miss rate for StoreCondReq accesses 85511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099542 # mshr miss rate for StoreCondReq accesses 85611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032855 # mshr miss rate for demand accesses 85711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.032855 # mshr miss rate for demand accesses 85811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036692 # mshr miss rate for overall accesses 85911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.036692 # mshr miss rate for overall accesses 86011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14375.151906 # average ReadReq mshr miss latency 86111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14375.151906 # average ReadReq mshr miss latency 86211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20103.780996 # average WriteReq mshr miss latency 86311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20103.780996 # average WriteReq mshr miss latency 86411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23059.951703 # average SoftPFReq mshr miss latency 86511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23059.951703 # average SoftPFReq mshr miss latency 86611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31263.996781 # average WriteLineReq mshr miss latency 86711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31263.996781 # average WriteLineReq mshr miss latency 86811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13615.355651 # average LoadLockedReq mshr miss latency 86911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13615.355651 # average LoadLockedReq mshr miss latency 87011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22732.039915 # average StoreCondReq mshr miss latency 87111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22732.039915 # average StoreCondReq mshr miss latency 87210535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 87310535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 87411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18442.195387 # average overall mshr miss latency 87511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 18442.195387 # average overall mshr miss latency 87611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.020509 # average overall mshr miss latency 87711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.020509 # average overall mshr miss latency 87811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185616.842684 # average ReadReq mshr uncacheable latency 87911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185616.842684 # average ReadReq mshr uncacheable latency 88011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89232.267058 # average overall mshr uncacheable latency 88111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89232.267058 # average overall mshr uncacheable latency 88211680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 88311680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 4959559 # number of replacements 88411680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 511.903947 # Cycle average of tags in use 88511680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 458982923 # Total number of references to valid blocks. 88611680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 4960071 # Sample count of references to valid blocks. 88711680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 92.535555 # Average number of references to valid blocks. 88811680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 30768955000 # Cycle when the warmup percentage was hit. 88911680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903947 # Average occupied blocks per requestor 89011680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy 89111680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy 89210535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 89311680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 89411680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 89511680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id 89611680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 89710535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 89811680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 932846061 # Number of tag accesses 89911680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 932846061 # Number of data accesses 90011680SCurtis.Dunham@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 90111680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 458982923 # number of ReadReq hits 90211680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 458982923 # number of ReadReq hits 90311680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 458982923 # number of demand (read+write) hits 90411680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 458982923 # number of demand (read+write) hits 90511680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 458982923 # number of overall hits 90611680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 458982923 # number of overall hits 90711680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 4960072 # number of ReadReq misses 90811680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 4960072 # number of ReadReq misses 90911680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 4960072 # number of demand (read+write) misses 91011680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 4960072 # number of demand (read+write) misses 91111680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 4960072 # number of overall misses 91211680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 4960072 # number of overall misses 91311680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54306348500 # number of ReadReq miss cycles 91411680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 54306348500 # number of ReadReq miss cycles 91511680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 54306348500 # number of demand (read+write) miss cycles 91611680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_latency::total 54306348500 # number of demand (read+write) miss cycles 91711680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 54306348500 # number of overall miss cycles 91811680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_latency::total 54306348500 # number of overall miss cycles 91911680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 463942995 # number of ReadReq accesses(hits+misses) 92011680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 463942995 # number of ReadReq accesses(hits+misses) 92111680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 463942995 # number of demand (read+write) accesses 92211680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 463942995 # number of demand (read+write) accesses 92311680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 463942995 # number of overall (read+write) accesses 92411680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 463942995 # number of overall (read+write) accesses 92511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010691 # miss rate for ReadReq accesses 92611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.010691 # miss rate for ReadReq accesses 92711680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.010691 # miss rate for demand accesses 92811680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.010691 # miss rate for demand accesses 92911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.010691 # miss rate for overall accesses 93011680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.010691 # miss rate for overall accesses 93111680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.701652 # average ReadReq miss latency 93211680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10948.701652 # average ReadReq miss latency 93311680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency 93411680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10948.701652 # average overall miss latency 93511680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency 93611680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10948.701652 # average overall miss latency 93710535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 93810535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 93910535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 94010535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 94110535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 94210535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 94311680SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 4959559 # number of writebacks 94411680SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 4959559 # number of writebacks 94511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4960072 # number of ReadReq MSHR misses 94611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 4960072 # number of ReadReq MSHR misses 94711680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 4960072 # number of demand (read+write) MSHR misses 94811680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_misses::total 4960072 # number of demand (read+write) MSHR misses 94911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 4960072 # number of overall MSHR misses 95011680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_misses::total 4960072 # number of overall MSHR misses 95110827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 95210827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 95310827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 95410827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 95511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51826313000 # number of ReadReq MSHR miss cycles 95611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 51826313000 # number of ReadReq MSHR miss cycles 95711680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51826313000 # number of demand (read+write) MSHR miss cycles 95811680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 51826313000 # number of demand (read+write) MSHR miss cycles 95911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51826313000 # number of overall MSHR miss cycles 96011680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 51826313000 # number of overall MSHR miss cycles 96111680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles 96211680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles 96311680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles 96411680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles 96511680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for ReadReq accesses 96611680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010691 # mshr miss rate for ReadReq accesses 96711680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for demand accesses 96811680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses 96911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for overall accesses 97011680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.010691 # mshr miss rate for overall accesses 97111680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average ReadReq mshr miss latency 97211680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10448.701753 # average ReadReq mshr miss latency 97311680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency 97411680SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency 97511680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency 97611680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency 97711680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency 97811680SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency 97911680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency 98011680SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency 98111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 98211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7732053 # number of hwpf issued 98311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7732077 # number of prefetch candidates identified 98411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue 98510628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98610628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1019171 # number of prefetches not generated due to page crossing 98811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 98911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.replacements 2286879 # number of replacements 99011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15893.622807 # Cycle average of tags in use 99111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.total_refs 9162734 # Total number of references to valid blocks. 99211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2302009 # Sample count of references to valid blocks. 99311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.avg_refs 3.980321 # Average number of references to valid blocks. 99411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5406430500 # Cycle when the warmup percentage was hit. 99511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15603.896064 # Average occupied blocks per requestor 99611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 29.949034 # Average occupied blocks per requestor 99711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 16.856945 # Average occupied blocks per requestor 99811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 242.920764 # Average occupied blocks per requestor 99911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.952386 # Average percentage of cache occupancy 100011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001828 # Average percentage of cache occupancy 100111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001029 # Average percentage of cache occupancy 100211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014827 # Average percentage of cache occupancy 100311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.970070 # Average percentage of cache occupancy 100411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 306 # Occupied blocks per task id 100511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id 100611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14757 # Occupied blocks per task id 100711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id 100811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 139 # Occupied blocks per task id 100911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 67 # Occupied blocks per task id 101011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 101111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 101211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id 101311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 101411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 101511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 101611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4608 # Occupied blocks per task id 101711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8403 # Occupied blocks per task id 101811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1616 # Occupied blocks per task id 101911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018677 # Percentage of cache occupancy per task id 102011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id 102111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900696 # Percentage of cache occupancy per task id 102211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 368793343 # Number of tag accesses 102311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 368793343 # Number of data accesses 102411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 102511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 252482 # number of ReadReq hits 102611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 146217 # number of ReadReq hits 102711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 398699 # number of ReadReq hits 102811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3794669 # number of WritebackDirty hits 102911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3794669 # number of WritebackDirty hits 103011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 6895627 # number of WritebackClean hits 103111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 6895627 # number of WritebackClean hits 103211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 932984 # number of ReadExReq hits 103311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 932984 # number of ReadExReq hits 103411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4503327 # number of ReadCleanReq hits 103511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4503327 # number of ReadCleanReq hits 103611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2919116 # number of ReadSharedReq hits 103711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2919116 # number of ReadSharedReq hits 103811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 217183 # number of InvalidateReq hits 103911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 217183 # number of InvalidateReq hits 104011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 252482 # number of demand (read+write) hits 104111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 146217 # number of demand (read+write) hits 104211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4503327 # number of demand (read+write) hits 104311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3852100 # number of demand (read+write) hits 104411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::total 8754126 # number of demand (read+write) hits 104511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 252482 # number of overall hits 104611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 146217 # number of overall hits 104711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4503327 # number of overall hits 104811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3852100 # number of overall hits 104911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::total 8754126 # number of overall hits 105011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 17757 # number of ReadReq misses 105111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8990 # number of ReadReq misses 105211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 26747 # number of ReadReq misses 105311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 236502 # number of UpgradeReq misses 105411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 236502 # number of UpgradeReq misses 105511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200518 # number of SCUpgradeReq misses 105611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 200518 # number of SCUpgradeReq misses 105711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses 105811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 105911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 248602 # number of ReadExReq misses 106011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 248602 # number of ReadExReq misses 106111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 456745 # number of ReadCleanReq misses 106211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 456745 # number of ReadCleanReq misses 106311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 935783 # number of ReadSharedReq misses 106411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 935783 # number of ReadSharedReq misses 106511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 577322 # number of InvalidateReq misses 106611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 577322 # number of InvalidateReq misses 106711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 17757 # number of demand (read+write) misses 106811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8990 # number of demand (read+write) misses 106911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 456745 # number of demand (read+write) misses 107011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1184385 # number of demand (read+write) misses 107111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 1667877 # number of demand (read+write) misses 107211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 17757 # number of overall misses 107311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8990 # number of overall misses 107411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 456745 # number of overall misses 107511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1184385 # number of overall misses 107611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::total 1667877 # number of overall misses 107711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 557104000 # number of ReadReq miss cycles 107811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 362043000 # number of ReadReq miss cycles 107911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 919147000 # number of ReadReq miss cycles 108011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 930109500 # number of UpgradeReq miss cycles 108111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 930109500 # number of UpgradeReq miss cycles 108211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 320714500 # number of SCUpgradeReq miss cycles 108311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 320714500 # number of SCUpgradeReq miss cycles 108411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2109497 # number of SCUpgradeFailReq miss cycles 108511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2109497 # number of SCUpgradeFailReq miss cycles 108611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13818048499 # number of ReadExReq miss cycles 108711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 13818048499 # number of ReadExReq miss cycles 108811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17338170000 # number of ReadCleanReq miss cycles 108911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 17338170000 # number of ReadCleanReq miss cycles 109011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 36151090000 # number of ReadSharedReq miss cycles 109111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 36151090000 # number of ReadSharedReq miss cycles 109211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 305279500 # number of InvalidateReq miss cycles 109311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 305279500 # number of InvalidateReq miss cycles 109411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 557104000 # number of demand (read+write) miss cycles 109511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 362043000 # number of demand (read+write) miss cycles 109611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 17338170000 # number of demand (read+write) miss cycles 109711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 49969138499 # number of demand (read+write) miss cycles 109811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 68226455499 # number of demand (read+write) miss cycles 109911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 557104000 # number of overall miss cycles 110011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 362043000 # number of overall miss cycles 110111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 17338170000 # number of overall miss cycles 110211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 49969138499 # number of overall miss cycles 110311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 68226455499 # number of overall miss cycles 110411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 270239 # number of ReadReq accesses(hits+misses) 110511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155207 # number of ReadReq accesses(hits+misses) 110611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 425446 # number of ReadReq accesses(hits+misses) 110711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3794669 # number of WritebackDirty accesses(hits+misses) 110811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3794669 # number of WritebackDirty accesses(hits+misses) 110911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 6895627 # number of WritebackClean accesses(hits+misses) 111011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 6895627 # number of WritebackClean accesses(hits+misses) 111111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 236502 # number of UpgradeReq accesses(hits+misses) 111211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 236502 # number of UpgradeReq accesses(hits+misses) 111311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200518 # number of SCUpgradeReq accesses(hits+misses) 111411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 200518 # number of SCUpgradeReq accesses(hits+misses) 111511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) 111611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 111711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1181586 # number of ReadExReq accesses(hits+misses) 111811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1181586 # number of ReadExReq accesses(hits+misses) 111911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4960072 # number of ReadCleanReq accesses(hits+misses) 112011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 4960072 # number of ReadCleanReq accesses(hits+misses) 112111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3854899 # number of ReadSharedReq accesses(hits+misses) 112211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3854899 # number of ReadSharedReq accesses(hits+misses) 112311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794505 # number of InvalidateReq accesses(hits+misses) 112411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 794505 # number of InvalidateReq accesses(hits+misses) 112511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 270239 # number of demand (read+write) accesses 112611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155207 # number of demand (read+write) accesses 112711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 4960072 # number of demand (read+write) accesses 112811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5036485 # number of demand (read+write) accesses 112911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 10422003 # number of demand (read+write) accesses 113011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 270239 # number of overall (read+write) accesses 113111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155207 # number of overall (read+write) accesses 113211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 4960072 # number of overall (read+write) accesses 113311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5036485 # number of overall (read+write) accesses 113411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 10422003 # number of overall (read+write) accesses 113511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for ReadReq accesses 113611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057923 # miss rate for ReadReq accesses 113711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.062868 # miss rate for ReadReq accesses 113811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 113911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 114011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 114111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 114210535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 114310535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 114411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.210397 # miss rate for ReadExReq accesses 114511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.210397 # miss rate for ReadExReq accesses 114611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092084 # miss rate for ReadCleanReq accesses 114711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092084 # miss rate for ReadCleanReq accesses 114811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242752 # miss rate for ReadSharedReq accesses 114911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242752 # miss rate for ReadSharedReq accesses 115011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.726644 # miss rate for InvalidateReq accesses 115111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.726644 # miss rate for InvalidateReq accesses 115211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for demand accesses 115311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057923 # miss rate for demand accesses 115411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092084 # miss rate for demand accesses 115511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.235161 # miss rate for demand accesses 115611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.160034 # miss rate for demand accesses 115711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for overall accesses 115811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057923 # miss rate for overall accesses 115911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092084 # miss rate for overall accesses 116011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.235161 # miss rate for overall accesses 116111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.160034 # miss rate for overall accesses 116211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average ReadReq miss latency 116311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40271.746385 # average ReadReq miss latency 116411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 34364.489475 # average ReadReq miss latency 116511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3932.776467 # average UpgradeReq miss latency 116611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3932.776467 # average UpgradeReq miss latency 116711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1599.429976 # average SCUpgradeReq miss latency 116811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1599.429976 # average SCUpgradeReq miss latency 116911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 210949.700000 # average SCUpgradeFailReq miss latency 117011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 210949.700000 # average SCUpgradeFailReq miss latency 117111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55583.014211 # average ReadExReq miss latency 117211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55583.014211 # average ReadExReq miss latency 117311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37960.284185 # average ReadCleanReq miss latency 117411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37960.284185 # average ReadCleanReq miss latency 117511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38631.915733 # average ReadSharedReq miss latency 117611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38631.915733 # average ReadSharedReq miss latency 117711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 528.785496 # average InvalidateReq miss latency 117811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 528.785496 # average InvalidateReq miss latency 117911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average overall miss latency 118011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40271.746385 # average overall miss latency 118111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37960.284185 # average overall miss latency 118211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42189.945414 # average overall miss latency 118311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 40906.167241 # average overall miss latency 118411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average overall miss latency 118511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40271.746385 # average overall miss latency 118611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37960.284185 # average overall miss latency 118711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42189.945414 # average overall miss latency 118811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 40906.167241 # average overall miss latency 118910628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 119010535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119110628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 119210535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 119310628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 119410535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.unused_prefetches 38115 # number of HardPF blocks evicted w/o reference 119611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1518116 # number of writebacks 119711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 1518116 # number of writebacks 119811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6419 # number of ReadExReq MSHR hits 119911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 6419 # number of ReadExReq MSHR hits 120011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 459 # number of ReadSharedReq MSHR hits 120111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 459 # number of ReadSharedReq MSHR hits 120211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 6878 # number of demand (read+write) MSHR hits 120311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 6878 # number of demand (read+write) MSHR hits 120411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 6878 # number of overall MSHR hits 120511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 6878 # number of overall MSHR hits 120611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 17757 # number of ReadReq MSHR misses 120711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8990 # number of ReadReq MSHR misses 120811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 26747 # number of ReadReq MSHR misses 120911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 749864 # number of HardPFReq MSHR misses 121011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 749864 # number of HardPFReq MSHR misses 121111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 236502 # number of UpgradeReq MSHR misses 121211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 236502 # number of UpgradeReq MSHR misses 121311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 200518 # number of SCUpgradeReq MSHR misses 121411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 200518 # number of SCUpgradeReq MSHR misses 121511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses 121611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses 121711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 242183 # number of ReadExReq MSHR misses 121811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 242183 # number of ReadExReq MSHR misses 121911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 456745 # number of ReadCleanReq MSHR misses 122011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 456745 # number of ReadCleanReq MSHR misses 122111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 935324 # number of ReadSharedReq MSHR misses 122211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 935324 # number of ReadSharedReq MSHR misses 122311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 577322 # number of InvalidateReq MSHR misses 122411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 577322 # number of InvalidateReq MSHR misses 122511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 17757 # number of demand (read+write) MSHR misses 122611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8990 # number of demand (read+write) MSHR misses 122711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 456745 # number of demand (read+write) MSHR misses 122811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1177507 # number of demand (read+write) MSHR misses 122911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1660999 # number of demand (read+write) MSHR misses 123011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 17757 # number of overall MSHR misses 123111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8990 # number of overall MSHR misses 123211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 456745 # number of overall MSHR misses 123311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1177507 # number of overall MSHR misses 123411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 749864 # number of overall MSHR misses 123511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2410863 # number of overall MSHR misses 123610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 123711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable 123811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59506 # number of ReadReq MSHR uncacheable 123911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable 124011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable 124110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 124211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses 124311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77200 # number of overall MSHR uncacheable misses 124411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of ReadReq MSHR miss cycles 124511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 308103000 # number of ReadReq MSHR miss cycles 124611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 758665000 # number of ReadReq MSHR miss cycles 124711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37032584946 # number of HardPFReq MSHR miss cycles 124811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37032584946 # number of HardPFReq MSHR miss cycles 124911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4392780000 # number of UpgradeReq MSHR miss cycles 125011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4392780000 # number of UpgradeReq MSHR miss cycles 125111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3053423000 # number of SCUpgradeReq MSHR miss cycles 125211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3053423000 # number of SCUpgradeReq MSHR miss cycles 125311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1785497 # number of SCUpgradeFailReq MSHR miss cycles 125411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1785497 # number of SCUpgradeFailReq MSHR miss cycles 125511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11646133999 # number of ReadExReq MSHR miss cycles 125611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11646133999 # number of ReadExReq MSHR miss cycles 125711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14597700000 # number of ReadCleanReq MSHR miss cycles 125811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14597700000 # number of ReadCleanReq MSHR miss cycles 125911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30480683500 # number of ReadSharedReq MSHR miss cycles 126011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30480683500 # number of ReadSharedReq MSHR miss cycles 126111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18786696000 # number of InvalidateReq MSHR miss cycles 126211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18786696000 # number of InvalidateReq MSHR miss cycles 126311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of demand (read+write) MSHR miss cycles 126411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 308103000 # number of demand (read+write) MSHR miss cycles 126511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14597700000 # number of demand (read+write) MSHR miss cycles 126611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 42126817499 # number of demand (read+write) MSHR miss cycles 126711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 57483182499 # number of demand (read+write) MSHR miss cycles 126811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of overall MSHR miss cycles 126911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 308103000 # number of overall MSHR miss cycles 127011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14597700000 # number of overall MSHR miss cycles 127111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42126817499 # number of overall MSHR miss cycles 127211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37032584946 # number of overall MSHR miss cycles 127311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 94515767445 # number of overall MSHR miss cycles 127411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of ReadReq MSHR uncacheable cycles 127511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2909184500 # number of ReadReq MSHR uncacheable cycles 127611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6702281000 # number of ReadReq MSHR uncacheable cycles 127711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of overall MSHR uncacheable cycles 127811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2909184500 # number of overall MSHR uncacheable cycles 127911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6702281000 # number of overall MSHR uncacheable cycles 128011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for ReadReq accesses 128111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for ReadReq accesses 128211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062868 # mshr miss rate for ReadReq accesses 128310535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 128410535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 128511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 128611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 128711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 128811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 128910535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 129010535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 129111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.204964 # mshr miss rate for ReadExReq accesses 129211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.204964 # mshr miss rate for ReadExReq accesses 129311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for ReadCleanReq accesses 129411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092084 # mshr miss rate for ReadCleanReq accesses 129511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242633 # mshr miss rate for ReadSharedReq accesses 129611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242633 # mshr miss rate for ReadSharedReq accesses 129711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.726644 # mshr miss rate for InvalidateReq accesses 129811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.726644 # mshr miss rate for InvalidateReq accesses 129911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for demand accesses 130011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for demand accesses 130111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for demand accesses 130211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for demand accesses 130311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.159374 # mshr miss rate for demand accesses 130411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for overall accesses 130511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for overall accesses 130611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for overall accesses 130711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for overall accesses 130810535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 130911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.231324 # mshr miss rate for overall accesses 131011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average ReadReq mshr miss latency 131111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average ReadReq mshr miss latency 131211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28364.489475 # average ReadReq mshr miss latency 131311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average HardPFReq mshr miss latency 131411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49385.735208 # average HardPFReq mshr miss latency 131511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18573.965548 # average UpgradeReq mshr miss latency 131611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18573.965548 # average UpgradeReq mshr miss latency 131711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15227.675321 # average SCUpgradeReq mshr miss latency 131811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15227.675321 # average SCUpgradeReq mshr miss latency 131911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178549.700000 # average SCUpgradeFailReq mshr miss latency 132011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178549.700000 # average SCUpgradeFailReq mshr miss latency 132111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48088.156473 # average ReadExReq mshr miss latency 132211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48088.156473 # average ReadExReq mshr miss latency 132311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average ReadCleanReq mshr miss latency 132411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31960.284185 # average ReadCleanReq mshr miss latency 132511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32588.368843 # average ReadSharedReq mshr miss latency 132611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32588.368843 # average ReadSharedReq mshr miss latency 132711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32541.105310 # average InvalidateReq mshr miss latency 132811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32541.105310 # average InvalidateReq mshr miss latency 132911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency 133011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency 133111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency 133211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency 133311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34607.596091 # average overall mshr miss latency 133411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency 133511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency 133611680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency 133711680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency 133811680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average overall mshr miss latency 133911680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39204.122111 # average overall mshr miss latency 134011680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency 134111680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177595.049142 # average ReadReq mshr uncacheable latency 134211680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112632.020300 # average ReadReq mshr uncacheable latency 134311680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency 134411680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85375.920763 # average overall mshr uncacheable latency 134511680SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86817.111399 # average overall mshr uncacheable latency 134611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 22159208 # Total number of requests made to the snoop filter. 134711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 11368269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 134811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 134911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 619514 # Total number of snoops made to the snoop filter. 135011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 619512 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 135111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 135211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 135311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 553426 # Transaction distribution 135411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 9465318 # Transaction distribution 135511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 135611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 17695 # Transaction distribution 135711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 17694 # Transaction distribution 135811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5316723 # Transaction distribution 135911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 6896635 # Transaction distribution 136011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 1098455 # Transaction distribution 136111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 916448 # Transaction distribution 136211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 433150 # Transaction distribution 136311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 369627 # Transaction distribution 136411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 506111 # Transaction distribution 136511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution 136611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 136711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1214944 # Transaction distribution 136811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1192020 # Transaction distribution 136911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 4960072 # Transaction distribution 137011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4756139 # Transaction distribution 137111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 842201 # Transaction distribution 137211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 794505 # Transaction distribution 137311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14965952 # Packet count per connected master and slave (bytes) 137411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18512478 # Packet count per connected master and slave (bytes) 137511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327835 # Packet count per connected master and slave (bytes) 137611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 591529 # Packet count per connected master and slave (bytes) 137711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count::total 34397794 # Packet count per connected master and slave (bytes) 137811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 635028820 # Cumulative packet size per connected master and slave (bytes) 137911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696134983 # Cumulative packet size per connected master and slave (bytes) 138011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241656 # Cumulative packet size per connected master and slave (bytes) 138111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2161912 # Cumulative packet size per connected master and slave (bytes) 138211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1334567371 # Cumulative packet size per connected master and slave (bytes) 138311680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 5130075 # Total snoops (count) 138411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopTraffic 104832276 # Total snoop traffic (bytes) 138511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 16684270 # Request fanout histogram 138611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.051566 # Request fanout histogram 138711680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.221149 # Request fanout histogram 138810535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 138911680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 15823936 94.84% 94.84% # Request fanout histogram 139011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 860332 5.16% 100.00% # Request fanout histogram 139111680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram 139210535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 139311138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 139410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 139511680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 16684270 # Request fanout histogram 139611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 21945410994 # Layer occupancy (ticks) 139710535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 139811680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 195855793 # Layer occupancy (ticks) 139910535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 140011680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7483231500 # Layer occupancy (ticks) 140110535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 140211680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8196031021 # Layer occupancy (ticks) 140310535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 140411680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 172628000 # Layer occupancy (ticks) 140510535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 140611680SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 321290000 # Layer occupancy (ticks) 140710535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 140811680SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 140910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 141010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 141110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 141210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 141310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 141410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 141510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 141610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 141710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 141810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 141910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 142010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 142110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 142210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 142310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 142410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 142610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 142710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 142810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 142910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 143010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 143110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 143310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 143410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 143510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 143610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 143710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 143811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 143911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walks 99152 # Table walker walks requested 144011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLong 99152 # Table walker walks initiated with long descriptors 144111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8586 # Level at which table walker walks with long descriptors terminate 144211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75770 # Level at which table walker walks with long descriptors terminate 144311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting 144411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 99148 # Table walker wait (enqueue to first request) latency 144511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.080687 # Table walker wait (enqueue to first request) latency 144611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 25.406685 # Table walker wait (enqueue to first request) latency 144711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-511 99147 100.00% 100.00% # Table walker wait (enqueue to first request) latency 144811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 144911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 99148 # Table walker wait (enqueue to first request) latency 145011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 84360 # Table walker service (enqueue to completion) latency 145111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 24513.021574 # Table walker service (enqueue to completion) latency 145211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 22367.425597 # Table walker service (enqueue to completion) latency 145311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 18734.439703 # Table walker service (enqueue to completion) latency 145411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 83116 98.53% 98.53% # Table walker service (enqueue to completion) latency 145511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 940 1.11% 99.64% # Table walker service (enqueue to completion) latency 145611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.19% 99.83% # Table walker service (enqueue to completion) latency 145711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 58 0.07% 99.90% # Table walker service (enqueue to completion) latency 145811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.94% # Table walker service (enqueue to completion) latency 145911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.97% # Table walker service (enqueue to completion) latency 146011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 146111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 146211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.02% 100.00% # Table walker service (enqueue to completion) latency 146311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 146411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 146511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 84360 # Table walker service (enqueue to completion) latency 146611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::samples 407519048 # Table walker pending requests distribution 146711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::mean 2.490877 # Table walker pending requests distribution 146811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::0 -607560648 -149.09% -149.09% # Table walker pending requests distribution 146911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::1 1015079696 249.09% 100.00% # Table walker pending requests distribution 147011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::total 407519048 # Table walker pending requests distribution 147111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 75770 89.82% 89.82% # Table walker page sizes translated 147211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 8586 10.18% 100.00% # Table walker page sizes translated 147311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 84356 # Table walker page sizes translated 147411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99152 # Table walker requests started/completed, data/inst 147510628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 147611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99152 # Table walker requests started/completed, data/inst 147711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84356 # Table walker requests started/completed, data/inst 147810628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 147911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84356 # Table walker requests started/completed, data/inst 148011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 183508 # Table walker requests started/completed, data/inst 148110535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 148210535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 148311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 78885011 # DTB read hits 148411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 72039 # DTB read misses 148511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 71761800 # DTB write hits 148611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 27113 # DTB write misses 148710535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 148810535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID 149011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 149111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.flush_entries 36637 # Number of entries that have been flushed from TLB 149210535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 149311680SCurtis.Dunham@arm.comsystem.cpu1.dtb.prefetch_faults 3802 # Number of TLB faults due to prefetch 149410535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 149511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.perms_faults 10123 # Number of TLB faults due to permissions restrictions 149611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 78957050 # DTB read accesses 149711680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 71788913 # DTB write accesses 149810535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 149911680SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 150646811 # DTB hits 150011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.misses 99152 # DTB misses 150111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 150745963 # DTB accesses 150211680SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 150310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 150410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 150510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 150610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 150710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 150810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 150910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 151010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 151110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 151210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 151310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 151410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 151510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 151610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 151710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 151810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 151910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 152010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 152110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 152210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 152310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 152410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 152510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 152610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 152710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 152810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 152910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 153010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 153110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 153211680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 153311680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walks 58316 # Table walker walks requested 153411680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLong 58316 # Table walker walks initiated with long descriptors 153511680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate 153611680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 52495 # Level at which table walker walks with long descriptors terminate 153711680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 58316 # Table walker wait (enqueue to first request) latency 153811680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 58316 100.00% 100.00% # Table walker wait (enqueue to first request) latency 153911680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 58316 # Table walker wait (enqueue to first request) latency 154011680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 53121 # Table walker service (enqueue to completion) latency 154111680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 27183.693831 # Table walker service (enqueue to completion) latency 154211680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 24219.790403 # Table walker service (enqueue to completion) latency 154311680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 26514.333195 # Table walker service (enqueue to completion) latency 154411680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 51734 97.39% 97.39% # Table walker service (enqueue to completion) latency 154511680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 949 1.79% 99.18% # Table walker service (enqueue to completion) latency 154611680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 242 0.46% 99.63% # Table walker service (enqueue to completion) latency 154711680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.15% 99.78% # Table walker service (enqueue to completion) latency 154811680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.88% # Table walker service (enqueue to completion) latency 154911680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.91% # Table walker service (enqueue to completion) latency 155011680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.92% # Table walker service (enqueue to completion) latency 155111680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.93% # Table walker service (enqueue to completion) latency 155211680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 33 0.06% 99.99% # Table walker service (enqueue to completion) latency 155311680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::655360-720895 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 155411680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 53121 # Table walker service (enqueue to completion) latency 155511680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::samples -615394148 # Table walker pending requests distribution 155611680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::0 -615394148 100.00% 100.00% # Table walker pending requests distribution 155711680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::total -615394148 # Table walker pending requests distribution 155811680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 52495 98.82% 98.82% # Table walker page sizes translated 155911680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 626 1.18% 100.00% # Table walker page sizes translated 156011680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 53121 # Table walker page sizes translated 156110628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 156211680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58316 # Table walker requests started/completed, data/inst 156311680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 58316 # Table walker requests started/completed, data/inst 156410628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 156511680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53121 # Table walker requests started/completed, data/inst 156611680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 53121 # Table walker requests started/completed, data/inst 156711680SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 111437 # Table walker requests started/completed, data/inst 156811680SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 416140593 # ITB inst hits 156911680SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_misses 58316 # ITB inst misses 157010535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 157110535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 157210535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 157310535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 157410535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 157510535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 157611680SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID 157711680SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 157811680SCurtis.Dunham@arm.comsystem.cpu1.itb.flush_entries 25699 # Number of entries that have been flushed from TLB 157910535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 158010535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 158110535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 158210535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 158310535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 158410535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 158511680SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 416198909 # ITB inst accesses 158611680SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 416140593 # DTB hits 158711680SCurtis.Dunham@arm.comsystem.cpu1.itb.misses 58316 # DTB misses 158811680SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 416198909 # DTB accesses 158911680SCurtis.Dunham@arm.comsystem.cpu1.numPwrStateTransitions 28692 # Number of power state transitions 159011680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::samples 14346 # Distribution of time spent in the clock gated state 159111680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::mean 3269284130.341071 # Distribution of time spent in the clock gated state 159211680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 86001867955.202789 # Distribution of time spent in the clock gated state 159311680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 3953 27.55% 27.55% # Distribution of time spent in the clock gated state 159411680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 10364 72.24% 99.80% # Distribution of time spent in the clock gated state 159511680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.83% # Distribution of time spent in the clock gated state 159611680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 159711680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state 159811680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 159911680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 160011680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 160111680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 160211680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 160311680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 160411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 160511680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 7510077904252 # Distribution of time spent in the clock gated state 160611680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::total 14346 # Distribution of time spent in the clock gated state 160711680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 503862826627 # Cumulative time (in ticks) in various power states 160811680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46901150133873 # Cumulative time (in ticks) in various power states 160911680SCurtis.Dunham@arm.comsystem.cpu1.numCycles 94810025921 # number of cpu cycles simulated 161010535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 161110535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 161211167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 161311680SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 14346 # number of quiesce instructions executed 161411680SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 415840875 # Number of instructions committed 161511680SCurtis.Dunham@arm.comsystem.cpu1.committedOps 490335926 # Number of ops (including micro ops) committed 161611680SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 450775425 # Number of integer alu accesses 161711680SCurtis.Dunham@arm.comsystem.cpu1.num_fp_alu_accesses 467875 # Number of float alu accesses 161811680SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 24835210 # number of times a function call or return occured 161911680SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 63203882 # number of instructions that are conditional controls 162011680SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 450775425 # number of integer instructions 162111680SCurtis.Dunham@arm.comsystem.cpu1.num_fp_insts 467875 # number of float instructions 162211680SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 655878523 # number of times the integer registers were read 162311680SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 357644258 # number of times the integer registers were written 162411680SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_reads 746575 # number of times the floating registers were read 162511680SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_writes 415812 # number of times the floating registers were written 162611680SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_reads 107608929 # number of times the CC registers were read 162711680SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_writes 107374492 # number of times the CC registers were written 162811680SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 150638767 # number of memory refs 162911680SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 78882725 # Number of load instructions 163011680SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 71756042 # Number of store instructions 163111680SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 93802300267.744019 # Number of idle cycles 163211680SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 1007725653.255979 # Number of busy cycles 163311680SCurtis.Dunham@arm.comsystem.cpu1.not_idle_fraction 0.010629 # Percentage of non-idle cycles 163411680SCurtis.Dunham@arm.comsystem.cpu1.idle_fraction 0.989371 # Percentage of idle cycles 163511680SCurtis.Dunham@arm.comsystem.cpu1.Branches 92635099 # Number of branches fetched 163611680SCurtis.Dunham@arm.comsystem.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 163711680SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 338840052 69.06% 69.06% # Class of executed instruction 163811680SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntMult 1031473 0.21% 69.27% # Class of executed instruction 163911680SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntDiv 58381 0.01% 69.28% # Class of executed instruction 164011680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.28% # Class of executed instruction 164111680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.28% # Class of executed instruction 164211680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.28% # Class of executed instruction 164311680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.28% # Class of executed instruction 164411680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.28% # Class of executed instruction 164511680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.28% # Class of executed instruction 164611680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.28% # Class of executed instruction 164711680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.28% # Class of executed instruction 164811680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.28% # Class of executed instruction 164911680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.28% # Class of executed instruction 165011680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.28% # Class of executed instruction 165111680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.28% # Class of executed instruction 165211680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.28% # Class of executed instruction 165311680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.28% # Class of executed instruction 165411680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.28% # Class of executed instruction 165511680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.28% # Class of executed instruction 165611680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.28% # Class of executed instruction 165711680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAdd 8 0.00% 69.28% # Class of executed instruction 165811680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.28% # Class of executed instruction 165911680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCmp 13 0.00% 69.28% # Class of executed instruction 166011680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatCvt 21 0.00% 69.28% # Class of executed instruction 166111680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.28% # Class of executed instruction 166211680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMisc 67037 0.01% 69.30% # Class of executed instruction 166311680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction 166411680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction 166511680SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction 166611680SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemRead 78882725 16.08% 85.37% # Class of executed instruction 166711680SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemWrite 71756042 14.63% 100.00% # Class of executed instruction 166810535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 166910535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 167011680SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 490635753 # Class of executed instruction 167111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 167211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 4949273 # number of replacements 167311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 456.328608 # Cycle average of tags in use 167411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 145491110 # Total number of references to valid blocks. 167511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 4949785 # Sample count of references to valid blocks. 167611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 29.393420 # Average number of references to valid blocks. 167711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8379669141000 # Cycle when the warmup percentage was hit. 167811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 456.328608 # Average occupied blocks per requestor 167911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.891267 # Average percentage of cache occupancy 168011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.891267 # Average percentage of cache occupancy 168111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 168211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 168311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id 168411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id 168511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 168611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 306227498 # Number of tag accesses 168711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 306227498 # Number of data accesses 168811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 168911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 73475131 # number of ReadReq hits 169011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 73475131 # number of ReadReq hits 169111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 68103188 # number of WriteReq hits 169211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 68103188 # number of WriteReq hits 169311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 168046 # number of SoftPFReq hits 169411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 168046 # number of SoftPFReq hits 169511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 87192 # number of WriteLineReq hits 169611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 87192 # number of WriteLineReq hits 169711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1644934 # number of LoadLockedReq hits 169811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1644934 # number of LoadLockedReq hits 169911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602204 # number of StoreCondReq hits 170011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1602204 # number of StoreCondReq hits 170111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 141665511 # number of demand (read+write) hits 170211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 141665511 # number of demand (read+write) hits 170311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 141833557 # number of overall hits 170411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 141833557 # number of overall hits 170511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2804863 # number of ReadReq misses 170611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2804863 # number of ReadReq misses 170711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1292961 # number of WriteReq misses 170811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1292961 # number of WriteReq misses 170911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 609189 # number of SoftPFReq misses 171011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 609189 # number of SoftPFReq misses 171111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 443031 # number of WriteLineReq misses 171211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 443031 # number of WriteLineReq misses 171311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160663 # number of LoadLockedReq misses 171411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 160663 # number of LoadLockedReq misses 171511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 202242 # number of StoreCondReq misses 171611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 202242 # number of StoreCondReq misses 171711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4540855 # number of demand (read+write) misses 171811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 4540855 # number of demand (read+write) misses 171911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5150044 # number of overall misses 172011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 5150044 # number of overall misses 172111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42649111500 # number of ReadReq miss cycles 172211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 42649111500 # number of ReadReq miss cycles 172311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25017964000 # number of WriteReq miss cycles 172411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 25017964000 # number of WriteReq miss cycles 172511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10518897000 # number of WriteLineReq miss cycles 172611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 10518897000 # number of WriteLineReq miss cycles 172711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2505987000 # number of LoadLockedReq miss cycles 172811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2505987000 # number of LoadLockedReq miss cycles 172911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4791659000 # number of StoreCondReq miss cycles 173011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4791659000 # number of StoreCondReq miss cycles 173111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2159000 # number of StoreCondFailReq miss cycles 173211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 2159000 # number of StoreCondFailReq miss cycles 173311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 78185972500 # number of demand (read+write) miss cycles 173411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_latency::total 78185972500 # number of demand (read+write) miss cycles 173511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 78185972500 # number of overall miss cycles 173611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_latency::total 78185972500 # number of overall miss cycles 173711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 76279994 # number of ReadReq accesses(hits+misses) 173811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 76279994 # number of ReadReq accesses(hits+misses) 173911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 69396149 # number of WriteReq accesses(hits+misses) 174011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 69396149 # number of WriteReq accesses(hits+misses) 174111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 777235 # number of SoftPFReq accesses(hits+misses) 174211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 777235 # number of SoftPFReq accesses(hits+misses) 174311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 530223 # number of WriteLineReq accesses(hits+misses) 174411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 530223 # number of WriteLineReq accesses(hits+misses) 174511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1805597 # number of LoadLockedReq accesses(hits+misses) 174611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1805597 # number of LoadLockedReq accesses(hits+misses) 174711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1804446 # number of StoreCondReq accesses(hits+misses) 174811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1804446 # number of StoreCondReq accesses(hits+misses) 174911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 146206366 # number of demand (read+write) accesses 175011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 146206366 # number of demand (read+write) accesses 175111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 146983601 # number of overall (read+write) accesses 175211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 146983601 # number of overall (read+write) accesses 175311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036771 # miss rate for ReadReq accesses 175411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036771 # miss rate for ReadReq accesses 175511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018632 # miss rate for WriteReq accesses 175611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018632 # miss rate for WriteReq accesses 175711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783790 # miss rate for SoftPFReq accesses 175811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.783790 # miss rate for SoftPFReq accesses 175911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.835556 # miss rate for WriteLineReq accesses 176011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.835556 # miss rate for WriteLineReq accesses 176111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088981 # miss rate for LoadLockedReq accesses 176211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088981 # miss rate for LoadLockedReq accesses 176311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112080 # miss rate for StoreCondReq accesses 176411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.112080 # miss rate for StoreCondReq accesses 176511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.031058 # miss rate for demand accesses 176611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.031058 # miss rate for demand accesses 176711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.035038 # miss rate for overall accesses 176811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.035038 # miss rate for overall accesses 176911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.416985 # average ReadReq miss latency 177011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.416985 # average ReadReq miss latency 177111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19349.357019 # average WriteReq miss latency 177211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 19349.357019 # average WriteReq miss latency 177311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23743.027012 # average WriteLineReq miss latency 177411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23743.027012 # average WriteLineReq miss latency 177511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15597.785427 # average LoadLockedReq miss latency 177611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15597.785427 # average LoadLockedReq miss latency 177711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23692.699835 # average StoreCondReq miss latency 177811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23692.699835 # average StoreCondReq miss latency 177910535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 178010535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 178111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17218.337185 # average overall miss latency 178211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17218.337185 # average overall miss latency 178311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15181.612526 # average overall miss latency 178411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15181.612526 # average overall miss latency 178510535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 178610535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 178710535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 178810535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 178910535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179010535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 179111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 4949273 # number of writebacks 179211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 4949273 # number of writebacks 179311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18154 # number of ReadReq MSHR hits 179411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 18154 # number of ReadReq MSHR hits 179511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 423 # number of WriteReq MSHR hits 179611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 423 # number of WriteReq MSHR hits 179711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43805 # number of LoadLockedReq MSHR hits 179811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 43805 # number of LoadLockedReq MSHR hits 179911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 18577 # number of demand (read+write) MSHR hits 180011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 18577 # number of demand (read+write) MSHR hits 180111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 18577 # number of overall MSHR hits 180211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 18577 # number of overall MSHR hits 180311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2786709 # number of ReadReq MSHR misses 180411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2786709 # number of ReadReq MSHR misses 180511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1292538 # number of WriteReq MSHR misses 180611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1292538 # number of WriteReq MSHR misses 180711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 609189 # number of SoftPFReq MSHR misses 180811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 609189 # number of SoftPFReq MSHR misses 180911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 443031 # number of WriteLineReq MSHR misses 181011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 443031 # number of WriteLineReq MSHR misses 181111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116858 # number of LoadLockedReq MSHR misses 181211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 116858 # number of LoadLockedReq MSHR misses 181311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202242 # number of StoreCondReq MSHR misses 181411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 202242 # number of StoreCondReq MSHR misses 181511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4522278 # number of demand (read+write) MSHR misses 181611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4522278 # number of demand (read+write) MSHR misses 181711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5131467 # number of overall MSHR misses 181811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5131467 # number of overall MSHR misses 181911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable 182011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 22203 # number of ReadReq MSHR uncacheable 182111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable 182211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable 182311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses 182411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 42958 # number of overall MSHR uncacheable misses 182511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38628648000 # number of ReadReq MSHR miss cycles 182611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 38628648000 # number of ReadReq MSHR miss cycles 182711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23695979500 # number of WriteReq MSHR miss cycles 182811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 23695979500 # number of WriteReq MSHR miss cycles 182911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13886318000 # number of SoftPFReq MSHR miss cycles 183011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13886318000 # number of SoftPFReq MSHR miss cycles 183111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10075866000 # number of WriteLineReq MSHR miss cycles 183211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10075866000 # number of WriteLineReq MSHR miss cycles 183311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1623112500 # number of LoadLockedReq MSHR miss cycles 183411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1623112500 # number of LoadLockedReq MSHR miss cycles 183511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4589466000 # number of StoreCondReq MSHR miss cycles 183611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4589466000 # number of StoreCondReq MSHR miss cycles 183711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2110000 # number of StoreCondFailReq MSHR miss cycles 183811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2110000 # number of StoreCondFailReq MSHR miss cycles 183911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72400493500 # number of demand (read+write) MSHR miss cycles 184011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 72400493500 # number of demand (read+write) MSHR miss cycles 184111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 86286811500 # number of overall MSHR miss cycles 184211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 86286811500 # number of overall MSHR miss cycles 184311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3923399500 # number of ReadReq MSHR uncacheable cycles 184411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3923399500 # number of ReadReq MSHR uncacheable cycles 184511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3923399500 # number of overall MSHR uncacheable cycles 184611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 3923399500 # number of overall MSHR uncacheable cycles 184711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036533 # mshr miss rate for ReadReq accesses 184811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036533 # mshr miss rate for ReadReq accesses 184911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018626 # mshr miss rate for WriteReq accesses 185011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018626 # mshr miss rate for WriteReq accesses 185111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783790 # mshr miss rate for SoftPFReq accesses 185211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783790 # mshr miss rate for SoftPFReq accesses 185311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.835556 # mshr miss rate for WriteLineReq accesses 185411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.835556 # mshr miss rate for WriteLineReq accesses 185511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064720 # mshr miss rate for LoadLockedReq accesses 185611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064720 # mshr miss rate for LoadLockedReq accesses 185711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112080 # mshr miss rate for StoreCondReq accesses 185811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112080 # mshr miss rate for StoreCondReq accesses 185911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030931 # mshr miss rate for demand accesses 186011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.030931 # mshr miss rate for demand accesses 186111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034912 # mshr miss rate for overall accesses 186211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.034912 # mshr miss rate for overall accesses 186311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13861.744445 # average ReadReq mshr miss latency 186411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13861.744445 # average ReadReq mshr miss latency 186511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18332.907427 # average WriteReq mshr miss latency 186611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18332.907427 # average WriteReq mshr miss latency 186711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22794.761560 # average SoftPFReq mshr miss latency 186811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22794.761560 # average SoftPFReq mshr miss latency 186911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22743.027012 # average WriteLineReq mshr miss latency 187011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22743.027012 # average WriteLineReq mshr miss latency 187111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13889.613890 # average LoadLockedReq mshr miss latency 187211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13889.613890 # average LoadLockedReq mshr miss latency 187311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22692.942119 # average StoreCondReq mshr miss latency 187411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22692.942119 # average StoreCondReq mshr miss latency 187510535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 187610535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 187711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16009.739671 # average overall mshr miss latency 187811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16009.739671 # average overall mshr miss latency 187911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16815.232662 # average overall mshr miss latency 188011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 16815.232662 # average overall mshr miss latency 188111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176705.828041 # average ReadReq mshr uncacheable latency 188211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176705.828041 # average ReadReq mshr uncacheable latency 188311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91331.055915 # average overall mshr uncacheable latency 188411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91331.055915 # average overall mshr uncacheable latency 188511680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 188611680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 4981311 # number of replacements 188711680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 496.212019 # Cycle average of tags in use 188811680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 411158765 # Total number of references to valid blocks. 188911680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 4981823 # Sample count of references to valid blocks. 189011680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 82.531789 # Average number of references to valid blocks. 189111680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 8379594860000 # Cycle when the warmup percentage was hit. 189211680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.212019 # Average occupied blocks per requestor 189311680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy 189411680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy 189510535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 189611680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 189711680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 189811680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id 189910535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 190011680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 837263014 # Number of tag accesses 190111680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 837263014 # Number of data accesses 190211680SCurtis.Dunham@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 190311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 411158765 # number of ReadReq hits 190411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 411158765 # number of ReadReq hits 190511680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 411158765 # number of demand (read+write) hits 190611680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 411158765 # number of demand (read+write) hits 190711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 411158765 # number of overall hits 190811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 411158765 # number of overall hits 190911680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4981828 # number of ReadReq misses 191011680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 4981828 # number of ReadReq misses 191111680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4981828 # number of demand (read+write) misses 191211680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 4981828 # number of demand (read+write) misses 191311680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4981828 # number of overall misses 191411680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 4981828 # number of overall misses 191511680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54111358000 # number of ReadReq miss cycles 191611680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 54111358000 # number of ReadReq miss cycles 191711680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 54111358000 # number of demand (read+write) miss cycles 191811680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_latency::total 54111358000 # number of demand (read+write) miss cycles 191911680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 54111358000 # number of overall miss cycles 192011680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_latency::total 54111358000 # number of overall miss cycles 192111680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 416140593 # number of ReadReq accesses(hits+misses) 192211680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 416140593 # number of ReadReq accesses(hits+misses) 192311680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 416140593 # number of demand (read+write) accesses 192411680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 416140593 # number of demand (read+write) accesses 192511680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 416140593 # number of overall (read+write) accesses 192611680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 416140593 # number of overall (read+write) accesses 192711680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011972 # miss rate for ReadReq accesses 192811680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.011972 # miss rate for ReadReq accesses 192911680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.011972 # miss rate for demand accesses 193011680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.011972 # miss rate for demand accesses 193111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.011972 # miss rate for overall accesses 193211680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.011972 # miss rate for overall accesses 193311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10861.747535 # average ReadReq miss latency 193411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10861.747535 # average ReadReq miss latency 193511680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency 193611680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10861.747535 # average overall miss latency 193711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency 193811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10861.747535 # average overall miss latency 193910535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 194010535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 194110535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 194210535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 194310535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 194410535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 194511680SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 4981311 # number of writebacks 194611680SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 4981311 # number of writebacks 194711680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4981828 # number of ReadReq MSHR misses 194811680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 4981828 # number of ReadReq MSHR misses 194911680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 4981828 # number of demand (read+write) MSHR misses 195011680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_misses::total 4981828 # number of demand (read+write) MSHR misses 195111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 4981828 # number of overall MSHR misses 195211680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_misses::total 4981828 # number of overall MSHR misses 195310827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 195410827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 195510827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 195610827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 195711680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51620444000 # number of ReadReq MSHR miss cycles 195811680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 51620444000 # number of ReadReq MSHR miss cycles 195911680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51620444000 # number of demand (read+write) MSHR miss cycles 196011680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 51620444000 # number of demand (read+write) MSHR miss cycles 196111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51620444000 # number of overall MSHR miss cycles 196211680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 51620444000 # number of overall MSHR miss cycles 196311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10472000 # number of ReadReq MSHR uncacheable cycles 196411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10472000 # number of ReadReq MSHR uncacheable cycles 196511680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10472000 # number of overall MSHR uncacheable cycles 196611680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 10472000 # number of overall MSHR uncacheable cycles 196711680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for ReadReq accesses 196811680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011972 # mshr miss rate for ReadReq accesses 196911680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for demand accesses 197011680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.011972 # mshr miss rate for demand accesses 197111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for overall accesses 197211680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.011972 # mshr miss rate for overall accesses 197311680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average ReadReq mshr miss latency 197411680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10361.747535 # average ReadReq mshr miss latency 197511680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency 197611680SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency 197711680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency 197811680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency 197911680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average ReadReq mshr uncacheable latency 198011680SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95200 # average ReadReq mshr uncacheable latency 198111680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average overall mshr uncacheable latency 198211680SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95200 # average overall mshr uncacheable latency 198311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 198411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 6872416 # number of hwpf issued 198511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 6872436 # number of prefetch candidates identified 198611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 18 # number of redundant prefetches already in prefetch queue 198710628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 198810628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 198911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 852028 # number of prefetches not generated due to page crossing 199011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 199111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.replacements 1861043 # number of replacements 199211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tagsinuse 12976.163549 # Cycle average of tags in use 199311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.total_refs 8767962 # Total number of references to valid blocks. 199411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.sampled_refs 1876890 # Sample count of references to valid blocks. 199511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 4.671537 # Average number of references to valid blocks. 199611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 199711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12709.863020 # Average occupied blocks per requestor 199811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.854479 # Average occupied blocks per requestor 199911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 23.050365 # Average occupied blocks per requestor 200011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 215.395684 # Average occupied blocks per requestor 200111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.775748 # Average percentage of cache occupancy 200211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001700 # Average percentage of cache occupancy 200311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001407 # Average percentage of cache occupancy 200411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013147 # Average percentage of cache occupancy 200511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.792002 # Average percentage of cache occupancy 200611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 377 # Occupied blocks per task id 200711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id 200811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15415 # Occupied blocks per task id 200911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 201011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id 201111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 69 # Occupied blocks per task id 201211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 165 # Occupied blocks per task id 201311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id 201411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id 201511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 201611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 201711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1400 # Occupied blocks per task id 201811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5858 # Occupied blocks per task id 201911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4122 # Occupied blocks per task id 202011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3918 # Occupied blocks per task id 202111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.023010 # Percentage of cache occupancy per task id 202211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id 202311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940857 # Percentage of cache occupancy per task id 202411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 342605185 # Number of tag accesses 202511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 342605185 # Number of data accesses 202611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 202711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 220532 # number of ReadReq hits 202811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 147847 # number of ReadReq hits 202911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 368379 # number of ReadReq hits 203011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3122709 # number of WritebackDirty hits 203111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3122709 # number of WritebackDirty hits 203211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6807120 # number of WritebackClean hits 203311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6807120 # number of WritebackClean hits 203411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 835381 # number of ReadExReq hits 203511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 835381 # number of ReadExReq hits 203611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4529100 # number of ReadCleanReq hits 203711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4529100 # number of ReadCleanReq hits 203811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2623579 # number of ReadSharedReq hits 203911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2623579 # number of ReadSharedReq hits 204011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191618 # number of InvalidateReq hits 204111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 191618 # number of InvalidateReq hits 204211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 220532 # number of demand (read+write) hits 204311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 147847 # number of demand (read+write) hits 204411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4529100 # number of demand (read+write) hits 204511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3458960 # number of demand (read+write) hits 204611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::total 8356439 # number of demand (read+write) hits 204711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 220532 # number of overall hits 204811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 147847 # number of overall hits 204911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4529100 # number of overall hits 205011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3458960 # number of overall hits 205111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 8356439 # number of overall hits 205211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 17957 # number of ReadReq misses 205311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10279 # number of ReadReq misses 205411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 28236 # number of ReadReq misses 205511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208369 # number of UpgradeReq misses 205611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 208369 # number of UpgradeReq misses 205711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202239 # number of SCUpgradeReq misses 205811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 202239 # number of SCUpgradeReq misses 205911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 206011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 206111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 250965 # number of ReadExReq misses 206211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 250965 # number of ReadExReq misses 206311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 452728 # number of ReadCleanReq misses 206411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 452728 # number of ReadCleanReq misses 206511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 889177 # number of ReadSharedReq misses 206611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 889177 # number of ReadSharedReq misses 206711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 249433 # number of InvalidateReq misses 206811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 249433 # number of InvalidateReq misses 206911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 17957 # number of demand (read+write) misses 207011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 10279 # number of demand (read+write) misses 207111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 452728 # number of demand (read+write) misses 207211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1140142 # number of demand (read+write) misses 207311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 1621106 # number of demand (read+write) misses 207411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 17957 # number of overall misses 207511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 10279 # number of overall misses 207611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 452728 # number of overall misses 207711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1140142 # number of overall misses 207811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 1621106 # number of overall misses 207911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 590137500 # number of ReadReq miss cycles 208011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 422641500 # number of ReadReq miss cycles 208111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 1012779000 # number of ReadReq miss cycles 208211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 875652500 # number of UpgradeReq miss cycles 208311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 875652500 # number of UpgradeReq miss cycles 208411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 333590500 # number of SCUpgradeReq miss cycles 208511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 333590500 # number of SCUpgradeReq miss cycles 208611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2035999 # number of SCUpgradeFailReq miss cycles 208711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2035999 # number of SCUpgradeFailReq miss cycles 208811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11238175000 # number of ReadExReq miss cycles 208911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 11238175000 # number of ReadExReq miss cycles 209011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16933068500 # number of ReadCleanReq miss cycles 209111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 16933068500 # number of ReadCleanReq miss cycles 209211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31773824000 # number of ReadSharedReq miss cycles 209311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 31773824000 # number of ReadSharedReq miss cycles 209411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 403814500 # number of InvalidateReq miss cycles 209511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 403814500 # number of InvalidateReq miss cycles 209611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 590137500 # number of demand (read+write) miss cycles 209711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 422641500 # number of demand (read+write) miss cycles 209811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 16933068500 # number of demand (read+write) miss cycles 209911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 43011999000 # number of demand (read+write) miss cycles 210011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 60957846500 # number of demand (read+write) miss cycles 210111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 590137500 # number of overall miss cycles 210211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 422641500 # number of overall miss cycles 210311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 16933068500 # number of overall miss cycles 210411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 43011999000 # number of overall miss cycles 210511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 60957846500 # number of overall miss cycles 210611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 238489 # number of ReadReq accesses(hits+misses) 210711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 158126 # number of ReadReq accesses(hits+misses) 210811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 396615 # number of ReadReq accesses(hits+misses) 210911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3122709 # number of WritebackDirty accesses(hits+misses) 211011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3122709 # number of WritebackDirty accesses(hits+misses) 211111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6807120 # number of WritebackClean accesses(hits+misses) 211211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6807120 # number of WritebackClean accesses(hits+misses) 211311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208369 # number of UpgradeReq accesses(hits+misses) 211411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 208369 # number of UpgradeReq accesses(hits+misses) 211511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202239 # number of SCUpgradeReq accesses(hits+misses) 211611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 202239 # number of SCUpgradeReq accesses(hits+misses) 211711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 211811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 211911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1086346 # number of ReadExReq accesses(hits+misses) 212011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1086346 # number of ReadExReq accesses(hits+misses) 212111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4981828 # number of ReadCleanReq accesses(hits+misses) 212211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4981828 # number of ReadCleanReq accesses(hits+misses) 212311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3512756 # number of ReadSharedReq accesses(hits+misses) 212411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3512756 # number of ReadSharedReq accesses(hits+misses) 212511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 441051 # number of InvalidateReq accesses(hits+misses) 212611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 441051 # number of InvalidateReq accesses(hits+misses) 212711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 238489 # number of demand (read+write) accesses 212811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 158126 # number of demand (read+write) accesses 212911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4981828 # number of demand (read+write) accesses 213011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4599102 # number of demand (read+write) accesses 213111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::total 9977545 # number of demand (read+write) accesses 213211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 238489 # number of overall (read+write) accesses 213311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 158126 # number of overall (read+write) accesses 213411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4981828 # number of overall (read+write) accesses 213511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4599102 # number of overall (read+write) accesses 213611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::total 9977545 # number of overall (read+write) accesses 213711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for ReadReq accesses 213811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065005 # miss rate for ReadReq accesses 213911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.071192 # miss rate for ReadReq accesses 214011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 214111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 214211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 214311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 214410535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 214510535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 214611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231018 # miss rate for ReadExReq accesses 214711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.231018 # miss rate for ReadExReq accesses 214811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.090876 # miss rate for ReadCleanReq accesses 214911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.090876 # miss rate for ReadCleanReq accesses 215011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253128 # miss rate for ReadSharedReq accesses 215111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253128 # miss rate for ReadSharedReq accesses 215211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.565542 # miss rate for InvalidateReq accesses 215311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.565542 # miss rate for InvalidateReq accesses 215411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for demand accesses 215511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065005 # miss rate for demand accesses 215611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.090876 # miss rate for demand accesses 215711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.247905 # miss rate for demand accesses 215811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.162475 # miss rate for demand accesses 215911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for overall accesses 216011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065005 # miss rate for overall accesses 216111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.090876 # miss rate for overall accesses 216211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.247905 # miss rate for overall accesses 216311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.162475 # miss rate for overall accesses 216411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average ReadReq miss latency 216511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41116.986088 # average ReadReq miss latency 216611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 35868.359541 # average ReadReq miss latency 216711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4202.412547 # average UpgradeReq miss latency 216811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4202.412547 # average UpgradeReq miss latency 216911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1649.486499 # average SCUpgradeReq miss latency 217011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1649.486499 # average SCUpgradeReq miss latency 217111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 678666.333333 # average SCUpgradeFailReq miss latency 217211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 678666.333333 # average SCUpgradeFailReq miss latency 217311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44779.849780 # average ReadExReq miss latency 217411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44779.849780 # average ReadExReq miss latency 217511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37402.300057 # average ReadCleanReq miss latency 217611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37402.300057 # average ReadCleanReq miss latency 217711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35733.969727 # average ReadSharedReq miss latency 217811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35733.969727 # average ReadSharedReq miss latency 217911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1618.929733 # average InvalidateReq miss latency 218011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1618.929733 # average InvalidateReq miss latency 218111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average overall miss latency 218211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41116.986088 # average overall miss latency 218311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37402.300057 # average overall miss latency 218411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37725.124590 # average overall miss latency 218511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 37602.628391 # average overall miss latency 218611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average overall miss latency 218711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41116.986088 # average overall miss latency 218811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37402.300057 # average overall miss latency 218911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37725.124590 # average overall miss latency 219011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 37602.628391 # average overall miss latency 219110628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 219210535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 219310628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 219410535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 219510628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 219610535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 219711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.unused_prefetches 38928 # number of HardPF blocks evicted w/o reference 219811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1071108 # number of writebacks 219911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 1071108 # number of writebacks 220011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4423 # number of ReadExReq MSHR hits 220111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 4423 # number of ReadExReq MSHR hits 220211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 417 # number of ReadSharedReq MSHR hits 220311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 417 # number of ReadSharedReq MSHR hits 220411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 4840 # number of demand (read+write) MSHR hits 220511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 4840 # number of demand (read+write) MSHR hits 220611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 4840 # number of overall MSHR hits 220711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 4840 # number of overall MSHR hits 220811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 17957 # number of ReadReq MSHR misses 220911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10279 # number of ReadReq MSHR misses 221011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 28236 # number of ReadReq MSHR misses 221111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 666851 # number of HardPFReq MSHR misses 221211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 666851 # number of HardPFReq MSHR misses 221311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208369 # number of UpgradeReq MSHR misses 221411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 208369 # number of UpgradeReq MSHR misses 221511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202239 # number of SCUpgradeReq MSHR misses 221611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202239 # number of SCUpgradeReq MSHR misses 221711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 221811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 221911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 246542 # number of ReadExReq MSHR misses 222011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 246542 # number of ReadExReq MSHR misses 222111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 452728 # number of ReadCleanReq MSHR misses 222211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 452728 # number of ReadCleanReq MSHR misses 222311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 888760 # number of ReadSharedReq MSHR misses 222411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 888760 # number of ReadSharedReq MSHR misses 222511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 249433 # number of InvalidateReq MSHR misses 222611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 249433 # number of InvalidateReq MSHR misses 222711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 17957 # number of demand (read+write) MSHR misses 222811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10279 # number of demand (read+write) MSHR misses 222911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 452728 # number of demand (read+write) MSHR misses 223011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1135302 # number of demand (read+write) MSHR misses 223111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1616266 # number of demand (read+write) MSHR misses 223211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 17957 # number of overall MSHR misses 223311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10279 # number of overall MSHR misses 223411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 452728 # number of overall MSHR misses 223511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1135302 # number of overall MSHR misses 223611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 666851 # number of overall MSHR misses 223711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2283117 # number of overall MSHR misses 223810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 223911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable 224011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22313 # number of ReadReq MSHR uncacheable 224111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable 224211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable 224310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 224411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses 224511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43068 # number of overall MSHR uncacheable misses 224611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of ReadReq MSHR miss cycles 224711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 360967500 # number of ReadReq MSHR miss cycles 224811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 843363000 # number of ReadReq MSHR miss cycles 224911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of HardPFReq MSHR miss cycles 225011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27800562984 # number of HardPFReq MSHR miss cycles 225111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3852073000 # number of UpgradeReq MSHR miss cycles 225211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3852073000 # number of UpgradeReq MSHR miss cycles 225311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3071337500 # number of SCUpgradeReq MSHR miss cycles 225411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3071337500 # number of SCUpgradeReq MSHR miss cycles 225511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1741999 # number of SCUpgradeFailReq MSHR miss cycles 225611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1741999 # number of SCUpgradeFailReq MSHR miss cycles 225711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9224946500 # number of ReadExReq MSHR miss cycles 225811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9224946500 # number of ReadExReq MSHR miss cycles 225911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14216700500 # number of ReadCleanReq MSHR miss cycles 226011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14216700500 # number of ReadCleanReq MSHR miss cycles 226111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26383538000 # number of ReadSharedReq MSHR miss cycles 226211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26383538000 # number of ReadSharedReq MSHR miss cycles 226311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6621907000 # number of InvalidateReq MSHR miss cycles 226411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6621907000 # number of InvalidateReq MSHR miss cycles 226511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of demand (read+write) MSHR miss cycles 226611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 360967500 # number of demand (read+write) MSHR miss cycles 226711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14216700500 # number of demand (read+write) MSHR miss cycles 226811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35608484500 # number of demand (read+write) MSHR miss cycles 226911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 50668548000 # number of demand (read+write) MSHR miss cycles 227011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of overall MSHR miss cycles 227111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 360967500 # number of overall MSHR miss cycles 227211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14216700500 # number of overall MSHR miss cycles 227311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35608484500 # number of overall MSHR miss cycles 227411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of overall MSHR miss cycles 227511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 78469110984 # number of overall MSHR miss cycles 227611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9647000 # number of ReadReq MSHR uncacheable cycles 227711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3745274000 # number of ReadReq MSHR uncacheable cycles 227811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3754921000 # number of ReadReq MSHR uncacheable cycles 227911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9647000 # number of overall MSHR uncacheable cycles 228011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3745274000 # number of overall MSHR uncacheable cycles 228111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3754921000 # number of overall MSHR uncacheable cycles 228211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for ReadReq accesses 228311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for ReadReq accesses 228411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.071192 # mshr miss rate for ReadReq accesses 228510535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 228610535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 228711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 228811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 228911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 229011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 229110535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 229210535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 229311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226946 # mshr miss rate for ReadExReq accesses 229411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226946 # mshr miss rate for ReadExReq accesses 229511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for ReadCleanReq accesses 229611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090876 # mshr miss rate for ReadCleanReq accesses 229711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253009 # mshr miss rate for ReadSharedReq accesses 229811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253009 # mshr miss rate for ReadSharedReq accesses 229911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565542 # mshr miss rate for InvalidateReq accesses 230011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565542 # mshr miss rate for InvalidateReq accesses 230111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for demand accesses 230211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for demand accesses 230311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for demand accesses 230411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for demand accesses 230511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.161990 # mshr miss rate for demand accesses 230611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for overall accesses 230711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for overall accesses 230811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for overall accesses 230911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for overall accesses 231010535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 231111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.228826 # mshr miss rate for overall accesses 231211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average ReadReq mshr miss latency 231311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average ReadReq mshr miss latency 231411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29868.359541 # average ReadReq mshr miss latency 231511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average HardPFReq mshr miss latency 231611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41689.317380 # average HardPFReq mshr miss latency 231711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18486.785462 # average UpgradeReq mshr miss latency 231811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18486.785462 # average UpgradeReq mshr miss latency 231911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15186.672699 # average SCUpgradeReq mshr miss latency 232011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15186.672699 # average SCUpgradeReq mshr miss latency 232111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 580666.333333 # average SCUpgradeFailReq mshr miss latency 232211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 580666.333333 # average SCUpgradeFailReq mshr miss latency 232311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37417.342684 # average ReadExReq mshr miss latency 232411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37417.342684 # average ReadExReq mshr miss latency 232511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average ReadCleanReq mshr miss latency 232611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31402.300057 # average ReadCleanReq mshr miss latency 232711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29685.784689 # average ReadSharedReq mshr miss latency 232811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29685.784689 # average ReadSharedReq mshr miss latency 232911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26547.838498 # average InvalidateReq mshr miss latency 233011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26547.838498 # average InvalidateReq mshr miss latency 233111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency 233211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency 233311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency 233411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency 233511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31349.139312 # average overall mshr miss latency 233611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency 233711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency 233811680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency 233911680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency 234011680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average overall mshr miss latency 234111680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34369.290310 # average overall mshr miss latency 234211680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average ReadReq mshr uncacheable latency 234311680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168683.241003 # average ReadReq mshr uncacheable latency 234411680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168284.004840 # average ReadReq mshr uncacheable latency 234511680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average overall mshr uncacheable latency 234611680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87184.552353 # average overall mshr uncacheable latency 234711680SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87185.868859 # average overall mshr uncacheable latency 234811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 20600525 # Total number of requests made to the snoop filter. 234911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 10578683 # Number of requests hitting in the snoop filter with a single holder of the requested data. 235011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 235111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 558580 # Total number of snoops made to the snoop filter. 235211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 558580 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 235311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 235411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 235511680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 484798 # Transaction distribution 235611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9068801 # Transaction distribution 235711680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 20755 # Transaction distribution 235811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 20755 # Transaction distribution 235911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4199993 # Transaction distribution 236011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6807874 # Transaction distribution 236111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 1098101 # Transaction distribution 236211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 809012 # Transaction distribution 236311680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 236411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 385894 # Transaction distribution 236511680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368515 # Transaction distribution 236611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 474989 # Transaction distribution 236711680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution 236811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 236911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1114310 # Transaction distribution 237011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1093127 # Transaction distribution 237111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4981828 # Transaction distribution 237211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4385137 # Transaction distribution 237311680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 490192 # Transaction distribution 237411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 441051 # Transaction distribution 237511680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14945187 # Packet count per connected master and slave (bytes) 237611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16097398 # Packet count per connected master and slave (bytes) 237711680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332311 # Packet count per connected master and slave (bytes) 237811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 526789 # Packet count per connected master and slave (bytes) 237911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count::total 31901685 # Packet count per connected master and slave (bytes) 238011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 637641336 # Cumulative packet size per connected master and slave (bytes) 238111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617397659 # Cumulative packet size per connected master and slave (bytes) 238211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1265008 # Cumulative packet size per connected master and slave (bytes) 238311680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1907912 # Cumulative packet size per connected master and slave (bytes) 238411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1258211915 # Cumulative packet size per connected master and slave (bytes) 238511680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoops 4504290 # Total snoops (count) 238611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopTraffic 75632944 # Total snoop traffic (bytes) 238711680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 15215883 # Request fanout histogram 238811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.052359 # Request fanout histogram 238911680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.222750 # Request fanout histogram 239010535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 239111680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 14419192 94.76% 94.76% # Request fanout histogram 239211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 796691 5.24% 100.00% # Request fanout histogram 239311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 239410535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 239511138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 239611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 239711680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 15215883 # Request fanout histogram 239811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 20375325498 # Layer occupancy (ticks) 239910535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 240011680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 176794994 # Layer occupancy (ticks) 240110535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 240211680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7472852000 # Layer occupancy (ticks) 240310535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 240411680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7357432377 # Layer occupancy (ticks) 240510535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 240611680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 174185000 # Layer occupancy (ticks) 240710535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 240811680SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 288300000 # Layer occupancy (ticks) 240910535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 241011680SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 241111680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 40355 # Transaction distribution 241211680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 40355 # Transaction distribution 241311680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteReq 136628 # Transaction distribution 241411680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteResp 136628 # Transaction distribution 241511680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) 241610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 241711245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 241810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 241910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 242010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 242110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 242210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 242310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 242410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 242510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 242611680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 242710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 242811680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) 242911680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) 243011680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) 243110535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 243210535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 243311680SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) 243411680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) 243510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 243611245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 243710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 243810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 243910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 244010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 244410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 244511680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 244610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 244711680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) 244811680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) 244911680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) 245010535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 245110535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 245211680SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 7496784 # Cumulative packet size per connected master and slave (bytes) 245311680SCurtis.Dunham@arm.comsystem.iobus.reqLayer0.occupancy 36982500 # Layer occupancy (ticks) 245410535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 245511680SCurtis.Dunham@arm.comsystem.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) 245610535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 245711680SCurtis.Dunham@arm.comsystem.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) 245810535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 245911680SCurtis.Dunham@arm.comsystem.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 246010535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 246111680SCurtis.Dunham@arm.comsystem.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) 246211245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 246310535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 246410535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 246511353Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 246610535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 246711606Sandreas.sandberg@arm.comsystem.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 246810535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 246911201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 247010535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 247111502SCurtis.Dunham@arm.comsystem.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 247210535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 247311570SCurtis.Dunham@arm.comsystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 247410535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 247511680SCurtis.Dunham@arm.comsystem.iobus.reqLayer23.occupancy 26451500 # Layer occupancy (ticks) 247610535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 247711680SCurtis.Dunham@arm.comsystem.iobus.reqLayer24.occupancy 37417000 # Layer occupancy (ticks) 247810535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 247911680SCurtis.Dunham@arm.comsystem.iobus.reqLayer25.occupancy 569427501 # Layer occupancy (ticks) 248010535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 248111680SCurtis.Dunham@arm.comsystem.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) 248210535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 248311680SCurtis.Dunham@arm.comsystem.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) 248410535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 248510892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 248610535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 248711680SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 248811680SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 115615 # number of replacements 248911680SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 11.298649 # Cycle average of tags in use 249011336Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 249111680SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. 249211336Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 249311680SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 9136560427000 # Cycle when the warmup percentage was hit. 249411680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.416178 # Average occupied blocks per requestor 249511680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.882471 # Average occupied blocks per requestor 249611680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.463511 # Average percentage of cache occupancy 249711680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.242654 # Average percentage of cache occupancy 249811680SCurtis.Dunham@arm.comsystem.iocache.tags.occ_percent::total 0.706166 # Average percentage of cache occupancy 249910535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 250010535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 250110535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 250211680SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 1040856 # Number of tag accesses 250311680SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 1040856 # Number of data accesses 250411680SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 250510535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 250611680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses 250711680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 8920 # number of ReadReq misses 250810535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 250910535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 251011680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 251111680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 251210535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 251311680SCurtis.Dunham@arm.comsystem.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses 251411680SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 115651 # number of demand (read+write) misses 251510535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 251611680SCurtis.Dunham@arm.comsystem.iocache.overall_misses::realview.ide 115611 # number of overall misses 251711680SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 115651 # number of overall misses 251811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5193500 # number of ReadReq miss cycles 251911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1828649003 # number of ReadReq miss cycles 252011680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::total 1833842503 # number of ReadReq miss cycles 252110726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 252210726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 252311680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13346157998 # number of WriteLineReq miss cycles 252411680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13346157998 # number of WriteLineReq miss cycles 252511680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5562500 # number of demand (read+write) miss cycles 252611680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::realview.ide 15174807001 # number of demand (read+write) miss cycles 252711680SCurtis.Dunham@arm.comsystem.iocache.demand_miss_latency::total 15180369501 # number of demand (read+write) miss cycles 252811680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5562500 # number of overall miss cycles 252911680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::realview.ide 15174807001 # number of overall miss cycles 253011680SCurtis.Dunham@arm.comsystem.iocache.overall_miss_latency::total 15180369501 # number of overall miss cycles 253110535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 253211680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) 253311680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) 253410535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 253510535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 253611680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 253711680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 253810535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 253911680SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses 254011680SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses 254110535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 254211680SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses 254311680SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses 254410535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 254510535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 254610535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 254710535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 254810535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 254911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 255011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 255110535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 255210535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 255310535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 255410535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 255510535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 255610535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 255711680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140364.864865 # average ReadReq miss latency 255811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 205859.394686 # average ReadReq miss latency 255911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 205587.724552 # average ReadReq miss latency 256010726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 256110726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 256211680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 125048.328442 # average WriteLineReq miss latency 256311680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 125048.328442 # average WriteLineReq miss latency 256411680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency 256511680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency 256611680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_miss_latency::total 131260.166371 # average overall miss latency 256711680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency 256811680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency 256911680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_miss_latency::total 131260.166371 # average overall miss latency 257011680SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 41899 # number of cycles access was blocked 257110535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 257211680SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked 257310535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 257411680SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 11.852617 # average number of cycles each access was blocked 257510535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 257611680SCurtis.Dunham@arm.comsystem.iocache.writebacks::writebacks 106702 # number of writebacks 257711680SCurtis.Dunham@arm.comsystem.iocache.writebacks::total 106702 # number of writebacks 257810535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 257911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses 258011680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses 258110535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 258210535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 258311680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 258411680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 258510535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 258611680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses 258711680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses 258810535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 258911680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses 259011680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses 259111680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3343500 # number of ReadReq MSHR miss cycles 259211680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1384499003 # number of ReadReq MSHR miss cycles 259311680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1387842503 # number of ReadReq MSHR miss cycles 259410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 259510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 259611680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8000796585 # number of WriteLineReq MSHR miss cycles 259711680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8000796585 # number of WriteLineReq MSHR miss cycles 259811680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3562500 # number of demand (read+write) MSHR miss cycles 259911680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 9385295588 # number of demand (read+write) MSHR miss cycles 260011680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_miss_latency::total 9388858088 # number of demand (read+write) MSHR miss cycles 260111680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3562500 # number of overall MSHR miss cycles 260211680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 9385295588 # number of overall MSHR miss cycles 260311680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_miss_latency::total 9388858088 # number of overall MSHR miss cycles 260410535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 260510535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 260610535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 260710535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 260810535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 260911336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 261011336Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 261110535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 261210535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 261310535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 261410535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 261510535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 261610535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 261711680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90364.864865 # average ReadReq mshr miss latency 261811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 155859.394686 # average ReadReq mshr miss latency 261911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 155587.724552 # average ReadReq mshr miss latency 262010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 262110892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 262211680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74964.363475 # average WriteLineReq mshr miss latency 262311680SCurtis.Dunham@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 74964.363475 # average WriteLineReq mshr miss latency 262411680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency 262511680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency 262611680SCurtis.Dunham@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 81182.679683 # average overall mshr miss latency 262711680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency 262811680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency 262911680SCurtis.Dunham@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 81182.679683 # average overall mshr miss latency 263011680SCurtis.Dunham@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 263111680SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 1376932 # number of replacements 263211680SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 65061.419917 # Cycle average of tags in use 263311680SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 5975056 # Total number of references to valid blocks. 263411680SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 1437120 # Sample count of references to valid blocks. 263511680SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 4.157660 # Average number of references to valid blocks. 263611680SCurtis.Dunham@arm.comsystem.l2c.tags.warmup_cycle 9858759500 # Cycle when the warmup percentage was hit. 263711680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 11843.449139 # Average occupied blocks per requestor 263811680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 304.799159 # Average occupied blocks per requestor 263911680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 356.696004 # Average occupied blocks per requestor 264011680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3585.763677 # Average occupied blocks per requestor 264111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 19085.445505 # Average occupied blocks per requestor 264211680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14223.146945 # Average occupied blocks per requestor 264311680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 128.223998 # Average occupied blocks per requestor 264411680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 149.509582 # Average occupied blocks per requestor 264511680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3193.954857 # Average occupied blocks per requestor 264611680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 6240.562219 # Average occupied blocks per requestor 264711680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5949.868833 # Average occupied blocks per requestor 264811680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.180717 # Average percentage of cache occupancy 264911680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.004651 # Average percentage of cache occupancy 265011680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.005443 # Average percentage of cache occupancy 265111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.054714 # Average percentage of cache occupancy 265211680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.291221 # Average percentage of cache occupancy 265311680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217028 # Average percentage of cache occupancy 265411680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.001957 # Average percentage of cache occupancy 265511680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.002281 # Average percentage of cache occupancy 265611680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.048736 # Average percentage of cache occupancy 265711680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.095223 # Average percentage of cache occupancy 265811680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.090788 # Average percentage of cache occupancy 265911680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.992758 # Average percentage of cache occupancy 266011680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 11266 # Occupied blocks per task id 266111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 259 # Occupied blocks per task id 266211680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 48663 # Occupied blocks per task id 266311680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 266411680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id 266511680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 297 # Occupied blocks per task id 266611680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 10816 # Occupied blocks per task id 266711680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id 266811680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 266911680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 267011680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 888 # Occupied blocks per task id 267111680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4525 # Occupied blocks per task id 267211680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 43209 # Occupied blocks per task id 267311680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.171906 # Percentage of cache occupancy per task id 267411680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003952 # Percentage of cache occupancy per task id 267511680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.742538 # Percentage of cache occupancy per task id 267611680SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 68586261 # Number of tag accesses 267711680SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 68586261 # Number of data accesses 267811680SCurtis.Dunham@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 267911680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2589224 # number of WritebackDirty hits 268011680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 2589224 # number of WritebackDirty hits 268111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 191644 # number of UpgradeReq hits 268211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 164185 # number of UpgradeReq hits 268311680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 355829 # number of UpgradeReq hits 268411680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 48914 # number of SCUpgradeReq hits 268511680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 48173 # number of SCUpgradeReq hits 268611680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 97087 # number of SCUpgradeReq hits 268711680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 47737 # number of ReadExReq hits 268811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 58567 # number of ReadExReq hits 268911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 106304 # number of ReadExReq hits 269011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 9201 # number of ReadSharedReq hits 269111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3860 # number of ReadSharedReq hits 269211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 408160 # number of ReadSharedReq hits 269311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 537157 # number of ReadSharedReq hits 269411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 271610 # number of ReadSharedReq hits 269511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10477 # number of ReadSharedReq hits 269611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 5555 # number of ReadSharedReq hits 269711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 408048 # number of ReadSharedReq hits 269811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 521656 # number of ReadSharedReq hits 269911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 272486 # number of ReadSharedReq hits 270011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 2448210 # number of ReadSharedReq hits 270111680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 124551 # number of InvalidateReq hits 270211680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 127410 # number of InvalidateReq hits 270311680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_hits::total 251961 # number of InvalidateReq hits 270411680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 9201 # number of demand (read+write) hits 270511680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3860 # number of demand (read+write) hits 270611680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 408160 # number of demand (read+write) hits 270711680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 584894 # number of demand (read+write) hits 270811680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 271610 # number of demand (read+write) hits 270911680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 10477 # number of demand (read+write) hits 271011680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 5555 # number of demand (read+write) hits 271111680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 408048 # number of demand (read+write) hits 271211680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 580223 # number of demand (read+write) hits 271311680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 272486 # number of demand (read+write) hits 271411680SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 2554514 # number of demand (read+write) hits 271511680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 9201 # number of overall hits 271611680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3860 # number of overall hits 271711680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 408160 # number of overall hits 271811680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 584894 # number of overall hits 271911680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 271610 # number of overall hits 272011680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 10477 # number of overall hits 272111680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 5555 # number of overall hits 272211680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 408048 # number of overall hits 272311680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 580223 # number of overall hits 272411680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 272486 # number of overall hits 272511680SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 2554514 # number of overall hits 272611680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 24439 # number of UpgradeReq misses 272711680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 23204 # number of UpgradeReq misses 272811680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 47643 # number of UpgradeReq misses 272911680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 628 # number of SCUpgradeReq misses 273011680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 554 # number of SCUpgradeReq misses 273111680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::total 1182 # number of SCUpgradeReq misses 273211680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 75730 # number of ReadExReq misses 273311680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 50449 # number of ReadExReq misses 273411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 126179 # number of ReadExReq misses 273511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1681 # number of ReadSharedReq misses 273611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1744 # number of ReadSharedReq misses 273711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 48585 # number of ReadSharedReq misses 273811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 141383 # number of ReadSharedReq misses 273911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 241091 # number of ReadSharedReq misses 274011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1909 # number of ReadSharedReq misses 274111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1973 # number of ReadSharedReq misses 274211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 44680 # number of ReadSharedReq misses 274311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 100605 # number of ReadSharedReq misses 274411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169474 # number of ReadSharedReq misses 274511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 753125 # number of ReadSharedReq misses 274611680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 440725 # number of InvalidateReq misses 274711680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 106525 # number of InvalidateReq misses 274811680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_misses::total 547250 # number of InvalidateReq misses 274911680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1681 # number of demand (read+write) misses 275011680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1744 # number of demand (read+write) misses 275111680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 48585 # number of demand (read+write) misses 275211680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 217113 # number of demand (read+write) misses 275311680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 241091 # number of demand (read+write) misses 275411680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1909 # number of demand (read+write) misses 275511680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1973 # number of demand (read+write) misses 275611680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 44680 # number of demand (read+write) misses 275711680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 151054 # number of demand (read+write) misses 275811680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 169474 # number of demand (read+write) misses 275911680SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 879304 # number of demand (read+write) misses 276011680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1681 # number of overall misses 276111680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1744 # number of overall misses 276211680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 48585 # number of overall misses 276311680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 217113 # number of overall misses 276411680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 241091 # number of overall misses 276511680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1909 # number of overall misses 276611680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1973 # number of overall misses 276711680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 44680 # number of overall misses 276811680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 151054 # number of overall misses 276911680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 169474 # number of overall misses 277011680SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 879304 # number of overall misses 277111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 162640000 # number of UpgradeReq miss cycles 277211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 138377500 # number of UpgradeReq miss cycles 277311680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::total 301017500 # number of UpgradeReq miss cycles 277411680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 7502500 # number of SCUpgradeReq miss cycles 277511680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 7047000 # number of SCUpgradeReq miss cycles 277611680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 14549500 # number of SCUpgradeReq miss cycles 277711680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 8218459999 # number of ReadExReq miss cycles 277811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 5520286999 # number of ReadExReq miss cycles 277911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_latency::total 13738746998 # number of ReadExReq miss cycles 278011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 167721500 # number of ReadSharedReq miss cycles 278111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 180518500 # number of ReadSharedReq miss cycles 278211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 5556413500 # number of ReadSharedReq miss cycles 278311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 15487743000 # number of ReadSharedReq miss cycles 278411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of ReadSharedReq miss cycles 278511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 194137000 # number of ReadSharedReq miss cycles 278611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 210753000 # number of ReadSharedReq miss cycles 278711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 5171670000 # number of ReadSharedReq miss cycles 278811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 11743795000 # number of ReadSharedReq miss cycles 278911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of ReadSharedReq miss cycles 279011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 93664269011 # number of ReadSharedReq miss cycles 279111680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu0.data 42596000 # number of InvalidateReq miss cycles 279211680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::cpu1.data 33301500 # number of InvalidateReq miss cycles 279311680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_latency::total 75897500 # number of InvalidateReq miss cycles 279411680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 167721500 # number of demand (read+write) miss cycles 279511680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 180518500 # number of demand (read+write) miss cycles 279611680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 5556413500 # number of demand (read+write) miss cycles 279711680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.data 23706202999 # number of demand (read+write) miss cycles 279811680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of demand (read+write) miss cycles 279911680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 194137000 # number of demand (read+write) miss cycles 280011680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 210753000 # number of demand (read+write) miss cycles 280111680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 5171670000 # number of demand (read+write) miss cycles 280211680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.data 17264081999 # number of demand (read+write) miss cycles 280311680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of demand (read+write) miss cycles 280411680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_latency::total 107403016009 # number of demand (read+write) miss cycles 280511680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 167721500 # number of overall miss cycles 280611680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 180518500 # number of overall miss cycles 280711680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 5556413500 # number of overall miss cycles 280811680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.data 23706202999 # number of overall miss cycles 280911680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of overall miss cycles 281011680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 194137000 # number of overall miss cycles 281111680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 210753000 # number of overall miss cycles 281211680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 5171670000 # number of overall miss cycles 281311680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.data 17264081999 # number of overall miss cycles 281411680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of overall miss cycles 281511680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_latency::total 107403016009 # number of overall miss cycles 281611680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2589224 # number of WritebackDirty accesses(hits+misses) 281711680SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 2589224 # number of WritebackDirty accesses(hits+misses) 281811680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 216083 # number of UpgradeReq accesses(hits+misses) 281911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 187389 # number of UpgradeReq accesses(hits+misses) 282011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 403472 # number of UpgradeReq accesses(hits+misses) 282111680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 49542 # number of SCUpgradeReq accesses(hits+misses) 282211680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 48727 # number of SCUpgradeReq accesses(hits+misses) 282311680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 98269 # number of SCUpgradeReq accesses(hits+misses) 282411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 123467 # number of ReadExReq accesses(hits+misses) 282511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 109016 # number of ReadExReq accesses(hits+misses) 282611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 232483 # number of ReadExReq accesses(hits+misses) 282711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10882 # number of ReadSharedReq accesses(hits+misses) 282811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5604 # number of ReadSharedReq accesses(hits+misses) 282911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 456745 # number of ReadSharedReq accesses(hits+misses) 283011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 678540 # number of ReadSharedReq accesses(hits+misses) 283111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 512701 # number of ReadSharedReq accesses(hits+misses) 283211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12386 # number of ReadSharedReq accesses(hits+misses) 283311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7528 # number of ReadSharedReq accesses(hits+misses) 283411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 452728 # number of ReadSharedReq accesses(hits+misses) 283511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 622261 # number of ReadSharedReq accesses(hits+misses) 283611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 441960 # number of ReadSharedReq accesses(hits+misses) 283711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 3201335 # number of ReadSharedReq accesses(hits+misses) 283811680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 565276 # number of InvalidateReq accesses(hits+misses) 283911680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 233935 # number of InvalidateReq accesses(hits+misses) 284011680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_accesses::total 799211 # number of InvalidateReq accesses(hits+misses) 284111680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 10882 # number of demand (read+write) accesses 284211680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 5604 # number of demand (read+write) accesses 284311680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 456745 # number of demand (read+write) accesses 284411680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 802007 # number of demand (read+write) accesses 284511680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 512701 # number of demand (read+write) accesses 284611680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 12386 # number of demand (read+write) accesses 284711680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7528 # number of demand (read+write) accesses 284811680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 452728 # number of demand (read+write) accesses 284911680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 731277 # number of demand (read+write) accesses 285011680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 441960 # number of demand (read+write) accesses 285111680SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 3433818 # number of demand (read+write) accesses 285211680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 10882 # number of overall (read+write) accesses 285311680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 5604 # number of overall (read+write) accesses 285411680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 456745 # number of overall (read+write) accesses 285511680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 802007 # number of overall (read+write) accesses 285611680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 512701 # number of overall (read+write) accesses 285711680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 12386 # number of overall (read+write) accesses 285811680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7528 # number of overall (read+write) accesses 285911680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 452728 # number of overall (read+write) accesses 286011680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 731277 # number of overall (read+write) accesses 286111680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 441960 # number of overall (read+write) accesses 286211680SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 3433818 # number of overall (read+write) accesses 286311680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.113100 # miss rate for UpgradeReq accesses 286411680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.123828 # miss rate for UpgradeReq accesses 286511680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.118083 # miss rate for UpgradeReq accesses 286611680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012676 # miss rate for SCUpgradeReq accesses 286711680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.011369 # miss rate for SCUpgradeReq accesses 286811680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.012028 # miss rate for SCUpgradeReq accesses 286911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.613362 # miss rate for ReadExReq accesses 287011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.462767 # miss rate for ReadExReq accesses 287111680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.542745 # miss rate for ReadExReq accesses 287211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for ReadSharedReq accesses 287311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.311206 # miss rate for ReadSharedReq accesses 287411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.106372 # miss rate for ReadSharedReq accesses 287511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.208364 # miss rate for ReadSharedReq accesses 287611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for ReadSharedReq accesses 287711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for ReadSharedReq accesses 287811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.262088 # miss rate for ReadSharedReq accesses 287911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098691 # miss rate for ReadSharedReq accesses 288011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.161677 # miss rate for ReadSharedReq accesses 288111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for ReadSharedReq accesses 288211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.235253 # miss rate for ReadSharedReq accesses 288311680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.779663 # miss rate for InvalidateReq accesses 288411680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.455362 # miss rate for InvalidateReq accesses 288511680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.684738 # miss rate for InvalidateReq accesses 288611680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for demand accesses 288711680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.311206 # miss rate for demand accesses 288811680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.106372 # miss rate for demand accesses 288911680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.270712 # miss rate for demand accesses 289011680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for demand accesses 289111680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for demand accesses 289211680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.262088 # miss rate for demand accesses 289311680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.098691 # miss rate for demand accesses 289411680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.206562 # miss rate for demand accesses 289511680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for demand accesses 289611680SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.256072 # miss rate for demand accesses 289711680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for overall accesses 289811680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.311206 # miss rate for overall accesses 289911680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.106372 # miss rate for overall accesses 290011680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.270712 # miss rate for overall accesses 290111680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for overall accesses 290211680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for overall accesses 290311680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.262088 # miss rate for overall accesses 290411680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.098691 # miss rate for overall accesses 290511680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.206562 # miss rate for overall accesses 290611680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for overall accesses 290711680SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.256072 # miss rate for overall accesses 290811680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6654.936781 # average UpgradeReq miss latency 290911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5963.519221 # average UpgradeReq miss latency 291011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 6318.189451 # average UpgradeReq miss latency 291111680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11946.656051 # average SCUpgradeReq miss latency 291211680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12720.216606 # average SCUpgradeReq miss latency 291311680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 12309.221658 # average SCUpgradeReq miss latency 291411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 108523.174422 # average ReadExReq miss latency 291511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 109423.120359 # average ReadExReq miss latency 291611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 108882.991607 # average ReadExReq miss latency 291711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average ReadSharedReq miss latency 291811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 103508.314220 # average ReadSharedReq miss latency 291911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114364.793661 # average ReadSharedReq miss latency 292011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109544.591641 # average ReadSharedReq miss latency 292111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average ReadSharedReq miss latency 292211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average ReadSharedReq miss latency 292311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 106818.550431 # average ReadSharedReq miss latency 292411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 115749.104745 # average ReadSharedReq miss latency 292511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116731.723075 # average ReadSharedReq miss latency 292611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average ReadSharedReq miss latency 292711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 124367.494122 # average ReadSharedReq miss latency 292811680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu0.data 96.649838 # average InvalidateReq miss latency 292911680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::cpu1.data 312.616757 # average InvalidateReq miss latency 293011680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_miss_latency::total 138.688899 # average InvalidateReq miss latency 293111680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average overall miss latency 293211680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 103508.314220 # average overall miss latency 293311680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 114364.793661 # average overall miss latency 293411680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 109188.316678 # average overall miss latency 293511680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average overall miss latency 293611680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average overall miss latency 293711680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 106818.550431 # average overall miss latency 293811680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 115749.104745 # average overall miss latency 293911680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 114290.796662 # average overall miss latency 294011680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average overall miss latency 294111680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_miss_latency::total 122145.487805 # average overall miss latency 294211680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average overall miss latency 294311680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 103508.314220 # average overall miss latency 294411680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 114364.793661 # average overall miss latency 294511680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 109188.316678 # average overall miss latency 294611680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average overall miss latency 294711680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average overall miss latency 294811680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 106818.550431 # average overall miss latency 294911680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 115749.104745 # average overall miss latency 295011680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 114290.796662 # average overall miss latency 295111680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average overall miss latency 295211680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_miss_latency::total 122145.487805 # average overall miss latency 295311680SCurtis.Dunham@arm.comsystem.l2c.blocked_cycles::no_mshrs 340 # number of cycles access was blocked 295410515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 295511680SCurtis.Dunham@arm.comsystem.l2c.blocked::no_mshrs 16 # number of cycles access was blocked 295610515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 295711680SCurtis.Dunham@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 21.250000 # average number of cycles each access was blocked 295810515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 295911680SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 1062552 # number of writebacks 296011680SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 1062552 # number of writebacks 296111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 178 # number of ReadSharedReq MSHR hits 296211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 32 # number of ReadSharedReq MSHR hits 296311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 123 # number of ReadSharedReq MSHR hits 296411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 57 # number of ReadSharedReq MSHR hits 296511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 390 # number of ReadSharedReq MSHR hits 296611680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 178 # number of demand (read+write) MSHR hits 296711680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 32 # number of demand (read+write) MSHR hits 296811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 123 # number of demand (read+write) MSHR hits 296911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits 297011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits 297111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 178 # number of overall MSHR hits 297211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 32 # number of overall MSHR hits 297311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 123 # number of overall MSHR hits 297411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits 297511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_hits::total 390 # number of overall MSHR hits 297611680SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 55381 # number of CleanEvict MSHR misses 297711680SCurtis.Dunham@arm.comsystem.l2c.CleanEvict_mshr_misses::total 55381 # number of CleanEvict MSHR misses 297811680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 24439 # number of UpgradeReq MSHR misses 297911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 23204 # number of UpgradeReq MSHR misses 298011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 47643 # number of UpgradeReq MSHR misses 298111680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 628 # number of SCUpgradeReq MSHR misses 298211680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 554 # number of SCUpgradeReq MSHR misses 298311680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 1182 # number of SCUpgradeReq MSHR misses 298411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 75730 # number of ReadExReq MSHR misses 298511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 50449 # number of ReadExReq MSHR misses 298611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_misses::total 126179 # number of ReadExReq MSHR misses 298711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1681 # number of ReadSharedReq MSHR misses 298811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1744 # number of ReadSharedReq MSHR misses 298911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 48407 # number of ReadSharedReq MSHR misses 299011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 141351 # number of ReadSharedReq MSHR misses 299111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of ReadSharedReq MSHR misses 299211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1909 # number of ReadSharedReq MSHR misses 299311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1973 # number of ReadSharedReq MSHR misses 299411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44557 # number of ReadSharedReq MSHR misses 299511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 100548 # number of ReadSharedReq MSHR misses 299611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of ReadSharedReq MSHR misses 299711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 752735 # number of ReadSharedReq MSHR misses 299811680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu0.data 440725 # number of InvalidateReq MSHR misses 299911680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::cpu1.data 106525 # number of InvalidateReq MSHR misses 300011680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_misses::total 547250 # number of InvalidateReq MSHR misses 300111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1681 # number of demand (read+write) MSHR misses 300211680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1744 # number of demand (read+write) MSHR misses 300311680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 48407 # number of demand (read+write) MSHR misses 300411680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 217081 # number of demand (read+write) MSHR misses 300511680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of demand (read+write) MSHR misses 300611680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1909 # number of demand (read+write) MSHR misses 300711680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1973 # number of demand (read+write) MSHR misses 300811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 44557 # number of demand (read+write) MSHR misses 300911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 150997 # number of demand (read+write) MSHR misses 301011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of demand (read+write) MSHR misses 301111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_misses::total 878914 # number of demand (read+write) MSHR misses 301211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1681 # number of overall MSHR misses 301311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1744 # number of overall MSHR misses 301411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 48407 # number of overall MSHR misses 301511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 217081 # number of overall MSHR misses 301611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of overall MSHR misses 301711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1909 # number of overall MSHR misses 301811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1973 # number of overall MSHR misses 301911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 44557 # number of overall MSHR misses 302011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 150997 # number of overall MSHR misses 302111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of overall MSHR misses 302211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_misses::total 878914 # number of overall MSHR misses 302310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 302411680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable 302510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 302611680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 22201 # number of ReadReq MSHR uncacheable 302711680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 81817 # number of ReadReq MSHR uncacheable 302811680SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable 302911680SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable 303011680SCurtis.Dunham@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38449 # number of WriteReq MSHR uncacheable 303110827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 303211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses 303310827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 303411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 42956 # number of overall MSHR uncacheable misses 303511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 120266 # number of overall MSHR uncacheable misses 303611680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 494587500 # number of UpgradeReq MSHR miss cycles 303711680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 479394000 # number of UpgradeReq MSHR miss cycles 303811680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 973981500 # number of UpgradeReq MSHR miss cycles 303911680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15163500 # number of SCUpgradeReq MSHR miss cycles 304011680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13789000 # number of SCUpgradeReq MSHR miss cycles 304111680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 28952500 # number of SCUpgradeReq MSHR miss cycles 304211680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7461135548 # number of ReadExReq MSHR miss cycles 304311680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5015765562 # number of ReadExReq MSHR miss cycles 304411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 12476901110 # number of ReadExReq MSHR miss cycles 304511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of ReadSharedReq MSHR miss cycles 304611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 163078500 # number of ReadSharedReq MSHR miss cycles 304711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5057062528 # number of ReadSharedReq MSHR miss cycles 304811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14070826165 # number of ReadSharedReq MSHR miss cycles 304911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of ReadSharedReq MSHR miss cycles 305011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of ReadSharedReq MSHR miss cycles 305111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 191021503 # number of ReadSharedReq MSHR miss cycles 305211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4714685544 # number of ReadSharedReq MSHR miss cycles 305311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10733108269 # number of ReadSharedReq MSHR miss cycles 305411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of ReadSharedReq MSHR miss cycles 305511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 86101249279 # number of ReadSharedReq MSHR miss cycles 305611680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8759971500 # number of InvalidateReq MSHR miss cycles 305711680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2141412000 # number of InvalidateReq MSHR miss cycles 305811680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_latency::total 10901383500 # number of InvalidateReq MSHR miss cycles 305911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of demand (read+write) MSHR miss cycles 306011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 163078500 # number of demand (read+write) MSHR miss cycles 306111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 5057062528 # number of demand (read+write) MSHR miss cycles 306211680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 21531961713 # number of demand (read+write) MSHR miss cycles 306311680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of demand (read+write) MSHR miss cycles 306411680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of demand (read+write) MSHR miss cycles 306511680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 191021503 # number of demand (read+write) MSHR miss cycles 306611680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 4714685544 # number of demand (read+write) MSHR miss cycles 306711680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 15748873831 # number of demand (read+write) MSHR miss cycles 306811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of demand (read+write) MSHR miss cycles 306911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_latency::total 98578150389 # number of demand (read+write) MSHR miss cycles 307011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of overall MSHR miss cycles 307111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 163078500 # number of overall MSHR miss cycles 307211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 5057062528 # number of overall MSHR miss cycles 307311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 21531961713 # number of overall MSHR miss cycles 307411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of overall MSHR miss cycles 307511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of overall MSHR miss cycles 307611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 191021503 # number of overall MSHR miss cycles 307711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 4714685544 # number of overall MSHR miss cycles 307811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 15748873831 # number of overall MSHR miss cycles 307911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of overall MSHR miss cycles 308011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_latency::total 98578150389 # number of overall MSHR miss cycles 308111680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of ReadReq MSHR uncacheable cycles 308211680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2614209002 # number of ReadReq MSHR uncacheable cycles 308311680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7665500 # number of ReadReq MSHR uncacheable cycles 308411680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3345576000 # number of ReadReq MSHR uncacheable cycles 308511680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 8984296502 # number of ReadReq MSHR uncacheable cycles 308611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of overall MSHR uncacheable cycles 308711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 2614209002 # number of overall MSHR uncacheable cycles 308811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7665500 # number of overall MSHR uncacheable cycles 308911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 3345576000 # number of overall MSHR uncacheable cycles 309011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 8984296502 # number of overall MSHR uncacheable cycles 309110892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 309210892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 309311680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.113100 # mshr miss rate for UpgradeReq accesses 309411680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.123828 # mshr miss rate for UpgradeReq accesses 309511680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.118083 # mshr miss rate for UpgradeReq accesses 309611680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012676 # mshr miss rate for SCUpgradeReq accesses 309711680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011369 # mshr miss rate for SCUpgradeReq accesses 309811680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.012028 # mshr miss rate for SCUpgradeReq accesses 309911680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.613362 # mshr miss rate for ReadExReq accesses 310011680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462767 # mshr miss rate for ReadExReq accesses 310111680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.542745 # mshr miss rate for ReadExReq accesses 310211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for ReadSharedReq accesses 310311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for ReadSharedReq accesses 310411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for ReadSharedReq accesses 310511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208316 # mshr miss rate for ReadSharedReq accesses 310611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for ReadSharedReq accesses 310711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for ReadSharedReq accesses 310811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for ReadSharedReq accesses 310911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for ReadSharedReq accesses 311011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.161585 # mshr miss rate for ReadSharedReq accesses 311111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for ReadSharedReq accesses 311211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.235132 # mshr miss rate for ReadSharedReq accesses 311311680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.779663 # mshr miss rate for InvalidateReq accesses 311411680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.455362 # mshr miss rate for InvalidateReq accesses 311511680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_mshr_miss_rate::total 0.684738 # mshr miss rate for InvalidateReq accesses 311611680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for demand accesses 311711680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for demand accesses 311811680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for demand accesses 311911680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for demand accesses 312011680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for demand accesses 312111680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for demand accesses 312211680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for demand accesses 312311680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for demand accesses 312411680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for demand accesses 312511680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for demand accesses 312611680SCurtis.Dunham@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.255958 # mshr miss rate for demand accesses 312711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for overall accesses 312811680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for overall accesses 312911680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for overall accesses 313011680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for overall accesses 313111680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for overall accesses 313211680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for overall accesses 313311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for overall accesses 313411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for overall accesses 313511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for overall accesses 313611680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for overall accesses 313711680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.255958 # mshr miss rate for overall accesses 313811680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20237.632473 # average UpgradeReq mshr miss latency 313911680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20659.972419 # average UpgradeReq mshr miss latency 314011680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 20443.328506 # average UpgradeReq mshr miss latency 314111680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24145.700637 # average SCUpgradeReq mshr miss latency 314211680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24889.891697 # average SCUpgradeReq mshr miss latency 314311680SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24494.500846 # average SCUpgradeReq mshr miss latency 314411680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98522.851552 # average ReadExReq mshr miss latency 314511680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99422.497215 # average ReadExReq mshr miss latency 314611680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 98882.548681 # average ReadExReq mshr miss latency 314711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average ReadSharedReq mshr miss latency 314811680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average ReadSharedReq mshr miss latency 314911680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average ReadSharedReq mshr miss latency 315011680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99545.289138 # average ReadSharedReq mshr miss latency 315111680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average ReadSharedReq mshr miss latency 315211680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average ReadSharedReq mshr miss latency 315311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average ReadSharedReq mshr miss latency 315411680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average ReadSharedReq mshr miss latency 315511680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106746.113985 # average ReadSharedReq mshr miss latency 315611680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average ReadSharedReq mshr miss latency 315711680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114384.543404 # average ReadSharedReq mshr miss latency 315811680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19876.275455 # average InvalidateReq mshr miss latency 315911680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20102.436048 # average InvalidateReq mshr miss latency 316011680SCurtis.Dunham@arm.comsystem.l2c.InvalidateReq_avg_mshr_miss_latency::total 19920.298767 # average InvalidateReq mshr miss latency 316111680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency 316211680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency 316311680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency 316411680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency 316511680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency 316611680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency 316711680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency 316811680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency 316911680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency 317011680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency 317111680SCurtis.Dunham@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency 317211680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency 317311680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency 317411680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency 317511680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency 317611680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency 317711680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency 317811680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency 317911680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency 318011680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency 318111680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency 318211680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency 318311680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency 318411680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159587.876320 # average ReadReq mshr uncacheable latency 318511680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average ReadReq mshr uncacheable latency 318611680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150694.833566 # average ReadReq mshr uncacheable latency 318711680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109809.654497 # average ReadReq mshr uncacheable latency 318811680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency 318911680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76719.266383 # average overall mshr uncacheable latency 319011680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average overall mshr uncacheable latency 319111680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77883.788062 # average overall mshr uncacheable latency 319211680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 74703.544659 # average overall mshr uncacheable latency 319311680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 3576184 # Total number of requests made to the snoop filter. 319411680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 2127782 # Number of requests hitting in the snoop filter with a single holder of the requested data. 319511680SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 319611502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 319711502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 319811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 319911680SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 320011680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 81817 # Transaction distribution 320111680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 843472 # Transaction distribution 320211680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 38449 # Transaction distribution 320311680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 38449 # Transaction distribution 320411680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 1169254 # Transaction distribution 320511680SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 223620 # Transaction distribution 320611680SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 320332 # Transaction distribution 320711680SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 305580 # Transaction distribution 320811680SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 16 # Transaction distribution 320911680SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 321011680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 143723 # Transaction distribution 321111680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 125482 # Transaction distribution 321211680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 761655 # Transaction distribution 321311680SCurtis.Dunham@arm.comsystem.membus.trans_dist::InvalidateReq 651499 # Transaction distribution 321411680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) 321510535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 321611680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26178 # Packet count per connected master and slave (bytes) 321711680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4313500 # Packet count per connected master and slave (bytes) 321811680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4462434 # Packet count per connected master and slave (bytes) 321911680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238025 # Packet count per connected master and slave (bytes) 322011680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 238025 # Packet count per connected master and slave (bytes) 322111680SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 4700459 # Packet count per connected master and slave (bytes) 322211680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) 322310535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 322411680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52356 # Cumulative packet size per connected master and slave (bytes) 322511680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124357036 # Cumulative packet size per connected master and slave (bytes) 322611680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 124565390 # Cumulative packet size per connected master and slave (bytes) 322711680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7261504 # Cumulative packet size per connected master and slave (bytes) 322811680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7261504 # Cumulative packet size per connected master and slave (bytes) 322911680SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 131826894 # Cumulative packet size per connected master and slave (bytes) 323011680SCurtis.Dunham@arm.comsystem.membus.snoops 595046 # Total snoops (count) 323111680SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 184128 # Total snoop traffic (bytes) 323211680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 2303059 # Request fanout histogram 323311680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.014256 # Request fanout histogram 323411680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.118544 # Request fanout histogram 323510535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 323611680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 2270227 98.57% 98.57% # Request fanout histogram 323711680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 32832 1.43% 100.00% # Request fanout histogram 323810535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 323910535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 324011502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 324110535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 324211680SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 2303059 # Request fanout histogram 324311680SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 101257500 # Layer occupancy (ticks) 324410535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 324511138Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 324610535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 324711680SCurtis.Dunham@arm.comsystem.membus.reqLayer2.occupancy 21679000 # Layer occupancy (ticks) 324810535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 324911680SCurtis.Dunham@arm.comsystem.membus.reqLayer5.occupancy 8033203938 # Layer occupancy (ticks) 325010535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 325111680SCurtis.Dunham@arm.comsystem.membus.respLayer2.occupancy 4846349578 # Layer occupancy (ticks) 325210535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 325311680SCurtis.Dunham@arm.comsystem.membus.respLayer3.occupancy 45469982 # Layer occupancy (ticks) 325410535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 325511680SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 325611680SCurtis.Dunham@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 325711680SCurtis.Dunham@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 325811680SCurtis.Dunham@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 325911680SCurtis.Dunham@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 326011680SCurtis.Dunham@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 326111680SCurtis.Dunham@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 326211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 326311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 326411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 326511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 326611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 326711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 326811680SCurtis.Dunham@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 326911680SCurtis.Dunham@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 327010515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 327110515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 327210515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 327310515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 327410515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 327510515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 327610515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 327710515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 327810515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 327911374Ssteve.reinhardt@amd.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 328010515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 328110515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 328210515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 328311374Ssteve.reinhardt@amd.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 328410515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 328510515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 328610515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 328710515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 328810515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 328910515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 329010515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 329110515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 329210515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 329310515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 329410515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 329510515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 329610515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 329710515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 329810515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 329910515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 330010515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 330110515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 330210515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 330310515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 330410515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 330510515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 330610515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 330710515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 330810515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 330910515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 331010515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 331110515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 331211680SCurtis.Dunham@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 331311680SCurtis.Dunham@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 331411680SCurtis.Dunham@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 331511680SCurtis.Dunham@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 331611680SCurtis.Dunham@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 331711680SCurtis.Dunham@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 331811680SCurtis.Dunham@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 331911239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 332011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 332111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 332211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 332311680SCurtis.Dunham@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 332411680SCurtis.Dunham@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 332511680SCurtis.Dunham@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 332611680SCurtis.Dunham@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 332711680SCurtis.Dunham@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 332811680SCurtis.Dunham@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 332911680SCurtis.Dunham@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 333011680SCurtis.Dunham@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 333111680SCurtis.Dunham@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 333211680SCurtis.Dunham@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 333311680SCurtis.Dunham@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 333411680SCurtis.Dunham@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 333511680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 10759482 # Total number of requests made to the snoop filter. 333611680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5851735 # Number of requests hitting in the snoop filter with a single holder of the requested data. 333711680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1766751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 333811680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 181547 # Total number of snoops made to the snoop filter. 333911680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 166860 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 334011680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 14687 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 334111680SCurtis.Dunham@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 334211680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 81819 # Transaction distribution 334311680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 4062742 # Transaction distribution 334411680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 38449 # Transaction distribution 334511680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 38449 # Transaction distribution 334611680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3651776 # Transaction distribution 334711680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 2342209 # Transaction distribution 334811680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 672985 # Transaction distribution 334911680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 402667 # Transaction distribution 335011680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1075652 # Transaction distribution 335111680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution 335211680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 335311680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 288170 # Transaction distribution 335411680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 288170 # Transaction distribution 335511680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3981632 # Transaction distribution 335611680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 828938 # Transaction distribution 335711680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 799211 # Transaction distribution 335811680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8607895 # Packet count per connected master and slave (bytes) 335911680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7128520 # Packet count per connected master and slave (bytes) 336011680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 15736415 # Packet count per connected master and slave (bytes) 336111680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 211923339 # Cumulative packet size per connected master and slave (bytes) 336211680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 174059331 # Cumulative packet size per connected master and slave (bytes) 336311680SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 385982670 # Cumulative packet size per connected master and slave (bytes) 336411680SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 2818319 # Total snoops (count) 336511680SCurtis.Dunham@arm.comsystem.toL2Bus.snoopTraffic 121467536 # Total snoop traffic (bytes) 336611680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 7671705 # Request fanout histogram 336711680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.367658 # Request fanout histogram 336811680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.486122 # Request fanout histogram 336910515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 337011680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 4865825 63.43% 63.43% # Request fanout histogram 337111680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 2791193 36.38% 99.81% # Request fanout histogram 337211680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 14687 0.19% 100.00% # Request fanout histogram 337310515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 337411138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 337510515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 337611680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 7671705 # Request fanout histogram 337711680SCurtis.Dunham@arm.comsystem.toL2Bus.reqLayer0.occupancy 8456586164 # Layer occupancy (ticks) 337810515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 337911680SCurtis.Dunham@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2556167 # Layer occupancy (ticks) 338010515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 338111680SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer0.occupancy 3921212144 # Layer occupancy (ticks) 338210515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 338311680SCurtis.Dunham@arm.comsystem.toL2Bus.respLayer1.occupancy 3534160915 # Layer occupancy (ticks) 338410515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 338510515SN/A 338610515SN/A---------- End Simulation Statistics ---------- 3387