stats.txt revision 11680
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.405013 # Number of seconds simulated 4sim_ticks 47405012960500 # Number of ticks simulated 5final_tick 47405012960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 480061 # Simulator instruction rate (inst/s) 8host_op_rate 564722 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25874318289 # Simulator tick rate (ticks/s) 10host_mem_usage 758156 # Number of bytes of host memory used 11host_seconds 1832.13 # Real time elapsed on the host 12sim_insts 879531552 # Number of instructions simulated 13sim_ops 1034641707 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 107584 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 111616 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 3269620 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 13856200 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 15427200 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 122176 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 126272 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2852024 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 9626320 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 10834112 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 432576 # Number of bytes read from this memory 28system.physmem.bytes_read::total 56765700 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 3269620 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 2852024 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 6121644 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 74832256 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 74852840 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 1681 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 1744 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 91495 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 216516 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 241050 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 1909 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1973 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 44651 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 150424 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 169283 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6759 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 927485 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1169254 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1171828 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 2269 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 2355 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 68972 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 292294 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 325434 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2577 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2664 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 60163 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 203065 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 228544 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9125 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1197462 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 68972 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 60163 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 129135 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1578573 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1579007 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1578573 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 2269 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 2355 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 68972 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 292728 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 325434 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2577 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2664 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 60163 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 203066 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 228544 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9125 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2776469 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 927485 # Number of read requests accepted 85system.physmem.writeReqs 1171828 # Number of write requests accepted 86system.physmem.readBursts 927485 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1171828 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 59337472 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 21568 # Total number of bytes read from write queue 90system.physmem.bytesWritten 74850880 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 56765700 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 74852840 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 337 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 53188 # Per bank write bursts 97system.physmem.perBankRdBursts::1 58555 # Per bank write bursts 98system.physmem.perBankRdBursts::2 49548 # Per bank write bursts 99system.physmem.perBankRdBursts::3 58849 # Per bank write bursts 100system.physmem.perBankRdBursts::4 61060 # Per bank write bursts 101system.physmem.perBankRdBursts::5 64213 # Per bank write bursts 102system.physmem.perBankRdBursts::6 58593 # Per bank write bursts 103system.physmem.perBankRdBursts::7 62574 # Per bank write bursts 104system.physmem.perBankRdBursts::8 53530 # Per bank write bursts 105system.physmem.perBankRdBursts::9 96457 # Per bank write bursts 106system.physmem.perBankRdBursts::10 50033 # Per bank write bursts 107system.physmem.perBankRdBursts::11 57571 # Per bank write bursts 108system.physmem.perBankRdBursts::12 47029 # Per bank write bursts 109system.physmem.perBankRdBursts::13 51615 # Per bank write bursts 110system.physmem.perBankRdBursts::14 49510 # Per bank write bursts 111system.physmem.perBankRdBursts::15 54823 # Per bank write bursts 112system.physmem.perBankWrBursts::0 69378 # Per bank write bursts 113system.physmem.perBankWrBursts::1 74382 # Per bank write bursts 114system.physmem.perBankWrBursts::2 69427 # Per bank write bursts 115system.physmem.perBankWrBursts::3 75087 # Per bank write bursts 116system.physmem.perBankWrBursts::4 76532 # Per bank write bursts 117system.physmem.perBankWrBursts::5 78990 # Per bank write bursts 118system.physmem.perBankWrBursts::6 75385 # Per bank write bursts 119system.physmem.perBankWrBursts::7 77589 # Per bank write bursts 120system.physmem.perBankWrBursts::8 70916 # Per bank write bursts 121system.physmem.perBankWrBursts::9 76207 # Per bank write bursts 122system.physmem.perBankWrBursts::10 70858 # Per bank write bursts 123system.physmem.perBankWrBursts::11 75862 # Per bank write bursts 124system.physmem.perBankWrBursts::12 66596 # Per bank write bursts 125system.physmem.perBankWrBursts::13 70423 # Per bank write bursts 126system.physmem.perBankWrBursts::14 68869 # Per bank write bursts 127system.physmem.perBankWrBursts::15 73044 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 516 # Number of times write queue was full causing retry 130system.physmem.totGap 47405009605000 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 43195 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 884260 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1169254 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 645919 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 88942 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 42222 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 33520 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 28634 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 25074 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 21962 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 18312 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 15502 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 2962 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1110 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 816 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 608 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 446 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 249 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 195 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 28620 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 36458 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 48218 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 54653 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 60726 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 63711 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 65994 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 67665 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 70176 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 70363 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 73600 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 75174 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 72029 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 70698 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 71278 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 75021 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 68576 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 65669 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 3787 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 2027 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 1477 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 1239 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 975 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 1013 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 865 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 814 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 739 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 756 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 763 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 668 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 705 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 695 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 747 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 666 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 760 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 682 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 648 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 743 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 716 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 785 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 937 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 551 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 928 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 1380 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 1236 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 535 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 1170 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 929017 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 144.440810 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 98.331936 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 191.352121 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 617371 66.45% 66.45% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 189527 20.40% 86.86% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 44674 4.81% 91.66% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 20356 2.19% 93.85% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 14838 1.60% 95.45% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 9142 0.98% 96.44% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6196 0.67% 97.10% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5371 0.58% 97.68% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 21542 2.32% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 929017 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 60832 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 15.240992 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 130.606668 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-1023 60830 100.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 60832 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 60832 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 19.225819 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.418138 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 8.471341 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 49295 81.03% 81.03% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 4521 7.43% 88.47% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 2878 4.73% 93.20% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 1749 2.88% 96.07% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 1023 1.68% 97.75% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 226 0.37% 98.13% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 91 0.15% 98.28% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 113 0.19% 98.46% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 47 0.08% 98.54% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 23 0.04% 98.58% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 10 0.02% 98.59% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 42 0.07% 98.66% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 494 0.81% 99.47% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 82 0.13% 99.61% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 51 0.08% 99.69% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 57 0.09% 99.79% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 26 0.04% 99.83% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 3 0.00% 99.83% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 1 0.00% 99.84% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 4 0.01% 99.84% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 2 0.00% 99.85% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 5 0.01% 99.85% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 4 0.01% 99.86% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 14 0.02% 99.88% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::116-119 2 0.00% 99.89% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::124-127 3 0.00% 99.89% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::128-131 21 0.03% 99.93% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::132-135 3 0.00% 99.93% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::136-139 2 0.00% 99.93% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::140-143 13 0.02% 99.96% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::156-159 2 0.00% 99.97% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::180-183 3 0.00% 99.98% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::192-195 2 0.00% 99.99% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::total 60832 # Writes before turning the bus around for reads 309system.physmem.totQLat 46218732203 # Total ticks spent queuing 310system.physmem.totMemAccLat 63602757203 # Total ticks spent from burst creation until serviced by the DRAM 311system.physmem.totBusLat 4635740000 # Total ticks spent in databus transfers 312system.physmem.avgQLat 49850.44 # Average queueing delay per DRAM burst 313system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 314system.physmem.avgMemAccLat 68600.44 # Average memory access latency per DRAM burst 315system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s 316system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s 317system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s 318system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s 319system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 320system.physmem.busUtil 0.02 # Data bus utilization in percentage 321system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 322system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 323system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 324system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing 325system.physmem.readRowHits 685692 # Number of row buffer hits during reads 326system.physmem.writeRowHits 481982 # Number of row buffer hits during writes 327system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads 328system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes 329system.physmem.avgGap 22581201.38 # Average gap between requests 330system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined 331system.physmem_0.actEnergy 3446827860 # Energy for activate commands per rank (pJ) 332system.physmem_0.preEnergy 1832028660 # Energy for precharge commands per rank (pJ) 333system.physmem_0.readEnergy 3331381200 # Energy for read commands per rank (pJ) 334system.physmem_0.writeEnergy 3115139400 # Energy for write commands per rank (pJ) 335system.physmem_0.refreshEnergy 41510941680.000008 # Energy for refresh commands per rank (pJ) 336system.physmem_0.actBackEnergy 46501533090 # Energy for active background per rank (pJ) 337system.physmem_0.preBackEnergy 2234866560 # Energy for precharge background per rank (pJ) 338system.physmem_0.actPowerDownEnergy 80625696300 # Energy for active power-down per rank (pJ) 339system.physmem_0.prePowerDownEnergy 57761558880 # Energy for precharge power-down per rank (pJ) 340system.physmem_0.selfRefreshEnergy 11279719224960 # Energy for self refresh per rank (pJ) 341system.physmem_0.totalEnergy 11520096687780 # Total energy per rank (pJ) 342system.physmem_0.averagePower 243.014314 # Core power per rank (mW) 343system.physmem_0.totalIdleTime 47297174723637 # Total Idle time Per DRAM Rank 344system.physmem_0.memoryStateTime::IDLE 3911587994 # Time in different power states 345system.physmem_0.memoryStateTime::REF 17636282000 # Time in different power states 346system.physmem_0.memoryStateTime::SREF 46969945639000 # Time in different power states 347system.physmem_0.memoryStateTime::PRE_PDN 150420602883 # Time in different power states 348system.physmem_0.memoryStateTime::ACT 86288423369 # Time in different power states 349system.physmem_0.memoryStateTime::ACT_PDN 176810425254 # Time in different power states 350system.physmem_1.actEnergy 3186367800 # Energy for activate commands per rank (pJ) 351system.physmem_1.preEnergy 1693590855 # Energy for precharge commands per rank (pJ) 352system.physmem_1.readEnergy 3288455520 # Energy for read commands per rank (pJ) 353system.physmem_1.writeEnergy 2989885500 # Energy for write commands per rank (pJ) 354system.physmem_1.refreshEnergy 39461117280.000008 # Energy for refresh commands per rank (pJ) 355system.physmem_1.actBackEnergy 47361781080 # Energy for active background per rank (pJ) 356system.physmem_1.preBackEnergy 2153404320 # Energy for precharge background per rank (pJ) 357system.physmem_1.actPowerDownEnergy 72224847060 # Energy for active power-down per rank (pJ) 358system.physmem_1.prePowerDownEnergy 55366694400 # Energy for precharge power-down per rank (pJ) 359system.physmem_1.selfRefreshEnergy 11285008491285 # Energy for self refresh per rank (pJ) 360system.physmem_1.totalEnergy 11512750460370 # Total energy per rank (pJ) 361system.physmem_1.averagePower 242.859346 # Core power per rank (mW) 362system.physmem_1.totalIdleTime 47295506898407 # Total Idle time Per DRAM Rank 363system.physmem_1.memoryStateTime::IDLE 3731843770 # Time in different power states 364system.physmem_1.memoryStateTime::REF 16766470000 # Time in different power states 365system.physmem_1.memoryStateTime::SREF 46992934432500 # Time in different power states 366system.physmem_1.memoryStateTime::PRE_PDN 144184093324 # Time in different power states 367system.physmem_1.memoryStateTime::ACT 89007700573 # Time in different power states 368system.physmem_1.memoryStateTime::ACT_PDN 158388420333 # Time in different power states 369system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 370system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 371system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 372system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 373system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 374system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 375system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 376system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 377system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 378system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 379system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 380system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 381system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 382system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 383system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 384system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 385system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 386system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 387system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 388system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 389system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 390system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 391system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 392system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 393system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 394system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 395system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 396system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 397system.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 398system.bridge.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 399system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 400system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 401system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 402system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 403system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 404system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 405system.cpu_clk_domain.clock 500 # Clock period in ticks 406system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 410system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 411system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 414system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 415system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 416system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 417system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 418system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 419system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 420system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 421system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 422system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 423system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 424system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 425system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 426system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 427system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 428system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 429system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 430system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 431system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 432system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 433system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 434system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 435system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 436system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 437system.cpu0.dtb.walker.walks 110745 # Table walker walks requested 438system.cpu0.dtb.walker.walksLong 110745 # Table walker walks initiated with long descriptors 439system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10295 # Level at which table walker walks with long descriptors terminate 440system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84545 # Level at which table walker walks with long descriptors terminate 441system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting 442system.cpu0.dtb.walker.walkWaitTime::samples 110723 # Table walker wait (enqueue to first request) latency 443system.cpu0.dtb.walker.walkWaitTime::mean 0.234820 # Table walker wait (enqueue to first request) latency 444system.cpu0.dtb.walker.walkWaitTime::stdev 78.136585 # Table walker wait (enqueue to first request) latency 445system.cpu0.dtb.walker.walkWaitTime::0-2047 110722 100.00% 100.00% # Table walker wait (enqueue to first request) latency 446system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 447system.cpu0.dtb.walker.walkWaitTime::total 110723 # Table walker wait (enqueue to first request) latency 448system.cpu0.dtb.walker.walkCompletionTime::samples 94862 # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::mean 23879.314162 # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::gmean 22054.085361 # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::stdev 16759.177694 # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::0-65535 93763 98.84% 98.84% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::65536-131071 840 0.89% 99.73% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::131072-196607 113 0.12% 99.85% # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.96% # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.98% # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency 459system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 460system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 461system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.01% 100.00% # Table walker service (enqueue to completion) latency 462system.cpu0.dtb.walker.walkCompletionTime::total 94862 # Table walker service (enqueue to completion) latency 463system.cpu0.dtb.walker.walksPending::samples -2682325288 # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::mean 2.121047 # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::0 3007013124 -112.10% -112.10% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::1 -5689338412 212.10% 100.00% # Table walker pending requests distribution 468system.cpu0.dtb.walker.walksPending::total -2682325288 # Table walker pending requests distribution 469system.cpu0.dtb.walker.walkPageSizes::4K 84546 89.14% 89.14% # Table walker page sizes translated 470system.cpu0.dtb.walker.walkPageSizes::2M 10295 10.86% 100.00% # Table walker page sizes translated 471system.cpu0.dtb.walker.walkPageSizes::total 94841 # Table walker page sizes translated 472system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 110745 # Table walker requests started/completed, data/inst 473system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 110745 # Table walker requests started/completed, data/inst 475system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94841 # Table walker requests started/completed, data/inst 476system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94841 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.walker.walkRequestOrigin::total 205586 # Table walker requests started/completed, data/inst 479system.cpu0.dtb.inst_hits 0 # ITB inst hits 480system.cpu0.dtb.inst_misses 0 # ITB inst misses 481system.cpu0.dtb.read_hits 86849149 # DTB read hits 482system.cpu0.dtb.read_misses 83538 # DTB read misses 483system.cpu0.dtb.write_hits 78785461 # DTB write hits 484system.cpu0.dtb.write_misses 27207 # DTB write misses 485system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 486system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 487system.cpu0.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID 488system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 489system.cpu0.dtb.flush_entries 37555 # Number of entries that have been flushed from TLB 490system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 491system.cpu0.dtb.prefetch_faults 4746 # Number of TLB faults due to prefetch 492system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 493system.cpu0.dtb.perms_faults 9443 # Number of TLB faults due to permissions restrictions 494system.cpu0.dtb.read_accesses 86932687 # DTB read accesses 495system.cpu0.dtb.write_accesses 78812668 # DTB write accesses 496system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 497system.cpu0.dtb.hits 165634610 # DTB hits 498system.cpu0.dtb.misses 110745 # DTB misses 499system.cpu0.dtb.accesses 165745355 # DTB accesses 500system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 501system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 509system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 510system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 511system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 512system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 513system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 514system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 515system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 516system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 517system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 518system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 519system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 520system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 521system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 522system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 523system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 524system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 525system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 526system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 527system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 528system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 529system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 530system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 531system.cpu0.itb.walker.walks 57780 # Table walker walks requested 532system.cpu0.itb.walker.walksLong 57780 # Table walker walks initiated with long descriptors 533system.cpu0.itb.walker.walksLongTerminationLevel::Level2 572 # Level at which table walker walks with long descriptors terminate 534system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51544 # Level at which table walker walks with long descriptors terminate 535system.cpu0.itb.walker.walkWaitTime::samples 57780 # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::0 57780 100.00% 100.00% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::total 57780 # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkCompletionTime::samples 52116 # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::mean 25803.102694 # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::gmean 23425.328726 # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::stdev 22386.426518 # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::0-65535 51056 97.97% 97.97% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::65536-131071 692 1.33% 99.29% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::131072-196607 219 0.42% 99.71% # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::196608-262143 60 0.12% 99.83% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.10% 99.93% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.95% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.96% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.96% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::589824-655359 14 0.03% 99.99% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::total 52116 # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution 555system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution 556system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution 557system.cpu0.itb.walker.walkPageSizes::4K 51544 98.90% 98.90% # Table walker page sizes translated 558system.cpu0.itb.walker.walkPageSizes::2M 572 1.10% 100.00% # Table walker page sizes translated 559system.cpu0.itb.walker.walkPageSizes::total 52116 # Table walker page sizes translated 560system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 561system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57780 # Table walker requests started/completed, data/inst 562system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57780 # Table walker requests started/completed, data/inst 563system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 564system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52116 # Table walker requests started/completed, data/inst 565system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52116 # Table walker requests started/completed, data/inst 566system.cpu0.itb.walker.walkRequestOrigin::total 109896 # Table walker requests started/completed, data/inst 567system.cpu0.itb.inst_hits 463942995 # ITB inst hits 568system.cpu0.itb.inst_misses 57780 # ITB inst misses 569system.cpu0.itb.read_hits 0 # DTB read hits 570system.cpu0.itb.read_misses 0 # DTB read misses 571system.cpu0.itb.write_hits 0 # DTB write hits 572system.cpu0.itb.write_misses 0 # DTB write misses 573system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 574system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 575system.cpu0.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID 576system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 577system.cpu0.itb.flush_entries 26477 # Number of entries that have been flushed from TLB 578system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 579system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 580system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 581system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 582system.cpu0.itb.read_accesses 0 # DTB read accesses 583system.cpu0.itb.write_accesses 0 # DTB write accesses 584system.cpu0.itb.inst_accesses 464000775 # ITB inst accesses 585system.cpu0.itb.hits 463942995 # DTB hits 586system.cpu0.itb.misses 57780 # DTB misses 587system.cpu0.itb.accesses 464000775 # DTB accesses 588system.cpu0.numPwrStateTransitions 8984 # Number of power state transitions 589system.cpu0.pwrStateClkGateDist::samples 4492 # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::mean 10426010818.709705 # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::stdev 169261679723.888153 # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::underflows 3260 72.57% 72.57% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::1000-5e+10 1205 26.83% 99.40% # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::5e+10-1e+11 8 0.18% 99.58% # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.60% # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state 597system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::overflows 12 0.27% 100.00% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::max_value 7033293863000 # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::total 4492 # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateResidencyTicks::ON 571372362856 # Cumulative time (in ticks) in various power states 605system.cpu0.pwrStateResidencyTicks::CLK_GATED 46833640597644 # Cumulative time (in ticks) in various power states 606system.cpu0.numCycles 94810025915 # number of cpu cycles simulated 607system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 608system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 609system.cpu0.kern.inst.arm 0 # number of arm instructions executed 610system.cpu0.kern.inst.quiesce 4492 # number of quiesce instructions executed 611system.cpu0.committedInsts 463690677 # Number of instructions committed 612system.cpu0.committedOps 544305781 # Number of ops (including micro ops) committed 613system.cpu0.num_int_alu_accesses 499985272 # Number of integer alu accesses 614system.cpu0.num_fp_alu_accesses 430429 # Number of float alu accesses 615system.cpu0.num_func_calls 27825312 # number of times a function call or return occured 616system.cpu0.num_conditional_control_insts 70353837 # number of instructions that are conditional controls 617system.cpu0.num_int_insts 499985272 # number of integer instructions 618system.cpu0.num_fp_insts 430429 # number of float instructions 619system.cpu0.num_int_register_reads 725660016 # number of times the integer registers were read 620system.cpu0.num_int_register_writes 396645033 # number of times the integer registers were written 621system.cpu0.num_fp_register_reads 713342 # number of times the floating registers were read 622system.cpu0.num_fp_register_writes 322808 # number of times the floating registers were written 623system.cpu0.num_cc_register_reads 121489824 # number of times the CC registers were read 624system.cpu0.num_cc_register_writes 121106505 # number of times the CC registers were written 625system.cpu0.num_mem_refs 165624912 # number of memory refs 626system.cpu0.num_load_insts 86844124 # Number of load instructions 627system.cpu0.num_store_insts 78780788 # Number of store instructions 628system.cpu0.num_idle_cycles 93667281189.358337 # Number of idle cycles 629system.cpu0.num_busy_cycles 1142744725.641658 # Number of busy cycles 630system.cpu0.not_idle_fraction 0.012053 # Percentage of non-idle cycles 631system.cpu0.idle_fraction 0.987947 # Percentage of idle cycles 632system.cpu0.Branches 103560532 # Number of branches fetched 633system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 634system.cpu0.op_class::IntAlu 377679680 69.35% 69.35% # Class of executed instruction 635system.cpu0.op_class::IntMult 1190205 0.22% 69.57% # Class of executed instruction 636system.cpu0.op_class::IntDiv 61578 0.01% 69.58% # Class of executed instruction 637system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction 638system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction 639system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction 640system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction 641system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction 642system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction 643system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction 644system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction 645system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction 646system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction 647system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction 648system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction 649system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction 650system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction 651system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction 652system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction 653system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction 654system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction 655system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction 656system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction 657system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction 658system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction 659system.cpu0.op_class::SimdFloatMisc 44848 0.01% 69.59% # Class of executed instruction 660system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction 661system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction 662system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction 663system.cpu0.op_class::MemRead 86844124 15.95% 85.53% # Class of executed instruction 664system.cpu0.op_class::MemWrite 78780788 14.47% 100.00% # Class of executed instruction 665system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 666system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 667system.cpu0.op_class::total 544601223 # Class of executed instruction 668system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 669system.cpu0.dcache.tags.replacements 5731745 # number of replacements 670system.cpu0.dcache.tags.tagsinuse 479.859189 # Cycle average of tags in use 671system.cpu0.dcache.tags.total_refs 159669170 # Total number of references to valid blocks. 672system.cpu0.dcache.tags.sampled_refs 5732255 # Sample count of references to valid blocks. 673system.cpu0.dcache.tags.avg_refs 27.854513 # Average number of references to valid blocks. 674system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. 675system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.859189 # Average occupied blocks per requestor 676system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937225 # Average percentage of cache occupancy 677system.cpu0.dcache.tags.occ_percent::total 0.937225 # Average percentage of cache occupancy 678system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 679system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 680system.cpu0.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id 681system.cpu0.dcache.tags.age_task_id_blocks_1024::2 452 # Occupied blocks per task id 682system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 683system.cpu0.dcache.tags.tag_accesses 337018109 # Number of tag accesses 684system.cpu0.dcache.tags.data_accesses 337018109 # Number of data accesses 685system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 686system.cpu0.dcache.ReadReq_hits::cpu0.data 80850678 # number of ReadReq hits 687system.cpu0.dcache.ReadReq_hits::total 80850678 # number of ReadReq hits 688system.cpu0.dcache.WriteReq_hits::cpu0.data 74290365 # number of WriteReq hits 689system.cpu0.dcache.WriteReq_hits::total 74290365 # number of WriteReq hits 690system.cpu0.dcache.SoftPFReq_hits::cpu0.data 206988 # number of SoftPFReq hits 691system.cpu0.dcache.SoftPFReq_hits::total 206988 # number of SoftPFReq hits 692system.cpu0.dcache.WriteLineReq_hits::cpu0.data 237888 # number of WriteLineReq hits 693system.cpu0.dcache.WriteLineReq_hits::total 237888 # number of WriteLineReq hits 694system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1848102 # number of LoadLockedReq hits 695system.cpu0.dcache.LoadLockedReq_hits::total 1848102 # number of LoadLockedReq hits 696system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1813975 # number of StoreCondReq hits 697system.cpu0.dcache.StoreCondReq_hits::total 1813975 # number of StoreCondReq hits 698system.cpu0.dcache.demand_hits::cpu0.data 155378931 # number of demand (read+write) hits 699system.cpu0.dcache.demand_hits::total 155378931 # number of demand (read+write) hits 700system.cpu0.dcache.overall_hits::cpu0.data 155585919 # number of overall hits 701system.cpu0.dcache.overall_hits::total 155585919 # number of overall hits 702system.cpu0.dcache.ReadReq_misses::cpu0.data 3109712 # number of ReadReq misses 703system.cpu0.dcache.ReadReq_misses::total 3109712 # number of ReadReq misses 704system.cpu0.dcache.WriteReq_misses::cpu0.data 1421405 # number of WriteReq misses 705system.cpu0.dcache.WriteReq_misses::total 1421405 # number of WriteReq misses 706system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649654 # number of SoftPFReq misses 707system.cpu0.dcache.SoftPFReq_misses::total 649654 # number of SoftPFReq misses 708system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796576 # number of WriteLineReq misses 709system.cpu0.dcache.WriteLineReq_misses::total 796576 # number of WriteLineReq misses 710system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167654 # number of LoadLockedReq misses 711system.cpu0.dcache.LoadLockedReq_misses::total 167654 # number of LoadLockedReq misses 712system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200528 # number of StoreCondReq misses 713system.cpu0.dcache.StoreCondReq_misses::total 200528 # number of StoreCondReq misses 714system.cpu0.dcache.demand_misses::cpu0.data 5327693 # number of demand (read+write) misses 715system.cpu0.dcache.demand_misses::total 5327693 # number of demand (read+write) misses 716system.cpu0.dcache.overall_misses::cpu0.data 5977347 # number of overall misses 717system.cpu0.dcache.overall_misses::total 5977347 # number of overall misses 718system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 48841831500 # number of ReadReq miss cycles 719system.cpu0.dcache.ReadReq_miss_latency::total 48841831500 # number of ReadReq miss cycles 720system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 30112535000 # number of WriteReq miss cycles 721system.cpu0.dcache.WriteReq_miss_latency::total 30112535000 # number of WriteReq miss cycles 722system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25700725500 # number of WriteLineReq miss cycles 723system.cpu0.dcache.WriteLineReq_miss_latency::total 25700725500 # number of WriteLineReq miss cycles 724system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2575322000 # number of LoadLockedReq miss cycles 725system.cpu0.dcache.LoadLockedReq_miss_latency::total 2575322000 # number of LoadLockedReq miss cycles 726system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4758884500 # number of StoreCondReq miss cycles 727system.cpu0.dcache.StoreCondReq_miss_latency::total 4758884500 # number of StoreCondReq miss cycles 728system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2246000 # number of StoreCondFailReq miss cycles 729system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles 730system.cpu0.dcache.demand_miss_latency::cpu0.data 104655092000 # number of demand (read+write) miss cycles 731system.cpu0.dcache.demand_miss_latency::total 104655092000 # number of demand (read+write) miss cycles 732system.cpu0.dcache.overall_miss_latency::cpu0.data 104655092000 # number of overall miss cycles 733system.cpu0.dcache.overall_miss_latency::total 104655092000 # number of overall miss cycles 734system.cpu0.dcache.ReadReq_accesses::cpu0.data 83960390 # number of ReadReq accesses(hits+misses) 735system.cpu0.dcache.ReadReq_accesses::total 83960390 # number of ReadReq accesses(hits+misses) 736system.cpu0.dcache.WriteReq_accesses::cpu0.data 75711770 # number of WriteReq accesses(hits+misses) 737system.cpu0.dcache.WriteReq_accesses::total 75711770 # number of WriteReq accesses(hits+misses) 738system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 856642 # number of SoftPFReq accesses(hits+misses) 739system.cpu0.dcache.SoftPFReq_accesses::total 856642 # number of SoftPFReq accesses(hits+misses) 740system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1034464 # number of WriteLineReq accesses(hits+misses) 741system.cpu0.dcache.WriteLineReq_accesses::total 1034464 # number of WriteLineReq accesses(hits+misses) 742system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2015756 # number of LoadLockedReq accesses(hits+misses) 743system.cpu0.dcache.LoadLockedReq_accesses::total 2015756 # number of LoadLockedReq accesses(hits+misses) 744system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2014503 # number of StoreCondReq accesses(hits+misses) 745system.cpu0.dcache.StoreCondReq_accesses::total 2014503 # number of StoreCondReq accesses(hits+misses) 746system.cpu0.dcache.demand_accesses::cpu0.data 160706624 # number of demand (read+write) accesses 747system.cpu0.dcache.demand_accesses::total 160706624 # number of demand (read+write) accesses 748system.cpu0.dcache.overall_accesses::cpu0.data 161563266 # number of overall (read+write) accesses 749system.cpu0.dcache.overall_accesses::total 161563266 # number of overall (read+write) accesses 750system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037038 # miss rate for ReadReq accesses 751system.cpu0.dcache.ReadReq_miss_rate::total 0.037038 # miss rate for ReadReq accesses 752system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018774 # miss rate for WriteReq accesses 753system.cpu0.dcache.WriteReq_miss_rate::total 0.018774 # miss rate for WriteReq accesses 754system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758373 # miss rate for SoftPFReq accesses 755system.cpu0.dcache.SoftPFReq_miss_rate::total 0.758373 # miss rate for SoftPFReq accesses 756system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.770037 # miss rate for WriteLineReq accesses 757system.cpu0.dcache.WriteLineReq_miss_rate::total 0.770037 # miss rate for WriteLineReq accesses 758system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083172 # miss rate for LoadLockedReq accesses 759system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083172 # miss rate for LoadLockedReq accesses 760system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.099542 # miss rate for StoreCondReq accesses 761system.cpu0.dcache.StoreCondReq_miss_rate::total 0.099542 # miss rate for StoreCondReq accesses 762system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033152 # miss rate for demand accesses 763system.cpu0.dcache.demand_miss_rate::total 0.033152 # miss rate for demand accesses 764system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036997 # miss rate for overall accesses 765system.cpu0.dcache.overall_miss_rate::total 0.036997 # miss rate for overall accesses 766system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15706.223438 # average ReadReq miss latency 767system.cpu0.dcache.ReadReq_avg_miss_latency::total 15706.223438 # average ReadReq miss latency 768system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21185.049300 # average WriteReq miss latency 769system.cpu0.dcache.WriteReq_avg_miss_latency::total 21185.049300 # average WriteReq miss latency 770system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32263.996781 # average WriteLineReq miss latency 771system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32263.996781 # average WriteLineReq miss latency 772system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15360.933828 # average LoadLockedReq miss latency 773system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15360.933828 # average LoadLockedReq miss latency 774system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23731.770626 # average StoreCondReq miss latency 775system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23731.770626 # average StoreCondReq miss latency 776system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 777system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 778system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19643.604089 # average overall miss latency 779system.cpu0.dcache.demand_avg_miss_latency::total 19643.604089 # average overall miss latency 780system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17508.619125 # average overall miss latency 781system.cpu0.dcache.overall_avg_miss_latency::total 17508.619125 # average overall miss latency 782system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 783system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 784system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 785system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 786system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 787system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 788system.cpu0.dcache.writebacks::writebacks 5731745 # number of writebacks 789system.cpu0.dcache.writebacks::total 5731745 # number of writebacks 790system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26385 # number of ReadReq MSHR hits 791system.cpu0.dcache.ReadReq_mshr_hits::total 26385 # number of ReadReq MSHR hits 792system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21245 # number of WriteReq MSHR hits 793system.cpu0.dcache.WriteReq_mshr_hits::total 21245 # number of WriteReq MSHR hits 794system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44162 # number of LoadLockedReq MSHR hits 795system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44162 # number of LoadLockedReq MSHR hits 796system.cpu0.dcache.demand_mshr_hits::cpu0.data 47630 # number of demand (read+write) MSHR hits 797system.cpu0.dcache.demand_mshr_hits::total 47630 # number of demand (read+write) MSHR hits 798system.cpu0.dcache.overall_mshr_hits::cpu0.data 47630 # number of overall MSHR hits 799system.cpu0.dcache.overall_mshr_hits::total 47630 # number of overall MSHR hits 800system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3083327 # number of ReadReq MSHR misses 801system.cpu0.dcache.ReadReq_mshr_misses::total 3083327 # number of ReadReq MSHR misses 802system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1400160 # number of WriteReq MSHR misses 803system.cpu0.dcache.WriteReq_mshr_misses::total 1400160 # number of WriteReq MSHR misses 804system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648080 # number of SoftPFReq MSHR misses 805system.cpu0.dcache.SoftPFReq_mshr_misses::total 648080 # number of SoftPFReq MSHR misses 806system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796576 # number of WriteLineReq MSHR misses 807system.cpu0.dcache.WriteLineReq_mshr_misses::total 796576 # number of WriteLineReq MSHR misses 808system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123492 # number of LoadLockedReq MSHR misses 809system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123492 # number of LoadLockedReq MSHR misses 810system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200528 # number of StoreCondReq MSHR misses 811system.cpu0.dcache.StoreCondReq_mshr_misses::total 200528 # number of StoreCondReq MSHR misses 812system.cpu0.dcache.demand_mshr_misses::cpu0.data 5280063 # number of demand (read+write) MSHR misses 813system.cpu0.dcache.demand_mshr_misses::total 5280063 # number of demand (read+write) MSHR misses 814system.cpu0.dcache.overall_mshr_misses::cpu0.data 5928143 # number of overall MSHR misses 815system.cpu0.dcache.overall_mshr_misses::total 5928143 # number of overall MSHR misses 816system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable 817system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16381 # number of ReadReq MSHR uncacheable 818system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable 819system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable 820system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses 821system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34075 # number of overall MSHR uncacheable misses 822system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44323294000 # number of ReadReq MSHR miss cycles 823system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44323294000 # number of ReadReq MSHR miss cycles 824system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28148510000 # number of WriteReq MSHR miss cycles 825system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28148510000 # number of WriteReq MSHR miss cycles 826system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14944693500 # number of SoftPFReq MSHR miss cycles 827system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14944693500 # number of SoftPFReq MSHR miss cycles 828system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24904149500 # number of WriteLineReq MSHR miss cycles 829system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24904149500 # number of WriteLineReq MSHR miss cycles 830system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1681387500 # number of LoadLockedReq MSHR miss cycles 831system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1681387500 # number of LoadLockedReq MSHR miss cycles 832system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4558410500 # number of StoreCondReq MSHR miss cycles 833system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4558410500 # number of StoreCondReq MSHR miss cycles 834system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2192000 # number of StoreCondFailReq MSHR miss cycles 835system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2192000 # number of StoreCondFailReq MSHR miss cycles 836system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 97375953500 # number of demand (read+write) MSHR miss cycles 837system.cpu0.dcache.demand_mshr_miss_latency::total 97375953500 # number of demand (read+write) MSHR miss cycles 838system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112320647000 # number of overall MSHR miss cycles 839system.cpu0.dcache.overall_mshr_miss_latency::total 112320647000 # number of overall MSHR miss cycles 840system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3040589500 # number of ReadReq MSHR uncacheable cycles 841system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3040589500 # number of ReadReq MSHR uncacheable cycles 842system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3040589500 # number of overall MSHR uncacheable cycles 843system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3040589500 # number of overall MSHR uncacheable cycles 844system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036724 # mshr miss rate for ReadReq accesses 845system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036724 # mshr miss rate for ReadReq accesses 846system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018493 # mshr miss rate for WriteReq accesses 847system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018493 # mshr miss rate for WriteReq accesses 848system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756535 # mshr miss rate for SoftPFReq accesses 849system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756535 # mshr miss rate for SoftPFReq accesses 850system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.770037 # mshr miss rate for WriteLineReq accesses 851system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.770037 # mshr miss rate for WriteLineReq accesses 852system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061263 # mshr miss rate for LoadLockedReq accesses 853system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061263 # mshr miss rate for LoadLockedReq accesses 854system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099542 # mshr miss rate for StoreCondReq accesses 855system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099542 # mshr miss rate for StoreCondReq accesses 856system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032855 # mshr miss rate for demand accesses 857system.cpu0.dcache.demand_mshr_miss_rate::total 0.032855 # mshr miss rate for demand accesses 858system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036692 # mshr miss rate for overall accesses 859system.cpu0.dcache.overall_mshr_miss_rate::total 0.036692 # mshr miss rate for overall accesses 860system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14375.151906 # average ReadReq mshr miss latency 861system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14375.151906 # average ReadReq mshr miss latency 862system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20103.780996 # average WriteReq mshr miss latency 863system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20103.780996 # average WriteReq mshr miss latency 864system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23059.951703 # average SoftPFReq mshr miss latency 865system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23059.951703 # average SoftPFReq mshr miss latency 866system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31263.996781 # average WriteLineReq mshr miss latency 867system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31263.996781 # average WriteLineReq mshr miss latency 868system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13615.355651 # average LoadLockedReq mshr miss latency 869system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13615.355651 # average LoadLockedReq mshr miss latency 870system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22732.039915 # average StoreCondReq mshr miss latency 871system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22732.039915 # average StoreCondReq mshr miss latency 872system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 873system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 874system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18442.195387 # average overall mshr miss latency 875system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18442.195387 # average overall mshr miss latency 876system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.020509 # average overall mshr miss latency 877system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.020509 # average overall mshr miss latency 878system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185616.842684 # average ReadReq mshr uncacheable latency 879system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185616.842684 # average ReadReq mshr uncacheable latency 880system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89232.267058 # average overall mshr uncacheable latency 881system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89232.267058 # average overall mshr uncacheable latency 882system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 883system.cpu0.icache.tags.replacements 4959559 # number of replacements 884system.cpu0.icache.tags.tagsinuse 511.903947 # Cycle average of tags in use 885system.cpu0.icache.tags.total_refs 458982923 # Total number of references to valid blocks. 886system.cpu0.icache.tags.sampled_refs 4960071 # Sample count of references to valid blocks. 887system.cpu0.icache.tags.avg_refs 92.535555 # Average number of references to valid blocks. 888system.cpu0.icache.tags.warmup_cycle 30768955000 # Cycle when the warmup percentage was hit. 889system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903947 # Average occupied blocks per requestor 890system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy 891system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy 892system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 893system.cpu0.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 894system.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 895system.cpu0.icache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id 896system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id 897system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 898system.cpu0.icache.tags.tag_accesses 932846061 # Number of tag accesses 899system.cpu0.icache.tags.data_accesses 932846061 # Number of data accesses 900system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 901system.cpu0.icache.ReadReq_hits::cpu0.inst 458982923 # number of ReadReq hits 902system.cpu0.icache.ReadReq_hits::total 458982923 # number of ReadReq hits 903system.cpu0.icache.demand_hits::cpu0.inst 458982923 # number of demand (read+write) hits 904system.cpu0.icache.demand_hits::total 458982923 # number of demand (read+write) hits 905system.cpu0.icache.overall_hits::cpu0.inst 458982923 # number of overall hits 906system.cpu0.icache.overall_hits::total 458982923 # number of overall hits 907system.cpu0.icache.ReadReq_misses::cpu0.inst 4960072 # number of ReadReq misses 908system.cpu0.icache.ReadReq_misses::total 4960072 # number of ReadReq misses 909system.cpu0.icache.demand_misses::cpu0.inst 4960072 # number of demand (read+write) misses 910system.cpu0.icache.demand_misses::total 4960072 # number of demand (read+write) misses 911system.cpu0.icache.overall_misses::cpu0.inst 4960072 # number of overall misses 912system.cpu0.icache.overall_misses::total 4960072 # number of overall misses 913system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54306348500 # number of ReadReq miss cycles 914system.cpu0.icache.ReadReq_miss_latency::total 54306348500 # number of ReadReq miss cycles 915system.cpu0.icache.demand_miss_latency::cpu0.inst 54306348500 # number of demand (read+write) miss cycles 916system.cpu0.icache.demand_miss_latency::total 54306348500 # number of demand (read+write) miss cycles 917system.cpu0.icache.overall_miss_latency::cpu0.inst 54306348500 # number of overall miss cycles 918system.cpu0.icache.overall_miss_latency::total 54306348500 # number of overall miss cycles 919system.cpu0.icache.ReadReq_accesses::cpu0.inst 463942995 # number of ReadReq accesses(hits+misses) 920system.cpu0.icache.ReadReq_accesses::total 463942995 # number of ReadReq accesses(hits+misses) 921system.cpu0.icache.demand_accesses::cpu0.inst 463942995 # number of demand (read+write) accesses 922system.cpu0.icache.demand_accesses::total 463942995 # number of demand (read+write) accesses 923system.cpu0.icache.overall_accesses::cpu0.inst 463942995 # number of overall (read+write) accesses 924system.cpu0.icache.overall_accesses::total 463942995 # number of overall (read+write) accesses 925system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010691 # miss rate for ReadReq accesses 926system.cpu0.icache.ReadReq_miss_rate::total 0.010691 # miss rate for ReadReq accesses 927system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010691 # miss rate for demand accesses 928system.cpu0.icache.demand_miss_rate::total 0.010691 # miss rate for demand accesses 929system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010691 # miss rate for overall accesses 930system.cpu0.icache.overall_miss_rate::total 0.010691 # miss rate for overall accesses 931system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.701652 # average ReadReq miss latency 932system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.701652 # average ReadReq miss latency 933system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency 934system.cpu0.icache.demand_avg_miss_latency::total 10948.701652 # average overall miss latency 935system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency 936system.cpu0.icache.overall_avg_miss_latency::total 10948.701652 # average overall miss latency 937system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 938system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 939system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 940system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 941system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 942system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 943system.cpu0.icache.writebacks::writebacks 4959559 # number of writebacks 944system.cpu0.icache.writebacks::total 4959559 # number of writebacks 945system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4960072 # number of ReadReq MSHR misses 946system.cpu0.icache.ReadReq_mshr_misses::total 4960072 # number of ReadReq MSHR misses 947system.cpu0.icache.demand_mshr_misses::cpu0.inst 4960072 # number of demand (read+write) MSHR misses 948system.cpu0.icache.demand_mshr_misses::total 4960072 # number of demand (read+write) MSHR misses 949system.cpu0.icache.overall_mshr_misses::cpu0.inst 4960072 # number of overall MSHR misses 950system.cpu0.icache.overall_mshr_misses::total 4960072 # number of overall MSHR misses 951system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 952system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 953system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 954system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 955system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51826313000 # number of ReadReq MSHR miss cycles 956system.cpu0.icache.ReadReq_mshr_miss_latency::total 51826313000 # number of ReadReq MSHR miss cycles 957system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51826313000 # number of demand (read+write) MSHR miss cycles 958system.cpu0.icache.demand_mshr_miss_latency::total 51826313000 # number of demand (read+write) MSHR miss cycles 959system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51826313000 # number of overall MSHR miss cycles 960system.cpu0.icache.overall_mshr_miss_latency::total 51826313000 # number of overall MSHR miss cycles 961system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles 962system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles 963system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles 964system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles 965system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for ReadReq accesses 966system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010691 # mshr miss rate for ReadReq accesses 967system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for demand accesses 968system.cpu0.icache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses 969system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for overall accesses 970system.cpu0.icache.overall_mshr_miss_rate::total 0.010691 # mshr miss rate for overall accesses 971system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average ReadReq mshr miss latency 972system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10448.701753 # average ReadReq mshr miss latency 973system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency 974system.cpu0.icache.demand_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency 975system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency 976system.cpu0.icache.overall_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency 977system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency 978system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency 979system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency 980system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency 981system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 982system.cpu0.l2cache.prefetcher.num_hwpf_issued 7732053 # number of hwpf issued 983system.cpu0.l2cache.prefetcher.pfIdentified 7732077 # number of prefetch candidates identified 984system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue 985system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 986system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 987system.cpu0.l2cache.prefetcher.pfSpanPage 1019171 # number of prefetches not generated due to page crossing 988system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 989system.cpu0.l2cache.tags.replacements 2286879 # number of replacements 990system.cpu0.l2cache.tags.tagsinuse 15893.622807 # Cycle average of tags in use 991system.cpu0.l2cache.tags.total_refs 9162734 # Total number of references to valid blocks. 992system.cpu0.l2cache.tags.sampled_refs 2302009 # Sample count of references to valid blocks. 993system.cpu0.l2cache.tags.avg_refs 3.980321 # Average number of references to valid blocks. 994system.cpu0.l2cache.tags.warmup_cycle 5406430500 # Cycle when the warmup percentage was hit. 995system.cpu0.l2cache.tags.occ_blocks::writebacks 15603.896064 # Average occupied blocks per requestor 996system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 29.949034 # Average occupied blocks per requestor 997system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 16.856945 # Average occupied blocks per requestor 998system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 242.920764 # Average occupied blocks per requestor 999system.cpu0.l2cache.tags.occ_percent::writebacks 0.952386 # Average percentage of cache occupancy 1000system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001828 # Average percentage of cache occupancy 1001system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001029 # Average percentage of cache occupancy 1002system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014827 # Average percentage of cache occupancy 1003system.cpu0.l2cache.tags.occ_percent::total 0.970070 # Average percentage of cache occupancy 1004system.cpu0.l2cache.tags.occ_task_id_blocks::1022 306 # Occupied blocks per task id 1005system.cpu0.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id 1006system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14757 # Occupied blocks per task id 1007system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id 1008system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 139 # Occupied blocks per task id 1009system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 67 # Occupied blocks per task id 1010system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1011system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id 1012system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 42 # Occupied blocks per task id 1013system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1014system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 1015system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 1016system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4608 # Occupied blocks per task id 1017system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8403 # Occupied blocks per task id 1018system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1616 # Occupied blocks per task id 1019system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018677 # Percentage of cache occupancy per task id 1020system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id 1021system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900696 # Percentage of cache occupancy per task id 1022system.cpu0.l2cache.tags.tag_accesses 368793343 # Number of tag accesses 1023system.cpu0.l2cache.tags.data_accesses 368793343 # Number of data accesses 1024system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1025system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 252482 # number of ReadReq hits 1026system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 146217 # number of ReadReq hits 1027system.cpu0.l2cache.ReadReq_hits::total 398699 # number of ReadReq hits 1028system.cpu0.l2cache.WritebackDirty_hits::writebacks 3794669 # number of WritebackDirty hits 1029system.cpu0.l2cache.WritebackDirty_hits::total 3794669 # number of WritebackDirty hits 1030system.cpu0.l2cache.WritebackClean_hits::writebacks 6895627 # number of WritebackClean hits 1031system.cpu0.l2cache.WritebackClean_hits::total 6895627 # number of WritebackClean hits 1032system.cpu0.l2cache.ReadExReq_hits::cpu0.data 932984 # number of ReadExReq hits 1033system.cpu0.l2cache.ReadExReq_hits::total 932984 # number of ReadExReq hits 1034system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4503327 # number of ReadCleanReq hits 1035system.cpu0.l2cache.ReadCleanReq_hits::total 4503327 # number of ReadCleanReq hits 1036system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2919116 # number of ReadSharedReq hits 1037system.cpu0.l2cache.ReadSharedReq_hits::total 2919116 # number of ReadSharedReq hits 1038system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 217183 # number of InvalidateReq hits 1039system.cpu0.l2cache.InvalidateReq_hits::total 217183 # number of InvalidateReq hits 1040system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 252482 # number of demand (read+write) hits 1041system.cpu0.l2cache.demand_hits::cpu0.itb.walker 146217 # number of demand (read+write) hits 1042system.cpu0.l2cache.demand_hits::cpu0.inst 4503327 # number of demand (read+write) hits 1043system.cpu0.l2cache.demand_hits::cpu0.data 3852100 # number of demand (read+write) hits 1044system.cpu0.l2cache.demand_hits::total 8754126 # number of demand (read+write) hits 1045system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 252482 # number of overall hits 1046system.cpu0.l2cache.overall_hits::cpu0.itb.walker 146217 # number of overall hits 1047system.cpu0.l2cache.overall_hits::cpu0.inst 4503327 # number of overall hits 1048system.cpu0.l2cache.overall_hits::cpu0.data 3852100 # number of overall hits 1049system.cpu0.l2cache.overall_hits::total 8754126 # number of overall hits 1050system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 17757 # number of ReadReq misses 1051system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8990 # number of ReadReq misses 1052system.cpu0.l2cache.ReadReq_misses::total 26747 # number of ReadReq misses 1053system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 236502 # number of UpgradeReq misses 1054system.cpu0.l2cache.UpgradeReq_misses::total 236502 # number of UpgradeReq misses 1055system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200518 # number of SCUpgradeReq misses 1056system.cpu0.l2cache.SCUpgradeReq_misses::total 200518 # number of SCUpgradeReq misses 1057system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses 1058system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 1059system.cpu0.l2cache.ReadExReq_misses::cpu0.data 248602 # number of ReadExReq misses 1060system.cpu0.l2cache.ReadExReq_misses::total 248602 # number of ReadExReq misses 1061system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 456745 # number of ReadCleanReq misses 1062system.cpu0.l2cache.ReadCleanReq_misses::total 456745 # number of ReadCleanReq misses 1063system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 935783 # number of ReadSharedReq misses 1064system.cpu0.l2cache.ReadSharedReq_misses::total 935783 # number of ReadSharedReq misses 1065system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 577322 # number of InvalidateReq misses 1066system.cpu0.l2cache.InvalidateReq_misses::total 577322 # number of InvalidateReq misses 1067system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 17757 # number of demand (read+write) misses 1068system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8990 # number of demand (read+write) misses 1069system.cpu0.l2cache.demand_misses::cpu0.inst 456745 # number of demand (read+write) misses 1070system.cpu0.l2cache.demand_misses::cpu0.data 1184385 # number of demand (read+write) misses 1071system.cpu0.l2cache.demand_misses::total 1667877 # number of demand (read+write) misses 1072system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 17757 # number of overall misses 1073system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8990 # number of overall misses 1074system.cpu0.l2cache.overall_misses::cpu0.inst 456745 # number of overall misses 1075system.cpu0.l2cache.overall_misses::cpu0.data 1184385 # number of overall misses 1076system.cpu0.l2cache.overall_misses::total 1667877 # number of overall misses 1077system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 557104000 # number of ReadReq miss cycles 1078system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 362043000 # number of ReadReq miss cycles 1079system.cpu0.l2cache.ReadReq_miss_latency::total 919147000 # number of ReadReq miss cycles 1080system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 930109500 # number of UpgradeReq miss cycles 1081system.cpu0.l2cache.UpgradeReq_miss_latency::total 930109500 # number of UpgradeReq miss cycles 1082system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 320714500 # number of SCUpgradeReq miss cycles 1083system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 320714500 # number of SCUpgradeReq miss cycles 1084system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2109497 # number of SCUpgradeFailReq miss cycles 1085system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2109497 # number of SCUpgradeFailReq miss cycles 1086system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13818048499 # number of ReadExReq miss cycles 1087system.cpu0.l2cache.ReadExReq_miss_latency::total 13818048499 # number of ReadExReq miss cycles 1088system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17338170000 # number of ReadCleanReq miss cycles 1089system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17338170000 # number of ReadCleanReq miss cycles 1090system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 36151090000 # number of ReadSharedReq miss cycles 1091system.cpu0.l2cache.ReadSharedReq_miss_latency::total 36151090000 # number of ReadSharedReq miss cycles 1092system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 305279500 # number of InvalidateReq miss cycles 1093system.cpu0.l2cache.InvalidateReq_miss_latency::total 305279500 # number of InvalidateReq miss cycles 1094system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 557104000 # number of demand (read+write) miss cycles 1095system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 362043000 # number of demand (read+write) miss cycles 1096system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17338170000 # number of demand (read+write) miss cycles 1097system.cpu0.l2cache.demand_miss_latency::cpu0.data 49969138499 # number of demand (read+write) miss cycles 1098system.cpu0.l2cache.demand_miss_latency::total 68226455499 # number of demand (read+write) miss cycles 1099system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 557104000 # number of overall miss cycles 1100system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 362043000 # number of overall miss cycles 1101system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17338170000 # number of overall miss cycles 1102system.cpu0.l2cache.overall_miss_latency::cpu0.data 49969138499 # number of overall miss cycles 1103system.cpu0.l2cache.overall_miss_latency::total 68226455499 # number of overall miss cycles 1104system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 270239 # number of ReadReq accesses(hits+misses) 1105system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 155207 # number of ReadReq accesses(hits+misses) 1106system.cpu0.l2cache.ReadReq_accesses::total 425446 # number of ReadReq accesses(hits+misses) 1107system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3794669 # number of WritebackDirty accesses(hits+misses) 1108system.cpu0.l2cache.WritebackDirty_accesses::total 3794669 # number of WritebackDirty accesses(hits+misses) 1109system.cpu0.l2cache.WritebackClean_accesses::writebacks 6895627 # number of WritebackClean accesses(hits+misses) 1110system.cpu0.l2cache.WritebackClean_accesses::total 6895627 # number of WritebackClean accesses(hits+misses) 1111system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 236502 # number of UpgradeReq accesses(hits+misses) 1112system.cpu0.l2cache.UpgradeReq_accesses::total 236502 # number of UpgradeReq accesses(hits+misses) 1113system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200518 # number of SCUpgradeReq accesses(hits+misses) 1114system.cpu0.l2cache.SCUpgradeReq_accesses::total 200518 # number of SCUpgradeReq accesses(hits+misses) 1115system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) 1116system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 1117system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1181586 # number of ReadExReq accesses(hits+misses) 1118system.cpu0.l2cache.ReadExReq_accesses::total 1181586 # number of ReadExReq accesses(hits+misses) 1119system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4960072 # number of ReadCleanReq accesses(hits+misses) 1120system.cpu0.l2cache.ReadCleanReq_accesses::total 4960072 # number of ReadCleanReq accesses(hits+misses) 1121system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3854899 # number of ReadSharedReq accesses(hits+misses) 1122system.cpu0.l2cache.ReadSharedReq_accesses::total 3854899 # number of ReadSharedReq accesses(hits+misses) 1123system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 794505 # number of InvalidateReq accesses(hits+misses) 1124system.cpu0.l2cache.InvalidateReq_accesses::total 794505 # number of InvalidateReq accesses(hits+misses) 1125system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 270239 # number of demand (read+write) accesses 1126system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 155207 # number of demand (read+write) accesses 1127system.cpu0.l2cache.demand_accesses::cpu0.inst 4960072 # number of demand (read+write) accesses 1128system.cpu0.l2cache.demand_accesses::cpu0.data 5036485 # number of demand (read+write) accesses 1129system.cpu0.l2cache.demand_accesses::total 10422003 # number of demand (read+write) accesses 1130system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 270239 # number of overall (read+write) accesses 1131system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 155207 # number of overall (read+write) accesses 1132system.cpu0.l2cache.overall_accesses::cpu0.inst 4960072 # number of overall (read+write) accesses 1133system.cpu0.l2cache.overall_accesses::cpu0.data 5036485 # number of overall (read+write) accesses 1134system.cpu0.l2cache.overall_accesses::total 10422003 # number of overall (read+write) accesses 1135system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for ReadReq accesses 1136system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057923 # miss rate for ReadReq accesses 1137system.cpu0.l2cache.ReadReq_miss_rate::total 0.062868 # miss rate for ReadReq accesses 1138system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1139system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1140system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1141system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1142system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1143system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1144system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.210397 # miss rate for ReadExReq accesses 1145system.cpu0.l2cache.ReadExReq_miss_rate::total 0.210397 # miss rate for ReadExReq accesses 1146system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092084 # miss rate for ReadCleanReq accesses 1147system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092084 # miss rate for ReadCleanReq accesses 1148system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242752 # miss rate for ReadSharedReq accesses 1149system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242752 # miss rate for ReadSharedReq accesses 1150system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.726644 # miss rate for InvalidateReq accesses 1151system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.726644 # miss rate for InvalidateReq accesses 1152system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for demand accesses 1153system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057923 # miss rate for demand accesses 1154system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092084 # miss rate for demand accesses 1155system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.235161 # miss rate for demand accesses 1156system.cpu0.l2cache.demand_miss_rate::total 0.160034 # miss rate for demand accesses 1157system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.065709 # miss rate for overall accesses 1158system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057923 # miss rate for overall accesses 1159system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092084 # miss rate for overall accesses 1160system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.235161 # miss rate for overall accesses 1161system.cpu0.l2cache.overall_miss_rate::total 0.160034 # miss rate for overall accesses 1162system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average ReadReq miss latency 1163system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40271.746385 # average ReadReq miss latency 1164system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34364.489475 # average ReadReq miss latency 1165system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3932.776467 # average UpgradeReq miss latency 1166system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3932.776467 # average UpgradeReq miss latency 1167system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1599.429976 # average SCUpgradeReq miss latency 1168system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1599.429976 # average SCUpgradeReq miss latency 1169system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 210949.700000 # average SCUpgradeFailReq miss latency 1170system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 210949.700000 # average SCUpgradeFailReq miss latency 1171system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55583.014211 # average ReadExReq miss latency 1172system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55583.014211 # average ReadExReq miss latency 1173system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37960.284185 # average ReadCleanReq miss latency 1174system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37960.284185 # average ReadCleanReq miss latency 1175system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 38631.915733 # average ReadSharedReq miss latency 1176system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 38631.915733 # average ReadSharedReq miss latency 1177system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 528.785496 # average InvalidateReq miss latency 1178system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 528.785496 # average InvalidateReq miss latency 1179system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average overall miss latency 1180system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40271.746385 # average overall miss latency 1181system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37960.284185 # average overall miss latency 1182system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42189.945414 # average overall miss latency 1183system.cpu0.l2cache.demand_avg_miss_latency::total 40906.167241 # average overall miss latency 1184system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31373.768091 # average overall miss latency 1185system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40271.746385 # average overall miss latency 1186system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37960.284185 # average overall miss latency 1187system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42189.945414 # average overall miss latency 1188system.cpu0.l2cache.overall_avg_miss_latency::total 40906.167241 # average overall miss latency 1189system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1190system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1191system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1192system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1193system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1194system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1195system.cpu0.l2cache.unused_prefetches 38115 # number of HardPF blocks evicted w/o reference 1196system.cpu0.l2cache.writebacks::writebacks 1518116 # number of writebacks 1197system.cpu0.l2cache.writebacks::total 1518116 # number of writebacks 1198system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6419 # number of ReadExReq MSHR hits 1199system.cpu0.l2cache.ReadExReq_mshr_hits::total 6419 # number of ReadExReq MSHR hits 1200system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 459 # number of ReadSharedReq MSHR hits 1201system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 459 # number of ReadSharedReq MSHR hits 1202system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6878 # number of demand (read+write) MSHR hits 1203system.cpu0.l2cache.demand_mshr_hits::total 6878 # number of demand (read+write) MSHR hits 1204system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6878 # number of overall MSHR hits 1205system.cpu0.l2cache.overall_mshr_hits::total 6878 # number of overall MSHR hits 1206system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 17757 # number of ReadReq MSHR misses 1207system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8990 # number of ReadReq MSHR misses 1208system.cpu0.l2cache.ReadReq_mshr_misses::total 26747 # number of ReadReq MSHR misses 1209system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 749864 # number of HardPFReq MSHR misses 1210system.cpu0.l2cache.HardPFReq_mshr_misses::total 749864 # number of HardPFReq MSHR misses 1211system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 236502 # number of UpgradeReq MSHR misses 1212system.cpu0.l2cache.UpgradeReq_mshr_misses::total 236502 # number of UpgradeReq MSHR misses 1213system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 200518 # number of SCUpgradeReq MSHR misses 1214system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 200518 # number of SCUpgradeReq MSHR misses 1215system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses 1216system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses 1217system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 242183 # number of ReadExReq MSHR misses 1218system.cpu0.l2cache.ReadExReq_mshr_misses::total 242183 # number of ReadExReq MSHR misses 1219system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 456745 # number of ReadCleanReq MSHR misses 1220system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 456745 # number of ReadCleanReq MSHR misses 1221system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 935324 # number of ReadSharedReq MSHR misses 1222system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 935324 # number of ReadSharedReq MSHR misses 1223system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 577322 # number of InvalidateReq MSHR misses 1224system.cpu0.l2cache.InvalidateReq_mshr_misses::total 577322 # number of InvalidateReq MSHR misses 1225system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 17757 # number of demand (read+write) MSHR misses 1226system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8990 # number of demand (read+write) MSHR misses 1227system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 456745 # number of demand (read+write) MSHR misses 1228system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1177507 # number of demand (read+write) MSHR misses 1229system.cpu0.l2cache.demand_mshr_misses::total 1660999 # number of demand (read+write) MSHR misses 1230system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 17757 # number of overall MSHR misses 1231system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8990 # number of overall MSHR misses 1232system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 456745 # number of overall MSHR misses 1233system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1177507 # number of overall MSHR misses 1234system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 749864 # number of overall MSHR misses 1235system.cpu0.l2cache.overall_mshr_misses::total 2410863 # number of overall MSHR misses 1236system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 1237system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable 1238system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59506 # number of ReadReq MSHR uncacheable 1239system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable 1240system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable 1241system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 1242system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses 1243system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77200 # number of overall MSHR uncacheable misses 1244system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of ReadReq MSHR miss cycles 1245system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 308103000 # number of ReadReq MSHR miss cycles 1246system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 758665000 # number of ReadReq MSHR miss cycles 1247system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37032584946 # number of HardPFReq MSHR miss cycles 1248system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37032584946 # number of HardPFReq MSHR miss cycles 1249system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4392780000 # number of UpgradeReq MSHR miss cycles 1250system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4392780000 # number of UpgradeReq MSHR miss cycles 1251system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3053423000 # number of SCUpgradeReq MSHR miss cycles 1252system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3053423000 # number of SCUpgradeReq MSHR miss cycles 1253system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1785497 # number of SCUpgradeFailReq MSHR miss cycles 1254system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1785497 # number of SCUpgradeFailReq MSHR miss cycles 1255system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11646133999 # number of ReadExReq MSHR miss cycles 1256system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11646133999 # number of ReadExReq MSHR miss cycles 1257system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14597700000 # number of ReadCleanReq MSHR miss cycles 1258system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14597700000 # number of ReadCleanReq MSHR miss cycles 1259system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 30480683500 # number of ReadSharedReq MSHR miss cycles 1260system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 30480683500 # number of ReadSharedReq MSHR miss cycles 1261system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 18786696000 # number of InvalidateReq MSHR miss cycles 1262system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 18786696000 # number of InvalidateReq MSHR miss cycles 1263system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of demand (read+write) MSHR miss cycles 1264system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 308103000 # number of demand (read+write) MSHR miss cycles 1265system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14597700000 # number of demand (read+write) MSHR miss cycles 1266system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 42126817499 # number of demand (read+write) MSHR miss cycles 1267system.cpu0.l2cache.demand_mshr_miss_latency::total 57483182499 # number of demand (read+write) MSHR miss cycles 1268system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 450562000 # number of overall MSHR miss cycles 1269system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 308103000 # number of overall MSHR miss cycles 1270system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14597700000 # number of overall MSHR miss cycles 1271system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42126817499 # number of overall MSHR miss cycles 1272system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37032584946 # number of overall MSHR miss cycles 1273system.cpu0.l2cache.overall_mshr_miss_latency::total 94515767445 # number of overall MSHR miss cycles 1274system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of ReadReq MSHR uncacheable cycles 1275system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2909184500 # number of ReadReq MSHR uncacheable cycles 1276system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6702281000 # number of ReadReq MSHR uncacheable cycles 1277system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3793096500 # number of overall MSHR uncacheable cycles 1278system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2909184500 # number of overall MSHR uncacheable cycles 1279system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6702281000 # number of overall MSHR uncacheable cycles 1280system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for ReadReq accesses 1281system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for ReadReq accesses 1282system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062868 # mshr miss rate for ReadReq accesses 1283system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1284system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1285system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1286system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1287system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1288system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1289system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1290system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1291system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.204964 # mshr miss rate for ReadExReq accesses 1292system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.204964 # mshr miss rate for ReadExReq accesses 1293system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for ReadCleanReq accesses 1294system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092084 # mshr miss rate for ReadCleanReq accesses 1295system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242633 # mshr miss rate for ReadSharedReq accesses 1296system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242633 # mshr miss rate for ReadSharedReq accesses 1297system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.726644 # mshr miss rate for InvalidateReq accesses 1298system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.726644 # mshr miss rate for InvalidateReq accesses 1299system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for demand accesses 1300system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for demand accesses 1301system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for demand accesses 1302system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for demand accesses 1303system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159374 # mshr miss rate for demand accesses 1304system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for overall accesses 1305system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for overall accesses 1306system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for overall accesses 1307system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for overall accesses 1308system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1309system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231324 # mshr miss rate for overall accesses 1310system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average ReadReq mshr miss latency 1311system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average ReadReq mshr miss latency 1312system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28364.489475 # average ReadReq mshr miss latency 1313system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average HardPFReq mshr miss latency 1314system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49385.735208 # average HardPFReq mshr miss latency 1315system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18573.965548 # average UpgradeReq mshr miss latency 1316system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18573.965548 # average UpgradeReq mshr miss latency 1317system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15227.675321 # average SCUpgradeReq mshr miss latency 1318system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15227.675321 # average SCUpgradeReq mshr miss latency 1319system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178549.700000 # average SCUpgradeFailReq mshr miss latency 1320system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178549.700000 # average SCUpgradeFailReq mshr miss latency 1321system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48088.156473 # average ReadExReq mshr miss latency 1322system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48088.156473 # average ReadExReq mshr miss latency 1323system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average ReadCleanReq mshr miss latency 1324system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31960.284185 # average ReadCleanReq mshr miss latency 1325system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32588.368843 # average ReadSharedReq mshr miss latency 1326system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32588.368843 # average ReadSharedReq mshr miss latency 1327system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32541.105310 # average InvalidateReq mshr miss latency 1328system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32541.105310 # average InvalidateReq mshr miss latency 1329system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency 1330system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency 1331system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency 1332system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency 1333system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34607.596091 # average overall mshr miss latency 1334system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency 1335system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency 1336system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency 1337system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency 1338system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average overall mshr miss latency 1339system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39204.122111 # average overall mshr miss latency 1340system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency 1341system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177595.049142 # average ReadReq mshr uncacheable latency 1342system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112632.020300 # average ReadReq mshr uncacheable latency 1343system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency 1344system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85375.920763 # average overall mshr uncacheable latency 1345system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86817.111399 # average overall mshr uncacheable latency 1346system.cpu0.toL2Bus.snoop_filter.tot_requests 22159208 # Total number of requests made to the snoop filter. 1347system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11368269 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1348system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1349system.cpu0.toL2Bus.snoop_filter.tot_snoops 619514 # Total number of snoops made to the snoop filter. 1350system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 619512 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1351system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1352system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1353system.cpu0.toL2Bus.trans_dist::ReadReq 553426 # Transaction distribution 1354system.cpu0.toL2Bus.trans_dist::ReadResp 9465318 # Transaction distribution 1355system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1356system.cpu0.toL2Bus.trans_dist::WriteReq 17695 # Transaction distribution 1357system.cpu0.toL2Bus.trans_dist::WriteResp 17694 # Transaction distribution 1358system.cpu0.toL2Bus.trans_dist::WritebackDirty 5316723 # Transaction distribution 1359system.cpu0.toL2Bus.trans_dist::WritebackClean 6896635 # Transaction distribution 1360system.cpu0.toL2Bus.trans_dist::CleanEvict 1098455 # Transaction distribution 1361system.cpu0.toL2Bus.trans_dist::HardPFReq 916448 # Transaction distribution 1362system.cpu0.toL2Bus.trans_dist::UpgradeReq 433150 # Transaction distribution 1363system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 369627 # Transaction distribution 1364system.cpu0.toL2Bus.trans_dist::UpgradeResp 506111 # Transaction distribution 1365system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution 1366system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 1367system.cpu0.toL2Bus.trans_dist::ReadExReq 1214944 # Transaction distribution 1368system.cpu0.toL2Bus.trans_dist::ReadExResp 1192020 # Transaction distribution 1369system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4960072 # Transaction distribution 1370system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4756139 # Transaction distribution 1371system.cpu0.toL2Bus.trans_dist::InvalidateReq 842201 # Transaction distribution 1372system.cpu0.toL2Bus.trans_dist::InvalidateResp 794505 # Transaction distribution 1373system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14965952 # Packet count per connected master and slave (bytes) 1374system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18512478 # Packet count per connected master and slave (bytes) 1375system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327835 # Packet count per connected master and slave (bytes) 1376system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 591529 # Packet count per connected master and slave (bytes) 1377system.cpu0.toL2Bus.pkt_count::total 34397794 # Packet count per connected master and slave (bytes) 1378system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 635028820 # Cumulative packet size per connected master and slave (bytes) 1379system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696134983 # Cumulative packet size per connected master and slave (bytes) 1380system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241656 # Cumulative packet size per connected master and slave (bytes) 1381system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2161912 # Cumulative packet size per connected master and slave (bytes) 1382system.cpu0.toL2Bus.pkt_size::total 1334567371 # Cumulative packet size per connected master and slave (bytes) 1383system.cpu0.toL2Bus.snoops 5130075 # Total snoops (count) 1384system.cpu0.toL2Bus.snoopTraffic 104832276 # Total snoop traffic (bytes) 1385system.cpu0.toL2Bus.snoop_fanout::samples 16684270 # Request fanout histogram 1386system.cpu0.toL2Bus.snoop_fanout::mean 0.051566 # Request fanout histogram 1387system.cpu0.toL2Bus.snoop_fanout::stdev 0.221149 # Request fanout histogram 1388system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1389system.cpu0.toL2Bus.snoop_fanout::0 15823936 94.84% 94.84% # Request fanout histogram 1390system.cpu0.toL2Bus.snoop_fanout::1 860332 5.16% 100.00% # Request fanout histogram 1391system.cpu0.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram 1392system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1393system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1394system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1395system.cpu0.toL2Bus.snoop_fanout::total 16684270 # Request fanout histogram 1396system.cpu0.toL2Bus.reqLayer0.occupancy 21945410994 # Layer occupancy (ticks) 1397system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1398system.cpu0.toL2Bus.snoopLayer0.occupancy 195855793 # Layer occupancy (ticks) 1399system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1400system.cpu0.toL2Bus.respLayer0.occupancy 7483231500 # Layer occupancy (ticks) 1401system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1402system.cpu0.toL2Bus.respLayer1.occupancy 8196031021 # Layer occupancy (ticks) 1403system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1404system.cpu0.toL2Bus.respLayer2.occupancy 172628000 # Layer occupancy (ticks) 1405system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1406system.cpu0.toL2Bus.respLayer3.occupancy 321290000 # Layer occupancy (ticks) 1407system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1408system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1409system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1410system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1411system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1412system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1413system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1414system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1415system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1416system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1417system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1418system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1419system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1420system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1421system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1422system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1423system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1424system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1425system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1426system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1427system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1428system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1429system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1430system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1431system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1432system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1433system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1434system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1435system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1436system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1437system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1438system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1439system.cpu1.dtb.walker.walks 99152 # Table walker walks requested 1440system.cpu1.dtb.walker.walksLong 99152 # Table walker walks initiated with long descriptors 1441system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8586 # Level at which table walker walks with long descriptors terminate 1442system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75770 # Level at which table walker walks with long descriptors terminate 1443system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting 1444system.cpu1.dtb.walker.walkWaitTime::samples 99148 # Table walker wait (enqueue to first request) latency 1445system.cpu1.dtb.walker.walkWaitTime::mean 0.080687 # Table walker wait (enqueue to first request) latency 1446system.cpu1.dtb.walker.walkWaitTime::stdev 25.406685 # Table walker wait (enqueue to first request) latency 1447system.cpu1.dtb.walker.walkWaitTime::0-511 99147 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1448system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1449system.cpu1.dtb.walker.walkWaitTime::total 99148 # Table walker wait (enqueue to first request) latency 1450system.cpu1.dtb.walker.walkCompletionTime::samples 84360 # Table walker service (enqueue to completion) latency 1451system.cpu1.dtb.walker.walkCompletionTime::mean 24513.021574 # Table walker service (enqueue to completion) latency 1452system.cpu1.dtb.walker.walkCompletionTime::gmean 22367.425597 # Table walker service (enqueue to completion) latency 1453system.cpu1.dtb.walker.walkCompletionTime::stdev 18734.439703 # Table walker service (enqueue to completion) latency 1454system.cpu1.dtb.walker.walkCompletionTime::0-65535 83116 98.53% 98.53% # Table walker service (enqueue to completion) latency 1455system.cpu1.dtb.walker.walkCompletionTime::65536-131071 940 1.11% 99.64% # Table walker service (enqueue to completion) latency 1456system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.19% 99.83% # Table walker service (enqueue to completion) latency 1457system.cpu1.dtb.walker.walkCompletionTime::196608-262143 58 0.07% 99.90% # Table walker service (enqueue to completion) latency 1458system.cpu1.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.94% # Table walker service (enqueue to completion) latency 1459system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.97% # Table walker service (enqueue to completion) latency 1460system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 1461system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 1462system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.02% 100.00% # Table walker service (enqueue to completion) latency 1463system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1464system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1465system.cpu1.dtb.walker.walkCompletionTime::total 84360 # Table walker service (enqueue to completion) latency 1466system.cpu1.dtb.walker.walksPending::samples 407519048 # Table walker pending requests distribution 1467system.cpu1.dtb.walker.walksPending::mean 2.490877 # Table walker pending requests distribution 1468system.cpu1.dtb.walker.walksPending::0 -607560648 -149.09% -149.09% # Table walker pending requests distribution 1469system.cpu1.dtb.walker.walksPending::1 1015079696 249.09% 100.00% # Table walker pending requests distribution 1470system.cpu1.dtb.walker.walksPending::total 407519048 # Table walker pending requests distribution 1471system.cpu1.dtb.walker.walkPageSizes::4K 75770 89.82% 89.82% # Table walker page sizes translated 1472system.cpu1.dtb.walker.walkPageSizes::2M 8586 10.18% 100.00% # Table walker page sizes translated 1473system.cpu1.dtb.walker.walkPageSizes::total 84356 # Table walker page sizes translated 1474system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99152 # Table walker requests started/completed, data/inst 1475system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1476system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99152 # Table walker requests started/completed, data/inst 1477system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84356 # Table walker requests started/completed, data/inst 1478system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1479system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84356 # Table walker requests started/completed, data/inst 1480system.cpu1.dtb.walker.walkRequestOrigin::total 183508 # Table walker requests started/completed, data/inst 1481system.cpu1.dtb.inst_hits 0 # ITB inst hits 1482system.cpu1.dtb.inst_misses 0 # ITB inst misses 1483system.cpu1.dtb.read_hits 78885011 # DTB read hits 1484system.cpu1.dtb.read_misses 72039 # DTB read misses 1485system.cpu1.dtb.write_hits 71761800 # DTB write hits 1486system.cpu1.dtb.write_misses 27113 # DTB write misses 1487system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1488system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1489system.cpu1.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID 1490system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 1491system.cpu1.dtb.flush_entries 36637 # Number of entries that have been flushed from TLB 1492system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1493system.cpu1.dtb.prefetch_faults 3802 # Number of TLB faults due to prefetch 1494system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1495system.cpu1.dtb.perms_faults 10123 # Number of TLB faults due to permissions restrictions 1496system.cpu1.dtb.read_accesses 78957050 # DTB read accesses 1497system.cpu1.dtb.write_accesses 71788913 # DTB write accesses 1498system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1499system.cpu1.dtb.hits 150646811 # DTB hits 1500system.cpu1.dtb.misses 99152 # DTB misses 1501system.cpu1.dtb.accesses 150745963 # DTB accesses 1502system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1503system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1504system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1505system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1506system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1507system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1508system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1509system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1510system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1511system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1512system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1513system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1514system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1515system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1516system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1517system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1518system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1519system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1520system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1521system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1522system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1523system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1524system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1525system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1526system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1527system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1528system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1529system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1530system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1531system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1532system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1533system.cpu1.itb.walker.walks 58316 # Table walker walks requested 1534system.cpu1.itb.walker.walksLong 58316 # Table walker walks initiated with long descriptors 1535system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate 1536system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52495 # Level at which table walker walks with long descriptors terminate 1537system.cpu1.itb.walker.walkWaitTime::samples 58316 # Table walker wait (enqueue to first request) latency 1538system.cpu1.itb.walker.walkWaitTime::0 58316 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1539system.cpu1.itb.walker.walkWaitTime::total 58316 # Table walker wait (enqueue to first request) latency 1540system.cpu1.itb.walker.walkCompletionTime::samples 53121 # Table walker service (enqueue to completion) latency 1541system.cpu1.itb.walker.walkCompletionTime::mean 27183.693831 # Table walker service (enqueue to completion) latency 1542system.cpu1.itb.walker.walkCompletionTime::gmean 24219.790403 # Table walker service (enqueue to completion) latency 1543system.cpu1.itb.walker.walkCompletionTime::stdev 26514.333195 # Table walker service (enqueue to completion) latency 1544system.cpu1.itb.walker.walkCompletionTime::0-65535 51734 97.39% 97.39% # Table walker service (enqueue to completion) latency 1545system.cpu1.itb.walker.walkCompletionTime::65536-131071 949 1.79% 99.18% # Table walker service (enqueue to completion) latency 1546system.cpu1.itb.walker.walkCompletionTime::131072-196607 242 0.46% 99.63% # Table walker service (enqueue to completion) latency 1547system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.15% 99.78% # Table walker service (enqueue to completion) latency 1548system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.88% # Table walker service (enqueue to completion) latency 1549system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.91% # Table walker service (enqueue to completion) latency 1550system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.92% # Table walker service (enqueue to completion) latency 1551system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.93% # Table walker service (enqueue to completion) latency 1552system.cpu1.itb.walker.walkCompletionTime::589824-655359 33 0.06% 99.99% # Table walker service (enqueue to completion) latency 1553system.cpu1.itb.walker.walkCompletionTime::655360-720895 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1554system.cpu1.itb.walker.walkCompletionTime::total 53121 # Table walker service (enqueue to completion) latency 1555system.cpu1.itb.walker.walksPending::samples -615394148 # Table walker pending requests distribution 1556system.cpu1.itb.walker.walksPending::0 -615394148 100.00% 100.00% # Table walker pending requests distribution 1557system.cpu1.itb.walker.walksPending::total -615394148 # Table walker pending requests distribution 1558system.cpu1.itb.walker.walkPageSizes::4K 52495 98.82% 98.82% # Table walker page sizes translated 1559system.cpu1.itb.walker.walkPageSizes::2M 626 1.18% 100.00% # Table walker page sizes translated 1560system.cpu1.itb.walker.walkPageSizes::total 53121 # Table walker page sizes translated 1561system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1562system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58316 # Table walker requests started/completed, data/inst 1563system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58316 # Table walker requests started/completed, data/inst 1564system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1565system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53121 # Table walker requests started/completed, data/inst 1566system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53121 # Table walker requests started/completed, data/inst 1567system.cpu1.itb.walker.walkRequestOrigin::total 111437 # Table walker requests started/completed, data/inst 1568system.cpu1.itb.inst_hits 416140593 # ITB inst hits 1569system.cpu1.itb.inst_misses 58316 # ITB inst misses 1570system.cpu1.itb.read_hits 0 # DTB read hits 1571system.cpu1.itb.read_misses 0 # DTB read misses 1572system.cpu1.itb.write_hits 0 # DTB write hits 1573system.cpu1.itb.write_misses 0 # DTB write misses 1574system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1575system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1576system.cpu1.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID 1577system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 1578system.cpu1.itb.flush_entries 25699 # Number of entries that have been flushed from TLB 1579system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1580system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1581system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1582system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1583system.cpu1.itb.read_accesses 0 # DTB read accesses 1584system.cpu1.itb.write_accesses 0 # DTB write accesses 1585system.cpu1.itb.inst_accesses 416198909 # ITB inst accesses 1586system.cpu1.itb.hits 416140593 # DTB hits 1587system.cpu1.itb.misses 58316 # DTB misses 1588system.cpu1.itb.accesses 416198909 # DTB accesses 1589system.cpu1.numPwrStateTransitions 28692 # Number of power state transitions 1590system.cpu1.pwrStateClkGateDist::samples 14346 # Distribution of time spent in the clock gated state 1591system.cpu1.pwrStateClkGateDist::mean 3269284130.341071 # Distribution of time spent in the clock gated state 1592system.cpu1.pwrStateClkGateDist::stdev 86001867955.202789 # Distribution of time spent in the clock gated state 1593system.cpu1.pwrStateClkGateDist::underflows 3953 27.55% 27.55% # Distribution of time spent in the clock gated state 1594system.cpu1.pwrStateClkGateDist::1000-5e+10 10364 72.24% 99.80% # Distribution of time spent in the clock gated state 1595system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.83% # Distribution of time spent in the clock gated state 1596system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 1597system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state 1598system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 1599system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 1600system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 1601system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 1602system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 1603system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 1604system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1605system.cpu1.pwrStateClkGateDist::max_value 7510077904252 # Distribution of time spent in the clock gated state 1606system.cpu1.pwrStateClkGateDist::total 14346 # Distribution of time spent in the clock gated state 1607system.cpu1.pwrStateResidencyTicks::ON 503862826627 # Cumulative time (in ticks) in various power states 1608system.cpu1.pwrStateResidencyTicks::CLK_GATED 46901150133873 # Cumulative time (in ticks) in various power states 1609system.cpu1.numCycles 94810025921 # number of cpu cycles simulated 1610system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1611system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1612system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1613system.cpu1.kern.inst.quiesce 14346 # number of quiesce instructions executed 1614system.cpu1.committedInsts 415840875 # Number of instructions committed 1615system.cpu1.committedOps 490335926 # Number of ops (including micro ops) committed 1616system.cpu1.num_int_alu_accesses 450775425 # Number of integer alu accesses 1617system.cpu1.num_fp_alu_accesses 467875 # Number of float alu accesses 1618system.cpu1.num_func_calls 24835210 # number of times a function call or return occured 1619system.cpu1.num_conditional_control_insts 63203882 # number of instructions that are conditional controls 1620system.cpu1.num_int_insts 450775425 # number of integer instructions 1621system.cpu1.num_fp_insts 467875 # number of float instructions 1622system.cpu1.num_int_register_reads 655878523 # number of times the integer registers were read 1623system.cpu1.num_int_register_writes 357644258 # number of times the integer registers were written 1624system.cpu1.num_fp_register_reads 746575 # number of times the floating registers were read 1625system.cpu1.num_fp_register_writes 415812 # number of times the floating registers were written 1626system.cpu1.num_cc_register_reads 107608929 # number of times the CC registers were read 1627system.cpu1.num_cc_register_writes 107374492 # number of times the CC registers were written 1628system.cpu1.num_mem_refs 150638767 # number of memory refs 1629system.cpu1.num_load_insts 78882725 # Number of load instructions 1630system.cpu1.num_store_insts 71756042 # Number of store instructions 1631system.cpu1.num_idle_cycles 93802300267.744019 # Number of idle cycles 1632system.cpu1.num_busy_cycles 1007725653.255979 # Number of busy cycles 1633system.cpu1.not_idle_fraction 0.010629 # Percentage of non-idle cycles 1634system.cpu1.idle_fraction 0.989371 # Percentage of idle cycles 1635system.cpu1.Branches 92635099 # Number of branches fetched 1636system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 1637system.cpu1.op_class::IntAlu 338840052 69.06% 69.06% # Class of executed instruction 1638system.cpu1.op_class::IntMult 1031473 0.21% 69.27% # Class of executed instruction 1639system.cpu1.op_class::IntDiv 58381 0.01% 69.28% # Class of executed instruction 1640system.cpu1.op_class::FloatAdd 0 0.00% 69.28% # Class of executed instruction 1641system.cpu1.op_class::FloatCmp 0 0.00% 69.28% # Class of executed instruction 1642system.cpu1.op_class::FloatCvt 0 0.00% 69.28% # Class of executed instruction 1643system.cpu1.op_class::FloatMult 0 0.00% 69.28% # Class of executed instruction 1644system.cpu1.op_class::FloatDiv 0 0.00% 69.28% # Class of executed instruction 1645system.cpu1.op_class::FloatSqrt 0 0.00% 69.28% # Class of executed instruction 1646system.cpu1.op_class::SimdAdd 0 0.00% 69.28% # Class of executed instruction 1647system.cpu1.op_class::SimdAddAcc 0 0.00% 69.28% # Class of executed instruction 1648system.cpu1.op_class::SimdAlu 0 0.00% 69.28% # Class of executed instruction 1649system.cpu1.op_class::SimdCmp 0 0.00% 69.28% # Class of executed instruction 1650system.cpu1.op_class::SimdCvt 0 0.00% 69.28% # Class of executed instruction 1651system.cpu1.op_class::SimdMisc 0 0.00% 69.28% # Class of executed instruction 1652system.cpu1.op_class::SimdMult 0 0.00% 69.28% # Class of executed instruction 1653system.cpu1.op_class::SimdMultAcc 0 0.00% 69.28% # Class of executed instruction 1654system.cpu1.op_class::SimdShift 0 0.00% 69.28% # Class of executed instruction 1655system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.28% # Class of executed instruction 1656system.cpu1.op_class::SimdSqrt 0 0.00% 69.28% # Class of executed instruction 1657system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.28% # Class of executed instruction 1658system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.28% # Class of executed instruction 1659system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.28% # Class of executed instruction 1660system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.28% # Class of executed instruction 1661system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.28% # Class of executed instruction 1662system.cpu1.op_class::SimdFloatMisc 67037 0.01% 69.30% # Class of executed instruction 1663system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction 1664system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction 1665system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction 1666system.cpu1.op_class::MemRead 78882725 16.08% 85.37% # Class of executed instruction 1667system.cpu1.op_class::MemWrite 71756042 14.63% 100.00% # Class of executed instruction 1668system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1669system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1670system.cpu1.op_class::total 490635753 # Class of executed instruction 1671system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1672system.cpu1.dcache.tags.replacements 4949273 # number of replacements 1673system.cpu1.dcache.tags.tagsinuse 456.328608 # Cycle average of tags in use 1674system.cpu1.dcache.tags.total_refs 145491110 # Total number of references to valid blocks. 1675system.cpu1.dcache.tags.sampled_refs 4949785 # Sample count of references to valid blocks. 1676system.cpu1.dcache.tags.avg_refs 29.393420 # Average number of references to valid blocks. 1677system.cpu1.dcache.tags.warmup_cycle 8379669141000 # Cycle when the warmup percentage was hit. 1678system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.328608 # Average occupied blocks per requestor 1679system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891267 # Average percentage of cache occupancy 1680system.cpu1.dcache.tags.occ_percent::total 0.891267 # Average percentage of cache occupancy 1681system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1682system.cpu1.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id 1683system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id 1684system.cpu1.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id 1685system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1686system.cpu1.dcache.tags.tag_accesses 306227498 # Number of tag accesses 1687system.cpu1.dcache.tags.data_accesses 306227498 # Number of data accesses 1688system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1689system.cpu1.dcache.ReadReq_hits::cpu1.data 73475131 # number of ReadReq hits 1690system.cpu1.dcache.ReadReq_hits::total 73475131 # number of ReadReq hits 1691system.cpu1.dcache.WriteReq_hits::cpu1.data 68103188 # number of WriteReq hits 1692system.cpu1.dcache.WriteReq_hits::total 68103188 # number of WriteReq hits 1693system.cpu1.dcache.SoftPFReq_hits::cpu1.data 168046 # number of SoftPFReq hits 1694system.cpu1.dcache.SoftPFReq_hits::total 168046 # number of SoftPFReq hits 1695system.cpu1.dcache.WriteLineReq_hits::cpu1.data 87192 # number of WriteLineReq hits 1696system.cpu1.dcache.WriteLineReq_hits::total 87192 # number of WriteLineReq hits 1697system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1644934 # number of LoadLockedReq hits 1698system.cpu1.dcache.LoadLockedReq_hits::total 1644934 # number of LoadLockedReq hits 1699system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602204 # number of StoreCondReq hits 1700system.cpu1.dcache.StoreCondReq_hits::total 1602204 # number of StoreCondReq hits 1701system.cpu1.dcache.demand_hits::cpu1.data 141665511 # number of demand (read+write) hits 1702system.cpu1.dcache.demand_hits::total 141665511 # number of demand (read+write) hits 1703system.cpu1.dcache.overall_hits::cpu1.data 141833557 # number of overall hits 1704system.cpu1.dcache.overall_hits::total 141833557 # number of overall hits 1705system.cpu1.dcache.ReadReq_misses::cpu1.data 2804863 # number of ReadReq misses 1706system.cpu1.dcache.ReadReq_misses::total 2804863 # number of ReadReq misses 1707system.cpu1.dcache.WriteReq_misses::cpu1.data 1292961 # number of WriteReq misses 1708system.cpu1.dcache.WriteReq_misses::total 1292961 # number of WriteReq misses 1709system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609189 # number of SoftPFReq misses 1710system.cpu1.dcache.SoftPFReq_misses::total 609189 # number of SoftPFReq misses 1711system.cpu1.dcache.WriteLineReq_misses::cpu1.data 443031 # number of WriteLineReq misses 1712system.cpu1.dcache.WriteLineReq_misses::total 443031 # number of WriteLineReq misses 1713system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160663 # number of LoadLockedReq misses 1714system.cpu1.dcache.LoadLockedReq_misses::total 160663 # number of LoadLockedReq misses 1715system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202242 # number of StoreCondReq misses 1716system.cpu1.dcache.StoreCondReq_misses::total 202242 # number of StoreCondReq misses 1717system.cpu1.dcache.demand_misses::cpu1.data 4540855 # number of demand (read+write) misses 1718system.cpu1.dcache.demand_misses::total 4540855 # number of demand (read+write) misses 1719system.cpu1.dcache.overall_misses::cpu1.data 5150044 # number of overall misses 1720system.cpu1.dcache.overall_misses::total 5150044 # number of overall misses 1721system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42649111500 # number of ReadReq miss cycles 1722system.cpu1.dcache.ReadReq_miss_latency::total 42649111500 # number of ReadReq miss cycles 1723system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25017964000 # number of WriteReq miss cycles 1724system.cpu1.dcache.WriteReq_miss_latency::total 25017964000 # number of WriteReq miss cycles 1725system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10518897000 # number of WriteLineReq miss cycles 1726system.cpu1.dcache.WriteLineReq_miss_latency::total 10518897000 # number of WriteLineReq miss cycles 1727system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2505987000 # number of LoadLockedReq miss cycles 1728system.cpu1.dcache.LoadLockedReq_miss_latency::total 2505987000 # number of LoadLockedReq miss cycles 1729system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4791659000 # number of StoreCondReq miss cycles 1730system.cpu1.dcache.StoreCondReq_miss_latency::total 4791659000 # number of StoreCondReq miss cycles 1731system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2159000 # number of StoreCondFailReq miss cycles 1732system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2159000 # number of StoreCondFailReq miss cycles 1733system.cpu1.dcache.demand_miss_latency::cpu1.data 78185972500 # number of demand (read+write) miss cycles 1734system.cpu1.dcache.demand_miss_latency::total 78185972500 # number of demand (read+write) miss cycles 1735system.cpu1.dcache.overall_miss_latency::cpu1.data 78185972500 # number of overall miss cycles 1736system.cpu1.dcache.overall_miss_latency::total 78185972500 # number of overall miss cycles 1737system.cpu1.dcache.ReadReq_accesses::cpu1.data 76279994 # number of ReadReq accesses(hits+misses) 1738system.cpu1.dcache.ReadReq_accesses::total 76279994 # number of ReadReq accesses(hits+misses) 1739system.cpu1.dcache.WriteReq_accesses::cpu1.data 69396149 # number of WriteReq accesses(hits+misses) 1740system.cpu1.dcache.WriteReq_accesses::total 69396149 # number of WriteReq accesses(hits+misses) 1741system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 777235 # number of SoftPFReq accesses(hits+misses) 1742system.cpu1.dcache.SoftPFReq_accesses::total 777235 # number of SoftPFReq accesses(hits+misses) 1743system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 530223 # number of WriteLineReq accesses(hits+misses) 1744system.cpu1.dcache.WriteLineReq_accesses::total 530223 # number of WriteLineReq accesses(hits+misses) 1745system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1805597 # number of LoadLockedReq accesses(hits+misses) 1746system.cpu1.dcache.LoadLockedReq_accesses::total 1805597 # number of LoadLockedReq accesses(hits+misses) 1747system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1804446 # number of StoreCondReq accesses(hits+misses) 1748system.cpu1.dcache.StoreCondReq_accesses::total 1804446 # number of StoreCondReq accesses(hits+misses) 1749system.cpu1.dcache.demand_accesses::cpu1.data 146206366 # number of demand (read+write) accesses 1750system.cpu1.dcache.demand_accesses::total 146206366 # number of demand (read+write) accesses 1751system.cpu1.dcache.overall_accesses::cpu1.data 146983601 # number of overall (read+write) accesses 1752system.cpu1.dcache.overall_accesses::total 146983601 # number of overall (read+write) accesses 1753system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036771 # miss rate for ReadReq accesses 1754system.cpu1.dcache.ReadReq_miss_rate::total 0.036771 # miss rate for ReadReq accesses 1755system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018632 # miss rate for WriteReq accesses 1756system.cpu1.dcache.WriteReq_miss_rate::total 0.018632 # miss rate for WriteReq accesses 1757system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783790 # miss rate for SoftPFReq accesses 1758system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783790 # miss rate for SoftPFReq accesses 1759system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.835556 # miss rate for WriteLineReq accesses 1760system.cpu1.dcache.WriteLineReq_miss_rate::total 0.835556 # miss rate for WriteLineReq accesses 1761system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088981 # miss rate for LoadLockedReq accesses 1762system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088981 # miss rate for LoadLockedReq accesses 1763system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112080 # miss rate for StoreCondReq accesses 1764system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112080 # miss rate for StoreCondReq accesses 1765system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031058 # miss rate for demand accesses 1766system.cpu1.dcache.demand_miss_rate::total 0.031058 # miss rate for demand accesses 1767system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035038 # miss rate for overall accesses 1768system.cpu1.dcache.overall_miss_rate::total 0.035038 # miss rate for overall accesses 1769system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.416985 # average ReadReq miss latency 1770system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.416985 # average ReadReq miss latency 1771system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19349.357019 # average WriteReq miss latency 1772system.cpu1.dcache.WriteReq_avg_miss_latency::total 19349.357019 # average WriteReq miss latency 1773system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23743.027012 # average WriteLineReq miss latency 1774system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23743.027012 # average WriteLineReq miss latency 1775system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15597.785427 # average LoadLockedReq miss latency 1776system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15597.785427 # average LoadLockedReq miss latency 1777system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23692.699835 # average StoreCondReq miss latency 1778system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23692.699835 # average StoreCondReq miss latency 1779system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1780system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1781system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17218.337185 # average overall miss latency 1782system.cpu1.dcache.demand_avg_miss_latency::total 17218.337185 # average overall miss latency 1783system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15181.612526 # average overall miss latency 1784system.cpu1.dcache.overall_avg_miss_latency::total 15181.612526 # average overall miss latency 1785system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1786system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1787system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1788system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1789system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1790system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1791system.cpu1.dcache.writebacks::writebacks 4949273 # number of writebacks 1792system.cpu1.dcache.writebacks::total 4949273 # number of writebacks 1793system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18154 # number of ReadReq MSHR hits 1794system.cpu1.dcache.ReadReq_mshr_hits::total 18154 # number of ReadReq MSHR hits 1795system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 423 # number of WriteReq MSHR hits 1796system.cpu1.dcache.WriteReq_mshr_hits::total 423 # number of WriteReq MSHR hits 1797system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43805 # number of LoadLockedReq MSHR hits 1798system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43805 # number of LoadLockedReq MSHR hits 1799system.cpu1.dcache.demand_mshr_hits::cpu1.data 18577 # number of demand (read+write) MSHR hits 1800system.cpu1.dcache.demand_mshr_hits::total 18577 # number of demand (read+write) MSHR hits 1801system.cpu1.dcache.overall_mshr_hits::cpu1.data 18577 # number of overall MSHR hits 1802system.cpu1.dcache.overall_mshr_hits::total 18577 # number of overall MSHR hits 1803system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2786709 # number of ReadReq MSHR misses 1804system.cpu1.dcache.ReadReq_mshr_misses::total 2786709 # number of ReadReq MSHR misses 1805system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1292538 # number of WriteReq MSHR misses 1806system.cpu1.dcache.WriteReq_mshr_misses::total 1292538 # number of WriteReq MSHR misses 1807system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 609189 # number of SoftPFReq MSHR misses 1808system.cpu1.dcache.SoftPFReq_mshr_misses::total 609189 # number of SoftPFReq MSHR misses 1809system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 443031 # number of WriteLineReq MSHR misses 1810system.cpu1.dcache.WriteLineReq_mshr_misses::total 443031 # number of WriteLineReq MSHR misses 1811system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116858 # number of LoadLockedReq MSHR misses 1812system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116858 # number of LoadLockedReq MSHR misses 1813system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202242 # number of StoreCondReq MSHR misses 1814system.cpu1.dcache.StoreCondReq_mshr_misses::total 202242 # number of StoreCondReq MSHR misses 1815system.cpu1.dcache.demand_mshr_misses::cpu1.data 4522278 # number of demand (read+write) MSHR misses 1816system.cpu1.dcache.demand_mshr_misses::total 4522278 # number of demand (read+write) MSHR misses 1817system.cpu1.dcache.overall_mshr_misses::cpu1.data 5131467 # number of overall MSHR misses 1818system.cpu1.dcache.overall_mshr_misses::total 5131467 # number of overall MSHR misses 1819system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable 1820system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22203 # number of ReadReq MSHR uncacheable 1821system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable 1822system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable 1823system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses 1824system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42958 # number of overall MSHR uncacheable misses 1825system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38628648000 # number of ReadReq MSHR miss cycles 1826system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38628648000 # number of ReadReq MSHR miss cycles 1827system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23695979500 # number of WriteReq MSHR miss cycles 1828system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23695979500 # number of WriteReq MSHR miss cycles 1829system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13886318000 # number of SoftPFReq MSHR miss cycles 1830system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13886318000 # number of SoftPFReq MSHR miss cycles 1831system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10075866000 # number of WriteLineReq MSHR miss cycles 1832system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10075866000 # number of WriteLineReq MSHR miss cycles 1833system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1623112500 # number of LoadLockedReq MSHR miss cycles 1834system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1623112500 # number of LoadLockedReq MSHR miss cycles 1835system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4589466000 # number of StoreCondReq MSHR miss cycles 1836system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4589466000 # number of StoreCondReq MSHR miss cycles 1837system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2110000 # number of StoreCondFailReq MSHR miss cycles 1838system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2110000 # number of StoreCondFailReq MSHR miss cycles 1839system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72400493500 # number of demand (read+write) MSHR miss cycles 1840system.cpu1.dcache.demand_mshr_miss_latency::total 72400493500 # number of demand (read+write) MSHR miss cycles 1841system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 86286811500 # number of overall MSHR miss cycles 1842system.cpu1.dcache.overall_mshr_miss_latency::total 86286811500 # number of overall MSHR miss cycles 1843system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3923399500 # number of ReadReq MSHR uncacheable cycles 1844system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3923399500 # number of ReadReq MSHR uncacheable cycles 1845system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3923399500 # number of overall MSHR uncacheable cycles 1846system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3923399500 # number of overall MSHR uncacheable cycles 1847system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036533 # mshr miss rate for ReadReq accesses 1848system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036533 # mshr miss rate for ReadReq accesses 1849system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018626 # mshr miss rate for WriteReq accesses 1850system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018626 # mshr miss rate for WriteReq accesses 1851system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783790 # mshr miss rate for SoftPFReq accesses 1852system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783790 # mshr miss rate for SoftPFReq accesses 1853system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.835556 # mshr miss rate for WriteLineReq accesses 1854system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.835556 # mshr miss rate for WriteLineReq accesses 1855system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064720 # mshr miss rate for LoadLockedReq accesses 1856system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064720 # mshr miss rate for LoadLockedReq accesses 1857system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112080 # mshr miss rate for StoreCondReq accesses 1858system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112080 # mshr miss rate for StoreCondReq accesses 1859system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030931 # mshr miss rate for demand accesses 1860system.cpu1.dcache.demand_mshr_miss_rate::total 0.030931 # mshr miss rate for demand accesses 1861system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034912 # mshr miss rate for overall accesses 1862system.cpu1.dcache.overall_mshr_miss_rate::total 0.034912 # mshr miss rate for overall accesses 1863system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13861.744445 # average ReadReq mshr miss latency 1864system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13861.744445 # average ReadReq mshr miss latency 1865system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18332.907427 # average WriteReq mshr miss latency 1866system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18332.907427 # average WriteReq mshr miss latency 1867system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22794.761560 # average SoftPFReq mshr miss latency 1868system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22794.761560 # average SoftPFReq mshr miss latency 1869system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22743.027012 # average WriteLineReq mshr miss latency 1870system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22743.027012 # average WriteLineReq mshr miss latency 1871system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13889.613890 # average LoadLockedReq mshr miss latency 1872system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13889.613890 # average LoadLockedReq mshr miss latency 1873system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22692.942119 # average StoreCondReq mshr miss latency 1874system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22692.942119 # average StoreCondReq mshr miss latency 1875system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1876system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1877system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16009.739671 # average overall mshr miss latency 1878system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16009.739671 # average overall mshr miss latency 1879system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16815.232662 # average overall mshr miss latency 1880system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16815.232662 # average overall mshr miss latency 1881system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176705.828041 # average ReadReq mshr uncacheable latency 1882system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176705.828041 # average ReadReq mshr uncacheable latency 1883system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91331.055915 # average overall mshr uncacheable latency 1884system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91331.055915 # average overall mshr uncacheable latency 1885system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1886system.cpu1.icache.tags.replacements 4981311 # number of replacements 1887system.cpu1.icache.tags.tagsinuse 496.212019 # Cycle average of tags in use 1888system.cpu1.icache.tags.total_refs 411158765 # Total number of references to valid blocks. 1889system.cpu1.icache.tags.sampled_refs 4981823 # Sample count of references to valid blocks. 1890system.cpu1.icache.tags.avg_refs 82.531789 # Average number of references to valid blocks. 1891system.cpu1.icache.tags.warmup_cycle 8379594860000 # Cycle when the warmup percentage was hit. 1892system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.212019 # Average occupied blocks per requestor 1893system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy 1894system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy 1895system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1896system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 1897system.cpu1.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id 1898system.cpu1.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id 1899system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1900system.cpu1.icache.tags.tag_accesses 837263014 # Number of tag accesses 1901system.cpu1.icache.tags.data_accesses 837263014 # Number of data accesses 1902system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1903system.cpu1.icache.ReadReq_hits::cpu1.inst 411158765 # number of ReadReq hits 1904system.cpu1.icache.ReadReq_hits::total 411158765 # number of ReadReq hits 1905system.cpu1.icache.demand_hits::cpu1.inst 411158765 # number of demand (read+write) hits 1906system.cpu1.icache.demand_hits::total 411158765 # number of demand (read+write) hits 1907system.cpu1.icache.overall_hits::cpu1.inst 411158765 # number of overall hits 1908system.cpu1.icache.overall_hits::total 411158765 # number of overall hits 1909system.cpu1.icache.ReadReq_misses::cpu1.inst 4981828 # number of ReadReq misses 1910system.cpu1.icache.ReadReq_misses::total 4981828 # number of ReadReq misses 1911system.cpu1.icache.demand_misses::cpu1.inst 4981828 # number of demand (read+write) misses 1912system.cpu1.icache.demand_misses::total 4981828 # number of demand (read+write) misses 1913system.cpu1.icache.overall_misses::cpu1.inst 4981828 # number of overall misses 1914system.cpu1.icache.overall_misses::total 4981828 # number of overall misses 1915system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54111358000 # number of ReadReq miss cycles 1916system.cpu1.icache.ReadReq_miss_latency::total 54111358000 # number of ReadReq miss cycles 1917system.cpu1.icache.demand_miss_latency::cpu1.inst 54111358000 # number of demand (read+write) miss cycles 1918system.cpu1.icache.demand_miss_latency::total 54111358000 # number of demand (read+write) miss cycles 1919system.cpu1.icache.overall_miss_latency::cpu1.inst 54111358000 # number of overall miss cycles 1920system.cpu1.icache.overall_miss_latency::total 54111358000 # number of overall miss cycles 1921system.cpu1.icache.ReadReq_accesses::cpu1.inst 416140593 # number of ReadReq accesses(hits+misses) 1922system.cpu1.icache.ReadReq_accesses::total 416140593 # number of ReadReq accesses(hits+misses) 1923system.cpu1.icache.demand_accesses::cpu1.inst 416140593 # number of demand (read+write) accesses 1924system.cpu1.icache.demand_accesses::total 416140593 # number of demand (read+write) accesses 1925system.cpu1.icache.overall_accesses::cpu1.inst 416140593 # number of overall (read+write) accesses 1926system.cpu1.icache.overall_accesses::total 416140593 # number of overall (read+write) accesses 1927system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011972 # miss rate for ReadReq accesses 1928system.cpu1.icache.ReadReq_miss_rate::total 0.011972 # miss rate for ReadReq accesses 1929system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011972 # miss rate for demand accesses 1930system.cpu1.icache.demand_miss_rate::total 0.011972 # miss rate for demand accesses 1931system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011972 # miss rate for overall accesses 1932system.cpu1.icache.overall_miss_rate::total 0.011972 # miss rate for overall accesses 1933system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10861.747535 # average ReadReq miss latency 1934system.cpu1.icache.ReadReq_avg_miss_latency::total 10861.747535 # average ReadReq miss latency 1935system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency 1936system.cpu1.icache.demand_avg_miss_latency::total 10861.747535 # average overall miss latency 1937system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10861.747535 # average overall miss latency 1938system.cpu1.icache.overall_avg_miss_latency::total 10861.747535 # average overall miss latency 1939system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1940system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1941system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1942system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1943system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1944system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1945system.cpu1.icache.writebacks::writebacks 4981311 # number of writebacks 1946system.cpu1.icache.writebacks::total 4981311 # number of writebacks 1947system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4981828 # number of ReadReq MSHR misses 1948system.cpu1.icache.ReadReq_mshr_misses::total 4981828 # number of ReadReq MSHR misses 1949system.cpu1.icache.demand_mshr_misses::cpu1.inst 4981828 # number of demand (read+write) MSHR misses 1950system.cpu1.icache.demand_mshr_misses::total 4981828 # number of demand (read+write) MSHR misses 1951system.cpu1.icache.overall_mshr_misses::cpu1.inst 4981828 # number of overall MSHR misses 1952system.cpu1.icache.overall_mshr_misses::total 4981828 # number of overall MSHR misses 1953system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1954system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1955system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1956system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1957system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 51620444000 # number of ReadReq MSHR miss cycles 1958system.cpu1.icache.ReadReq_mshr_miss_latency::total 51620444000 # number of ReadReq MSHR miss cycles 1959system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 51620444000 # number of demand (read+write) MSHR miss cycles 1960system.cpu1.icache.demand_mshr_miss_latency::total 51620444000 # number of demand (read+write) MSHR miss cycles 1961system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 51620444000 # number of overall MSHR miss cycles 1962system.cpu1.icache.overall_mshr_miss_latency::total 51620444000 # number of overall MSHR miss cycles 1963system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10472000 # number of ReadReq MSHR uncacheable cycles 1964system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10472000 # number of ReadReq MSHR uncacheable cycles 1965system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10472000 # number of overall MSHR uncacheable cycles 1966system.cpu1.icache.overall_mshr_uncacheable_latency::total 10472000 # number of overall MSHR uncacheable cycles 1967system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for ReadReq accesses 1968system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011972 # mshr miss rate for ReadReq accesses 1969system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for demand accesses 1970system.cpu1.icache.demand_mshr_miss_rate::total 0.011972 # mshr miss rate for demand accesses 1971system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011972 # mshr miss rate for overall accesses 1972system.cpu1.icache.overall_mshr_miss_rate::total 0.011972 # mshr miss rate for overall accesses 1973system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average ReadReq mshr miss latency 1974system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10361.747535 # average ReadReq mshr miss latency 1975system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency 1976system.cpu1.icache.demand_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency 1977system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10361.747535 # average overall mshr miss latency 1978system.cpu1.icache.overall_avg_mshr_miss_latency::total 10361.747535 # average overall mshr miss latency 1979system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average ReadReq mshr uncacheable latency 1980system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 95200 # average ReadReq mshr uncacheable latency 1981system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 95200 # average overall mshr uncacheable latency 1982system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 95200 # average overall mshr uncacheable latency 1983system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1984system.cpu1.l2cache.prefetcher.num_hwpf_issued 6872416 # number of hwpf issued 1985system.cpu1.l2cache.prefetcher.pfIdentified 6872436 # number of prefetch candidates identified 1986system.cpu1.l2cache.prefetcher.pfBufferHit 18 # number of redundant prefetches already in prefetch queue 1987system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1988system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1989system.cpu1.l2cache.prefetcher.pfSpanPage 852028 # number of prefetches not generated due to page crossing 1990system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 1991system.cpu1.l2cache.tags.replacements 1861043 # number of replacements 1992system.cpu1.l2cache.tags.tagsinuse 12976.163549 # Cycle average of tags in use 1993system.cpu1.l2cache.tags.total_refs 8767962 # Total number of references to valid blocks. 1994system.cpu1.l2cache.tags.sampled_refs 1876890 # Sample count of references to valid blocks. 1995system.cpu1.l2cache.tags.avg_refs 4.671537 # Average number of references to valid blocks. 1996system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1997system.cpu1.l2cache.tags.occ_blocks::writebacks 12709.863020 # Average occupied blocks per requestor 1998system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.854479 # Average occupied blocks per requestor 1999system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 23.050365 # Average occupied blocks per requestor 2000system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 215.395684 # Average occupied blocks per requestor 2001system.cpu1.l2cache.tags.occ_percent::writebacks 0.775748 # Average percentage of cache occupancy 2002system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001700 # Average percentage of cache occupancy 2003system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001407 # Average percentage of cache occupancy 2004system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013147 # Average percentage of cache occupancy 2005system.cpu1.l2cache.tags.occ_percent::total 0.792002 # Average percentage of cache occupancy 2006system.cpu1.l2cache.tags.occ_task_id_blocks::1022 377 # Occupied blocks per task id 2007system.cpu1.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id 2008system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15415 # Occupied blocks per task id 2009system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 2010system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id 2011system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 69 # Occupied blocks per task id 2012system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 165 # Occupied blocks per task id 2013system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id 2014system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id 2015system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 2016system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 2017system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1400 # Occupied blocks per task id 2018system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5858 # Occupied blocks per task id 2019system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4122 # Occupied blocks per task id 2020system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3918 # Occupied blocks per task id 2021system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.023010 # Percentage of cache occupancy per task id 2022system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id 2023system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940857 # Percentage of cache occupancy per task id 2024system.cpu1.l2cache.tags.tag_accesses 342605185 # Number of tag accesses 2025system.cpu1.l2cache.tags.data_accesses 342605185 # Number of data accesses 2026system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2027system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 220532 # number of ReadReq hits 2028system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 147847 # number of ReadReq hits 2029system.cpu1.l2cache.ReadReq_hits::total 368379 # number of ReadReq hits 2030system.cpu1.l2cache.WritebackDirty_hits::writebacks 3122709 # number of WritebackDirty hits 2031system.cpu1.l2cache.WritebackDirty_hits::total 3122709 # number of WritebackDirty hits 2032system.cpu1.l2cache.WritebackClean_hits::writebacks 6807120 # number of WritebackClean hits 2033system.cpu1.l2cache.WritebackClean_hits::total 6807120 # number of WritebackClean hits 2034system.cpu1.l2cache.ReadExReq_hits::cpu1.data 835381 # number of ReadExReq hits 2035system.cpu1.l2cache.ReadExReq_hits::total 835381 # number of ReadExReq hits 2036system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4529100 # number of ReadCleanReq hits 2037system.cpu1.l2cache.ReadCleanReq_hits::total 4529100 # number of ReadCleanReq hits 2038system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2623579 # number of ReadSharedReq hits 2039system.cpu1.l2cache.ReadSharedReq_hits::total 2623579 # number of ReadSharedReq hits 2040system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191618 # number of InvalidateReq hits 2041system.cpu1.l2cache.InvalidateReq_hits::total 191618 # number of InvalidateReq hits 2042system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 220532 # number of demand (read+write) hits 2043system.cpu1.l2cache.demand_hits::cpu1.itb.walker 147847 # number of demand (read+write) hits 2044system.cpu1.l2cache.demand_hits::cpu1.inst 4529100 # number of demand (read+write) hits 2045system.cpu1.l2cache.demand_hits::cpu1.data 3458960 # number of demand (read+write) hits 2046system.cpu1.l2cache.demand_hits::total 8356439 # number of demand (read+write) hits 2047system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 220532 # number of overall hits 2048system.cpu1.l2cache.overall_hits::cpu1.itb.walker 147847 # number of overall hits 2049system.cpu1.l2cache.overall_hits::cpu1.inst 4529100 # number of overall hits 2050system.cpu1.l2cache.overall_hits::cpu1.data 3458960 # number of overall hits 2051system.cpu1.l2cache.overall_hits::total 8356439 # number of overall hits 2052system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 17957 # number of ReadReq misses 2053system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10279 # number of ReadReq misses 2054system.cpu1.l2cache.ReadReq_misses::total 28236 # number of ReadReq misses 2055system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208369 # number of UpgradeReq misses 2056system.cpu1.l2cache.UpgradeReq_misses::total 208369 # number of UpgradeReq misses 2057system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202239 # number of SCUpgradeReq misses 2058system.cpu1.l2cache.SCUpgradeReq_misses::total 202239 # number of SCUpgradeReq misses 2059system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 2060system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 2061system.cpu1.l2cache.ReadExReq_misses::cpu1.data 250965 # number of ReadExReq misses 2062system.cpu1.l2cache.ReadExReq_misses::total 250965 # number of ReadExReq misses 2063system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 452728 # number of ReadCleanReq misses 2064system.cpu1.l2cache.ReadCleanReq_misses::total 452728 # number of ReadCleanReq misses 2065system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 889177 # number of ReadSharedReq misses 2066system.cpu1.l2cache.ReadSharedReq_misses::total 889177 # number of ReadSharedReq misses 2067system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 249433 # number of InvalidateReq misses 2068system.cpu1.l2cache.InvalidateReq_misses::total 249433 # number of InvalidateReq misses 2069system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 17957 # number of demand (read+write) misses 2070system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10279 # number of demand (read+write) misses 2071system.cpu1.l2cache.demand_misses::cpu1.inst 452728 # number of demand (read+write) misses 2072system.cpu1.l2cache.demand_misses::cpu1.data 1140142 # number of demand (read+write) misses 2073system.cpu1.l2cache.demand_misses::total 1621106 # number of demand (read+write) misses 2074system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 17957 # number of overall misses 2075system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10279 # number of overall misses 2076system.cpu1.l2cache.overall_misses::cpu1.inst 452728 # number of overall misses 2077system.cpu1.l2cache.overall_misses::cpu1.data 1140142 # number of overall misses 2078system.cpu1.l2cache.overall_misses::total 1621106 # number of overall misses 2079system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 590137500 # number of ReadReq miss cycles 2080system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 422641500 # number of ReadReq miss cycles 2081system.cpu1.l2cache.ReadReq_miss_latency::total 1012779000 # number of ReadReq miss cycles 2082system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 875652500 # number of UpgradeReq miss cycles 2083system.cpu1.l2cache.UpgradeReq_miss_latency::total 875652500 # number of UpgradeReq miss cycles 2084system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 333590500 # number of SCUpgradeReq miss cycles 2085system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 333590500 # number of SCUpgradeReq miss cycles 2086system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2035999 # number of SCUpgradeFailReq miss cycles 2087system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2035999 # number of SCUpgradeFailReq miss cycles 2088system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11238175000 # number of ReadExReq miss cycles 2089system.cpu1.l2cache.ReadExReq_miss_latency::total 11238175000 # number of ReadExReq miss cycles 2090system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16933068500 # number of ReadCleanReq miss cycles 2091system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16933068500 # number of ReadCleanReq miss cycles 2092system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31773824000 # number of ReadSharedReq miss cycles 2093system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31773824000 # number of ReadSharedReq miss cycles 2094system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 403814500 # number of InvalidateReq miss cycles 2095system.cpu1.l2cache.InvalidateReq_miss_latency::total 403814500 # number of InvalidateReq miss cycles 2096system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 590137500 # number of demand (read+write) miss cycles 2097system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 422641500 # number of demand (read+write) miss cycles 2098system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16933068500 # number of demand (read+write) miss cycles 2099system.cpu1.l2cache.demand_miss_latency::cpu1.data 43011999000 # number of demand (read+write) miss cycles 2100system.cpu1.l2cache.demand_miss_latency::total 60957846500 # number of demand (read+write) miss cycles 2101system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 590137500 # number of overall miss cycles 2102system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 422641500 # number of overall miss cycles 2103system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16933068500 # number of overall miss cycles 2104system.cpu1.l2cache.overall_miss_latency::cpu1.data 43011999000 # number of overall miss cycles 2105system.cpu1.l2cache.overall_miss_latency::total 60957846500 # number of overall miss cycles 2106system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 238489 # number of ReadReq accesses(hits+misses) 2107system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 158126 # number of ReadReq accesses(hits+misses) 2108system.cpu1.l2cache.ReadReq_accesses::total 396615 # number of ReadReq accesses(hits+misses) 2109system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3122709 # number of WritebackDirty accesses(hits+misses) 2110system.cpu1.l2cache.WritebackDirty_accesses::total 3122709 # number of WritebackDirty accesses(hits+misses) 2111system.cpu1.l2cache.WritebackClean_accesses::writebacks 6807120 # number of WritebackClean accesses(hits+misses) 2112system.cpu1.l2cache.WritebackClean_accesses::total 6807120 # number of WritebackClean accesses(hits+misses) 2113system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208369 # number of UpgradeReq accesses(hits+misses) 2114system.cpu1.l2cache.UpgradeReq_accesses::total 208369 # number of UpgradeReq accesses(hits+misses) 2115system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202239 # number of SCUpgradeReq accesses(hits+misses) 2116system.cpu1.l2cache.SCUpgradeReq_accesses::total 202239 # number of SCUpgradeReq accesses(hits+misses) 2117system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 2118system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 2119system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1086346 # number of ReadExReq accesses(hits+misses) 2120system.cpu1.l2cache.ReadExReq_accesses::total 1086346 # number of ReadExReq accesses(hits+misses) 2121system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4981828 # number of ReadCleanReq accesses(hits+misses) 2122system.cpu1.l2cache.ReadCleanReq_accesses::total 4981828 # number of ReadCleanReq accesses(hits+misses) 2123system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3512756 # number of ReadSharedReq accesses(hits+misses) 2124system.cpu1.l2cache.ReadSharedReq_accesses::total 3512756 # number of ReadSharedReq accesses(hits+misses) 2125system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 441051 # number of InvalidateReq accesses(hits+misses) 2126system.cpu1.l2cache.InvalidateReq_accesses::total 441051 # number of InvalidateReq accesses(hits+misses) 2127system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 238489 # number of demand (read+write) accesses 2128system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 158126 # number of demand (read+write) accesses 2129system.cpu1.l2cache.demand_accesses::cpu1.inst 4981828 # number of demand (read+write) accesses 2130system.cpu1.l2cache.demand_accesses::cpu1.data 4599102 # number of demand (read+write) accesses 2131system.cpu1.l2cache.demand_accesses::total 9977545 # number of demand (read+write) accesses 2132system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 238489 # number of overall (read+write) accesses 2133system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 158126 # number of overall (read+write) accesses 2134system.cpu1.l2cache.overall_accesses::cpu1.inst 4981828 # number of overall (read+write) accesses 2135system.cpu1.l2cache.overall_accesses::cpu1.data 4599102 # number of overall (read+write) accesses 2136system.cpu1.l2cache.overall_accesses::total 9977545 # number of overall (read+write) accesses 2137system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for ReadReq accesses 2138system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.065005 # miss rate for ReadReq accesses 2139system.cpu1.l2cache.ReadReq_miss_rate::total 0.071192 # miss rate for ReadReq accesses 2140system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2141system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2142system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2143system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2144system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2145system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2146system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231018 # miss rate for ReadExReq accesses 2147system.cpu1.l2cache.ReadExReq_miss_rate::total 0.231018 # miss rate for ReadExReq accesses 2148system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.090876 # miss rate for ReadCleanReq accesses 2149system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.090876 # miss rate for ReadCleanReq accesses 2150system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253128 # miss rate for ReadSharedReq accesses 2151system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253128 # miss rate for ReadSharedReq accesses 2152system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.565542 # miss rate for InvalidateReq accesses 2153system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.565542 # miss rate for InvalidateReq accesses 2154system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for demand accesses 2155system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.065005 # miss rate for demand accesses 2156system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.090876 # miss rate for demand accesses 2157system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.247905 # miss rate for demand accesses 2158system.cpu1.l2cache.demand_miss_rate::total 0.162475 # miss rate for demand accesses 2159system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.075295 # miss rate for overall accesses 2160system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.065005 # miss rate for overall accesses 2161system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.090876 # miss rate for overall accesses 2162system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.247905 # miss rate for overall accesses 2163system.cpu1.l2cache.overall_miss_rate::total 0.162475 # miss rate for overall accesses 2164system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average ReadReq miss latency 2165system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41116.986088 # average ReadReq miss latency 2166system.cpu1.l2cache.ReadReq_avg_miss_latency::total 35868.359541 # average ReadReq miss latency 2167system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4202.412547 # average UpgradeReq miss latency 2168system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4202.412547 # average UpgradeReq miss latency 2169system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1649.486499 # average SCUpgradeReq miss latency 2170system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1649.486499 # average SCUpgradeReq miss latency 2171system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 678666.333333 # average SCUpgradeFailReq miss latency 2172system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 678666.333333 # average SCUpgradeFailReq miss latency 2173system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44779.849780 # average ReadExReq miss latency 2174system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44779.849780 # average ReadExReq miss latency 2175system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37402.300057 # average ReadCleanReq miss latency 2176system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37402.300057 # average ReadCleanReq miss latency 2177system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35733.969727 # average ReadSharedReq miss latency 2178system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35733.969727 # average ReadSharedReq miss latency 2179system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1618.929733 # average InvalidateReq miss latency 2180system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1618.929733 # average InvalidateReq miss latency 2181system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average overall miss latency 2182system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41116.986088 # average overall miss latency 2183system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37402.300057 # average overall miss latency 2184system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37725.124590 # average overall miss latency 2185system.cpu1.l2cache.demand_avg_miss_latency::total 37602.628391 # average overall miss latency 2186system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32863.924932 # average overall miss latency 2187system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41116.986088 # average overall miss latency 2188system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37402.300057 # average overall miss latency 2189system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37725.124590 # average overall miss latency 2190system.cpu1.l2cache.overall_avg_miss_latency::total 37602.628391 # average overall miss latency 2191system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2192system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2193system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2194system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2195system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2196system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2197system.cpu1.l2cache.unused_prefetches 38928 # number of HardPF blocks evicted w/o reference 2198system.cpu1.l2cache.writebacks::writebacks 1071108 # number of writebacks 2199system.cpu1.l2cache.writebacks::total 1071108 # number of writebacks 2200system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4423 # number of ReadExReq MSHR hits 2201system.cpu1.l2cache.ReadExReq_mshr_hits::total 4423 # number of ReadExReq MSHR hits 2202system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 417 # number of ReadSharedReq MSHR hits 2203system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 417 # number of ReadSharedReq MSHR hits 2204system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4840 # number of demand (read+write) MSHR hits 2205system.cpu1.l2cache.demand_mshr_hits::total 4840 # number of demand (read+write) MSHR hits 2206system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4840 # number of overall MSHR hits 2207system.cpu1.l2cache.overall_mshr_hits::total 4840 # number of overall MSHR hits 2208system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 17957 # number of ReadReq MSHR misses 2209system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10279 # number of ReadReq MSHR misses 2210system.cpu1.l2cache.ReadReq_mshr_misses::total 28236 # number of ReadReq MSHR misses 2211system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 666851 # number of HardPFReq MSHR misses 2212system.cpu1.l2cache.HardPFReq_mshr_misses::total 666851 # number of HardPFReq MSHR misses 2213system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208369 # number of UpgradeReq MSHR misses 2214system.cpu1.l2cache.UpgradeReq_mshr_misses::total 208369 # number of UpgradeReq MSHR misses 2215system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202239 # number of SCUpgradeReq MSHR misses 2216system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202239 # number of SCUpgradeReq MSHR misses 2217system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 2218system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2219system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 246542 # number of ReadExReq MSHR misses 2220system.cpu1.l2cache.ReadExReq_mshr_misses::total 246542 # number of ReadExReq MSHR misses 2221system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 452728 # number of ReadCleanReq MSHR misses 2222system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 452728 # number of ReadCleanReq MSHR misses 2223system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 888760 # number of ReadSharedReq MSHR misses 2224system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 888760 # number of ReadSharedReq MSHR misses 2225system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 249433 # number of InvalidateReq MSHR misses 2226system.cpu1.l2cache.InvalidateReq_mshr_misses::total 249433 # number of InvalidateReq MSHR misses 2227system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 17957 # number of demand (read+write) MSHR misses 2228system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10279 # number of demand (read+write) MSHR misses 2229system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 452728 # number of demand (read+write) MSHR misses 2230system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1135302 # number of demand (read+write) MSHR misses 2231system.cpu1.l2cache.demand_mshr_misses::total 1616266 # number of demand (read+write) MSHR misses 2232system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 17957 # number of overall MSHR misses 2233system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10279 # number of overall MSHR misses 2234system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 452728 # number of overall MSHR misses 2235system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1135302 # number of overall MSHR misses 2236system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 666851 # number of overall MSHR misses 2237system.cpu1.l2cache.overall_mshr_misses::total 2283117 # number of overall MSHR misses 2238system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2239system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable 2240system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22313 # number of ReadReq MSHR uncacheable 2241system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable 2242system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable 2243system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2244system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses 2245system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43068 # number of overall MSHR uncacheable misses 2246system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of ReadReq MSHR miss cycles 2247system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 360967500 # number of ReadReq MSHR miss cycles 2248system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 843363000 # number of ReadReq MSHR miss cycles 2249system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of HardPFReq MSHR miss cycles 2250system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27800562984 # number of HardPFReq MSHR miss cycles 2251system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3852073000 # number of UpgradeReq MSHR miss cycles 2252system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3852073000 # number of UpgradeReq MSHR miss cycles 2253system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3071337500 # number of SCUpgradeReq MSHR miss cycles 2254system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3071337500 # number of SCUpgradeReq MSHR miss cycles 2255system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1741999 # number of SCUpgradeFailReq MSHR miss cycles 2256system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1741999 # number of SCUpgradeFailReq MSHR miss cycles 2257system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9224946500 # number of ReadExReq MSHR miss cycles 2258system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9224946500 # number of ReadExReq MSHR miss cycles 2259system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14216700500 # number of ReadCleanReq MSHR miss cycles 2260system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14216700500 # number of ReadCleanReq MSHR miss cycles 2261system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26383538000 # number of ReadSharedReq MSHR miss cycles 2262system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26383538000 # number of ReadSharedReq MSHR miss cycles 2263system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6621907000 # number of InvalidateReq MSHR miss cycles 2264system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6621907000 # number of InvalidateReq MSHR miss cycles 2265system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of demand (read+write) MSHR miss cycles 2266system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 360967500 # number of demand (read+write) MSHR miss cycles 2267system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14216700500 # number of demand (read+write) MSHR miss cycles 2268system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35608484500 # number of demand (read+write) MSHR miss cycles 2269system.cpu1.l2cache.demand_mshr_miss_latency::total 50668548000 # number of demand (read+write) MSHR miss cycles 2270system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of overall MSHR miss cycles 2271system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 360967500 # number of overall MSHR miss cycles 2272system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14216700500 # number of overall MSHR miss cycles 2273system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35608484500 # number of overall MSHR miss cycles 2274system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of overall MSHR miss cycles 2275system.cpu1.l2cache.overall_mshr_miss_latency::total 78469110984 # number of overall MSHR miss cycles 2276system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9647000 # number of ReadReq MSHR uncacheable cycles 2277system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3745274000 # number of ReadReq MSHR uncacheable cycles 2278system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3754921000 # number of ReadReq MSHR uncacheable cycles 2279system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9647000 # number of overall MSHR uncacheable cycles 2280system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3745274000 # number of overall MSHR uncacheable cycles 2281system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3754921000 # number of overall MSHR uncacheable cycles 2282system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for ReadReq accesses 2283system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for ReadReq accesses 2284system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.071192 # mshr miss rate for ReadReq accesses 2285system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2286system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2287system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2288system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2289system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2290system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2291system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2292system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2293system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226946 # mshr miss rate for ReadExReq accesses 2294system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226946 # mshr miss rate for ReadExReq accesses 2295system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for ReadCleanReq accesses 2296system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090876 # mshr miss rate for ReadCleanReq accesses 2297system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253009 # mshr miss rate for ReadSharedReq accesses 2298system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253009 # mshr miss rate for ReadSharedReq accesses 2299system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565542 # mshr miss rate for InvalidateReq accesses 2300system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565542 # mshr miss rate for InvalidateReq accesses 2301system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for demand accesses 2302system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for demand accesses 2303system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for demand accesses 2304system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for demand accesses 2305system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161990 # mshr miss rate for demand accesses 2306system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for overall accesses 2307system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for overall accesses 2308system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for overall accesses 2309system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for overall accesses 2310system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2311system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228826 # mshr miss rate for overall accesses 2312system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average ReadReq mshr miss latency 2313system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average ReadReq mshr miss latency 2314system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29868.359541 # average ReadReq mshr miss latency 2315system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average HardPFReq mshr miss latency 2316system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41689.317380 # average HardPFReq mshr miss latency 2317system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18486.785462 # average UpgradeReq mshr miss latency 2318system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18486.785462 # average UpgradeReq mshr miss latency 2319system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15186.672699 # average SCUpgradeReq mshr miss latency 2320system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15186.672699 # average SCUpgradeReq mshr miss latency 2321system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 580666.333333 # average SCUpgradeFailReq mshr miss latency 2322system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 580666.333333 # average SCUpgradeFailReq mshr miss latency 2323system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37417.342684 # average ReadExReq mshr miss latency 2324system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37417.342684 # average ReadExReq mshr miss latency 2325system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average ReadCleanReq mshr miss latency 2326system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31402.300057 # average ReadCleanReq mshr miss latency 2327system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29685.784689 # average ReadSharedReq mshr miss latency 2328system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29685.784689 # average ReadSharedReq mshr miss latency 2329system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26547.838498 # average InvalidateReq mshr miss latency 2330system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26547.838498 # average InvalidateReq mshr miss latency 2331system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency 2332system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency 2333system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency 2334system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency 2335system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31349.139312 # average overall mshr miss latency 2336system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency 2337system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency 2338system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency 2339system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency 2340system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average overall mshr miss latency 2341system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34369.290310 # average overall mshr miss latency 2342system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average ReadReq mshr uncacheable latency 2343system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168683.241003 # average ReadReq mshr uncacheable latency 2344system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168284.004840 # average ReadReq mshr uncacheable latency 2345system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average overall mshr uncacheable latency 2346system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87184.552353 # average overall mshr uncacheable latency 2347system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87185.868859 # average overall mshr uncacheable latency 2348system.cpu1.toL2Bus.snoop_filter.tot_requests 20600525 # Total number of requests made to the snoop filter. 2349system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10578683 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2350system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2351system.cpu1.toL2Bus.snoop_filter.tot_snoops 558580 # Total number of snoops made to the snoop filter. 2352system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 558580 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2353system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2354system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2355system.cpu1.toL2Bus.trans_dist::ReadReq 484798 # Transaction distribution 2356system.cpu1.toL2Bus.trans_dist::ReadResp 9068801 # Transaction distribution 2357system.cpu1.toL2Bus.trans_dist::WriteReq 20755 # Transaction distribution 2358system.cpu1.toL2Bus.trans_dist::WriteResp 20755 # Transaction distribution 2359system.cpu1.toL2Bus.trans_dist::WritebackDirty 4199993 # Transaction distribution 2360system.cpu1.toL2Bus.trans_dist::WritebackClean 6807874 # Transaction distribution 2361system.cpu1.toL2Bus.trans_dist::CleanEvict 1098101 # Transaction distribution 2362system.cpu1.toL2Bus.trans_dist::HardPFReq 809012 # Transaction distribution 2363system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2364system.cpu1.toL2Bus.trans_dist::UpgradeReq 385894 # Transaction distribution 2365system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368515 # Transaction distribution 2366system.cpu1.toL2Bus.trans_dist::UpgradeResp 474989 # Transaction distribution 2367system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution 2368system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 2369system.cpu1.toL2Bus.trans_dist::ReadExReq 1114310 # Transaction distribution 2370system.cpu1.toL2Bus.trans_dist::ReadExResp 1093127 # Transaction distribution 2371system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4981828 # Transaction distribution 2372system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4385137 # Transaction distribution 2373system.cpu1.toL2Bus.trans_dist::InvalidateReq 490192 # Transaction distribution 2374system.cpu1.toL2Bus.trans_dist::InvalidateResp 441051 # Transaction distribution 2375system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14945187 # Packet count per connected master and slave (bytes) 2376system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16097398 # Packet count per connected master and slave (bytes) 2377system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332311 # Packet count per connected master and slave (bytes) 2378system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 526789 # Packet count per connected master and slave (bytes) 2379system.cpu1.toL2Bus.pkt_count::total 31901685 # Packet count per connected master and slave (bytes) 2380system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 637641336 # Cumulative packet size per connected master and slave (bytes) 2381system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617397659 # Cumulative packet size per connected master and slave (bytes) 2382system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1265008 # Cumulative packet size per connected master and slave (bytes) 2383system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1907912 # Cumulative packet size per connected master and slave (bytes) 2384system.cpu1.toL2Bus.pkt_size::total 1258211915 # Cumulative packet size per connected master and slave (bytes) 2385system.cpu1.toL2Bus.snoops 4504290 # Total snoops (count) 2386system.cpu1.toL2Bus.snoopTraffic 75632944 # Total snoop traffic (bytes) 2387system.cpu1.toL2Bus.snoop_fanout::samples 15215883 # Request fanout histogram 2388system.cpu1.toL2Bus.snoop_fanout::mean 0.052359 # Request fanout histogram 2389system.cpu1.toL2Bus.snoop_fanout::stdev 0.222750 # Request fanout histogram 2390system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2391system.cpu1.toL2Bus.snoop_fanout::0 14419192 94.76% 94.76% # Request fanout histogram 2392system.cpu1.toL2Bus.snoop_fanout::1 796691 5.24% 100.00% # Request fanout histogram 2393system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2394system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2395system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2396system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 2397system.cpu1.toL2Bus.snoop_fanout::total 15215883 # Request fanout histogram 2398system.cpu1.toL2Bus.reqLayer0.occupancy 20375325498 # Layer occupancy (ticks) 2399system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2400system.cpu1.toL2Bus.snoopLayer0.occupancy 176794994 # Layer occupancy (ticks) 2401system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2402system.cpu1.toL2Bus.respLayer0.occupancy 7472852000 # Layer occupancy (ticks) 2403system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2404system.cpu1.toL2Bus.respLayer1.occupancy 7357432377 # Layer occupancy (ticks) 2405system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2406system.cpu1.toL2Bus.respLayer2.occupancy 174185000 # Layer occupancy (ticks) 2407system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2408system.cpu1.toL2Bus.respLayer3.occupancy 288300000 # Layer occupancy (ticks) 2409system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2410system.iobus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2411system.iobus.trans_dist::ReadReq 40355 # Transaction distribution 2412system.iobus.trans_dist::ReadResp 40355 # Transaction distribution 2413system.iobus.trans_dist::WriteReq 136628 # Transaction distribution 2414system.iobus.trans_dist::WriteResp 136628 # Transaction distribution 2415system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) 2416system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2417system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2418system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2419system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2420system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2421system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2422system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2423system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2424system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2425system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2426system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 2427system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2428system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) 2429system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) 2430system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) 2431system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2432system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2433system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) 2434system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) 2435system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2436system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2437system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2438system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2439system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2440system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2441system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2442system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2443system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2444system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2445system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 2446system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2447system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) 2448system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) 2449system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) 2450system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2451system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2452system.iobus.pkt_size::total 7496784 # Cumulative packet size per connected master and slave (bytes) 2453system.iobus.reqLayer0.occupancy 36982500 # Layer occupancy (ticks) 2454system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2455system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) 2456system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2457system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) 2458system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2459system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 2460system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2461system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) 2462system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2463system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2464system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2465system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2466system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2467system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2468system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2469system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2470system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2471system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 2472system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2473system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2474system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2475system.iobus.reqLayer23.occupancy 26451500 # Layer occupancy (ticks) 2476system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2477system.iobus.reqLayer24.occupancy 37417000 # Layer occupancy (ticks) 2478system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2479system.iobus.reqLayer25.occupancy 569427501 # Layer occupancy (ticks) 2480system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2481system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) 2482system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2483system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) 2484system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2485system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2486system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2487system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2488system.iocache.tags.replacements 115615 # number of replacements 2489system.iocache.tags.tagsinuse 11.298649 # Cycle average of tags in use 2490system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2491system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. 2492system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2493system.iocache.tags.warmup_cycle 9136560427000 # Cycle when the warmup percentage was hit. 2494system.iocache.tags.occ_blocks::realview.ethernet 7.416178 # Average occupied blocks per requestor 2495system.iocache.tags.occ_blocks::realview.ide 3.882471 # Average occupied blocks per requestor 2496system.iocache.tags.occ_percent::realview.ethernet 0.463511 # Average percentage of cache occupancy 2497system.iocache.tags.occ_percent::realview.ide 0.242654 # Average percentage of cache occupancy 2498system.iocache.tags.occ_percent::total 0.706166 # Average percentage of cache occupancy 2499system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2500system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2501system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2502system.iocache.tags.tag_accesses 1040856 # Number of tag accesses 2503system.iocache.tags.data_accesses 1040856 # Number of data accesses 2504system.iocache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2505system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2506system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses 2507system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses 2508system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2509system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2510system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2511system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2512system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2513system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses 2514system.iocache.demand_misses::total 115651 # number of demand (read+write) misses 2515system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2516system.iocache.overall_misses::realview.ide 115611 # number of overall misses 2517system.iocache.overall_misses::total 115651 # number of overall misses 2518system.iocache.ReadReq_miss_latency::realview.ethernet 5193500 # number of ReadReq miss cycles 2519system.iocache.ReadReq_miss_latency::realview.ide 1828649003 # number of ReadReq miss cycles 2520system.iocache.ReadReq_miss_latency::total 1833842503 # number of ReadReq miss cycles 2521system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2522system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2523system.iocache.WriteLineReq_miss_latency::realview.ide 13346157998 # number of WriteLineReq miss cycles 2524system.iocache.WriteLineReq_miss_latency::total 13346157998 # number of WriteLineReq miss cycles 2525system.iocache.demand_miss_latency::realview.ethernet 5562500 # number of demand (read+write) miss cycles 2526system.iocache.demand_miss_latency::realview.ide 15174807001 # number of demand (read+write) miss cycles 2527system.iocache.demand_miss_latency::total 15180369501 # number of demand (read+write) miss cycles 2528system.iocache.overall_miss_latency::realview.ethernet 5562500 # number of overall miss cycles 2529system.iocache.overall_miss_latency::realview.ide 15174807001 # number of overall miss cycles 2530system.iocache.overall_miss_latency::total 15180369501 # number of overall miss cycles 2531system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2532system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) 2533system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) 2534system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2535system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2536system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2537system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2538system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2539system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses 2540system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses 2541system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2542system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses 2543system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses 2544system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2545system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2546system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2547system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2548system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2549system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2550system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2551system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2552system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2553system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2554system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2555system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2556system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2557system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140364.864865 # average ReadReq miss latency 2558system.iocache.ReadReq_avg_miss_latency::realview.ide 205859.394686 # average ReadReq miss latency 2559system.iocache.ReadReq_avg_miss_latency::total 205587.724552 # average ReadReq miss latency 2560system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2561system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2562system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125048.328442 # average WriteLineReq miss latency 2563system.iocache.WriteLineReq_avg_miss_latency::total 125048.328442 # average WriteLineReq miss latency 2564system.iocache.demand_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency 2565system.iocache.demand_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency 2566system.iocache.demand_avg_miss_latency::total 131260.166371 # average overall miss latency 2567system.iocache.overall_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency 2568system.iocache.overall_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency 2569system.iocache.overall_avg_miss_latency::total 131260.166371 # average overall miss latency 2570system.iocache.blocked_cycles::no_mshrs 41899 # number of cycles access was blocked 2571system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2572system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked 2573system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2574system.iocache.avg_blocked_cycles::no_mshrs 11.852617 # average number of cycles each access was blocked 2575system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2576system.iocache.writebacks::writebacks 106702 # number of writebacks 2577system.iocache.writebacks::total 106702 # number of writebacks 2578system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2579system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses 2580system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses 2581system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2582system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2583system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2584system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2585system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2586system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses 2587system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses 2588system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2589system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses 2590system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses 2591system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3343500 # number of ReadReq MSHR miss cycles 2592system.iocache.ReadReq_mshr_miss_latency::realview.ide 1384499003 # number of ReadReq MSHR miss cycles 2593system.iocache.ReadReq_mshr_miss_latency::total 1387842503 # number of ReadReq MSHR miss cycles 2594system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2595system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2596system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8000796585 # number of WriteLineReq MSHR miss cycles 2597system.iocache.WriteLineReq_mshr_miss_latency::total 8000796585 # number of WriteLineReq MSHR miss cycles 2598system.iocache.demand_mshr_miss_latency::realview.ethernet 3562500 # number of demand (read+write) MSHR miss cycles 2599system.iocache.demand_mshr_miss_latency::realview.ide 9385295588 # number of demand (read+write) MSHR miss cycles 2600system.iocache.demand_mshr_miss_latency::total 9388858088 # number of demand (read+write) MSHR miss cycles 2601system.iocache.overall_mshr_miss_latency::realview.ethernet 3562500 # number of overall MSHR miss cycles 2602system.iocache.overall_mshr_miss_latency::realview.ide 9385295588 # number of overall MSHR miss cycles 2603system.iocache.overall_mshr_miss_latency::total 9388858088 # number of overall MSHR miss cycles 2604system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2605system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2606system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2607system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2608system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2609system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2610system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2611system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2612system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2613system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2614system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2615system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2616system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2617system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90364.864865 # average ReadReq mshr miss latency 2618system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 155859.394686 # average ReadReq mshr miss latency 2619system.iocache.ReadReq_avg_mshr_miss_latency::total 155587.724552 # average ReadReq mshr miss latency 2620system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2621system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2622system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 74964.363475 # average WriteLineReq mshr miss latency 2623system.iocache.WriteLineReq_avg_mshr_miss_latency::total 74964.363475 # average WriteLineReq mshr miss latency 2624system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency 2625system.iocache.demand_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency 2626system.iocache.demand_avg_mshr_miss_latency::total 81182.679683 # average overall mshr miss latency 2627system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89062.500000 # average overall mshr miss latency 2628system.iocache.overall_avg_mshr_miss_latency::realview.ide 81179.953361 # average overall mshr miss latency 2629system.iocache.overall_avg_mshr_miss_latency::total 81182.679683 # average overall mshr miss latency 2630system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2631system.l2c.tags.replacements 1376932 # number of replacements 2632system.l2c.tags.tagsinuse 65061.419917 # Cycle average of tags in use 2633system.l2c.tags.total_refs 5975056 # Total number of references to valid blocks. 2634system.l2c.tags.sampled_refs 1437120 # Sample count of references to valid blocks. 2635system.l2c.tags.avg_refs 4.157660 # Average number of references to valid blocks. 2636system.l2c.tags.warmup_cycle 9858759500 # Cycle when the warmup percentage was hit. 2637system.l2c.tags.occ_blocks::writebacks 11843.449139 # Average occupied blocks per requestor 2638system.l2c.tags.occ_blocks::cpu0.dtb.walker 304.799159 # Average occupied blocks per requestor 2639system.l2c.tags.occ_blocks::cpu0.itb.walker 356.696004 # Average occupied blocks per requestor 2640system.l2c.tags.occ_blocks::cpu0.inst 3585.763677 # Average occupied blocks per requestor 2641system.l2c.tags.occ_blocks::cpu0.data 19085.445505 # Average occupied blocks per requestor 2642system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14223.146945 # Average occupied blocks per requestor 2643system.l2c.tags.occ_blocks::cpu1.dtb.walker 128.223998 # Average occupied blocks per requestor 2644system.l2c.tags.occ_blocks::cpu1.itb.walker 149.509582 # Average occupied blocks per requestor 2645system.l2c.tags.occ_blocks::cpu1.inst 3193.954857 # Average occupied blocks per requestor 2646system.l2c.tags.occ_blocks::cpu1.data 6240.562219 # Average occupied blocks per requestor 2647system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5949.868833 # Average occupied blocks per requestor 2648system.l2c.tags.occ_percent::writebacks 0.180717 # Average percentage of cache occupancy 2649system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004651 # Average percentage of cache occupancy 2650system.l2c.tags.occ_percent::cpu0.itb.walker 0.005443 # Average percentage of cache occupancy 2651system.l2c.tags.occ_percent::cpu0.inst 0.054714 # Average percentage of cache occupancy 2652system.l2c.tags.occ_percent::cpu0.data 0.291221 # Average percentage of cache occupancy 2653system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217028 # Average percentage of cache occupancy 2654system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001957 # Average percentage of cache occupancy 2655system.l2c.tags.occ_percent::cpu1.itb.walker 0.002281 # Average percentage of cache occupancy 2656system.l2c.tags.occ_percent::cpu1.inst 0.048736 # Average percentage of cache occupancy 2657system.l2c.tags.occ_percent::cpu1.data 0.095223 # Average percentage of cache occupancy 2658system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.090788 # Average percentage of cache occupancy 2659system.l2c.tags.occ_percent::total 0.992758 # Average percentage of cache occupancy 2660system.l2c.tags.occ_task_id_blocks::1022 11266 # Occupied blocks per task id 2661system.l2c.tags.occ_task_id_blocks::1023 259 # Occupied blocks per task id 2662system.l2c.tags.occ_task_id_blocks::1024 48663 # Occupied blocks per task id 2663system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 2664system.l2c.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id 2665system.l2c.tags.age_task_id_blocks_1022::3 297 # Occupied blocks per task id 2666system.l2c.tags.age_task_id_blocks_1022::4 10816 # Occupied blocks per task id 2667system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id 2668system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id 2669system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 2670system.l2c.tags.age_task_id_blocks_1024::2 888 # Occupied blocks per task id 2671system.l2c.tags.age_task_id_blocks_1024::3 4525 # Occupied blocks per task id 2672system.l2c.tags.age_task_id_blocks_1024::4 43209 # Occupied blocks per task id 2673system.l2c.tags.occ_task_id_percent::1022 0.171906 # Percentage of cache occupancy per task id 2674system.l2c.tags.occ_task_id_percent::1023 0.003952 # Percentage of cache occupancy per task id 2675system.l2c.tags.occ_task_id_percent::1024 0.742538 # Percentage of cache occupancy per task id 2676system.l2c.tags.tag_accesses 68586261 # Number of tag accesses 2677system.l2c.tags.data_accesses 68586261 # Number of data accesses 2678system.l2c.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 2679system.l2c.WritebackDirty_hits::writebacks 2589224 # number of WritebackDirty hits 2680system.l2c.WritebackDirty_hits::total 2589224 # number of WritebackDirty hits 2681system.l2c.UpgradeReq_hits::cpu0.data 191644 # number of UpgradeReq hits 2682system.l2c.UpgradeReq_hits::cpu1.data 164185 # number of UpgradeReq hits 2683system.l2c.UpgradeReq_hits::total 355829 # number of UpgradeReq hits 2684system.l2c.SCUpgradeReq_hits::cpu0.data 48914 # number of SCUpgradeReq hits 2685system.l2c.SCUpgradeReq_hits::cpu1.data 48173 # number of SCUpgradeReq hits 2686system.l2c.SCUpgradeReq_hits::total 97087 # number of SCUpgradeReq hits 2687system.l2c.ReadExReq_hits::cpu0.data 47737 # number of ReadExReq hits 2688system.l2c.ReadExReq_hits::cpu1.data 58567 # number of ReadExReq hits 2689system.l2c.ReadExReq_hits::total 106304 # number of ReadExReq hits 2690system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 9201 # number of ReadSharedReq hits 2691system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3860 # number of ReadSharedReq hits 2692system.l2c.ReadSharedReq_hits::cpu0.inst 408160 # number of ReadSharedReq hits 2693system.l2c.ReadSharedReq_hits::cpu0.data 537157 # number of ReadSharedReq hits 2694system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 271610 # number of ReadSharedReq hits 2695system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 10477 # number of ReadSharedReq hits 2696system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5555 # number of ReadSharedReq hits 2697system.l2c.ReadSharedReq_hits::cpu1.inst 408048 # number of ReadSharedReq hits 2698system.l2c.ReadSharedReq_hits::cpu1.data 521656 # number of ReadSharedReq hits 2699system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 272486 # number of ReadSharedReq hits 2700system.l2c.ReadSharedReq_hits::total 2448210 # number of ReadSharedReq hits 2701system.l2c.InvalidateReq_hits::cpu0.data 124551 # number of InvalidateReq hits 2702system.l2c.InvalidateReq_hits::cpu1.data 127410 # number of InvalidateReq hits 2703system.l2c.InvalidateReq_hits::total 251961 # number of InvalidateReq hits 2704system.l2c.demand_hits::cpu0.dtb.walker 9201 # number of demand (read+write) hits 2705system.l2c.demand_hits::cpu0.itb.walker 3860 # number of demand (read+write) hits 2706system.l2c.demand_hits::cpu0.inst 408160 # number of demand (read+write) hits 2707system.l2c.demand_hits::cpu0.data 584894 # number of demand (read+write) hits 2708system.l2c.demand_hits::cpu0.l2cache.prefetcher 271610 # number of demand (read+write) hits 2709system.l2c.demand_hits::cpu1.dtb.walker 10477 # number of demand (read+write) hits 2710system.l2c.demand_hits::cpu1.itb.walker 5555 # number of demand (read+write) hits 2711system.l2c.demand_hits::cpu1.inst 408048 # number of demand (read+write) hits 2712system.l2c.demand_hits::cpu1.data 580223 # number of demand (read+write) hits 2713system.l2c.demand_hits::cpu1.l2cache.prefetcher 272486 # number of demand (read+write) hits 2714system.l2c.demand_hits::total 2554514 # number of demand (read+write) hits 2715system.l2c.overall_hits::cpu0.dtb.walker 9201 # number of overall hits 2716system.l2c.overall_hits::cpu0.itb.walker 3860 # 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number of ReadSharedReq misses 2743system.l2c.ReadSharedReq_misses::cpu1.data 100605 # number of ReadSharedReq misses 2744system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 169474 # number of ReadSharedReq misses 2745system.l2c.ReadSharedReq_misses::total 753125 # number of ReadSharedReq misses 2746system.l2c.InvalidateReq_misses::cpu0.data 440725 # number of InvalidateReq misses 2747system.l2c.InvalidateReq_misses::cpu1.data 106525 # number of InvalidateReq misses 2748system.l2c.InvalidateReq_misses::total 547250 # number of InvalidateReq misses 2749system.l2c.demand_misses::cpu0.dtb.walker 1681 # number of demand (read+write) misses 2750system.l2c.demand_misses::cpu0.itb.walker 1744 # number of demand (read+write) misses 2751system.l2c.demand_misses::cpu0.inst 48585 # number of demand (read+write) misses 2752system.l2c.demand_misses::cpu0.data 217113 # number of demand (read+write) misses 2753system.l2c.demand_misses::cpu0.l2cache.prefetcher 241091 # number of demand (read+write) misses 2754system.l2c.demand_misses::cpu1.dtb.walker 1909 # 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number of demand (read+write) miss cycles 2799system.l2c.demand_miss_latency::cpu1.dtb.walker 194137000 # number of demand (read+write) miss cycles 2800system.l2c.demand_miss_latency::cpu1.itb.walker 210753000 # number of demand (read+write) miss cycles 2801system.l2c.demand_miss_latency::cpu1.inst 5171670000 # number of demand (read+write) miss cycles 2802system.l2c.demand_miss_latency::cpu1.data 17264081999 # number of demand (read+write) miss cycles 2803system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of demand (read+write) miss cycles 2804system.l2c.demand_miss_latency::total 107403016009 # number of demand (read+write) miss cycles 2805system.l2c.overall_miss_latency::cpu0.dtb.walker 167721500 # number of overall miss cycles 2806system.l2c.overall_miss_latency::cpu0.itb.walker 180518500 # number of overall miss cycles 2807system.l2c.overall_miss_latency::cpu0.inst 5556413500 # number of overall miss cycles 2808system.l2c.overall_miss_latency::cpu0.data 23706202999 # number of overall miss cycles 2809system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32099260605 # number of overall miss cycles 2810system.l2c.overall_miss_latency::cpu1.dtb.walker 194137000 # number of overall miss cycles 2811system.l2c.overall_miss_latency::cpu1.itb.walker 210753000 # number of overall miss cycles 2812system.l2c.overall_miss_latency::cpu1.inst 5171670000 # number of overall miss cycles 2813system.l2c.overall_miss_latency::cpu1.data 17264081999 # number of overall miss cycles 2814system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22852256906 # number of overall miss cycles 2815system.l2c.overall_miss_latency::total 107403016009 # number of overall miss cycles 2816system.l2c.WritebackDirty_accesses::writebacks 2589224 # number of WritebackDirty accesses(hits+misses) 2817system.l2c.WritebackDirty_accesses::total 2589224 # number of WritebackDirty accesses(hits+misses) 2818system.l2c.UpgradeReq_accesses::cpu0.data 216083 # number of UpgradeReq accesses(hits+misses) 2819system.l2c.UpgradeReq_accesses::cpu1.data 187389 # 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number of ReadSharedReq accesses(hits+misses) 2831system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 512701 # number of ReadSharedReq accesses(hits+misses) 2832system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12386 # number of ReadSharedReq accesses(hits+misses) 2833system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7528 # number of ReadSharedReq accesses(hits+misses) 2834system.l2c.ReadSharedReq_accesses::cpu1.inst 452728 # number of ReadSharedReq accesses(hits+misses) 2835system.l2c.ReadSharedReq_accesses::cpu1.data 622261 # number of ReadSharedReq accesses(hits+misses) 2836system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 441960 # number of ReadSharedReq accesses(hits+misses) 2837system.l2c.ReadSharedReq_accesses::total 3201335 # number of ReadSharedReq accesses(hits+misses) 2838system.l2c.InvalidateReq_accesses::cpu0.data 565276 # number of InvalidateReq accesses(hits+misses) 2839system.l2c.InvalidateReq_accesses::cpu1.data 233935 # number of InvalidateReq accesses(hits+misses) 2840system.l2c.InvalidateReq_accesses::total 799211 # number of InvalidateReq accesses(hits+misses) 2841system.l2c.demand_accesses::cpu0.dtb.walker 10882 # number of demand (read+write) accesses 2842system.l2c.demand_accesses::cpu0.itb.walker 5604 # number of demand (read+write) accesses 2843system.l2c.demand_accesses::cpu0.inst 456745 # number of demand (read+write) accesses 2844system.l2c.demand_accesses::cpu0.data 802007 # number of demand (read+write) accesses 2845system.l2c.demand_accesses::cpu0.l2cache.prefetcher 512701 # number of demand (read+write) accesses 2846system.l2c.demand_accesses::cpu1.dtb.walker 12386 # number of demand (read+write) accesses 2847system.l2c.demand_accesses::cpu1.itb.walker 7528 # number of demand (read+write) accesses 2848system.l2c.demand_accesses::cpu1.inst 452728 # number of demand (read+write) accesses 2849system.l2c.demand_accesses::cpu1.data 731277 # number of demand (read+write) accesses 2850system.l2c.demand_accesses::cpu1.l2cache.prefetcher 441960 # number of demand (read+write) accesses 2851system.l2c.demand_accesses::total 3433818 # number of demand (read+write) accesses 2852system.l2c.overall_accesses::cpu0.dtb.walker 10882 # number of overall (read+write) accesses 2853system.l2c.overall_accesses::cpu0.itb.walker 5604 # number of overall (read+write) accesses 2854system.l2c.overall_accesses::cpu0.inst 456745 # number of overall (read+write) accesses 2855system.l2c.overall_accesses::cpu0.data 802007 # number of overall (read+write) accesses 2856system.l2c.overall_accesses::cpu0.l2cache.prefetcher 512701 # number of overall (read+write) accesses 2857system.l2c.overall_accesses::cpu1.dtb.walker 12386 # number of overall (read+write) accesses 2858system.l2c.overall_accesses::cpu1.itb.walker 7528 # number of overall (read+write) accesses 2859system.l2c.overall_accesses::cpu1.inst 452728 # number of overall (read+write) accesses 2860system.l2c.overall_accesses::cpu1.data 731277 # number of overall (read+write) accesses 2861system.l2c.overall_accesses::cpu1.l2cache.prefetcher 441960 # number of overall (read+write) accesses 2862system.l2c.overall_accesses::total 3433818 # number of overall (read+write) accesses 2863system.l2c.UpgradeReq_miss_rate::cpu0.data 0.113100 # miss rate for UpgradeReq accesses 2864system.l2c.UpgradeReq_miss_rate::cpu1.data 0.123828 # miss rate for UpgradeReq accesses 2865system.l2c.UpgradeReq_miss_rate::total 0.118083 # miss rate for UpgradeReq accesses 2866system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012676 # miss rate for SCUpgradeReq accesses 2867system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.011369 # miss rate for SCUpgradeReq accesses 2868system.l2c.SCUpgradeReq_miss_rate::total 0.012028 # miss rate for SCUpgradeReq accesses 2869system.l2c.ReadExReq_miss_rate::cpu0.data 0.613362 # miss rate for ReadExReq accesses 2870system.l2c.ReadExReq_miss_rate::cpu1.data 0.462767 # miss rate for ReadExReq accesses 2871system.l2c.ReadExReq_miss_rate::total 0.542745 # miss rate for ReadExReq accesses 2872system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for ReadSharedReq accesses 2873system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.311206 # miss rate for ReadSharedReq accesses 2874system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.106372 # miss rate for ReadSharedReq accesses 2875system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.208364 # miss rate for ReadSharedReq accesses 2876system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for ReadSharedReq accesses 2877system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for ReadSharedReq accesses 2878system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.262088 # miss rate for ReadSharedReq accesses 2879system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098691 # miss rate for ReadSharedReq accesses 2880system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.161677 # miss rate for ReadSharedReq accesses 2881system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for ReadSharedReq accesses 2882system.l2c.ReadSharedReq_miss_rate::total 0.235253 # miss rate for ReadSharedReq accesses 2883system.l2c.InvalidateReq_miss_rate::cpu0.data 0.779663 # miss rate for InvalidateReq accesses 2884system.l2c.InvalidateReq_miss_rate::cpu1.data 0.455362 # miss rate for InvalidateReq accesses 2885system.l2c.InvalidateReq_miss_rate::total 0.684738 # miss rate for InvalidateReq accesses 2886system.l2c.demand_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for demand accesses 2887system.l2c.demand_miss_rate::cpu0.itb.walker 0.311206 # miss rate for demand accesses 2888system.l2c.demand_miss_rate::cpu0.inst 0.106372 # miss rate for demand accesses 2889system.l2c.demand_miss_rate::cpu0.data 0.270712 # miss rate for demand accesses 2890system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for demand accesses 2891system.l2c.demand_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for demand accesses 2892system.l2c.demand_miss_rate::cpu1.itb.walker 0.262088 # miss rate for demand accesses 2893system.l2c.demand_miss_rate::cpu1.inst 0.098691 # miss rate for demand accesses 2894system.l2c.demand_miss_rate::cpu1.data 0.206562 # miss rate for demand accesses 2895system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for demand accesses 2896system.l2c.demand_miss_rate::total 0.256072 # miss rate for demand accesses 2897system.l2c.overall_miss_rate::cpu0.dtb.walker 0.154475 # miss rate for overall accesses 2898system.l2c.overall_miss_rate::cpu0.itb.walker 0.311206 # miss rate for overall accesses 2899system.l2c.overall_miss_rate::cpu0.inst 0.106372 # miss rate for overall accesses 2900system.l2c.overall_miss_rate::cpu0.data 0.270712 # miss rate for overall accesses 2901system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.470237 # miss rate for overall accesses 2902system.l2c.overall_miss_rate::cpu1.dtb.walker 0.154126 # miss rate for overall accesses 2903system.l2c.overall_miss_rate::cpu1.itb.walker 0.262088 # miss rate for overall accesses 2904system.l2c.overall_miss_rate::cpu1.inst 0.098691 # miss rate for overall accesses 2905system.l2c.overall_miss_rate::cpu1.data 0.206562 # miss rate for overall accesses 2906system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.383460 # miss rate for overall accesses 2907system.l2c.overall_miss_rate::total 0.256072 # miss rate for overall accesses 2908system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6654.936781 # average UpgradeReq miss latency 2909system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5963.519221 # average UpgradeReq miss latency 2910system.l2c.UpgradeReq_avg_miss_latency::total 6318.189451 # average UpgradeReq miss latency 2911system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11946.656051 # average SCUpgradeReq miss latency 2912system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12720.216606 # average SCUpgradeReq miss latency 2913system.l2c.SCUpgradeReq_avg_miss_latency::total 12309.221658 # average SCUpgradeReq miss latency 2914system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108523.174422 # average ReadExReq miss latency 2915system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109423.120359 # average ReadExReq miss latency 2916system.l2c.ReadExReq_avg_miss_latency::total 108882.991607 # average ReadExReq miss latency 2917system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average ReadSharedReq miss latency 2918system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 103508.314220 # average ReadSharedReq miss latency 2919system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114364.793661 # average ReadSharedReq miss latency 2920system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109544.591641 # average ReadSharedReq miss latency 2921system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average ReadSharedReq miss latency 2922system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average ReadSharedReq miss latency 2923system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 106818.550431 # average ReadSharedReq miss latency 2924system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 115749.104745 # average ReadSharedReq miss latency 2925system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 116731.723075 # average ReadSharedReq miss latency 2926system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average ReadSharedReq miss latency 2927system.l2c.ReadSharedReq_avg_miss_latency::total 124367.494122 # average ReadSharedReq miss latency 2928system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 96.649838 # average InvalidateReq miss latency 2929system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 312.616757 # average InvalidateReq miss latency 2930system.l2c.InvalidateReq_avg_miss_latency::total 138.688899 # average InvalidateReq miss latency 2931system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average overall miss latency 2932system.l2c.demand_avg_miss_latency::cpu0.itb.walker 103508.314220 # average overall miss latency 2933system.l2c.demand_avg_miss_latency::cpu0.inst 114364.793661 # average overall miss latency 2934system.l2c.demand_avg_miss_latency::cpu0.data 109188.316678 # average overall miss latency 2935system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average overall miss latency 2936system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average overall miss latency 2937system.l2c.demand_avg_miss_latency::cpu1.itb.walker 106818.550431 # average overall miss latency 2938system.l2c.demand_avg_miss_latency::cpu1.inst 115749.104745 # average overall miss latency 2939system.l2c.demand_avg_miss_latency::cpu1.data 114290.796662 # average overall miss latency 2940system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average overall miss latency 2941system.l2c.demand_avg_miss_latency::total 122145.487805 # average overall miss latency 2942system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 99774.836407 # average overall miss latency 2943system.l2c.overall_avg_miss_latency::cpu0.itb.walker 103508.314220 # average overall miss latency 2944system.l2c.overall_avg_miss_latency::cpu0.inst 114364.793661 # average overall miss latency 2945system.l2c.overall_avg_miss_latency::cpu0.data 109188.316678 # average overall miss latency 2946system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133141.679304 # average overall miss latency 2947system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 101695.652174 # average overall miss latency 2948system.l2c.overall_avg_miss_latency::cpu1.itb.walker 106818.550431 # average overall miss latency 2949system.l2c.overall_avg_miss_latency::cpu1.inst 115749.104745 # average overall miss latency 2950system.l2c.overall_avg_miss_latency::cpu1.data 114290.796662 # average overall miss latency 2951system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134842.258435 # average overall miss latency 2952system.l2c.overall_avg_miss_latency::total 122145.487805 # average overall miss latency 2953system.l2c.blocked_cycles::no_mshrs 340 # number of cycles access was blocked 2954system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2955system.l2c.blocked::no_mshrs 16 # number of cycles access was blocked 2956system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2957system.l2c.avg_blocked_cycles::no_mshrs 21.250000 # average number of cycles each access was blocked 2958system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2959system.l2c.writebacks::writebacks 1062552 # number of writebacks 2960system.l2c.writebacks::total 1062552 # number of writebacks 2961system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 178 # number of ReadSharedReq MSHR hits 2962system.l2c.ReadSharedReq_mshr_hits::cpu0.data 32 # number of ReadSharedReq MSHR hits 2963system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 123 # number of ReadSharedReq MSHR hits 2964system.l2c.ReadSharedReq_mshr_hits::cpu1.data 57 # number of ReadSharedReq MSHR hits 2965system.l2c.ReadSharedReq_mshr_hits::total 390 # number of ReadSharedReq MSHR hits 2966system.l2c.demand_mshr_hits::cpu0.inst 178 # number of demand (read+write) MSHR hits 2967system.l2c.demand_mshr_hits::cpu0.data 32 # number of demand (read+write) MSHR hits 2968system.l2c.demand_mshr_hits::cpu1.inst 123 # number of demand (read+write) MSHR hits 2969system.l2c.demand_mshr_hits::cpu1.data 57 # number of demand (read+write) MSHR hits 2970system.l2c.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits 2971system.l2c.overall_mshr_hits::cpu0.inst 178 # number of overall MSHR hits 2972system.l2c.overall_mshr_hits::cpu0.data 32 # number of overall MSHR hits 2973system.l2c.overall_mshr_hits::cpu1.inst 123 # number of overall MSHR hits 2974system.l2c.overall_mshr_hits::cpu1.data 57 # number of overall MSHR hits 2975system.l2c.overall_mshr_hits::total 390 # number of overall MSHR hits 2976system.l2c.CleanEvict_mshr_misses::writebacks 55381 # number of CleanEvict MSHR misses 2977system.l2c.CleanEvict_mshr_misses::total 55381 # number of CleanEvict MSHR misses 2978system.l2c.UpgradeReq_mshr_misses::cpu0.data 24439 # number of UpgradeReq MSHR misses 2979system.l2c.UpgradeReq_mshr_misses::cpu1.data 23204 # number of UpgradeReq MSHR misses 2980system.l2c.UpgradeReq_mshr_misses::total 47643 # number of UpgradeReq MSHR misses 2981system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 628 # number of SCUpgradeReq MSHR misses 2982system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 554 # number of SCUpgradeReq MSHR misses 2983system.l2c.SCUpgradeReq_mshr_misses::total 1182 # number of SCUpgradeReq MSHR misses 2984system.l2c.ReadExReq_mshr_misses::cpu0.data 75730 # number of ReadExReq MSHR misses 2985system.l2c.ReadExReq_mshr_misses::cpu1.data 50449 # number of ReadExReq MSHR misses 2986system.l2c.ReadExReq_mshr_misses::total 126179 # number of ReadExReq MSHR misses 2987system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1681 # number of ReadSharedReq MSHR misses 2988system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1744 # number of ReadSharedReq MSHR misses 2989system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 48407 # number of ReadSharedReq MSHR misses 2990system.l2c.ReadSharedReq_mshr_misses::cpu0.data 141351 # number of ReadSharedReq MSHR misses 2991system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of ReadSharedReq MSHR misses 2992system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1909 # number of ReadSharedReq MSHR misses 2993system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1973 # number of ReadSharedReq MSHR misses 2994system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44557 # number of ReadSharedReq MSHR misses 2995system.l2c.ReadSharedReq_mshr_misses::cpu1.data 100548 # number of ReadSharedReq MSHR misses 2996system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of ReadSharedReq MSHR misses 2997system.l2c.ReadSharedReq_mshr_misses::total 752735 # number of ReadSharedReq MSHR misses 2998system.l2c.InvalidateReq_mshr_misses::cpu0.data 440725 # number of InvalidateReq MSHR misses 2999system.l2c.InvalidateReq_mshr_misses::cpu1.data 106525 # number of InvalidateReq MSHR misses 3000system.l2c.InvalidateReq_mshr_misses::total 547250 # number of InvalidateReq MSHR misses 3001system.l2c.demand_mshr_misses::cpu0.dtb.walker 1681 # number of demand (read+write) MSHR misses 3002system.l2c.demand_mshr_misses::cpu0.itb.walker 1744 # number of demand (read+write) MSHR misses 3003system.l2c.demand_mshr_misses::cpu0.inst 48407 # number of demand (read+write) MSHR misses 3004system.l2c.demand_mshr_misses::cpu0.data 217081 # number of demand (read+write) MSHR misses 3005system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of demand (read+write) MSHR misses 3006system.l2c.demand_mshr_misses::cpu1.dtb.walker 1909 # number of demand (read+write) MSHR misses 3007system.l2c.demand_mshr_misses::cpu1.itb.walker 1973 # number of demand (read+write) MSHR misses 3008system.l2c.demand_mshr_misses::cpu1.inst 44557 # number of demand (read+write) MSHR misses 3009system.l2c.demand_mshr_misses::cpu1.data 150997 # number of demand (read+write) MSHR misses 3010system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of demand (read+write) MSHR misses 3011system.l2c.demand_mshr_misses::total 878914 # number of demand (read+write) MSHR misses 3012system.l2c.overall_mshr_misses::cpu0.dtb.walker 1681 # number of overall MSHR misses 3013system.l2c.overall_mshr_misses::cpu0.itb.walker 1744 # number of overall MSHR misses 3014system.l2c.overall_mshr_misses::cpu0.inst 48407 # number of overall MSHR misses 3015system.l2c.overall_mshr_misses::cpu0.data 217081 # number of overall MSHR misses 3016system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 241091 # number of overall MSHR misses 3017system.l2c.overall_mshr_misses::cpu1.dtb.walker 1909 # number of overall MSHR misses 3018system.l2c.overall_mshr_misses::cpu1.itb.walker 1973 # number of overall MSHR misses 3019system.l2c.overall_mshr_misses::cpu1.inst 44557 # number of overall MSHR misses 3020system.l2c.overall_mshr_misses::cpu1.data 150997 # number of overall MSHR misses 3021system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 169474 # number of overall MSHR misses 3022system.l2c.overall_mshr_misses::total 878914 # number of overall MSHR misses 3023system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 3024system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable 3025system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 3026system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22201 # number of ReadReq MSHR uncacheable 3027system.l2c.ReadReq_mshr_uncacheable::total 81817 # number of ReadReq MSHR uncacheable 3028system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable 3029system.l2c.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable 3030system.l2c.WriteReq_mshr_uncacheable::total 38449 # number of WriteReq MSHR uncacheable 3031system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 3032system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses 3033system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 3034system.l2c.overall_mshr_uncacheable_misses::cpu1.data 42956 # number of overall MSHR uncacheable misses 3035system.l2c.overall_mshr_uncacheable_misses::total 120266 # number of overall MSHR uncacheable misses 3036system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 494587500 # number of UpgradeReq MSHR miss cycles 3037system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 479394000 # number of UpgradeReq MSHR miss cycles 3038system.l2c.UpgradeReq_mshr_miss_latency::total 973981500 # number of UpgradeReq MSHR miss cycles 3039system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15163500 # number of SCUpgradeReq MSHR miss cycles 3040system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 13789000 # number of SCUpgradeReq MSHR miss cycles 3041system.l2c.SCUpgradeReq_mshr_miss_latency::total 28952500 # number of SCUpgradeReq MSHR miss cycles 3042system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7461135548 # number of ReadExReq MSHR miss cycles 3043system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5015765562 # number of ReadExReq MSHR miss cycles 3044system.l2c.ReadExReq_mshr_miss_latency::total 12476901110 # number of ReadExReq MSHR miss cycles 3045system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of ReadSharedReq MSHR miss cycles 3046system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 163078500 # number of ReadSharedReq MSHR miss cycles 3047system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5057062528 # number of ReadSharedReq MSHR miss cycles 3048system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14070826165 # number of ReadSharedReq MSHR miss cycles 3049system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of ReadSharedReq MSHR miss cycles 3050system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of ReadSharedReq MSHR miss cycles 3051system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 191021503 # number of ReadSharedReq MSHR miss cycles 3052system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4714685544 # number of ReadSharedReq MSHR miss cycles 3053system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10733108269 # number of ReadSharedReq MSHR miss cycles 3054system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of ReadSharedReq MSHR miss cycles 3055system.l2c.ReadSharedReq_mshr_miss_latency::total 86101249279 # number of ReadSharedReq MSHR miss cycles 3056system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8759971500 # number of InvalidateReq MSHR miss cycles 3057system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2141412000 # number of InvalidateReq MSHR miss cycles 3058system.l2c.InvalidateReq_mshr_miss_latency::total 10901383500 # number of InvalidateReq MSHR miss cycles 3059system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of demand (read+write) MSHR miss cycles 3060system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 163078500 # number of demand (read+write) MSHR miss cycles 3061system.l2c.demand_mshr_miss_latency::cpu0.inst 5057062528 # number of demand (read+write) MSHR miss cycles 3062system.l2c.demand_mshr_miss_latency::cpu0.data 21531961713 # number of demand (read+write) MSHR miss cycles 3063system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of demand (read+write) MSHR miss cycles 3064system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of demand (read+write) MSHR miss cycles 3065system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 191021503 # number of demand (read+write) MSHR miss cycles 3066system.l2c.demand_mshr_miss_latency::cpu1.inst 4714685544 # number of demand (read+write) MSHR miss cycles 3067system.l2c.demand_mshr_miss_latency::cpu1.data 15748873831 # number of demand (read+write) MSHR miss cycles 3068system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of demand (read+write) MSHR miss cycles 3069system.l2c.demand_mshr_miss_latency::total 98578150389 # number of demand (read+write) MSHR miss cycles 3070system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 150911500 # number of overall MSHR miss cycles 3071system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 163078500 # number of overall MSHR miss cycles 3072system.l2c.overall_mshr_miss_latency::cpu0.inst 5057062528 # number of overall MSHR miss cycles 3073system.l2c.overall_mshr_miss_latency::cpu0.data 21531961713 # number of overall MSHR miss cycles 3074system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 29688205910 # number of overall MSHR miss cycles 3075system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 175047000 # number of overall MSHR miss cycles 3076system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 191021503 # number of overall MSHR miss cycles 3077system.l2c.overall_mshr_miss_latency::cpu1.inst 4714685544 # number of overall MSHR miss cycles 3078system.l2c.overall_mshr_miss_latency::cpu1.data 15748873831 # number of overall MSHR miss cycles 3079system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21157302360 # number of overall MSHR miss cycles 3080system.l2c.overall_mshr_miss_latency::total 98578150389 # number of overall MSHR miss cycles 3081system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of ReadReq MSHR uncacheable cycles 3082system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2614209002 # number of ReadReq MSHR uncacheable cycles 3083system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7665500 # number of ReadReq MSHR uncacheable cycles 3084system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3345576000 # number of ReadReq MSHR uncacheable cycles 3085system.l2c.ReadReq_mshr_uncacheable_latency::total 8984296502 # number of ReadReq MSHR uncacheable cycles 3086system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3016846000 # number of overall MSHR uncacheable cycles 3087system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2614209002 # number of overall MSHR uncacheable cycles 3088system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7665500 # number of overall MSHR uncacheable cycles 3089system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3345576000 # number of overall MSHR uncacheable cycles 3090system.l2c.overall_mshr_uncacheable_latency::total 8984296502 # number of overall MSHR uncacheable cycles 3091system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3092system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3093system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.113100 # mshr miss rate for UpgradeReq accesses 3094system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.123828 # mshr miss rate for UpgradeReq accesses 3095system.l2c.UpgradeReq_mshr_miss_rate::total 0.118083 # mshr miss rate for UpgradeReq accesses 3096system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012676 # mshr miss rate for SCUpgradeReq accesses 3097system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011369 # mshr miss rate for SCUpgradeReq accesses 3098system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.012028 # mshr miss rate for SCUpgradeReq accesses 3099system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.613362 # mshr miss rate for ReadExReq accesses 3100system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462767 # mshr miss rate for ReadExReq accesses 3101system.l2c.ReadExReq_mshr_miss_rate::total 0.542745 # mshr miss rate for ReadExReq accesses 3102system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for ReadSharedReq accesses 3103system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for ReadSharedReq accesses 3104system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for ReadSharedReq accesses 3105system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208316 # mshr miss rate for ReadSharedReq accesses 3106system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for ReadSharedReq accesses 3107system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for ReadSharedReq accesses 3108system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for ReadSharedReq accesses 3109system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for ReadSharedReq accesses 3110system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.161585 # mshr miss rate for ReadSharedReq accesses 3111system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for ReadSharedReq accesses 3112system.l2c.ReadSharedReq_mshr_miss_rate::total 0.235132 # mshr miss rate for ReadSharedReq accesses 3113system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.779663 # mshr miss rate for InvalidateReq accesses 3114system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.455362 # mshr miss rate for InvalidateReq accesses 3115system.l2c.InvalidateReq_mshr_miss_rate::total 0.684738 # mshr miss rate for InvalidateReq accesses 3116system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for demand accesses 3117system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for demand accesses 3118system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for demand accesses 3119system.l2c.demand_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for demand accesses 3120system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for demand accesses 3121system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for demand accesses 3122system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for demand accesses 3123system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for demand accesses 3124system.l2c.demand_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for demand accesses 3125system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for demand accesses 3126system.l2c.demand_mshr_miss_rate::total 0.255958 # mshr miss rate for demand accesses 3127system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for overall accesses 3128system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for overall accesses 3129system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for overall accesses 3130system.l2c.overall_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for overall accesses 3131system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for overall accesses 3132system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for overall accesses 3133system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for overall accesses 3134system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for overall accesses 3135system.l2c.overall_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for overall accesses 3136system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for overall accesses 3137system.l2c.overall_mshr_miss_rate::total 0.255958 # mshr miss rate for overall accesses 3138system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20237.632473 # average UpgradeReq mshr miss latency 3139system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20659.972419 # average UpgradeReq mshr miss latency 3140system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20443.328506 # average UpgradeReq mshr miss latency 3141system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24145.700637 # average SCUpgradeReq mshr miss latency 3142system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24889.891697 # average SCUpgradeReq mshr miss latency 3143system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24494.500846 # average SCUpgradeReq mshr miss latency 3144system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98522.851552 # average ReadExReq mshr miss latency 3145system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99422.497215 # average ReadExReq mshr miss latency 3146system.l2c.ReadExReq_avg_mshr_miss_latency::total 98882.548681 # average ReadExReq mshr miss latency 3147system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average ReadSharedReq mshr miss latency 3148system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average ReadSharedReq mshr miss latency 3149system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average ReadSharedReq mshr miss latency 3150system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99545.289138 # average ReadSharedReq mshr miss latency 3151system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average ReadSharedReq mshr miss latency 3152system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average ReadSharedReq mshr miss latency 3153system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average ReadSharedReq mshr miss latency 3154system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average ReadSharedReq mshr miss latency 3155system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106746.113985 # average ReadSharedReq mshr miss latency 3156system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average ReadSharedReq mshr miss latency 3157system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114384.543404 # average ReadSharedReq mshr miss latency 3158system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19876.275455 # average InvalidateReq mshr miss latency 3159system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20102.436048 # average InvalidateReq mshr miss latency 3160system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19920.298767 # average InvalidateReq mshr miss latency 3161system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency 3162system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency 3163system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency 3164system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency 3165system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency 3166system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency 3167system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency 3168system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency 3169system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency 3170system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency 3171system.l2c.demand_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency 3172system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency 3173system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency 3174system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency 3175system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency 3176system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency 3177system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency 3178system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency 3179system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency 3180system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency 3181system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency 3182system.l2c.overall_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency 3183system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency 3184system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159587.876320 # average ReadReq mshr uncacheable latency 3185system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average ReadReq mshr uncacheable latency 3186system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150694.833566 # average ReadReq mshr uncacheable latency 3187system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109809.654497 # average ReadReq mshr uncacheable latency 3188system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency 3189system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76719.266383 # average overall mshr uncacheable latency 3190system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average overall mshr uncacheable latency 3191system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77883.788062 # average overall mshr uncacheable latency 3192system.l2c.overall_avg_mshr_uncacheable_latency::total 74703.544659 # average overall mshr uncacheable latency 3193system.membus.snoop_filter.tot_requests 3576184 # Total number of requests made to the snoop filter. 3194system.membus.snoop_filter.hit_single_requests 2127782 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3195system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3196system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3197system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3198system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3199system.membus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3200system.membus.trans_dist::ReadReq 81817 # Transaction distribution 3201system.membus.trans_dist::ReadResp 843472 # Transaction distribution 3202system.membus.trans_dist::WriteReq 38449 # Transaction distribution 3203system.membus.trans_dist::WriteResp 38449 # Transaction distribution 3204system.membus.trans_dist::WritebackDirty 1169254 # Transaction distribution 3205system.membus.trans_dist::CleanEvict 223620 # Transaction distribution 3206system.membus.trans_dist::UpgradeReq 320332 # Transaction distribution 3207system.membus.trans_dist::SCUpgradeReq 305580 # Transaction distribution 3208system.membus.trans_dist::UpgradeResp 16 # Transaction distribution 3209system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 3210system.membus.trans_dist::ReadExReq 143723 # Transaction distribution 3211system.membus.trans_dist::ReadExResp 125482 # Transaction distribution 3212system.membus.trans_dist::ReadSharedReq 761655 # Transaction distribution 3213system.membus.trans_dist::InvalidateReq 651499 # Transaction distribution 3214system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) 3215system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3216system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26178 # Packet count per connected master and slave (bytes) 3217system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4313500 # Packet count per connected master and slave (bytes) 3218system.membus.pkt_count_system.l2c.mem_side::total 4462434 # Packet count per connected master and slave (bytes) 3219system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238025 # Packet count per connected master and slave (bytes) 3220system.membus.pkt_count_system.iocache.mem_side::total 238025 # Packet count per connected master and slave (bytes) 3221system.membus.pkt_count::total 4700459 # Packet count per connected master and slave (bytes) 3222system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) 3223system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3224system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52356 # Cumulative packet size per connected master and slave (bytes) 3225system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124357036 # Cumulative packet size per connected master and slave (bytes) 3226system.membus.pkt_size_system.l2c.mem_side::total 124565390 # Cumulative packet size per connected master and slave (bytes) 3227system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7261504 # Cumulative packet size per connected master and slave (bytes) 3228system.membus.pkt_size_system.iocache.mem_side::total 7261504 # Cumulative packet size per connected master and slave (bytes) 3229system.membus.pkt_size::total 131826894 # Cumulative packet size per connected master and slave (bytes) 3230system.membus.snoops 595046 # Total snoops (count) 3231system.membus.snoopTraffic 184128 # Total snoop traffic (bytes) 3232system.membus.snoop_fanout::samples 2303059 # Request fanout histogram 3233system.membus.snoop_fanout::mean 0.014256 # Request fanout histogram 3234system.membus.snoop_fanout::stdev 0.118544 # Request fanout histogram 3235system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3236system.membus.snoop_fanout::0 2270227 98.57% 98.57% # Request fanout histogram 3237system.membus.snoop_fanout::1 32832 1.43% 100.00% # Request fanout histogram 3238system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3239system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3240system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3241system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3242system.membus.snoop_fanout::total 2303059 # Request fanout histogram 3243system.membus.reqLayer0.occupancy 101257500 # Layer occupancy (ticks) 3244system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3245system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 3246system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3247system.membus.reqLayer2.occupancy 21679000 # Layer occupancy (ticks) 3248system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3249system.membus.reqLayer5.occupancy 8033203938 # Layer occupancy (ticks) 3250system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3251system.membus.respLayer2.occupancy 4846349578 # Layer occupancy (ticks) 3252system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3253system.membus.respLayer3.occupancy 45469982 # Layer occupancy (ticks) 3254system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3255system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3256system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3257system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3258system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3259system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3260system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3261system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3262system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3263system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3264system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3265system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3266system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3267system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3268system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3269system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3270system.realview.ethernet.txBytes 966 # Bytes Transmitted 3271system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3272system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3273system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3274system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3275system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3276system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3277system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3278system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3279system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3280system.realview.ethernet.totPackets 3 # Total Packets 3281system.realview.ethernet.totBytes 966 # Total Bytes 3282system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3283system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3284system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3285system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3286system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3287system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3288system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3289system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3290system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3291system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3292system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3293system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3294system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3295system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3296system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3297system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3298system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3299system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3300system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3301system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3302system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3303system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3304system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3305system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3306system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3307system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3308system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3309system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3310system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3311system.realview.ethernet.droppedPackets 0 # number of packets dropped 3312system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3313system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3314system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3315system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3316system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3317system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3318system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3319system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3320system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3321system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3322system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3323system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3324system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3325system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3326system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3327system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3328system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3329system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3330system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3331system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3332system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3333system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3334system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3335system.toL2Bus.snoop_filter.tot_requests 10759482 # Total number of requests made to the snoop filter. 3336system.toL2Bus.snoop_filter.hit_single_requests 5851735 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3337system.toL2Bus.snoop_filter.hit_multi_requests 1766751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3338system.toL2Bus.snoop_filter.tot_snoops 181547 # Total number of snoops made to the snoop filter. 3339system.toL2Bus.snoop_filter.hit_single_snoops 166860 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3340system.toL2Bus.snoop_filter.hit_multi_snoops 14687 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3341system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states 3342system.toL2Bus.trans_dist::ReadReq 81819 # Transaction distribution 3343system.toL2Bus.trans_dist::ReadResp 4062742 # Transaction distribution 3344system.toL2Bus.trans_dist::WriteReq 38449 # Transaction distribution 3345system.toL2Bus.trans_dist::WriteResp 38449 # Transaction distribution 3346system.toL2Bus.trans_dist::WritebackDirty 3651776 # Transaction distribution 3347system.toL2Bus.trans_dist::CleanEvict 2342209 # Transaction distribution 3348system.toL2Bus.trans_dist::UpgradeReq 672985 # Transaction distribution 3349system.toL2Bus.trans_dist::SCUpgradeReq 402667 # Transaction distribution 3350system.toL2Bus.trans_dist::UpgradeResp 1075652 # Transaction distribution 3351system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution 3352system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution 3353system.toL2Bus.trans_dist::ReadExReq 288170 # Transaction distribution 3354system.toL2Bus.trans_dist::ReadExResp 288170 # Transaction distribution 3355system.toL2Bus.trans_dist::ReadSharedReq 3981632 # Transaction distribution 3356system.toL2Bus.trans_dist::InvalidateReq 828938 # Transaction distribution 3357system.toL2Bus.trans_dist::InvalidateResp 799211 # Transaction distribution 3358system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8607895 # Packet count per connected master and slave (bytes) 3359system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7128520 # Packet count per connected master and slave (bytes) 3360system.toL2Bus.pkt_count::total 15736415 # Packet count per connected master and slave (bytes) 3361system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 211923339 # Cumulative packet size per connected master and slave (bytes) 3362system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 174059331 # Cumulative packet size per connected master and slave (bytes) 3363system.toL2Bus.pkt_size::total 385982670 # Cumulative packet size per connected master and slave (bytes) 3364system.toL2Bus.snoops 2818319 # Total snoops (count) 3365system.toL2Bus.snoopTraffic 121467536 # Total snoop traffic (bytes) 3366system.toL2Bus.snoop_fanout::samples 7671705 # Request fanout histogram 3367system.toL2Bus.snoop_fanout::mean 0.367658 # Request fanout histogram 3368system.toL2Bus.snoop_fanout::stdev 0.486122 # Request fanout histogram 3369system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3370system.toL2Bus.snoop_fanout::0 4865825 63.43% 63.43% # Request fanout histogram 3371system.toL2Bus.snoop_fanout::1 2791193 36.38% 99.81% # Request fanout histogram 3372system.toL2Bus.snoop_fanout::2 14687 0.19% 100.00% # Request fanout histogram 3373system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3374system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3375system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3376system.toL2Bus.snoop_fanout::total 7671705 # Request fanout histogram 3377system.toL2Bus.reqLayer0.occupancy 8456586164 # Layer occupancy (ticks) 3378system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3379system.toL2Bus.snoopLayer0.occupancy 2556167 # Layer occupancy (ticks) 3380system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3381system.toL2Bus.respLayer0.occupancy 3921212144 # Layer occupancy (ticks) 3382system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3383system.toL2Bus.respLayer1.occupancy 3534160915 # Layer occupancy (ticks) 3384system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3385 3386---------- End Simulation Statistics ---------- 3387