stats.txt revision 11245
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311245Sandreas.sandberg@arm.comsim_seconds 47.593744 # Number of seconds simulated 411245Sandreas.sandberg@arm.comsim_ticks 47593744171500 # Number of ticks simulated 511245Sandreas.sandberg@arm.comfinal_tick 47593744171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711245Sandreas.sandberg@arm.comhost_inst_rate 618435 # Simulator instruction rate (inst/s) 811245Sandreas.sandberg@arm.comhost_op_rate 727668 # Simulator op (including micro ops) rate (op/s) 911245Sandreas.sandberg@arm.comhost_tick_rate 34163076444 # Simulator tick rate (ticks/s) 1011245Sandreas.sandberg@arm.comhost_mem_usage 740160 # Number of bytes of host memory used 1111245Sandreas.sandberg@arm.comhost_seconds 1393.13 # Real time elapsed on the host 1211245Sandreas.sandberg@arm.comsim_insts 861562684 # Number of instructions simulated 1311245Sandreas.sandberg@arm.comsim_ops 1013739401 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 69440 # Number of bytes read from this memory 1711245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 68224 # Number of bytes read from this memory 1811245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.inst 3088500 # Number of bytes read from this memory 1911245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.data 37423496 # Number of bytes read from this memory 2011245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 12959872 # Number of bytes read from this memory 2111245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 98944 # Number of bytes read from this memory 2211245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 107776 # Number of bytes read from this memory 2311245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.inst 2567544 # Number of bytes read from this memory 2411245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.data 15084176 # Number of bytes read from this memory 2511245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 9154944 # Number of bytes read from this memory 2611245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory 2711245Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 81051908 # Number of bytes read from this memory 2811245Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3088500 # Number of instructions bytes read from this memory 2911245Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2567544 # Number of instructions bytes read from this memory 3011245Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::total 5656044 # Number of instructions bytes read from this memory 3111245Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 68863296 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411245Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 68883880 # Number of bytes written to this memory 3511245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1085 # Number of read requests responded to by this memory 3611245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1066 # Number of read requests responded to by this memory 3711245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.inst 88665 # Number of read requests responded to by this memory 3811245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.data 584755 # Number of read requests responded to by this memory 3911245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 202498 # Number of read requests responded to by this memory 4011245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1546 # Number of read requests responded to by this memory 4111245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1684 # Number of read requests responded to by this memory 4211245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.inst 40206 # Number of read requests responded to by this memory 4311245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.data 235703 # Number of read requests responded to by this memory 4411245Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 143046 # Number of read requests responded to by this memory 4511245Sandreas.sandberg@arm.comsystem.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory 4611245Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 1306957 # Number of read requests responded to by this memory 4711245Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 1075989 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011245Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 1078563 # Number of write requests responded to by this memory 5111245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 1459 # Total read bandwidth from this memory (bytes/s) 5211245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.itb.walker 1433 # Total read bandwidth from this memory (bytes/s) 5311245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.inst 64893 # Total read bandwidth from this memory (bytes/s) 5411245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.data 786311 # Total read bandwidth from this memory (bytes/s) 5511245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 272302 # Total read bandwidth from this memory (bytes/s) 5611245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2079 # Total read bandwidth from this memory (bytes/s) 5711245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.itb.walker 2264 # Total read bandwidth from this memory (bytes/s) 5811245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.inst 53947 # Total read bandwidth from this memory (bytes/s) 5911245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.data 316936 # Total read bandwidth from this memory (bytes/s) 6011245Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 192356 # Total read bandwidth from this memory (bytes/s) 6111245Sandreas.sandberg@arm.comsystem.physmem.bw_read::realview.ide 9014 # Total read bandwidth from this memory (bytes/s) 6211245Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 1702995 # Total read bandwidth from this memory (bytes/s) 6311245Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu0.inst 64893 # Instruction read bandwidth from this memory (bytes/s) 6411245Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu1.inst 53947 # Instruction read bandwidth from this memory (bytes/s) 6511245Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 118840 # Instruction read bandwidth from this memory (bytes/s) 6611245Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 1446898 # Write bandwidth from this memory (bytes/s) 6711201Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s) 6810585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911245Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 1447331 # Write bandwidth from this memory (bytes/s) 7011245Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 1446898 # Total bandwidth to/from this memory (bytes/s) 7111245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 1459 # Total bandwidth to/from this memory (bytes/s) 7211245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.itb.walker 1433 # Total bandwidth to/from this memory (bytes/s) 7311245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.inst 64893 # Total bandwidth to/from this memory (bytes/s) 7411245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.data 786744 # Total bandwidth to/from this memory (bytes/s) 7511245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 272302 # Total bandwidth to/from this memory (bytes/s) 7611245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2079 # Total bandwidth to/from this memory (bytes/s) 7711245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.itb.walker 2264 # Total bandwidth to/from this memory (bytes/s) 7811245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.inst 53947 # Total bandwidth to/from this memory (bytes/s) 7911245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.data 316936 # Total bandwidth to/from this memory (bytes/s) 8011245Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 192356 # Total bandwidth to/from this memory (bytes/s) 8111245Sandreas.sandberg@arm.comsystem.physmem.bw_total::realview.ide 9014 # Total bandwidth to/from this memory (bytes/s) 8211245Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 3150326 # Total bandwidth to/from this memory (bytes/s) 8311245Sandreas.sandberg@arm.comsystem.physmem.readReqs 1306957 # Number of read requests accepted 8411245Sandreas.sandberg@arm.comsystem.physmem.writeReqs 1078563 # Number of write requests accepted 8511245Sandreas.sandberg@arm.comsystem.physmem.readBursts 1306957 # Number of DRAM read bursts, including those serviced by the write queue 8611245Sandreas.sandberg@arm.comsystem.physmem.writeBursts 1078563 # Number of DRAM write bursts, including those merged in the write queue 8711245Sandreas.sandberg@arm.comsystem.physmem.bytesReadDRAM 83609728 # Total number of bytes read from DRAM 8811245Sandreas.sandberg@arm.comsystem.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue 8911245Sandreas.sandberg@arm.comsystem.physmem.bytesWritten 68881216 # Total number of bytes written to DRAM 9011245Sandreas.sandberg@arm.comsystem.physmem.bytesReadSys 81051908 # Total read bytes from the system interface side 9111245Sandreas.sandberg@arm.comsystem.physmem.bytesWrittenSys 68883880 # Total written bytes from the system interface side 9211245Sandreas.sandberg@arm.comsystem.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue 9311245Sandreas.sandberg@arm.comsystem.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one 9411245Sandreas.sandberg@arm.comsystem.physmem.neitherReadNorWriteReqs 450744 # Number of requests that are neither read nor write 9511245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::0 74137 # Per bank write bursts 9611245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::1 79440 # Per bank write bursts 9711245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::2 74164 # Per bank write bursts 9811245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::3 81483 # Per bank write bursts 9911245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::4 82988 # Per bank write bursts 10011245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::5 89928 # Per bank write bursts 10111245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::6 78492 # Per bank write bursts 10211245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::7 81076 # Per bank write bursts 10311245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::8 74414 # Per bank write bursts 10411245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::9 117966 # Per bank write bursts 10511245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::10 72212 # Per bank write bursts 10611245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::11 83486 # Per bank write bursts 10711245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::12 77461 # Per bank write bursts 10811245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::13 81836 # Per bank write bursts 10911245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::14 80080 # Per bank write bursts 11011245Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::15 77239 # Per bank write bursts 11111245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::0 62409 # Per bank write bursts 11211245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::1 67459 # Per bank write bursts 11311245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::2 64157 # Per bank write bursts 11411245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::3 68996 # Per bank write bursts 11511245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::4 69521 # Per bank write bursts 11611245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::5 74527 # Per bank write bursts 11711245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::6 66146 # Per bank write bursts 11811245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::7 68657 # Per bank write bursts 11911245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::8 63193 # Per bank write bursts 12011245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::9 66730 # Per bank write bursts 12111245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::10 63431 # Per bank write bursts 12211245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::11 70210 # Per bank write bursts 12311245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::12 65844 # Per bank write bursts 12411245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::13 70148 # Per bank write bursts 12511245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::14 68557 # Per bank write bursts 12611245Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::15 66284 # Per bank write bursts 12710515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811245Sandreas.sandberg@arm.comsystem.physmem.numWrRetry 30 # Number of times write queue was full causing retry 12911245Sandreas.sandberg@arm.comsystem.physmem.totGap 47593740806000 # Total gap between requests 13010515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611245Sandreas.sandberg@arm.comsystem.physmem.readPktSize::6 1263732 # Read request sizes (log2) 13710515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311245Sandreas.sandberg@arm.comsystem.physmem.writePktSize::6 1075989 # Write request sizes (log2) 14411245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::0 1091015 # What read queue length does an incoming req see 14511245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 68737 # What read queue length does an incoming req see 14611245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::2 30330 # What read queue length does an incoming req see 14711245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::3 25975 # What read queue length does an incoming req see 14811245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::4 22184 # What read queue length does an incoming req see 14911245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::5 19490 # What read queue length does an incoming req see 15011245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::6 16927 # What read queue length does an incoming req see 15111245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::7 14904 # What read queue length does an incoming req see 15211245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::8 11891 # What read queue length does an incoming req see 15311245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::9 1868 # What read queue length does an incoming req see 15411245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::10 888 # What read queue length does an incoming req see 15511245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::11 551 # What read queue length does an incoming req see 15611245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::12 438 # What read queue length does an incoming req see 15711245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::13 304 # What read queue length does an incoming req see 15811245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::14 237 # What read queue length does an incoming req see 15911245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::15 204 # What read queue length does an incoming req see 16011245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::16 179 # What read queue length does an incoming req see 16111245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::17 147 # What read queue length does an incoming req see 16211245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see 16311245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see 16411245Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 16511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16810628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::15 18318 # What write queue length does an incoming req see 19211245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::16 20896 # What write queue length does an incoming req see 19311245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::17 46603 # What write queue length does an incoming req see 19411245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::18 53376 # What write queue length does an incoming req see 19511245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::19 57792 # What write queue length does an incoming req see 19611245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::20 60877 # What write queue length does an incoming req see 19711245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::21 64132 # What write queue length does an incoming req see 19811245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::22 65344 # What write queue length does an incoming req see 19911245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::23 67196 # What write queue length does an incoming req see 20011245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::24 67473 # What write queue length does an incoming req see 20111245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::25 69715 # What write queue length does an incoming req see 20211245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::26 73497 # What write queue length does an incoming req see 20311245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::27 68447 # What write queue length does an incoming req see 20411245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::28 68375 # What write queue length does an incoming req see 20511245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::29 71528 # What write queue length does an incoming req see 20611245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::30 66722 # What write queue length does an incoming req see 20711245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::31 63618 # What write queue length does an incoming req see 20811245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::32 62101 # What write queue length does an incoming req see 20911245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::33 1601 # What write queue length does an incoming req see 21011245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::34 1148 # What write queue length does an incoming req see 21111245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::35 781 # What write queue length does an incoming req see 21211245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::36 693 # What write queue length does an incoming req see 21311245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::37 586 # What write queue length does an incoming req see 21411245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::38 407 # What write queue length does an incoming req see 21511245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::39 317 # What write queue length does an incoming req see 21611245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::40 356 # What write queue length does an incoming req see 21711245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see 21811245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::42 373 # What write queue length does an incoming req see 21911245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::43 287 # What write queue length does an incoming req see 22011245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::44 363 # What write queue length does an incoming req see 22111245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::45 225 # What write queue length does an incoming req see 22211245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::46 274 # What write queue length does an incoming req see 22311245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::47 301 # What write queue length does an incoming req see 22411245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::48 271 # What write queue length does an incoming req see 22511245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::49 314 # What write queue length does an incoming req see 22611245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::50 215 # What write queue length does an incoming req see 22711245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see 22811245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::52 195 # What write queue length does an incoming req see 22911245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see 23011245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see 23111245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::55 110 # What write queue length does an incoming req see 23211245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see 23311245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see 23411245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see 23511245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::59 67 # What write queue length does an incoming req see 23611245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::60 71 # What write queue length does an incoming req see 23711245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see 23811245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see 23911245Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see 24011245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 840117 # Bytes accessed per row activation 24111245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 181.511175 # Bytes accessed per row activation 24211245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 111.812729 # Bytes accessed per row activation 24311245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 240.875315 # Bytes accessed per row activation 24411245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::0-127 520248 61.93% 61.93% # Bytes accessed per row activation 24511245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::128-255 156423 18.62% 80.54% # Bytes accessed per row activation 24611245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 51977 6.19% 86.73% # Bytes accessed per row activation 24711245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 27385 3.26% 89.99% # Bytes accessed per row activation 24811245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 18542 2.21% 92.20% # Bytes accessed per row activation 24911245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 11713 1.39% 93.59% # Bytes accessed per row activation 25011245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::768-895 8913 1.06% 94.65% # Bytes accessed per row activation 25111245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::896-1023 8910 1.06% 95.71% # Bytes accessed per row activation 25211245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::1024-1151 36006 4.29% 100.00% # Bytes accessed per row activation 25311245Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 840117 # Bytes accessed per row activation 25411245Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::samples 60330 # Reads before turning the bus around for writes 25511245Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::mean 21.654169 # Reads before turning the bus around for writes 25611245Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::stdev 330.190002 # Reads before turning the bus around for writes 25711245Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::0-4095 60327 100.00% 100.00% # Reads before turning the bus around for writes 25811201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 25910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 26010892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 26111245Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::total 60330 # Reads before turning the bus around for writes 26211245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::samples 60330 # Writes before turning the bus around for reads 26311245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::mean 17.839698 # Writes before turning the bus around for reads 26411245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::gmean 17.269040 # Writes before turning the bus around for reads 26511245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::stdev 7.176072 # Writes before turning the bus around for reads 26611245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::16-19 56620 93.85% 93.85% # Writes before turning the bus around for reads 26711245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::20-23 1546 2.56% 96.41% # Writes before turning the bus around for reads 26811245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::24-27 276 0.46% 96.87% # Writes before turning the bus around for reads 26911245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::28-31 296 0.49% 97.36% # Writes before turning the bus around for reads 27011245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::32-35 110 0.18% 97.54% # Writes before turning the bus around for reads 27111245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::36-39 266 0.44% 97.98% # Writes before turning the bus around for reads 27211245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::40-43 180 0.30% 98.28% # Writes before turning the bus around for reads 27311245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::44-47 98 0.16% 98.45% # Writes before turning the bus around for reads 27411245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::48-51 97 0.16% 98.61% # Writes before turning the bus around for reads 27511245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::52-55 84 0.14% 98.75% # Writes before turning the bus around for reads 27611245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::56-59 48 0.08% 98.82% # Writes before turning the bus around for reads 27711245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::60-63 66 0.11% 98.93% # Writes before turning the bus around for reads 27811245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::64-67 398 0.66% 99.59% # Writes before turning the bus around for reads 27911245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::68-71 43 0.07% 99.67% # Writes before turning the bus around for reads 28011245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::72-75 35 0.06% 99.72% # Writes before turning the bus around for reads 28111245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::76-79 96 0.16% 99.88% # Writes before turning the bus around for reads 28211245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::80-83 19 0.03% 99.91% # Writes before turning the bus around for reads 28311245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads 28411245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::100-103 3 0.00% 99.92% # Writes before turning the bus around for reads 28511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads 28611245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads 28711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads 28811245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads 28911245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads 29011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads 29111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 24 0.04% 99.97% # Writes before turning the bus around for reads 29211245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads 29311245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 29411245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::140-143 3 0.00% 99.98% # Writes before turning the bus around for reads 29511245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::152-155 7 0.01% 99.99% # Writes before turning the bus around for reads 29611245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads 29711245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads 29811245Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::total 60330 # Writes before turning the bus around for reads 29911245Sandreas.sandberg@arm.comsystem.physmem.totQLat 28430560155 # Total ticks spent queuing 30011245Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 52925597655 # Total ticks spent from burst creation until serviced by the DRAM 30111245Sandreas.sandberg@arm.comsystem.physmem.totBusLat 6532010000 # Total ticks spent in databus transfers 30211245Sandreas.sandberg@arm.comsystem.physmem.avgQLat 21762.49 # Average queueing delay per DRAM burst 30310515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30411245Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 40512.49 # Average memory access latency per DRAM burst 30511245Sandreas.sandberg@arm.comsystem.physmem.avgRdBW 1.76 # Average DRAM read bandwidth in MiByte/s 30611201Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s 30711245Sandreas.sandberg@arm.comsystem.physmem.avgRdBWSys 1.70 # Average system read bandwidth in MiByte/s 30811201Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s 30910515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31010827Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31111201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 31210892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31311201Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing 31411245Sandreas.sandberg@arm.comsystem.physmem.avgWrQLen 26.65 # Average write queue length when enqueuing 31511245Sandreas.sandberg@arm.comsystem.physmem.readRowHits 1047491 # Number of row buffer hits during reads 31611245Sandreas.sandberg@arm.comsystem.physmem.writeRowHits 495062 # Number of row buffer hits during writes 31711245Sandreas.sandberg@arm.comsystem.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads 31811245Sandreas.sandberg@arm.comsystem.physmem.writeRowHitRate 46.00 # Row buffer hit rate for writes 31911245Sandreas.sandberg@arm.comsystem.physmem.avgGap 19951096.95 # Average gap between requests 32011245Sandreas.sandberg@arm.comsystem.physmem.pageHitRate 64.74 # Row buffer hit rate, read and write combined 32111245Sandreas.sandberg@arm.comsystem.physmem_0.actEnergy 3221134560 # Energy for activate commands per rank (pJ) 32211245Sandreas.sandberg@arm.comsystem.physmem_0.preEnergy 1757563500 # Energy for precharge commands per rank (pJ) 32311245Sandreas.sandberg@arm.comsystem.physmem_0.readEnergy 5005283400 # Energy for read commands per rank (pJ) 32411245Sandreas.sandberg@arm.comsystem.physmem_0.writeEnergy 3511330560 # Energy for write commands per rank (pJ) 32511245Sandreas.sandberg@arm.comsystem.physmem_0.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ) 32611245Sandreas.sandberg@arm.comsystem.physmem_0.actBackEnergy 1216360497735 # Energy for active background per rank (pJ) 32711245Sandreas.sandberg@arm.comsystem.physmem_0.preBackEnergy 27489261984750 # Energy for precharge background per rank (pJ) 32811245Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 31827709611225 # Total energy per rank (pJ) 32911245Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 668.737288 # Core power per rank (mW) 33011245Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 45730304477620 # Time in different power states 33111245Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::REF 1589259620000 # Time in different power states 33210628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33311245Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::ACT 274179379380 # Time in different power states 33410628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 33511245Sandreas.sandberg@arm.comsystem.physmem_1.actEnergy 3130149960 # Energy for activate commands per rank (pJ) 33611245Sandreas.sandberg@arm.comsystem.physmem_1.preEnergy 1707919125 # Energy for precharge commands per rank (pJ) 33711245Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 5184613200 # Energy for read commands per rank (pJ) 33811245Sandreas.sandberg@arm.comsystem.physmem_1.writeEnergy 3462892560 # Energy for write commands per rank (pJ) 33911245Sandreas.sandberg@arm.comsystem.physmem_1.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ) 34011245Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 1215861151230 # Energy for active background per rank (pJ) 34111245Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 27489700008000 # Energy for precharge background per rank (pJ) 34211245Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 31827638550795 # Total energy per rank (pJ) 34311245Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 668.735795 # Core power per rank (mW) 34411245Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 45731003279682 # Time in different power states 34511245Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::REF 1589259620000 # Time in different power states 34610628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 34711245Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 273478576568 # Time in different power states 34810628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 34910515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 35010515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35110515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 35210515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35310515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 35410515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 35510515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 35610515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 35710515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 35810515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 35910515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 36010515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36110515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 36210515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 36310515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36410515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 36510515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 36610515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 36710515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 36810515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 36910515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 37010515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 37110515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37210515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37410515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 37510535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 37610535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 37710535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 37811245Sandreas.sandberg@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 37911245Sandreas.sandberg@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38011245Sandreas.sandberg@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38110515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 38210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41111245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walks 93408 # Table walker walks requested 41211245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksLong 93408 # Table walker walks initiated with long descriptors 41311245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7983 # Level at which table walker walks with long descriptors terminate 41411245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 70276 # Level at which table walker walks with long descriptors terminate 41511245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting 41611245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 93401 # Table walker wait (enqueue to first request) latency 41711245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.278370 # Table walker wait (enqueue to first request) latency 41811245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 85.074143 # Table walker wait (enqueue to first request) latency 41911245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-2047 93400 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 42111245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 93401 # Table walker wait (enqueue to first request) latency 42211245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 78266 # Table walker service (enqueue to completion) latency 42311245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 22499.341988 # Table walker service (enqueue to completion) latency 42411245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 20923.382111 # Table walker service (enqueue to completion) latency 42511245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 16650.912887 # Table walker service (enqueue to completion) latency 42611245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 77590 99.14% 99.14% # Table walker service (enqueue to completion) latency 42711245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 164 0.21% 99.35% # Table walker service (enqueue to completion) latency 42811245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 417 0.53% 99.88% # Table walker service (enqueue to completion) latency 42911245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.91% # Table walker service (enqueue to completion) latency 43011245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 25 0.03% 99.94% # Table walker service (enqueue to completion) latency 43111245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.95% # Table walker service (enqueue to completion) latency 43211245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.04% 99.99% # Table walker service (enqueue to completion) latency 43311245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 43411245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 43511245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 78266 # Table walker service (enqueue to completion) latency 43611245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::samples 5219685476 # Table walker pending requests distribution 43711245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::mean 0.596746 # Table walker pending requests distribution 43811245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::stdev 0.490551 # Table walker pending requests distribution 43911245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::0 2104860204 40.33% 40.33% # Table walker pending requests distribution 44011245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::1 3114825272 59.67% 100.00% # Table walker pending requests distribution 44111245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walksPending::total 5219685476 # Table walker pending requests distribution 44211245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 70276 89.80% 89.80% # Table walker page sizes translated 44311245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 7983 10.20% 100.00% # Table walker page sizes translated 44411245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 78259 # Table walker page sizes translated 44511245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 93408 # Table walker requests started/completed, data/inst 44610628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44711245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 93408 # Table walker requests started/completed, data/inst 44811245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78259 # Table walker requests started/completed, data/inst 44910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45011245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78259 # Table walker requests started/completed, data/inst 45111245Sandreas.sandberg@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 171667 # Table walker requests started/completed, data/inst 45210535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 45310535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 45411245Sandreas.sandberg@arm.comsystem.cpu0.dtb.read_hits 80327529 # DTB read hits 45511245Sandreas.sandberg@arm.comsystem.cpu0.dtb.read_misses 69973 # DTB read misses 45611245Sandreas.sandberg@arm.comsystem.cpu0.dtb.write_hits 72902451 # DTB write hits 45711245Sandreas.sandberg@arm.comsystem.cpu0.dtb.write_misses 23435 # DTB write misses 45810535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 45910535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46011245Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID 46111245Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID 46211245Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_entries 34709 # Number of entries that have been flushed from TLB 46310535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 46411245Sandreas.sandberg@arm.comsystem.cpu0.dtb.prefetch_faults 4393 # Number of TLB faults due to prefetch 46510535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 46611245Sandreas.sandberg@arm.comsystem.cpu0.dtb.perms_faults 8867 # Number of TLB faults due to permissions restrictions 46711245Sandreas.sandberg@arm.comsystem.cpu0.dtb.read_accesses 80397502 # DTB read accesses 46811245Sandreas.sandberg@arm.comsystem.cpu0.dtb.write_accesses 72925886 # DTB write accesses 46910535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47011245Sandreas.sandberg@arm.comsystem.cpu0.dtb.hits 153229980 # DTB hits 47111245Sandreas.sandberg@arm.comsystem.cpu0.dtb.misses 93408 # DTB misses 47211245Sandreas.sandberg@arm.comsystem.cpu0.dtb.accesses 153323388 # DTB accesses 47310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 47410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 47910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 48310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 48410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 48610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 48910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 49210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 49310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 49410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 49510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 49610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 49710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 49810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 49910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 50211245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walks 52417 # Table walker walks requested 50311245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walksLong 52417 # Table walker walks initiated with long descriptors 50411245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 598 # Level at which table walker walks with long descriptors terminate 50511245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 46386 # Level at which table walker walks with long descriptors terminate 50611245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 52417 # Table walker wait (enqueue to first request) latency 50711245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 52417 100.00% 100.00% # Table walker wait (enqueue to first request) latency 50811245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 52417 # Table walker wait (enqueue to first request) latency 50911245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 46984 # Table walker service (enqueue to completion) latency 51011245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 25232.568534 # Table walker service (enqueue to completion) latency 51111245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 22985.913240 # Table walker service (enqueue to completion) latency 51211245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 21269.412068 # Table walker service (enqueue to completion) latency 51311245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 46328 98.60% 98.60% # Table walker service (enqueue to completion) latency 51411245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.09% 98.69% # Table walker service (enqueue to completion) latency 51511245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 530 1.13% 99.82% # Table walker service (enqueue to completion) latency 51611245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 16 0.03% 99.85% # Table walker service (enqueue to completion) latency 51711245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 24 0.05% 99.90% # Table walker service (enqueue to completion) latency 51811245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.04% 99.94% # Table walker service (enqueue to completion) latency 51911245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 22 0.05% 99.99% # Table walker service (enqueue to completion) latency 52011245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 52111245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 52211245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 52311245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 46984 # Table walker service (enqueue to completion) latency 52411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution 52511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution 52611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution 52711245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 46386 98.73% 98.73% # Table walker page sizes translated 52811245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 598 1.27% 100.00% # Table walker page sizes translated 52911245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 46984 # Table walker page sizes translated 53010628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 53111245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52417 # Table walker requests started/completed, data/inst 53211245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 52417 # Table walker requests started/completed, data/inst 53310628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 53411245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 46984 # Table walker requests started/completed, data/inst 53511245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 46984 # Table walker requests started/completed, data/inst 53611245Sandreas.sandberg@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 99401 # Table walker requests started/completed, data/inst 53711245Sandreas.sandberg@arm.comsystem.cpu0.itb.inst_hits 426699171 # ITB inst hits 53811245Sandreas.sandberg@arm.comsystem.cpu0.itb.inst_misses 52417 # ITB inst misses 53910535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 54010535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 54110535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 54210535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 54310535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 54410535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 54511245Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID 54611245Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID 54711245Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_entries 24801 # Number of entries that have been flushed from TLB 54810535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 54910535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55010535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 55110535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 55210535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 55310535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 55411245Sandreas.sandberg@arm.comsystem.cpu0.itb.inst_accesses 426751588 # ITB inst accesses 55511245Sandreas.sandberg@arm.comsystem.cpu0.itb.hits 426699171 # DTB hits 55611245Sandreas.sandberg@arm.comsystem.cpu0.itb.misses 52417 # DTB misses 55711245Sandreas.sandberg@arm.comsystem.cpu0.itb.accesses 426751588 # DTB accesses 55811245Sandreas.sandberg@arm.comsystem.cpu0.numCycles 95186924479 # number of cpu cycles simulated 55910535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 56010535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 56111167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 56211245Sandreas.sandberg@arm.comsystem.cpu0.kern.inst.quiesce 4674 # number of quiesce instructions executed 56311245Sandreas.sandberg@arm.comsystem.cpu0.committedInsts 426454163 # Number of instructions committed 56411245Sandreas.sandberg@arm.comsystem.cpu0.committedOps 501120280 # Number of ops (including micro ops) committed 56511245Sandreas.sandberg@arm.comsystem.cpu0.num_int_alu_accesses 460758133 # Number of integer alu accesses 56611245Sandreas.sandberg@arm.comsystem.cpu0.num_fp_alu_accesses 395268 # Number of float alu accesses 56711245Sandreas.sandberg@arm.comsystem.cpu0.num_func_calls 25675920 # number of times a function call or return occured 56811245Sandreas.sandberg@arm.comsystem.cpu0.num_conditional_control_insts 64224693 # number of instructions that are conditional controls 56911245Sandreas.sandberg@arm.comsystem.cpu0.num_int_insts 460758133 # number of integer instructions 57011245Sandreas.sandberg@arm.comsystem.cpu0.num_fp_insts 395268 # number of float instructions 57111245Sandreas.sandberg@arm.comsystem.cpu0.num_int_register_reads 666544840 # number of times the integer registers were read 57211245Sandreas.sandberg@arm.comsystem.cpu0.num_int_register_writes 365452769 # number of times the integer registers were written 57311245Sandreas.sandberg@arm.comsystem.cpu0.num_fp_register_reads 661868 # number of times the floating registers were read 57411245Sandreas.sandberg@arm.comsystem.cpu0.num_fp_register_writes 282064 # number of times the floating registers were written 57511245Sandreas.sandberg@arm.comsystem.cpu0.num_cc_register_reads 110079606 # number of times the CC registers were read 57611245Sandreas.sandberg@arm.comsystem.cpu0.num_cc_register_writes 109774743 # number of times the CC registers were written 57711245Sandreas.sandberg@arm.comsystem.cpu0.num_mem_refs 153223313 # number of memory refs 57811245Sandreas.sandberg@arm.comsystem.cpu0.num_load_insts 80324545 # Number of load instructions 57911245Sandreas.sandberg@arm.comsystem.cpu0.num_store_insts 72898768 # Number of store instructions 58011245Sandreas.sandberg@arm.comsystem.cpu0.num_idle_cycles 94023627088.560516 # Number of idle cycles 58111245Sandreas.sandberg@arm.comsystem.cpu0.num_busy_cycles 1163297390.439485 # Number of busy cycles 58211245Sandreas.sandberg@arm.comsystem.cpu0.not_idle_fraction 0.012221 # Percentage of non-idle cycles 58311245Sandreas.sandberg@arm.comsystem.cpu0.idle_fraction 0.987779 # Percentage of idle cycles 58411245Sandreas.sandberg@arm.comsystem.cpu0.Branches 94888903 # Number of branches fetched 58511201Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 58611245Sandreas.sandberg@arm.comsystem.cpu0.op_class::IntAlu 346960051 69.20% 69.20% # Class of executed instruction 58711245Sandreas.sandberg@arm.comsystem.cpu0.op_class::IntMult 1125201 0.22% 69.42% # Class of executed instruction 58811245Sandreas.sandberg@arm.comsystem.cpu0.op_class::IntDiv 62694 0.01% 69.43% # Class of executed instruction 58911201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction 59011201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction 59111201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction 59211201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction 59311201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction 59411201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction 59511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction 59611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction 59711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction 59811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction 59911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction 60011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction 60111201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction 60211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction 60311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction 60411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction 60511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction 60611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction 60711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction 60811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction 60911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction 61011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction 61111245Sandreas.sandberg@arm.comsystem.cpu0.op_class::SimdFloatMisc 37154 0.01% 69.44% # Class of executed instruction 61211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction 61311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction 61411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction 61511245Sandreas.sandberg@arm.comsystem.cpu0.op_class::MemRead 80324545 16.02% 85.46% # Class of executed instruction 61611245Sandreas.sandberg@arm.comsystem.cpu0.op_class::MemWrite 72898768 14.54% 100.00% # Class of executed instruction 61710535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 61810535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 61911245Sandreas.sandberg@arm.comsystem.cpu0.op_class::total 501408413 # Class of executed instruction 62011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.replacements 5237512 # number of replacements 62111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tagsinuse 505.877232 # Cycle average of tags in use 62211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.total_refs 147745204 # Total number of references to valid blocks. 62311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.sampled_refs 5237891 # Sample count of references to valid blocks. 62411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.avg_refs 28.207002 # Average number of references to valid blocks. 62511201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. 62611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 505.877232 # Average occupied blocks per requestor 62711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988041 # Average percentage of cache occupancy 62811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988041 # Average percentage of cache occupancy 62911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 379 # Occupied blocks per task id 63011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 370 # Occupied blocks per task id 63111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 63211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.740234 # Percentage of cache occupancy per task id 63311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.tag_accesses 311719457 # Number of tag accesses 63411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.tags.data_accesses 311719457 # Number of data accesses 63511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 74802484 # number of ReadReq hits 63611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_hits::total 74802484 # number of ReadReq hits 63711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 68840975 # number of WriteReq hits 63811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::total 68840975 # number of WriteReq hits 63911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 186514 # number of SoftPFReq hits 64011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 186514 # number of SoftPFReq hits 64111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 133741 # number of WriteLineReq hits 64211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 133741 # number of WriteLineReq hits 64311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1712983 # number of LoadLockedReq hits 64411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1712983 # number of LoadLockedReq hits 64511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1673957 # number of StoreCondReq hits 64611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1673957 # number of StoreCondReq hits 64711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 143643459 # number of demand (read+write) hits 64811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::total 143643459 # number of demand (read+write) hits 64911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 143829973 # number of overall hits 65011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::total 143829973 # number of overall hits 65111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 2859232 # number of ReadReq misses 65211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_misses::total 2859232 # number of ReadReq misses 65311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1316810 # number of WriteReq misses 65411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1316810 # number of WriteReq misses 65511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 596453 # number of SoftPFReq misses 65611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 596453 # number of SoftPFReq misses 65711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 721743 # number of WriteLineReq misses 65811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 721743 # number of WriteLineReq misses 65911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153137 # number of LoadLockedReq misses 66011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 153137 # number of LoadLockedReq misses 66111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 190741 # number of StoreCondReq misses 66211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 190741 # number of StoreCondReq misses 66311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4176042 # number of demand (read+write) misses 66411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::total 4176042 # number of demand (read+write) misses 66511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 4772495 # number of overall misses 66611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::total 4772495 # number of overall misses 66711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45650819500 # number of ReadReq miss cycles 66811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 45650819500 # number of ReadReq miss cycles 66911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34330450500 # number of WriteReq miss cycles 67011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 34330450500 # number of WriteReq miss cycles 67111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65187396500 # number of WriteLineReq miss cycles 67211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 65187396500 # number of WriteLineReq miss cycles 67311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2390631500 # number of LoadLockedReq miss cycles 67411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2390631500 # number of LoadLockedReq miss cycles 67511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5489081000 # number of StoreCondReq miss cycles 67611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 5489081000 # number of StoreCondReq miss cycles 67711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7149000 # number of StoreCondFailReq miss cycles 67811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 7149000 # number of StoreCondFailReq miss cycles 67911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 79981270000 # number of demand (read+write) miss cycles 68011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_latency::total 79981270000 # number of demand (read+write) miss cycles 68111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 79981270000 # number of overall miss cycles 68211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_latency::total 79981270000 # number of overall miss cycles 68311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 77661716 # number of ReadReq accesses(hits+misses) 68411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 77661716 # number of ReadReq accesses(hits+misses) 68511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 70157785 # number of WriteReq accesses(hits+misses) 68611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 70157785 # number of WriteReq accesses(hits+misses) 68711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 782967 # number of SoftPFReq accesses(hits+misses) 68811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 782967 # number of SoftPFReq accesses(hits+misses) 68911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 855484 # number of WriteLineReq accesses(hits+misses) 69011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 855484 # number of WriteLineReq accesses(hits+misses) 69111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1866120 # number of LoadLockedReq accesses(hits+misses) 69211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1866120 # number of LoadLockedReq accesses(hits+misses) 69311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1864698 # number of StoreCondReq accesses(hits+misses) 69411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1864698 # number of StoreCondReq accesses(hits+misses) 69511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 147819501 # number of demand (read+write) accesses 69611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_accesses::total 147819501 # number of demand (read+write) accesses 69711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 148602468 # number of overall (read+write) accesses 69811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_accesses::total 148602468 # number of overall (read+write) accesses 69911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036816 # miss rate for ReadReq accesses 70011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036816 # miss rate for ReadReq accesses 70111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018769 # miss rate for WriteReq accesses 70211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018769 # miss rate for WriteReq accesses 70311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761786 # miss rate for SoftPFReq accesses 70411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.761786 # miss rate for SoftPFReq accesses 70511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843666 # miss rate for WriteLineReq accesses 70611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.843666 # miss rate for WriteLineReq accesses 70711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.082062 # miss rate for LoadLockedReq accesses 70811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.082062 # miss rate for LoadLockedReq accesses 70911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102291 # miss rate for StoreCondReq accesses 71011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.102291 # miss rate for StoreCondReq accesses 71111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.028251 # miss rate for demand accesses 71211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.028251 # miss rate for demand accesses 71311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032116 # miss rate for overall accesses 71411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032116 # miss rate for overall accesses 71511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15966.112404 # average ReadReq miss latency 71611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 15966.112404 # average ReadReq miss latency 71711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26070.921773 # average WriteReq miss latency 71811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 26070.921773 # average WriteReq miss latency 71911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90319.402474 # average WriteLineReq miss latency 72011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90319.402474 # average WriteLineReq miss latency 72111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15611.063949 # average LoadLockedReq miss latency 72211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15611.063949 # average LoadLockedReq miss latency 72311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28777.667098 # average StoreCondReq miss latency 72411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28777.667098 # average StoreCondReq miss latency 72510535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 72610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 72711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19152.410345 # average overall miss latency 72811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19152.410345 # average overall miss latency 72911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16758.795976 # average overall miss latency 73011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 16758.795976 # average overall miss latency 73110535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 73210535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 73310535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 73410535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 73510535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 73610535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 73710585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 73810535SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 73911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::writebacks 5237512 # number of writebacks 74011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.writebacks::total 5237512 # number of writebacks 74111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25341 # number of ReadReq MSHR hits 74211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 25341 # number of ReadReq MSHR hits 74311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21295 # number of WriteReq MSHR hits 74411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21295 # number of WriteReq MSHR hits 74511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39838 # number of LoadLockedReq MSHR hits 74611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 39838 # number of LoadLockedReq MSHR hits 74711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 46636 # number of demand (read+write) MSHR hits 74811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 46636 # number of demand (read+write) MSHR hits 74911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 46636 # number of overall MSHR hits 75011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 46636 # number of overall MSHR hits 75111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2833891 # number of ReadReq MSHR misses 75211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2833891 # number of ReadReq MSHR misses 75311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1295515 # number of WriteReq MSHR misses 75411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1295515 # number of WriteReq MSHR misses 75511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 595169 # number of SoftPFReq MSHR misses 75611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 595169 # number of SoftPFReq MSHR misses 75711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 721743 # number of WriteLineReq MSHR misses 75811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 721743 # number of WriteLineReq MSHR misses 75911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113299 # number of LoadLockedReq MSHR misses 76011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 113299 # number of LoadLockedReq MSHR misses 76111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190741 # number of StoreCondReq MSHR misses 76211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 190741 # number of StoreCondReq MSHR misses 76311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4129406 # number of demand (read+write) MSHR misses 76411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4129406 # number of demand (read+write) MSHR misses 76511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 4724575 # number of overall MSHR misses 76611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 4724575 # number of overall MSHR misses 76711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16746 # number of ReadReq MSHR uncacheable 76811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 16746 # number of ReadReq MSHR uncacheable 76911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17968 # number of WriteReq MSHR uncacheable 77011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 17968 # number of WriteReq MSHR uncacheable 77111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34714 # number of overall MSHR uncacheable misses 77211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 34714 # number of overall MSHR uncacheable misses 77311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41050881000 # number of ReadReq MSHR miss cycles 77411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 41050881000 # number of ReadReq MSHR miss cycles 77511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32444395000 # number of WriteReq MSHR miss cycles 77611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 32444395000 # number of WriteReq MSHR miss cycles 77711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14818032000 # number of SoftPFReq MSHR miss cycles 77811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14818032000 # number of SoftPFReq MSHR miss cycles 77911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 64465653500 # number of WriteLineReq MSHR miss cycles 78011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64465653500 # number of WriteLineReq MSHR miss cycles 78111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564895500 # number of LoadLockedReq MSHR miss cycles 78211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564895500 # number of LoadLockedReq MSHR miss cycles 78311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5298419000 # number of StoreCondReq MSHR miss cycles 78411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5298419000 # number of StoreCondReq MSHR miss cycles 78511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7070000 # number of StoreCondFailReq MSHR miss cycles 78611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7070000 # number of StoreCondFailReq MSHR miss cycles 78711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73495276000 # number of demand (read+write) MSHR miss cycles 78811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 73495276000 # number of demand (read+write) MSHR miss cycles 78911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 88313308000 # number of overall MSHR miss cycles 79011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 88313308000 # number of overall MSHR miss cycles 79111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897717500 # number of ReadReq MSHR uncacheable cycles 79211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897717500 # number of ReadReq MSHR uncacheable cycles 79311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3102799000 # number of WriteReq MSHR uncacheable cycles 79411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3102799000 # number of WriteReq MSHR uncacheable cycles 79511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6000516500 # number of overall MSHR uncacheable cycles 79611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 6000516500 # number of overall MSHR uncacheable cycles 79711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036490 # mshr miss rate for ReadReq accesses 79811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036490 # mshr miss rate for ReadReq accesses 79911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018466 # mshr miss rate for WriteReq accesses 80011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses 80111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.760146 # mshr miss rate for SoftPFReq accesses 80211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760146 # mshr miss rate for SoftPFReq accesses 80311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.843666 # mshr miss rate for WriteLineReq accesses 80411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.843666 # mshr miss rate for WriteLineReq accesses 80511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060714 # mshr miss rate for LoadLockedReq accesses 80611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060714 # mshr miss rate for LoadLockedReq accesses 80711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102291 # mshr miss rate for StoreCondReq accesses 80811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102291 # mshr miss rate for StoreCondReq accesses 80911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027935 # mshr miss rate for demand accesses 81011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.027935 # mshr miss rate for demand accesses 81111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031793 # mshr miss rate for overall accesses 81211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031793 # mshr miss rate for overall accesses 81311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14485.695110 # average ReadReq mshr miss latency 81411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14485.695110 # average ReadReq mshr miss latency 81511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25043.627438 # average WriteReq mshr miss latency 81611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25043.627438 # average WriteReq mshr miss latency 81711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24897.183825 # average SoftPFReq mshr miss latency 81811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24897.183825 # average SoftPFReq mshr miss latency 81911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89319.402474 # average WriteLineReq mshr miss latency 82011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89319.402474 # average WriteLineReq mshr miss latency 82111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13812.085720 # average LoadLockedReq mshr miss latency 82211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.085720 # average LoadLockedReq mshr miss latency 82311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27778.081273 # average StoreCondReq mshr miss latency 82411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27778.081273 # average StoreCondReq mshr miss latency 82510535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 82610535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 82711245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17798.026157 # average overall mshr miss latency 82811245Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 17798.026157 # average overall mshr miss latency 82911245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18692.328516 # average overall mshr miss latency 83011245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18692.328516 # average overall mshr miss latency 83111245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173039.382539 # average ReadReq mshr uncacheable latency 83211245Sandreas.sandberg@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173039.382539 # average ReadReq mshr uncacheable latency 83311245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172684.717275 # average WriteReq mshr uncacheable latency 83411245Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172684.717275 # average WriteReq mshr uncacheable latency 83511245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172855.807455 # average overall mshr uncacheable latency 83611245Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172855.807455 # average overall mshr uncacheable latency 83710535SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 83811245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.replacements 4772370 # number of replacements 83911245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tagsinuse 511.827216 # Cycle average of tags in use 84011245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.total_refs 421926289 # Total number of references to valid blocks. 84111245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.sampled_refs 4772882 # Sample count of references to valid blocks. 84211245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.avg_refs 88.400738 # Average number of references to valid blocks. 84311201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 59167640000 # Cycle when the warmup percentage was hit. 84411245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827216 # Average occupied blocks per requestor 84511201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999663 # Average percentage of cache occupancy 84611201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy 84710535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 84811245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 395 # Occupied blocks per task id 84911245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 117 # Occupied blocks per task id 85010535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 85111245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.tag_accesses 858171224 # Number of tag accesses 85211245Sandreas.sandberg@arm.comsystem.cpu0.icache.tags.data_accesses 858171224 # Number of data accesses 85311245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 421926289 # number of ReadReq hits 85411245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_hits::total 421926289 # number of ReadReq hits 85511245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 421926289 # number of demand (read+write) hits 85611245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_hits::total 421926289 # number of demand (read+write) hits 85711245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 421926289 # number of overall hits 85811245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_hits::total 421926289 # number of overall hits 85911245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 4772882 # number of ReadReq misses 86011245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_misses::total 4772882 # number of ReadReq misses 86111245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 4772882 # number of demand (read+write) misses 86211245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_misses::total 4772882 # number of demand (read+write) misses 86311245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 4772882 # number of overall misses 86411245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_misses::total 4772882 # number of overall misses 86511245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52975952000 # number of ReadReq miss cycles 86611245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 52975952000 # number of ReadReq miss cycles 86711245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 52975952000 # number of demand (read+write) miss cycles 86811245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_latency::total 52975952000 # number of demand (read+write) miss cycles 86911245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 52975952000 # number of overall miss cycles 87011245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_latency::total 52975952000 # number of overall miss cycles 87111245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 426699171 # number of ReadReq accesses(hits+misses) 87211245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_accesses::total 426699171 # number of ReadReq accesses(hits+misses) 87311245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 426699171 # number of demand (read+write) accesses 87411245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_accesses::total 426699171 # number of demand (read+write) accesses 87511245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 426699171 # number of overall (read+write) accesses 87611245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_accesses::total 426699171 # number of overall (read+write) accesses 87711245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011186 # miss rate for ReadReq accesses 87811245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011186 # miss rate for ReadReq accesses 87911245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011186 # miss rate for demand accesses 88011245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011186 # miss rate for demand accesses 88111245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011186 # miss rate for overall accesses 88211245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011186 # miss rate for overall accesses 88311245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11099.363445 # average ReadReq miss latency 88411245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 11099.363445 # average ReadReq miss latency 88511245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency 88611245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 11099.363445 # average overall miss latency 88711245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency 88811245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 11099.363445 # average overall miss latency 88910535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89010535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89110535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89210535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 89310535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 89410535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 89510535SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 89610535SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 89711245Sandreas.sandberg@arm.comsystem.cpu0.icache.writebacks::writebacks 4772370 # number of writebacks 89811245Sandreas.sandberg@arm.comsystem.cpu0.icache.writebacks::total 4772370 # number of writebacks 89911245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4772882 # number of ReadReq MSHR misses 90011245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 4772882 # number of ReadReq MSHR misses 90111245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 4772882 # number of demand (read+write) MSHR misses 90211245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_misses::total 4772882 # number of demand (read+write) MSHR misses 90311245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 4772882 # number of overall MSHR misses 90411245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_misses::total 4772882 # number of overall MSHR misses 90510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 90610827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 90710827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 90810827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 90911245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 50589511000 # number of ReadReq MSHR miss cycles 91011245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 50589511000 # number of ReadReq MSHR miss cycles 91111245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 50589511000 # number of demand (read+write) MSHR miss cycles 91211245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 50589511000 # number of demand (read+write) MSHR miss cycles 91311245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 50589511000 # number of overall MSHR miss cycles 91411245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 50589511000 # number of overall MSHR miss cycles 91511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles 91611201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles 91711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles 91811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles 91911245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for ReadReq accesses 92011245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011186 # mshr miss rate for ReadReq accesses 92111245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for demand accesses 92211245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.011186 # mshr miss rate for demand accesses 92311245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for overall accesses 92411245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.011186 # mshr miss rate for overall accesses 92511245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average ReadReq mshr miss latency 92611245Sandreas.sandberg@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.363445 # average ReadReq mshr miss latency 92711245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency 92811245Sandreas.sandberg@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency 92911245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency 93011245Sandreas.sandberg@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency 93111201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency 93211201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency 93311201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency 93411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency 93510535SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 93611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7230591 # number of hwpf issued 93711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7230639 # number of prefetch candidates identified 93811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue 93910628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 94010628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 94111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 940745 # number of prefetches not generated due to page crossing 94211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.replacements 2188465 # number of replacements 94311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16163.582102 # Cycle average of tags in use 94411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.total_refs 14109503 # Total number of references to valid blocks. 94511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2203636 # Sample count of references to valid blocks. 94611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.avg_refs 6.402828 # Average number of references to valid blocks. 94711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 8764179000 # Cycle when the warmup percentage was hit. 94811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15163.258465 # Average occupied blocks per requestor 94911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.967950 # Average occupied blocks per requestor 95011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 74.840251 # Average occupied blocks per requestor 95111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 875.515436 # Average occupied blocks per requestor 95211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.925492 # Average percentage of cache occupancy 95311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003050 # Average percentage of cache occupancy 95411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004568 # Average percentage of cache occupancy 95511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053437 # Average percentage of cache occupancy 95611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.986547 # Average percentage of cache occupancy 95711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1542 # Occupied blocks per task id 95811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 95911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 13561 # Occupied blocks per task id 96011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 58 # Occupied blocks per task id 96111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 726 # Occupied blocks per task id 96211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 758 # Occupied blocks per task id 96311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 36 # Occupied blocks per task id 96411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id 96511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 590 # Occupied blocks per task id 96611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6261 # Occupied blocks per task id 96711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 6710 # Occupied blocks per task id 96811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.094116 # Percentage of cache occupancy per task id 96911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 97011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.827698 # Percentage of cache occupancy per task id 97111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tag_accesses 339677714 # Number of tag accesses 97211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.data_accesses 339677714 # Number of data accesses 97311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 214201 # number of ReadReq hits 97411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 132495 # number of ReadReq hits 97511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 346696 # number of ReadReq hits 97611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3462500 # number of WritebackDirty hits 97711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3462500 # number of WritebackDirty hits 97811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 6546722 # number of WritebackClean hits 97911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 6546722 # number of WritebackClean hits 98011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 323 # number of UpgradeReq hits 98111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 323 # number of UpgradeReq hits 98211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 835467 # number of ReadExReq hits 98311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 835467 # number of ReadExReq hits 98411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4337083 # number of ReadCleanReq hits 98511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4337083 # number of ReadCleanReq hits 98611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2670834 # number of ReadSharedReq hits 98711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2670834 # number of ReadSharedReq hits 98811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 164201 # number of InvalidateReq hits 98911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 164201 # number of InvalidateReq hits 99011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 214201 # number of demand (read+write) hits 99111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 132495 # number of demand (read+write) hits 99211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4337083 # number of demand (read+write) hits 99311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3506301 # number of demand (read+write) hits 99411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::total 8190080 # number of demand (read+write) hits 99511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 214201 # number of overall hits 99611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 132495 # number of overall hits 99711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4337083 # number of overall hits 99811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3506301 # number of overall hits 99911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::total 8190080 # number of overall hits 100011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9167 # number of ReadReq misses 100111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7221 # number of ReadReq misses 100211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 16388 # number of ReadReq misses 100311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 234409 # number of UpgradeReq misses 100411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 234409 # number of UpgradeReq misses 100511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190710 # number of SCUpgradeReq misses 100611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 190710 # number of SCUpgradeReq misses 100711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 31 # number of SCUpgradeFailReq misses 100811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 31 # number of SCUpgradeFailReq misses 100911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 244449 # number of ReadExReq misses 101011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 244449 # number of ReadExReq misses 101111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 435799 # number of ReadCleanReq misses 101211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 435799 # number of ReadCleanReq misses 101311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 871525 # number of ReadSharedReq misses 101411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 871525 # number of ReadSharedReq misses 101511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 555346 # number of InvalidateReq misses 101611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 555346 # number of InvalidateReq misses 101711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9167 # number of demand (read+write) misses 101811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 7221 # number of demand (read+write) misses 101911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 435799 # number of demand (read+write) misses 102011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1115974 # number of demand (read+write) misses 102111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::total 1568161 # number of demand (read+write) misses 102211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9167 # number of overall misses 102311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 7221 # number of overall misses 102411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 435799 # number of overall misses 102511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1115974 # number of overall misses 102611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::total 1568161 # number of overall misses 102711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 351604000 # number of ReadReq miss cycles 102811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 298997000 # number of ReadReq miss cycles 102911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 650601000 # number of ReadReq miss cycles 103011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3324963500 # number of UpgradeReq miss cycles 103111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 3324963500 # number of UpgradeReq miss cycles 103211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1970779500 # number of SCUpgradeReq miss cycles 103311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1970779500 # number of SCUpgradeReq miss cycles 103411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 6951500 # number of SCUpgradeFailReq miss cycles 103511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 6951500 # number of SCUpgradeFailReq miss cycles 103611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15779075998 # number of ReadExReq miss cycles 103711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 15779075998 # number of ReadExReq miss cycles 103811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17377629000 # number of ReadCleanReq miss cycles 103911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 17377629000 # number of ReadCleanReq miss cycles 104011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 34720917000 # number of ReadSharedReq miss cycles 104111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 34720917000 # number of ReadSharedReq miss cycles 104211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62263259000 # number of InvalidateReq miss cycles 104311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 62263259000 # number of InvalidateReq miss cycles 104411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 351604000 # number of demand (read+write) miss cycles 104511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 298997000 # number of demand (read+write) miss cycles 104611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 17377629000 # number of demand (read+write) miss cycles 104711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 50499992998 # number of demand (read+write) miss cycles 104811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 68528222998 # number of demand (read+write) miss cycles 104911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 351604000 # number of overall miss cycles 105011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 298997000 # number of overall miss cycles 105111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 17377629000 # number of overall miss cycles 105211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 50499992998 # number of overall miss cycles 105311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 68528222998 # number of overall miss cycles 105411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 223368 # number of ReadReq accesses(hits+misses) 105511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 139716 # number of ReadReq accesses(hits+misses) 105611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 363084 # number of ReadReq accesses(hits+misses) 105711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3462500 # number of WritebackDirty accesses(hits+misses) 105811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3462500 # number of WritebackDirty accesses(hits+misses) 105911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 6546722 # number of WritebackClean accesses(hits+misses) 106011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 6546722 # number of WritebackClean accesses(hits+misses) 106111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 234732 # number of UpgradeReq accesses(hits+misses) 106211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 234732 # number of UpgradeReq accesses(hits+misses) 106311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190710 # number of SCUpgradeReq accesses(hits+misses) 106411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 190710 # number of SCUpgradeReq accesses(hits+misses) 106511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 31 # number of SCUpgradeFailReq accesses(hits+misses) 106611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 31 # number of SCUpgradeFailReq accesses(hits+misses) 106711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1079916 # number of ReadExReq accesses(hits+misses) 106811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1079916 # number of ReadExReq accesses(hits+misses) 106911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4772882 # number of ReadCleanReq accesses(hits+misses) 107011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 4772882 # number of ReadCleanReq accesses(hits+misses) 107111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3542359 # number of ReadSharedReq accesses(hits+misses) 107211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3542359 # number of ReadSharedReq accesses(hits+misses) 107311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 719547 # number of InvalidateReq accesses(hits+misses) 107411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 719547 # number of InvalidateReq accesses(hits+misses) 107511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 223368 # number of demand (read+write) accesses 107611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 139716 # number of demand (read+write) accesses 107711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 4772882 # number of demand (read+write) accesses 107811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4622275 # number of demand (read+write) accesses 107911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::total 9758241 # number of demand (read+write) accesses 108011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 223368 # number of overall (read+write) accesses 108111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 139716 # number of overall (read+write) accesses 108211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 4772882 # number of overall (read+write) accesses 108311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 4622275 # number of overall (read+write) accesses 108411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::total 9758241 # number of overall (read+write) accesses 108511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.041040 # miss rate for ReadReq accesses 108611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051683 # miss rate for ReadReq accesses 108711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.045136 # miss rate for ReadReq accesses 108811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998624 # miss rate for UpgradeReq accesses 108911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998624 # miss rate for UpgradeReq accesses 109011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 109111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 109210535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 109310535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 109411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.226359 # miss rate for ReadExReq accesses 109511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.226359 # miss rate for ReadExReq accesses 109611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091307 # miss rate for ReadCleanReq accesses 109711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091307 # miss rate for ReadCleanReq accesses 109811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.246030 # miss rate for ReadSharedReq accesses 109911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.246030 # miss rate for ReadSharedReq accesses 110011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.771799 # miss rate for InvalidateReq accesses 110111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.771799 # miss rate for InvalidateReq accesses 110211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.041040 # miss rate for demand accesses 110311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051683 # miss rate for demand accesses 110411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091307 # miss rate for demand accesses 110511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241434 # miss rate for demand accesses 110611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.160701 # miss rate for demand accesses 110711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.041040 # miss rate for overall accesses 110811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051683 # miss rate for overall accesses 110911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091307 # miss rate for overall accesses 111011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241434 # miss rate for overall accesses 111111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.160701 # miss rate for overall accesses 111211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38355.405258 # average ReadReq miss latency 111311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41406.591885 # average ReadReq miss latency 111411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 39699.841347 # average ReadReq miss latency 111511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14184.453242 # average UpgradeReq miss latency 111611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14184.453242 # average UpgradeReq miss latency 111711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10333.907504 # average SCUpgradeReq miss latency 111811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10333.907504 # average SCUpgradeReq miss latency 111911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 224241.935484 # average SCUpgradeFailReq miss latency 112011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 224241.935484 # average SCUpgradeFailReq miss latency 112111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64549.562477 # average ReadExReq miss latency 112211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64549.562477 # average ReadExReq miss latency 112311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39875.330141 # average ReadCleanReq miss latency 112411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39875.330141 # average ReadCleanReq miss latency 112511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39839.266802 # average ReadSharedReq miss latency 112611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39839.266802 # average ReadSharedReq miss latency 112711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 112116.156414 # average InvalidateReq miss latency 112811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 112116.156414 # average InvalidateReq miss latency 112911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38355.405258 # average overall miss latency 113011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41406.591885 # average overall miss latency 113111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39875.330141 # average overall miss latency 113211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45251.944040 # average overall miss latency 113311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 43699.736824 # average overall miss latency 113411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38355.405258 # average overall miss latency 113511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41406.591885 # average overall miss latency 113611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39875.330141 # average overall miss latency 113711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45251.944040 # average overall miss latency 113811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 43699.736824 # average overall miss latency 113910628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 114010535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 114110628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 114210535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 114310628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 114410535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 114510535SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 114610535SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 114711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1408018 # number of writebacks 114811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::total 1408018 # number of writebacks 114911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5268 # number of ReadExReq MSHR hits 115011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 5268 # number of ReadExReq MSHR hits 115111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 532 # number of ReadSharedReq MSHR hits 115211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 532 # number of ReadSharedReq MSHR hits 115311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 5800 # number of demand (read+write) MSHR hits 115411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 5800 # number of demand (read+write) MSHR hits 115511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 5800 # number of overall MSHR hits 115611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 5800 # number of overall MSHR hits 115711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9167 # number of ReadReq MSHR misses 115811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7221 # number of ReadReq MSHR misses 115911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 16388 # number of ReadReq MSHR misses 116011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 673244 # number of HardPFReq MSHR misses 116111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 673244 # number of HardPFReq MSHR misses 116211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 234409 # number of UpgradeReq MSHR misses 116311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 234409 # number of UpgradeReq MSHR misses 116411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 190710 # number of SCUpgradeReq MSHR misses 116511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 190710 # number of SCUpgradeReq MSHR misses 116611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 31 # number of SCUpgradeFailReq MSHR misses 116711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 31 # number of SCUpgradeFailReq MSHR misses 116811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 239181 # number of ReadExReq MSHR misses 116911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 239181 # number of ReadExReq MSHR misses 117011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 435799 # number of ReadCleanReq MSHR misses 117111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 435799 # number of ReadCleanReq MSHR misses 117211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 870993 # number of ReadSharedReq MSHR misses 117311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 870993 # number of ReadSharedReq MSHR misses 117411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 555346 # number of InvalidateReq MSHR misses 117511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 555346 # number of InvalidateReq MSHR misses 117611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9167 # number of demand (read+write) MSHR misses 117711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7221 # number of demand (read+write) MSHR misses 117811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 435799 # number of demand (read+write) MSHR misses 117911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1110174 # number of demand (read+write) MSHR misses 118011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1562361 # number of demand (read+write) MSHR misses 118111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9167 # number of overall MSHR misses 118211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7221 # number of overall MSHR misses 118311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 435799 # number of overall MSHR misses 118411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1110174 # number of overall MSHR misses 118511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 673244 # number of overall MSHR misses 118611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2235605 # number of overall MSHR misses 118710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 118811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16746 # number of ReadReq MSHR uncacheable 118911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59871 # number of ReadReq MSHR uncacheable 119011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17968 # number of WriteReq MSHR uncacheable 119111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17968 # number of WriteReq MSHR uncacheable 119210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 119311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34714 # number of overall MSHR uncacheable misses 119411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77839 # number of overall MSHR uncacheable misses 119511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 296602000 # number of ReadReq MSHR miss cycles 119611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 255671000 # number of ReadReq MSHR miss cycles 119711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 552273000 # number of ReadReq MSHR miss cycles 119811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37620512818 # number of HardPFReq MSHR miss cycles 119911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37620512818 # number of HardPFReq MSHR miss cycles 120011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7511827000 # number of UpgradeReq MSHR miss cycles 120111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7511827000 # number of UpgradeReq MSHR miss cycles 120211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3867075000 # number of SCUpgradeReq MSHR miss cycles 120311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3867075000 # number of SCUpgradeReq MSHR miss cycles 120411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6477500 # number of SCUpgradeFailReq MSHR miss cycles 120511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6477500 # number of SCUpgradeFailReq MSHR miss cycles 120611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13744375998 # number of ReadExReq MSHR miss cycles 120711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13744375998 # number of ReadExReq MSHR miss cycles 120811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14762835000 # number of ReadCleanReq MSHR miss cycles 120911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14762835000 # number of ReadCleanReq MSHR miss cycles 121011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 29450022000 # number of ReadSharedReq MSHR miss cycles 121111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 29450022000 # number of ReadSharedReq MSHR miss cycles 121211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 58931183000 # number of InvalidateReq MSHR miss cycles 121311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 58931183000 # number of InvalidateReq MSHR miss cycles 121411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 296602000 # number of demand (read+write) MSHR miss cycles 121511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 255671000 # number of demand (read+write) MSHR miss cycles 121611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14762835000 # number of demand (read+write) MSHR miss cycles 121711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43194397998 # number of demand (read+write) MSHR miss cycles 121811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 58509505998 # number of demand (read+write) MSHR miss cycles 121911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 296602000 # number of overall MSHR miss cycles 122011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 255671000 # number of overall MSHR miss cycles 122111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14762835000 # number of overall MSHR miss cycles 122211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43194397998 # number of overall MSHR miss cycles 122311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37620512818 # number of overall MSHR miss cycles 122411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 96130018816 # number of overall MSHR miss cycles 122511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles 122611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2763179500 # number of ReadReq MSHR uncacheable cycles 122711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8393951000 # number of ReadReq MSHR uncacheable cycles 122811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2967633500 # number of WriteReq MSHR uncacheable cycles 122911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2967633500 # number of WriteReq MSHR uncacheable cycles 123011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles 123111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5730813000 # number of overall MSHR uncacheable cycles 123211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11361584500 # number of overall MSHR uncacheable cycles 123311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for ReadReq accesses 123411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for ReadReq accesses 123511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.045136 # mshr miss rate for ReadReq accesses 123610535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 123710535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 123811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998624 # mshr miss rate for UpgradeReq accesses 123911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998624 # mshr miss rate for UpgradeReq accesses 124011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 124111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 124210535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 124310535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 124411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221481 # mshr miss rate for ReadExReq accesses 124511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221481 # mshr miss rate for ReadExReq accesses 124611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for ReadCleanReq accesses 124711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091307 # mshr miss rate for ReadCleanReq accesses 124811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.245879 # mshr miss rate for ReadSharedReq accesses 124911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245879 # mshr miss rate for ReadSharedReq accesses 125011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771799 # mshr miss rate for InvalidateReq accesses 125111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771799 # mshr miss rate for InvalidateReq accesses 125211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for demand accesses 125311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for demand accesses 125411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for demand accesses 125511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240179 # mshr miss rate for demand accesses 125611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.160107 # mshr miss rate for demand accesses 125711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for overall accesses 125811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for overall accesses 125911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for overall accesses 126011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240179 # mshr miss rate for overall accesses 126110535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 126211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.229099 # mshr miss rate for overall accesses 126311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average ReadReq mshr miss latency 126411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average ReadReq mshr miss latency 126511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33699.841347 # average ReadReq mshr miss latency 126611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450 # average HardPFReq mshr miss latency 126711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55879.462450 # average HardPFReq mshr miss latency 126811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32045.813087 # average UpgradeReq mshr miss latency 126911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32045.813087 # average UpgradeReq mshr miss latency 127011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20277.253421 # average SCUpgradeReq mshr miss latency 127111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20277.253421 # average SCUpgradeReq mshr miss latency 127211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 208951.612903 # average SCUpgradeFailReq mshr miss latency 127311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 208951.612903 # average SCUpgradeFailReq mshr miss latency 127411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57464.330352 # average ReadExReq mshr miss latency 127511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57464.330352 # average ReadExReq mshr miss latency 127611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average ReadCleanReq mshr miss latency 127711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33875.330141 # average ReadCleanReq mshr miss latency 127811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33812.007674 # average ReadSharedReq mshr miss latency 127911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33812.007674 # average ReadSharedReq mshr miss latency 128011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 106116.156414 # average InvalidateReq mshr miss latency 128111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 106116.156414 # average InvalidateReq mshr miss latency 128211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency 128311245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency 128411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency 128511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency 128611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37449.415339 # average overall mshr miss latency 128711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency 128811245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency 128911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency 129011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency 129111245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450 # average overall mshr miss latency 129211245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42999.554401 # average overall mshr miss latency 129311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency 129411245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165005.344560 # average ReadReq mshr uncacheable latency 129511245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 140200.614655 # average ReadReq mshr uncacheable latency 129611245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165162.149377 # average WriteReq mshr uncacheable latency 129711245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165162.149377 # average WriteReq mshr uncacheable latency 129811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency 129911245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165086.506885 # average overall mshr uncacheable latency 130011245Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145962.621565 # average overall mshr uncacheable latency 130110535SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 130211245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 20776945 # Total number of requests made to the snoop filter. 130311245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 10662406 # Number of requests hitting in the snoop filter with a single holder of the requested data. 130411245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 659 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 130511245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1726264 # Total number of snoops made to the snoop filter. 130611245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1726085 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 130711245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 179 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 130811245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 488069 # Transaction distribution 130911245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 8911186 # Transaction distribution 131011245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 17968 # Transaction distribution 131111245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 17968 # Transaction distribution 131211245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 4874700 # Transaction distribution 131311245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 6546722 # Transaction distribution 131411245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 2139143 # Transaction distribution 131511245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 829102 # Transaction distribution 131611245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 434919 # Transaction distribution 131711245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 350602 # Transaction distribution 131811245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 501065 # Transaction distribution 131911245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution 132011245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 132111245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1159158 # Transaction distribution 132211245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1092705 # Transaction distribution 132311245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 4772882 # Transaction distribution 132411245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4419934 # Transaction distribution 132511245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 726049 # Transaction distribution 132611245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 719547 # Transaction distribution 132711245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14404114 # Packet count per connected master and slave (bytes) 132811245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17037537 # Packet count per connected master and slave (bytes) 132911245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296236 # Packet count per connected master and slave (bytes) 133011245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 495044 # Packet count per connected master and slave (bytes) 133111245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count::total 32232931 # Packet count per connected master and slave (bytes) 133211245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 611051348 # Cumulative packet size per connected master and slave (bytes) 133311245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 638823901 # Cumulative packet size per connected master and slave (bytes) 133411245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1117728 # Cumulative packet size per connected master and slave (bytes) 133511245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1786944 # Cumulative packet size per connected master and slave (bytes) 133611245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1252779921 # Cumulative packet size per connected master and slave (bytes) 133711245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoops 5965413 # Total snoops (count) 133811245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 16750116 # Request fanout histogram 133911245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.116655 # Request fanout histogram 134011245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.321042 # Request fanout histogram 134110535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 134211245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 14796306 88.34% 88.34% # Request fanout histogram 134311245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 1953631 11.66% 100.00% # Request fanout histogram 134411245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 179 0.00% 100.00% # Request fanout histogram 134510535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 134611138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 134710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 134811245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 16750116 # Request fanout histogram 134911245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 20546913496 # Layer occupancy (ticks) 135010535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 135111245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 219185391 # Layer occupancy (ticks) 135210535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 135311245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7202448000 # Layer occupancy (ticks) 135410535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 135511245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7531952589 # Layer occupancy (ticks) 135610535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 135711245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 156520499 # Layer occupancy (ticks) 135810535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 135911245Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 271676000 # Layer occupancy (ticks) 136010535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 136110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 136210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 136310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 136410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 136610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 136710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 136810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 136910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 137010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 137110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 137210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 137310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 137410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 137510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 137610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 137710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 137910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 138010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 138110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 138210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 138310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 138410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 138510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 138610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 138710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 138810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 138910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 139011245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walks 101882 # Table walker walks requested 139111245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksLong 101882 # Table walker walks initiated with long descriptors 139211245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8030 # Level at which table walker walks with long descriptors terminate 139311245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79527 # Level at which table walker walks with long descriptors terminate 139411245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting 139511245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 101873 # Table walker wait (enqueue to first request) latency 139611245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.078529 # Table walker wait (enqueue to first request) latency 139711245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 25.064580 # Table walker wait (enqueue to first request) latency 139811245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-511 101872 100.00% 100.00% # Table walker wait (enqueue to first request) latency 139911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 140011245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 101873 # Table walker wait (enqueue to first request) latency 140111245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 87566 # Table walker service (enqueue to completion) latency 140211245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 23519.505287 # Table walker service (enqueue to completion) latency 140311245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21365.105207 # Table walker service (enqueue to completion) latency 140411245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 20825.826742 # Table walker service (enqueue to completion) latency 140511245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 86337 98.60% 98.60% # Table walker service (enqueue to completion) latency 140611245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 178 0.20% 98.80% # Table walker service (enqueue to completion) latency 140711245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 904 1.03% 99.83% # Table walker service (enqueue to completion) latency 140811245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 19 0.02% 99.85% # Table walker service (enqueue to completion) latency 140911245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 55 0.06% 99.92% # Table walker service (enqueue to completion) latency 141011245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.93% # Table walker service (enqueue to completion) latency 141111245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency 141211245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency 141311245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 141411245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 141511245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 141611245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 87566 # Table walker service (enqueue to completion) latency 141711245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::samples 239339024 # Table walker pending requests distribution 141811245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::mean 9.661342 # Table walker pending requests distribution 141911245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::0 -2072997220 -866.13% -866.13% # Table walker pending requests distribution 142011245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::1 2312336244 966.13% 100.00% # Table walker pending requests distribution 142111245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walksPending::total 239339024 # Table walker pending requests distribution 142211245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 79528 90.83% 90.83% # Table walker page sizes translated 142311245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 8030 9.17% 100.00% # Table walker page sizes translated 142411245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 87558 # Table walker page sizes translated 142511245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101882 # Table walker requests started/completed, data/inst 142610628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 142711245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101882 # Table walker requests started/completed, data/inst 142811245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87558 # Table walker requests started/completed, data/inst 142910628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 143011245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87558 # Table walker requests started/completed, data/inst 143111245Sandreas.sandberg@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 189440 # Table walker requests started/completed, data/inst 143210535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 143310535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 143411245Sandreas.sandberg@arm.comsystem.cpu1.dtb.read_hits 82176038 # DTB read hits 143511245Sandreas.sandberg@arm.comsystem.cpu1.dtb.read_misses 74927 # DTB read misses 143611245Sandreas.sandberg@arm.comsystem.cpu1.dtb.write_hits 74775352 # DTB write hits 143711245Sandreas.sandberg@arm.comsystem.cpu1.dtb.write_misses 26955 # DTB write misses 143810535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 143910535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 144011245Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID 144111245Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID 144211245Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_entries 37701 # Number of entries that have been flushed from TLB 144310535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 144411245Sandreas.sandberg@arm.comsystem.cpu1.dtb.prefetch_faults 4186 # Number of TLB faults due to prefetch 144510535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 144611245Sandreas.sandberg@arm.comsystem.cpu1.dtb.perms_faults 10277 # Number of TLB faults due to permissions restrictions 144711245Sandreas.sandberg@arm.comsystem.cpu1.dtb.read_accesses 82250965 # DTB read accesses 144811245Sandreas.sandberg@arm.comsystem.cpu1.dtb.write_accesses 74802307 # DTB write accesses 144910535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 145011245Sandreas.sandberg@arm.comsystem.cpu1.dtb.hits 156951390 # DTB hits 145111245Sandreas.sandberg@arm.comsystem.cpu1.dtb.misses 101882 # DTB misses 145211245Sandreas.sandberg@arm.comsystem.cpu1.dtb.accesses 157053272 # DTB accesses 145310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 145410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 145510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 145610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 145710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 145810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 145910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 146010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 146110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 146210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 146310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 146410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 146510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 146610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 146710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 146810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 146910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 147010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 147110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 147210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 147310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 147410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 147510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 147610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 147710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 147810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 147910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 148010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 148110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 148211245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walks 63786 # Table walker walks requested 148311245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksLong 63786 # Table walker walks initiated with long descriptors 148411245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 574 # Level at which table walker walks with long descriptors terminate 148511245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 58046 # Level at which table walker walks with long descriptors terminate 148611245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 63786 # Table walker wait (enqueue to first request) latency 148711245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 63786 100.00% 100.00% # Table walker wait (enqueue to first request) latency 148811245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 63786 # Table walker wait (enqueue to first request) latency 148911245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 58620 # Table walker service (enqueue to completion) latency 149011245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 26694.208461 # Table walker service (enqueue to completion) latency 149111245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23680.273613 # Table walker service (enqueue to completion) latency 149211245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 26398.773524 # Table walker service (enqueue to completion) latency 149311245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 57379 97.88% 97.88% # Table walker service (enqueue to completion) latency 149411245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 45 0.08% 97.96% # Table walker service (enqueue to completion) latency 149511245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 1025 1.75% 99.71% # Table walker service (enqueue to completion) latency 149611245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 33 0.06% 99.76% # Table walker service (enqueue to completion) latency 149711245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.85% # Table walker service (enqueue to completion) latency 149811245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.89% # Table walker service (enqueue to completion) latency 149911245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 49 0.08% 99.97% # Table walker service (enqueue to completion) latency 150011245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 9 0.02% 99.99% # Table walker service (enqueue to completion) latency 150111245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 150211245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 150311245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 58620 # Table walker service (enqueue to completion) latency 150411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -2103779220 # Table walker pending requests distribution 150511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -2103779220 100.00% 100.00% # Table walker pending requests distribution 150611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -2103779220 # Table walker pending requests distribution 150711245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 58046 99.02% 99.02% # Table walker page sizes translated 150811245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 574 0.98% 100.00% # Table walker page sizes translated 150911245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 58620 # Table walker page sizes translated 151010628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 151111245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63786 # Table walker requests started/completed, data/inst 151211245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 63786 # Table walker requests started/completed, data/inst 151310628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 151411245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58620 # Table walker requests started/completed, data/inst 151511245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 58620 # Table walker requests started/completed, data/inst 151611245Sandreas.sandberg@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 122406 # Table walker requests started/completed, data/inst 151711245Sandreas.sandberg@arm.comsystem.cpu1.itb.inst_hits 435405767 # ITB inst hits 151811245Sandreas.sandberg@arm.comsystem.cpu1.itb.inst_misses 63786 # ITB inst misses 151910535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 152010535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 152110535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 152210535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 152310535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 152410535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 152511245Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID 152611245Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID 152711245Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_entries 26334 # Number of entries that have been flushed from TLB 152810535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152910535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153010535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 153110535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 153210535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 153310535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 153411245Sandreas.sandberg@arm.comsystem.cpu1.itb.inst_accesses 435469553 # ITB inst accesses 153511245Sandreas.sandberg@arm.comsystem.cpu1.itb.hits 435405767 # DTB hits 153611245Sandreas.sandberg@arm.comsystem.cpu1.itb.misses 63786 # DTB misses 153711245Sandreas.sandberg@arm.comsystem.cpu1.itb.accesses 435469553 # DTB accesses 153811245Sandreas.sandberg@arm.comsystem.cpu1.numCycles 95187488343 # number of cpu cycles simulated 153910535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 154010535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 154111167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 154211245Sandreas.sandberg@arm.comsystem.cpu1.kern.inst.quiesce 14345 # number of quiesce instructions executed 154311245Sandreas.sandberg@arm.comsystem.cpu1.committedInsts 435108521 # Number of instructions committed 154411245Sandreas.sandberg@arm.comsystem.cpu1.committedOps 512619121 # Number of ops (including micro ops) committed 154511245Sandreas.sandberg@arm.comsystem.cpu1.num_int_alu_accesses 471360298 # Number of integer alu accesses 154611245Sandreas.sandberg@arm.comsystem.cpu1.num_fp_alu_accesses 517037 # Number of float alu accesses 154711245Sandreas.sandberg@arm.comsystem.cpu1.num_func_calls 26310177 # number of times a function call or return occured 154811245Sandreas.sandberg@arm.comsystem.cpu1.num_conditional_control_insts 66181606 # number of instructions that are conditional controls 154911245Sandreas.sandberg@arm.comsystem.cpu1.num_int_insts 471360298 # number of integer instructions 155011245Sandreas.sandberg@arm.comsystem.cpu1.num_fp_insts 517037 # number of float instructions 155111245Sandreas.sandberg@arm.comsystem.cpu1.num_int_register_reads 683625420 # number of times the integer registers were read 155211245Sandreas.sandberg@arm.comsystem.cpu1.num_int_register_writes 373659475 # number of times the integer registers were written 155311245Sandreas.sandberg@arm.comsystem.cpu1.num_fp_register_reads 819092 # number of times the floating registers were read 155411245Sandreas.sandberg@arm.comsystem.cpu1.num_fp_register_writes 470852 # number of times the floating registers were written 155511245Sandreas.sandberg@arm.comsystem.cpu1.num_cc_register_reads 112718016 # number of times the CC registers were read 155611245Sandreas.sandberg@arm.comsystem.cpu1.num_cc_register_writes 112414585 # number of times the CC registers were written 155711245Sandreas.sandberg@arm.comsystem.cpu1.num_mem_refs 156939308 # number of memory refs 155811245Sandreas.sandberg@arm.comsystem.cpu1.num_load_insts 82171340 # Number of load instructions 155911245Sandreas.sandberg@arm.comsystem.cpu1.num_store_insts 74767968 # Number of store instructions 156011245Sandreas.sandberg@arm.comsystem.cpu1.num_idle_cycles 94109373851.176025 # Number of idle cycles 156111245Sandreas.sandberg@arm.comsystem.cpu1.num_busy_cycles 1078114491.823977 # Number of busy cycles 156211245Sandreas.sandberg@arm.comsystem.cpu1.not_idle_fraction 0.011326 # Percentage of non-idle cycles 156311245Sandreas.sandberg@arm.comsystem.cpu1.idle_fraction 0.988674 # Percentage of idle cycles 156411245Sandreas.sandberg@arm.comsystem.cpu1.Branches 97258514 # Number of branches fetched 156511201Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 156611245Sandreas.sandberg@arm.comsystem.cpu1.op_class::IntAlu 354775953 69.17% 69.17% # Class of executed instruction 156711245Sandreas.sandberg@arm.comsystem.cpu1.op_class::IntMult 1066461 0.21% 69.38% # Class of executed instruction 156811245Sandreas.sandberg@arm.comsystem.cpu1.op_class::IntDiv 59336 0.01% 69.39% # Class of executed instruction 156911245Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.39% # Class of executed instruction 157011245Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.39% # Class of executed instruction 157111245Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.39% # Class of executed instruction 157211245Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.39% # Class of executed instruction 157311245Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.39% # Class of executed instruction 157411245Sandreas.sandberg@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.39% # Class of executed instruction 157511245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.39% # Class of executed instruction 157611245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.39% # Class of executed instruction 157711245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.39% # Class of executed instruction 157811245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.39% # Class of executed instruction 157911245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.39% # Class of executed instruction 158011245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.39% # Class of executed instruction 158111245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.39% # Class of executed instruction 158211245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.39% # Class of executed instruction 158311245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.39% # Class of executed instruction 158411245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.39% # Class of executed instruction 158511245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.39% # Class of executed instruction 158611245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatAdd 8 0.00% 69.39% # Class of executed instruction 158711245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.39% # Class of executed instruction 158811245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatCmp 13 0.00% 69.39% # Class of executed instruction 158911245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatCvt 21 0.00% 69.39% # Class of executed instruction 159011245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.39% # Class of executed instruction 159111245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMisc 75375 0.01% 69.40% # Class of executed instruction 159211245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.40% # Class of executed instruction 159311245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.40% # Class of executed instruction 159411245Sandreas.sandberg@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.40% # Class of executed instruction 159511245Sandreas.sandberg@arm.comsystem.cpu1.op_class::MemRead 82171340 16.02% 85.42% # Class of executed instruction 159611245Sandreas.sandberg@arm.comsystem.cpu1.op_class::MemWrite 74767968 14.58% 100.00% # Class of executed instruction 159710535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 159810535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 159911245Sandreas.sandberg@arm.comsystem.cpu1.op_class::total 512916476 # Class of executed instruction 160011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.replacements 5113111 # number of replacements 160111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tagsinuse 443.711015 # Cycle average of tags in use 160211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.total_refs 151630595 # Total number of references to valid blocks. 160311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.sampled_refs 5113623 # Sample count of references to valid blocks. 160411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.avg_refs 29.652283 # Average number of references to valid blocks. 160511201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8408412782000 # Cycle when the warmup percentage was hit. 160611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 443.711015 # Average occupied blocks per requestor 160711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.866623 # Average percentage of cache occupancy 160811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.866623 # Average percentage of cache occupancy 160911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 161011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 161111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id 161211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 161311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 161411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.tag_accesses 319002554 # Number of tag accesses 161511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.tags.data_accesses 319002554 # Number of data accesses 161611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 76632055 # number of ReadReq hits 161711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_hits::total 76632055 # number of ReadReq hits 161811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 70902064 # number of WriteReq hits 161911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::total 70902064 # number of WriteReq hits 162011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 183506 # number of SoftPFReq hits 162111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 183506 # number of SoftPFReq hits 162211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 192465 # number of WriteLineReq hits 162311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 192465 # number of WriteLineReq hits 162411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1673719 # number of LoadLockedReq hits 162511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1673719 # number of LoadLockedReq hits 162611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1647145 # number of StoreCondReq hits 162711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1647145 # number of StoreCondReq hits 162811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 147534119 # number of demand (read+write) hits 162911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::total 147534119 # number of demand (read+write) hits 163011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 147717625 # number of overall hits 163111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::total 147717625 # number of overall hits 163211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2895739 # number of ReadReq misses 163311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2895739 # number of ReadReq misses 163411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1291835 # number of WriteReq misses 163511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1291835 # number of WriteReq misses 163611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 599128 # number of SoftPFReq misses 163711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 599128 # number of SoftPFReq misses 163811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 515597 # number of WriteLineReq misses 163911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 515597 # number of WriteLineReq misses 164011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170116 # number of LoadLockedReq misses 164111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 170116 # number of LoadLockedReq misses 164211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 195350 # number of StoreCondReq misses 164311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 195350 # number of StoreCondReq misses 164411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4187574 # number of demand (read+write) misses 164511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::total 4187574 # number of demand (read+write) misses 164611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 4786702 # number of overall misses 164711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::total 4786702 # number of overall misses 164811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44430252500 # number of ReadReq miss cycles 164911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 44430252500 # number of ReadReq miss cycles 165011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 29275459500 # number of WriteReq miss cycles 165111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 29275459500 # number of WriteReq miss cycles 165211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21176769000 # number of WriteLineReq miss cycles 165311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 21176769000 # number of WriteLineReq miss cycles 165411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2717509500 # number of LoadLockedReq miss cycles 165511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2717509500 # number of LoadLockedReq miss cycles 165611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5539928000 # number of StoreCondReq miss cycles 165711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 5539928000 # number of StoreCondReq miss cycles 165811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5730000 # number of StoreCondFailReq miss cycles 165911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 5730000 # number of StoreCondFailReq miss cycles 166011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 73705712000 # number of demand (read+write) miss cycles 166111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_latency::total 73705712000 # number of demand (read+write) miss cycles 166211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 73705712000 # number of overall miss cycles 166311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_latency::total 73705712000 # number of overall miss cycles 166411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 79527794 # number of ReadReq accesses(hits+misses) 166511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 79527794 # number of ReadReq accesses(hits+misses) 166611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 72193899 # number of WriteReq accesses(hits+misses) 166711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 72193899 # number of WriteReq accesses(hits+misses) 166811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 782634 # number of SoftPFReq accesses(hits+misses) 166911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 782634 # number of SoftPFReq accesses(hits+misses) 167011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 708062 # number of WriteLineReq accesses(hits+misses) 167111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 708062 # number of WriteLineReq accesses(hits+misses) 167211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843835 # number of LoadLockedReq accesses(hits+misses) 167311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1843835 # number of LoadLockedReq accesses(hits+misses) 167411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1842495 # number of StoreCondReq accesses(hits+misses) 167511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1842495 # number of StoreCondReq accesses(hits+misses) 167611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 151721693 # number of demand (read+write) accesses 167711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_accesses::total 151721693 # number of demand (read+write) accesses 167811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 152504327 # number of overall (read+write) accesses 167911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_accesses::total 152504327 # number of overall (read+write) accesses 168011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036412 # miss rate for ReadReq accesses 168111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036412 # miss rate for ReadReq accesses 168211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017894 # miss rate for WriteReq accesses 168311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.017894 # miss rate for WriteReq accesses 168411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765528 # miss rate for SoftPFReq accesses 168511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.765528 # miss rate for SoftPFReq accesses 168611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.728181 # miss rate for WriteLineReq accesses 168711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.728181 # miss rate for WriteLineReq accesses 168811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092262 # miss rate for LoadLockedReq accesses 168911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092262 # miss rate for LoadLockedReq accesses 169011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106025 # miss rate for StoreCondReq accesses 169111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.106025 # miss rate for StoreCondReq accesses 169211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.027600 # miss rate for demand accesses 169311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.027600 # miss rate for demand accesses 169411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.031387 # miss rate for overall accesses 169511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.031387 # miss rate for overall accesses 169611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.320824 # average ReadReq miss latency 169711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.320824 # average ReadReq miss latency 169811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22661.918511 # average WriteReq miss latency 169911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 22661.918511 # average WriteReq miss latency 170011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41072.327806 # average WriteLineReq miss latency 170111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41072.327806 # average WriteLineReq miss latency 170211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.449787 # average LoadLockedReq miss latency 170311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.449787 # average LoadLockedReq miss latency 170411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28358.986435 # average StoreCondReq miss latency 170511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28358.986435 # average StoreCondReq miss latency 170610535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 170710535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 170811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17601.053020 # average overall miss latency 170911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17601.053020 # average overall miss latency 171011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15398.015586 # average overall miss latency 171111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15398.015586 # average overall miss latency 171210535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 171310535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171410535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 171510535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 171610535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 171710535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 171810585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 171910535SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 172011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::writebacks 5113111 # number of writebacks 172111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.writebacks::total 5113111 # number of writebacks 172211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16657 # number of ReadReq MSHR hits 172311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 16657 # number of ReadReq MSHR hits 172411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits 172511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits 172611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46028 # number of LoadLockedReq MSHR hits 172711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 46028 # number of LoadLockedReq MSHR hits 172811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 17059 # number of demand (read+write) MSHR hits 172911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 17059 # number of demand (read+write) MSHR hits 173011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 17059 # number of overall MSHR hits 173111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 17059 # number of overall MSHR hits 173211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879082 # number of ReadReq MSHR misses 173311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2879082 # number of ReadReq MSHR misses 173411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1291433 # number of WriteReq MSHR misses 173511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1291433 # number of WriteReq MSHR misses 173611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599128 # number of SoftPFReq MSHR misses 173711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 599128 # number of SoftPFReq MSHR misses 173811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 515597 # number of WriteLineReq MSHR misses 173911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 515597 # number of WriteLineReq MSHR misses 174011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 124088 # number of LoadLockedReq MSHR misses 174111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 124088 # number of LoadLockedReq MSHR misses 174211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195350 # number of StoreCondReq MSHR misses 174311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 195350 # number of StoreCondReq MSHR misses 174411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4170515 # number of demand (read+write) MSHR misses 174511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4170515 # number of demand (read+write) MSHR misses 174611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 4769643 # number of overall MSHR misses 174711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 4769643 # number of overall MSHR misses 174811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21793 # number of ReadReq MSHR uncacheable 174911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 21793 # number of ReadReq MSHR uncacheable 175011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable 175111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 20416 # number of WriteReq MSHR uncacheable 175211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42209 # number of overall MSHR uncacheable misses 175311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 42209 # number of overall MSHR uncacheable misses 175411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40268780500 # number of ReadReq MSHR miss cycles 175511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 40268780500 # number of ReadReq MSHR miss cycles 175611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27960090500 # number of WriteReq MSHR miss cycles 175711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 27960090500 # number of WriteReq MSHR miss cycles 175811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13604579000 # number of SoftPFReq MSHR miss cycles 175911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13604579000 # number of SoftPFReq MSHR miss cycles 176011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20661172000 # number of WriteLineReq MSHR miss cycles 176111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20661172000 # number of WriteLineReq MSHR miss cycles 176211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751690500 # number of LoadLockedReq MSHR miss cycles 176311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751690500 # number of LoadLockedReq MSHR miss cycles 176411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5344637000 # number of StoreCondReq MSHR miss cycles 176511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5344637000 # number of StoreCondReq MSHR miss cycles 176611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5671000 # number of StoreCondFailReq MSHR miss cycles 176711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5671000 # number of StoreCondFailReq MSHR miss cycles 176811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68228871000 # number of demand (read+write) MSHR miss cycles 176911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 68228871000 # number of demand (read+write) MSHR miss cycles 177011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81833450000 # number of overall MSHR miss cycles 177111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 81833450000 # number of overall MSHR miss cycles 177211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4030825000 # number of ReadReq MSHR uncacheable cycles 177311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4030825000 # number of ReadReq MSHR uncacheable cycles 177411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3797015500 # number of WriteReq MSHR uncacheable cycles 177511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3797015500 # number of WriteReq MSHR uncacheable cycles 177611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7827840500 # number of overall MSHR uncacheable cycles 177711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 7827840500 # number of overall MSHR uncacheable cycles 177811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036202 # mshr miss rate for ReadReq accesses 177911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036202 # mshr miss rate for ReadReq accesses 178011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for WriteReq accesses 178111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017888 # mshr miss rate for WriteReq accesses 178211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765528 # mshr miss rate for SoftPFReq accesses 178311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765528 # mshr miss rate for SoftPFReq accesses 178411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.728181 # mshr miss rate for WriteLineReq accesses 178511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.728181 # mshr miss rate for WriteLineReq accesses 178611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067299 # mshr miss rate for LoadLockedReq accesses 178711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067299 # mshr miss rate for LoadLockedReq accesses 178811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106025 # mshr miss rate for StoreCondReq accesses 178911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106025 # mshr miss rate for StoreCondReq accesses 179011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027488 # mshr miss rate for demand accesses 179111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.027488 # mshr miss rate for demand accesses 179211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031275 # mshr miss rate for overall accesses 179311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.031275 # mshr miss rate for overall accesses 179411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.673704 # average ReadReq mshr miss latency 179511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.673704 # average ReadReq mshr miss latency 179611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21650.438312 # average WriteReq mshr miss latency 179711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21650.438312 # average WriteReq mshr miss latency 179811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22707.299609 # average SoftPFReq mshr miss latency 179911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22707.299609 # average SoftPFReq mshr miss latency 180011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40072.327806 # average WriteLineReq mshr miss latency 180111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40072.327806 # average WriteLineReq mshr miss latency 180211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14116.518116 # average LoadLockedReq mshr miss latency 180311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14116.518116 # average LoadLockedReq mshr miss latency 180411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27359.288457 # average StoreCondReq mshr miss latency 180511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27359.288457 # average StoreCondReq mshr miss latency 180610535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 180710535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 180811245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16359.819111 # average overall mshr miss latency 180911245Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16359.819111 # average overall mshr miss latency 181011245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17157.143627 # average overall mshr miss latency 181111245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 17157.143627 # average overall mshr miss latency 181211245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184959.620061 # average ReadReq mshr uncacheable latency 181311245Sandreas.sandberg@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184959.620061 # average ReadReq mshr uncacheable latency 181411245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185982.342281 # average WriteReq mshr uncacheable latency 181511245Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185982.342281 # average WriteReq mshr uncacheable latency 181611245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185454.298846 # average overall mshr uncacheable latency 181711245Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 185454.298846 # average overall mshr uncacheable latency 181810535SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 181911245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.replacements 5153049 # number of replacements 182011245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.tagsinuse 495.966911 # Cycle average of tags in use 182111245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.total_refs 430252201 # Total number of references to valid blocks. 182211245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.sampled_refs 5153561 # Sample count of references to valid blocks. 182311245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.avg_refs 83.486390 # Average number of references to valid blocks. 182411201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8408381586000 # Cycle when the warmup percentage was hit. 182511245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 495.966911 # Average occupied blocks per requestor 182611245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.968685 # Average percentage of cache occupancy 182711245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.968685 # Average percentage of cache occupancy 182810535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 182911245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 183011245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id 183111245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id 183211245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 183310535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 183411245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.tag_accesses 875965100 # Number of tag accesses 183511245Sandreas.sandberg@arm.comsystem.cpu1.icache.tags.data_accesses 875965100 # Number of data accesses 183611245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 430252201 # number of ReadReq hits 183711245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_hits::total 430252201 # number of ReadReq hits 183811245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 430252201 # number of demand (read+write) hits 183911245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_hits::total 430252201 # number of demand (read+write) hits 184011245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 430252201 # number of overall hits 184111245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_hits::total 430252201 # number of overall hits 184211245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 5153566 # number of ReadReq misses 184311245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_misses::total 5153566 # number of ReadReq misses 184411245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 5153566 # number of demand (read+write) misses 184511245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_misses::total 5153566 # number of demand (read+write) misses 184611245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 5153566 # number of overall misses 184711245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_misses::total 5153566 # number of overall misses 184811245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 55699016000 # number of ReadReq miss cycles 184911245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 55699016000 # number of ReadReq miss cycles 185011245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 55699016000 # number of demand (read+write) miss cycles 185111245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_latency::total 55699016000 # number of demand (read+write) miss cycles 185211245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 55699016000 # number of overall miss cycles 185311245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_latency::total 55699016000 # number of overall miss cycles 185411245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 435405767 # number of ReadReq accesses(hits+misses) 185511245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_accesses::total 435405767 # number of ReadReq accesses(hits+misses) 185611245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 435405767 # number of demand (read+write) accesses 185711245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_accesses::total 435405767 # number of demand (read+write) accesses 185811245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 435405767 # number of overall (read+write) accesses 185911245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_accesses::total 435405767 # number of overall (read+write) accesses 186011245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011836 # miss rate for ReadReq accesses 186111245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.011836 # miss rate for ReadReq accesses 186211245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.011836 # miss rate for demand accesses 186311245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.011836 # miss rate for demand accesses 186411245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.011836 # miss rate for overall accesses 186511245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.011836 # miss rate for overall accesses 186611245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10807.859257 # average ReadReq miss latency 186711245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10807.859257 # average ReadReq miss latency 186811245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10807.859257 # average overall miss latency 186911245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10807.859257 # average overall miss latency 187011245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10807.859257 # average overall miss latency 187111245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10807.859257 # average overall miss latency 187210535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 187310535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 187410535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 187510535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 187610535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 187710535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 187810535SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 187910535SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 188011245Sandreas.sandberg@arm.comsystem.cpu1.icache.writebacks::writebacks 5153049 # number of writebacks 188111245Sandreas.sandberg@arm.comsystem.cpu1.icache.writebacks::total 5153049 # number of writebacks 188211245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5153566 # number of ReadReq MSHR misses 188311245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 5153566 # number of ReadReq MSHR misses 188411245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 5153566 # number of demand (read+write) MSHR misses 188511245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_misses::total 5153566 # number of demand (read+write) MSHR misses 188611245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 5153566 # number of overall MSHR misses 188711245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_misses::total 5153566 # number of overall MSHR misses 188810827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 188910827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 189010827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 189110827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 189211245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 53122233000 # number of ReadReq MSHR miss cycles 189311245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 53122233000 # number of ReadReq MSHR miss cycles 189411245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 53122233000 # number of demand (read+write) MSHR miss cycles 189511245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 53122233000 # number of demand (read+write) MSHR miss cycles 189611245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 53122233000 # number of overall MSHR miss cycles 189711245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 53122233000 # number of overall MSHR miss cycles 189811201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14799500 # number of ReadReq MSHR uncacheable cycles 189911201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14799500 # number of ReadReq MSHR uncacheable cycles 190011201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14799500 # number of overall MSHR uncacheable cycles 190111201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 14799500 # number of overall MSHR uncacheable cycles 190211245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for ReadReq accesses 190311245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011836 # mshr miss rate for ReadReq accesses 190411245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for demand accesses 190511245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.011836 # mshr miss rate for demand accesses 190611245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for overall accesses 190711245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.011836 # mshr miss rate for overall accesses 190811245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average ReadReq mshr miss latency 190911245Sandreas.sandberg@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10307.859257 # average ReadReq mshr miss latency 191011245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency 191111245Sandreas.sandberg@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency 191211245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency 191311245Sandreas.sandberg@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency 191411201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average ReadReq mshr uncacheable latency 191511201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091 # average ReadReq mshr uncacheable latency 191611201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average overall mshr uncacheable latency 191711201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091 # average overall mshr uncacheable latency 191810535SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 191911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 6859303 # number of hwpf issued 192011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 6859383 # number of prefetch candidates identified 192111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 70 # number of redundant prefetches already in prefetch queue 192210628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 192310628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 192411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 859985 # number of prefetches not generated due to page crossing 192511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.replacements 1911702 # number of replacements 192611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13239.490812 # Cycle average of tags in use 192711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.total_refs 15125743 # Total number of references to valid blocks. 192811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.sampled_refs 1927829 # Sample count of references to valid blocks. 192911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.avg_refs 7.845998 # Average number of references to valid blocks. 193011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 10087167671000 # Cycle when the warmup percentage was hit. 193111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12280.954827 # Average occupied blocks per requestor 193211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.921711 # Average occupied blocks per requestor 193311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.687685 # Average occupied blocks per requestor 193411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 831.926589 # Average occupied blocks per requestor 193511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.749570 # Average percentage of cache occupancy 193611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003230 # Average percentage of cache occupancy 193711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004498 # Average percentage of cache occupancy 193811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050777 # Average percentage of cache occupancy 193911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.808074 # Average percentage of cache occupancy 194011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1375 # Occupied blocks per task id 194111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id 194211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14698 # Occupied blocks per task id 194311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 194411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id 194511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 718 # Occupied blocks per task id 194611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 459 # Occupied blocks per task id 194711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id 194811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 194911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 195011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 195111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1004 # Occupied blocks per task id 195211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4268 # Occupied blocks per task id 195311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6358 # Occupied blocks per task id 195411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2989 # Occupied blocks per task id 195511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.083923 # Percentage of cache occupancy per task id 195611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id 195711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897095 # Percentage of cache occupancy per task id 195811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tag_accesses 347994589 # Number of tag accesses 195911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.data_accesses 347994589 # Number of data accesses 196011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 237538 # number of ReadReq hits 196111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 166264 # number of ReadReq hits 196211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 403802 # number of ReadReq hits 196311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3233759 # number of WritebackDirty hits 196411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3233759 # number of WritebackDirty hits 196511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 7031230 # number of WritebackClean hits 196611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 7031230 # number of WritebackClean hits 196711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 362 # number of UpgradeReq hits 196811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 362 # number of UpgradeReq hits 196911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 841313 # number of ReadExReq hits 197011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 841313 # number of ReadExReq hits 197111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4702873 # number of ReadCleanReq hits 197211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4702873 # number of ReadCleanReq hits 197311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2730195 # number of ReadSharedReq hits 197411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2730195 # number of ReadSharedReq hits 197511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 242884 # number of InvalidateReq hits 197611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 242884 # number of InvalidateReq hits 197711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 237538 # number of demand (read+write) hits 197811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 166264 # number of demand (read+write) hits 197911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4702873 # number of demand (read+write) hits 198011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3571508 # number of demand (read+write) hits 198111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::total 8678183 # number of demand (read+write) hits 198211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 237538 # number of overall hits 198311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 166264 # number of overall hits 198411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4702873 # number of overall hits 198511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3571508 # number of overall hits 198611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::total 8678183 # number of overall hits 198711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9658 # number of ReadReq misses 198811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8172 # number of ReadReq misses 198911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 17830 # number of ReadReq misses 199011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 204136 # number of UpgradeReq misses 199111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 204136 # number of UpgradeReq misses 199211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195335 # number of SCUpgradeReq misses 199311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 195335 # number of SCUpgradeReq misses 199411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 15 # number of SCUpgradeFailReq misses 199511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 15 # number of SCUpgradeFailReq misses 199611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 248244 # number of ReadExReq misses 199711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 248244 # number of ReadExReq misses 199811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 450693 # number of ReadCleanReq misses 199911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 450693 # number of ReadCleanReq misses 200011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 872103 # number of ReadSharedReq misses 200111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 872103 # number of ReadSharedReq misses 200211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 270299 # number of InvalidateReq misses 200311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 270299 # number of InvalidateReq misses 200411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9658 # number of demand (read+write) misses 200511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 8172 # number of demand (read+write) misses 200611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 450693 # number of demand (read+write) misses 200711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1120347 # number of demand (read+write) misses 200811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::total 1588870 # number of demand (read+write) misses 200911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9658 # number of overall misses 201011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 8172 # number of overall misses 201111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 450693 # number of overall misses 201211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1120347 # number of overall misses 201311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::total 1588870 # number of overall misses 201411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 420391500 # number of ReadReq miss cycles 201511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 400950500 # number of ReadReq miss cycles 201611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 821342000 # number of ReadReq miss cycles 201711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3230006000 # number of UpgradeReq miss cycles 201811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 3230006000 # number of UpgradeReq miss cycles 201911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1996070000 # number of SCUpgradeReq miss cycles 202011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1996070000 # number of SCUpgradeReq miss cycles 202111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5582500 # number of SCUpgradeFailReq miss cycles 202211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5582500 # number of SCUpgradeFailReq miss cycles 202311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12845706999 # number of ReadExReq miss cycles 202411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 12845706999 # number of ReadExReq miss cycles 202511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17128169000 # number of ReadCleanReq miss cycles 202611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 17128169000 # number of ReadCleanReq miss cycles 202711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32431804500 # number of ReadSharedReq miss cycles 202811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 32431804500 # number of ReadSharedReq miss cycles 202911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18248876500 # number of InvalidateReq miss cycles 203011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 18248876500 # number of InvalidateReq miss cycles 203111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 420391500 # number of demand (read+write) miss cycles 203211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 400950500 # number of demand (read+write) miss cycles 203311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 17128169000 # number of demand (read+write) miss cycles 203411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 45277511499 # number of demand (read+write) miss cycles 203511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 63227022499 # number of demand (read+write) miss cycles 203611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 420391500 # number of overall miss cycles 203711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 400950500 # number of overall miss cycles 203811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 17128169000 # number of overall miss cycles 203911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 45277511499 # number of overall miss cycles 204011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 63227022499 # number of overall miss cycles 204111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 247196 # number of ReadReq accesses(hits+misses) 204211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 174436 # number of ReadReq accesses(hits+misses) 204311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 421632 # number of ReadReq accesses(hits+misses) 204411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3233759 # number of WritebackDirty accesses(hits+misses) 204511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3233759 # number of WritebackDirty accesses(hits+misses) 204611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 7031230 # number of WritebackClean accesses(hits+misses) 204711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 7031230 # number of WritebackClean accesses(hits+misses) 204811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 204498 # number of UpgradeReq accesses(hits+misses) 204911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 204498 # number of UpgradeReq accesses(hits+misses) 205011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195335 # number of SCUpgradeReq accesses(hits+misses) 205111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 195335 # number of SCUpgradeReq accesses(hits+misses) 205211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 15 # number of SCUpgradeFailReq accesses(hits+misses) 205311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 15 # number of SCUpgradeFailReq accesses(hits+misses) 205411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1089557 # number of ReadExReq accesses(hits+misses) 205511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1089557 # number of ReadExReq accesses(hits+misses) 205611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5153566 # number of ReadCleanReq accesses(hits+misses) 205711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 5153566 # number of ReadCleanReq accesses(hits+misses) 205811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3602298 # number of ReadSharedReq accesses(hits+misses) 205911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3602298 # number of ReadSharedReq accesses(hits+misses) 206011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 513183 # number of InvalidateReq accesses(hits+misses) 206111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 513183 # number of InvalidateReq accesses(hits+misses) 206211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 247196 # number of demand (read+write) accesses 206311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 174436 # number of demand (read+write) accesses 206411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 5153566 # number of demand (read+write) accesses 206511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4691855 # number of demand (read+write) accesses 206611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::total 10267053 # number of demand (read+write) accesses 206711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 247196 # number of overall (read+write) accesses 206811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 174436 # number of overall (read+write) accesses 206911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 5153566 # number of overall (read+write) accesses 207011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4691855 # number of overall (read+write) accesses 207111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::total 10267053 # number of overall (read+write) accesses 207211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.039070 # miss rate for ReadReq accesses 207311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046848 # miss rate for ReadReq accesses 207411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.042288 # miss rate for ReadReq accesses 207511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998230 # miss rate for UpgradeReq accesses 207611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998230 # miss rate for UpgradeReq accesses 207711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 207811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 207910535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 208010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 208111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.227839 # miss rate for ReadExReq accesses 208211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.227839 # miss rate for ReadExReq accesses 208311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.087453 # miss rate for ReadCleanReq accesses 208411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.087453 # miss rate for ReadCleanReq accesses 208511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.242096 # miss rate for ReadSharedReq accesses 208611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.242096 # miss rate for ReadSharedReq accesses 208711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.526711 # miss rate for InvalidateReq accesses 208811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.526711 # miss rate for InvalidateReq accesses 208911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.039070 # miss rate for demand accesses 209011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046848 # miss rate for demand accesses 209111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.087453 # miss rate for demand accesses 209211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238786 # miss rate for demand accesses 209311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.154754 # miss rate for demand accesses 209411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.039070 # miss rate for overall accesses 209511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046848 # miss rate for overall accesses 209611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.087453 # miss rate for overall accesses 209711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238786 # miss rate for overall accesses 209811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.154754 # miss rate for overall accesses 209911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 43527.800787 # average ReadReq miss latency 210011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 49063.937837 # average ReadReq miss latency 210111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 46065.171060 # average ReadReq miss latency 210211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15822.814202 # average UpgradeReq miss latency 210311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15822.814202 # average UpgradeReq miss latency 210411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10218.701206 # average SCUpgradeReq miss latency 210511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10218.701206 # average SCUpgradeReq miss latency 210611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 372166.666667 # average SCUpgradeFailReq miss latency 210711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 372166.666667 # average SCUpgradeFailReq miss latency 210811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51746.293965 # average ReadExReq miss latency 210911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51746.293965 # average ReadExReq miss latency 211011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38004.071508 # average ReadCleanReq miss latency 211111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38004.071508 # average ReadCleanReq miss latency 211211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37188.043729 # average ReadSharedReq miss latency 211311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37188.043729 # average ReadSharedReq miss latency 211411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 67513.666347 # average InvalidateReq miss latency 211511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 67513.666347 # average InvalidateReq miss latency 211611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 43527.800787 # average overall miss latency 211711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 49063.937837 # average overall miss latency 211811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38004.071508 # average overall miss latency 211911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40413.828483 # average overall miss latency 212011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 39793.704015 # average overall miss latency 212111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 43527.800787 # average overall miss latency 212211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 49063.937837 # average overall miss latency 212311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38004.071508 # average overall miss latency 212411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40413.828483 # average overall miss latency 212511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 39793.704015 # average overall miss latency 212610628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212710535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 212810628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 212910535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 213010628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 213110535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 213210535SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 213310535SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 213411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1066343 # number of writebacks 213511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::total 1066343 # number of writebacks 213611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3931 # number of ReadExReq MSHR hits 213711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 3931 # number of ReadExReq MSHR hits 213811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 513 # number of ReadSharedReq MSHR hits 213911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 513 # number of ReadSharedReq MSHR hits 214011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 4444 # number of demand (read+write) MSHR hits 214111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 4444 # number of demand (read+write) MSHR hits 214211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 4444 # number of overall MSHR hits 214311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 4444 # number of overall MSHR hits 214411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9658 # number of ReadReq MSHR misses 214511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8172 # number of ReadReq MSHR misses 214611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 17830 # number of ReadReq MSHR misses 214711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 644489 # number of HardPFReq MSHR misses 214811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 644489 # number of HardPFReq MSHR misses 214911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 204136 # number of UpgradeReq MSHR misses 215011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 204136 # number of UpgradeReq MSHR misses 215111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195335 # number of SCUpgradeReq MSHR misses 215211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195335 # number of SCUpgradeReq MSHR misses 215311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 15 # number of SCUpgradeFailReq MSHR misses 215411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 15 # number of SCUpgradeFailReq MSHR misses 215511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 244313 # number of ReadExReq MSHR misses 215611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 244313 # number of ReadExReq MSHR misses 215711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 450693 # number of ReadCleanReq MSHR misses 215811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 450693 # number of ReadCleanReq MSHR misses 215911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 871590 # number of ReadSharedReq MSHR misses 216011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 871590 # number of ReadSharedReq MSHR misses 216111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 270299 # number of InvalidateReq MSHR misses 216211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 270299 # number of InvalidateReq MSHR misses 216311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9658 # number of demand (read+write) MSHR misses 216411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8172 # number of demand (read+write) MSHR misses 216511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 450693 # number of demand (read+write) MSHR misses 216611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1115903 # number of demand (read+write) MSHR misses 216711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1584426 # number of demand (read+write) MSHR misses 216811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9658 # number of overall MSHR misses 216911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8172 # number of overall MSHR misses 217011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 450693 # number of overall MSHR misses 217111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1115903 # number of overall MSHR misses 217211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 644489 # number of overall MSHR misses 217311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2228915 # number of overall MSHR misses 217410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 217511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21793 # number of ReadReq MSHR uncacheable 217611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21903 # number of ReadReq MSHR uncacheable 217711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable 217811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20416 # number of WriteReq MSHR uncacheable 217910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 218011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 42209 # number of overall MSHR uncacheable misses 218111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 42319 # number of overall MSHR uncacheable misses 218211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 362443500 # number of ReadReq MSHR miss cycles 218311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 351918500 # number of ReadReq MSHR miss cycles 218411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 714362000 # number of ReadReq MSHR miss cycles 218511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28219162309 # number of HardPFReq MSHR miss cycles 218611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 28219162309 # number of HardPFReq MSHR miss cycles 218711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6506833500 # number of UpgradeReq MSHR miss cycles 218811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6506833500 # number of UpgradeReq MSHR miss cycles 218911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3878333500 # number of SCUpgradeReq MSHR miss cycles 219011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3878333500 # number of SCUpgradeReq MSHR miss cycles 219111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5228500 # number of SCUpgradeFailReq MSHR miss cycles 219211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5228500 # number of SCUpgradeFailReq MSHR miss cycles 219311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10923389999 # number of ReadExReq MSHR miss cycles 219411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10923389999 # number of ReadExReq MSHR miss cycles 219511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14424011000 # number of ReadCleanReq MSHR miss cycles 219611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14424011000 # number of ReadCleanReq MSHR miss cycles 219711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27157045000 # number of ReadSharedReq MSHR miss cycles 219811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27157045000 # number of ReadSharedReq MSHR miss cycles 219911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16627082500 # number of InvalidateReq MSHR miss cycles 220011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16627082500 # number of InvalidateReq MSHR miss cycles 220111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 362443500 # number of demand (read+write) MSHR miss cycles 220211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 351918500 # number of demand (read+write) MSHR miss cycles 220311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14424011000 # number of demand (read+write) MSHR miss cycles 220411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38080434999 # number of demand (read+write) MSHR miss cycles 220511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 53218807999 # number of demand (read+write) MSHR miss cycles 220611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 362443500 # number of overall MSHR miss cycles 220711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 351918500 # number of overall MSHR miss cycles 220811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14424011000 # number of overall MSHR miss cycles 220911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38080434999 # number of overall MSHR miss cycles 221011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28219162309 # number of overall MSHR miss cycles 221111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 81437970308 # number of overall MSHR miss cycles 221211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13974500 # number of ReadReq MSHR uncacheable cycles 221311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3856157500 # number of ReadReq MSHR uncacheable cycles 221411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3870132000 # number of ReadReq MSHR uncacheable cycles 221511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3643453500 # number of WriteReq MSHR uncacheable cycles 221611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3643453500 # number of WriteReq MSHR uncacheable cycles 221711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13974500 # number of overall MSHR uncacheable cycles 221811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7499611000 # number of overall MSHR uncacheable cycles 221911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7513585500 # number of overall MSHR uncacheable cycles 222011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for ReadReq accesses 222111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for ReadReq accesses 222211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.042288 # mshr miss rate for ReadReq accesses 222310535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 222410535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 222511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998230 # mshr miss rate for UpgradeReq accesses 222611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998230 # mshr miss rate for UpgradeReq accesses 222711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 222811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 222910535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 223010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 223111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.224231 # mshr miss rate for ReadExReq accesses 223211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.224231 # mshr miss rate for ReadExReq accesses 223311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for ReadCleanReq accesses 223411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087453 # mshr miss rate for ReadCleanReq accesses 223511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.241954 # mshr miss rate for ReadSharedReq accesses 223611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241954 # mshr miss rate for ReadSharedReq accesses 223711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.526711 # mshr miss rate for InvalidateReq accesses 223811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.526711 # mshr miss rate for InvalidateReq accesses 223911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for demand accesses 224011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for demand accesses 224111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for demand accesses 224211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237838 # mshr miss rate for demand accesses 224311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.154321 # mshr miss rate for demand accesses 224411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for overall accesses 224511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for overall accesses 224611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for overall accesses 224711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237838 # mshr miss rate for overall accesses 224810535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 224911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.217094 # mshr miss rate for overall accesses 225011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average ReadReq mshr miss latency 225111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average ReadReq mshr miss latency 225211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 40065.171060 # average ReadReq mshr miss latency 225311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average HardPFReq mshr miss latency 225411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43785.328080 # average HardPFReq mshr miss latency 225511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31874.992652 # average UpgradeReq mshr miss latency 225611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31874.992652 # average UpgradeReq mshr miss latency 225711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19854.780249 # average SCUpgradeReq mshr miss latency 225811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19854.780249 # average SCUpgradeReq mshr miss latency 225911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 348566.666667 # average SCUpgradeFailReq mshr miss latency 226011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 348566.666667 # average SCUpgradeFailReq mshr miss latency 226111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44710.637580 # average ReadExReq mshr miss latency 226211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44710.637580 # average ReadExReq mshr miss latency 226311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average ReadCleanReq mshr miss latency 226411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32004.071508 # average ReadCleanReq mshr miss latency 226511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31158.050230 # average ReadSharedReq mshr miss latency 226611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31158.050230 # average ReadSharedReq mshr miss latency 226711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61513.666347 # average InvalidateReq mshr miss latency 226811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61513.666347 # average InvalidateReq mshr miss latency 226911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency 227011245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency 227111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency 227211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency 227311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33588.698998 # average overall mshr miss latency 227411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency 227511245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency 227611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency 227711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency 227811245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average overall mshr miss latency 227911245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36537.046190 # average overall mshr miss latency 228011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average ReadReq mshr uncacheable latency 228111245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176944.775845 # average ReadReq mshr uncacheable latency 228211245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176694.151486 # average ReadReq mshr uncacheable latency 228311245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178460.692594 # average WriteReq mshr uncacheable latency 228411245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178460.692594 # average WriteReq mshr uncacheable latency 228511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average overall mshr uncacheable latency 228611245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 177678.007060 # average overall mshr uncacheable latency 228711245Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 177546.385784 # average overall mshr uncacheable latency 228810535SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 228911245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 21257827 # Total number of requests made to the snoop filter. 229011245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 10899393 # Number of requests hitting in the snoop filter with a single holder of the requested data. 229111245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 229211245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1702072 # Total number of snoops made to the snoop filter. 229311245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1701871 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 229411245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 229511245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 509534 # Transaction distribution 229611245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9349922 # Transaction distribution 229711245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 20416 # Transaction distribution 229811245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 20416 # Transaction distribution 229911245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4305236 # Transaction distribution 230011245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 7031230 # Transaction distribution 230111245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2216107 # Transaction distribution 230211245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 785182 # Transaction distribution 230311245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 389899 # Transaction distribution 230411245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353464 # Transaction distribution 230511245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 462412 # Transaction distribution 230611245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution 230711245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 230811245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1157273 # Transaction distribution 230911245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1096575 # Transaction distribution 231011245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 5153566 # Transaction distribution 231111245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4436249 # Transaction distribution 231211245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 522065 # Transaction distribution 231311245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 513183 # Transaction distribution 231411245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15459725 # Packet count per connected master and slave (bytes) 231511245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16561050 # Packet count per connected master and slave (bytes) 231611245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365076 # Packet count per connected master and slave (bytes) 231711245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544187 # Packet count per connected master and slave (bytes) 231811245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count::total 32930038 # Packet count per connected master and slave (bytes) 231911245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 659580536 # Cumulative packet size per connected master and slave (bytes) 232011245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 633491086 # Cumulative packet size per connected master and slave (bytes) 232111245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395488 # Cumulative packet size per connected master and slave (bytes) 232211245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1977568 # Cumulative packet size per connected master and slave (bytes) 232311245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1296444678 # Cumulative packet size per connected master and slave (bytes) 232411245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoops 5547167 # Total snoops (count) 232511245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 16615326 # Request fanout histogram 232611245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.116559 # Request fanout histogram 232711245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.320932 # Request fanout histogram 232810535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 232911245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 14678862 88.35% 88.35% # Request fanout histogram 233011245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 1936263 11.65% 100.00% # Request fanout histogram 233111245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 201 0.00% 100.00% # Request fanout histogram 233210535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 233311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 233410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 233511245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 16615326 # Request fanout histogram 233611245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 21053645498 # Layer occupancy (ticks) 233710535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 233811245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 168856163 # Layer occupancy (ticks) 233910535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 234011245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7730459000 # Layer occupancy (ticks) 234110535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 234211245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7526670911 # Layer occupancy (ticks) 234310535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 234411245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 190640499 # Layer occupancy (ticks) 234510535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 234611245Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 296991000 # Layer occupancy (ticks) 234710535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 234811245Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadReq 40402 # Transaction distribution 234911245Sandreas.sandberg@arm.comsystem.iobus.trans_dist::ReadResp 40402 # Transaction distribution 235011245Sandreas.sandberg@arm.comsystem.iobus.trans_dist::WriteReq 136652 # Transaction distribution 235111245Sandreas.sandberg@arm.comsystem.iobus.trans_dist::WriteResp 136652 # Transaction distribution 235211245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47834 # Packet count per connected master and slave (bytes) 235310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 235411245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 235510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 235610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 235710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 235810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 235910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 236010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 236110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 236210535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 236311245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 236410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 236511245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122768 # Packet count per connected master and slave (bytes) 236611245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231260 # Packet count per connected master and slave (bytes) 236711245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231260 # Packet count per connected master and slave (bytes) 236810535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 236910535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 237011245Sandreas.sandberg@arm.comsystem.iobus.pkt_count::total 354108 # Packet count per connected master and slave (bytes) 237111245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47854 # Cumulative packet size per connected master and slave (bytes) 237210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 237311245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 237410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 237510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 237610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 237710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 237810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 237910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 238010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 238110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 238211245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 238310535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 238411245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155875 # Cumulative packet size per connected master and slave (bytes) 238511245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339056 # Cumulative packet size per connected master and slave (bytes) 238611245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7339056 # Cumulative packet size per connected master and slave (bytes) 238710535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 238810535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 238911245Sandreas.sandberg@arm.comsystem.iobus.pkt_size::total 7497017 # Cumulative packet size per connected master and slave (bytes) 239011245Sandreas.sandberg@arm.comsystem.iobus.reqLayer0.occupancy 37033500 # Layer occupancy (ticks) 239110535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 239211201Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) 239310535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 239411245Sandreas.sandberg@arm.comsystem.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) 239510535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 239611201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 239710535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 239811245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) 239911245Sandreas.sandberg@arm.comsystem.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 240010535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 240110535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 240211201Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) 240310535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 240411201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 240510535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 240611201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 240710535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 240811201Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 240910535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 241010535SN/Asystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 241110535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 241211245Sandreas.sandberg@arm.comsystem.iobus.reqLayer23.occupancy 26450500 # Layer occupancy (ticks) 241310535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 241411245Sandreas.sandberg@arm.comsystem.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks) 241510535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 241611245Sandreas.sandberg@arm.comsystem.iobus.reqLayer25.occupancy 565570401 # Layer occupancy (ticks) 241710535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 241811245Sandreas.sandberg@arm.comsystem.iobus.respLayer0.occupancy 92847000 # Layer occupancy (ticks) 241910535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 242011245Sandreas.sandberg@arm.comsystem.iobus.respLayer3.occupancy 147956000 # Layer occupancy (ticks) 242110535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 242210892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 242310535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 242411245Sandreas.sandberg@arm.comsystem.iocache.tags.replacements 115605 # number of replacements 242511245Sandreas.sandberg@arm.comsystem.iocache.tags.tagsinuse 11.294118 # Cycle average of tags in use 242611245Sandreas.sandberg@arm.comsystem.iocache.tags.total_refs 10 # Total number of references to valid blocks. 242711245Sandreas.sandberg@arm.comsystem.iocache.tags.sampled_refs 115621 # Sample count of references to valid blocks. 242811245Sandreas.sandberg@arm.comsystem.iocache.tags.avg_refs 0.000086 # Average number of references to valid blocks. 242911245Sandreas.sandberg@arm.comsystem.iocache.tags.warmup_cycle 9206098021000 # Cycle when the warmup percentage was hit. 243011245Sandreas.sandberg@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.822126 # Average occupied blocks per requestor 243111245Sandreas.sandberg@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.471992 # Average occupied blocks per requestor 243211245Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.238883 # Average percentage of cache occupancy 243311245Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy 243411245Sandreas.sandberg@arm.comsystem.iocache.tags.occ_percent::total 0.705882 # Average percentage of cache occupancy 243510535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 243610535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 243710535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 243811245Sandreas.sandberg@arm.comsystem.iocache.tags.tag_accesses 1041013 # Number of tag accesses 243911245Sandreas.sandberg@arm.comsystem.iocache.tags.data_accesses 1041013 # Number of data accesses 244011245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_hits::realview.ide 5 # number of WriteLineReq hits 244111245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_hits::total 5 # number of WriteLineReq hits 244210535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 244311245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses 244411245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_misses::total 8939 # number of ReadReq misses 244510535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 244610535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 244711245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106723 # number of WriteLineReq misses 244811245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_misses::total 106723 # number of WriteLineReq misses 244910535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 245011245Sandreas.sandberg@arm.comsystem.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses 245111245Sandreas.sandberg@arm.comsystem.iocache.demand_misses::total 8942 # number of demand (read+write) misses 245210535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 245311245Sandreas.sandberg@arm.comsystem.iocache.overall_misses::realview.ide 8902 # number of overall misses 245411245Sandreas.sandberg@arm.comsystem.iocache.overall_misses::total 8942 # number of overall misses 245511201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 245611245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1679170514 # number of ReadReq miss cycles 245711245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_miss_latency::total 1684370014 # number of ReadReq miss cycles 245810726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 245910726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 246011245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13974494387 # number of WriteLineReq miss cycles 246111245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13974494387 # number of WriteLineReq miss cycles 246211201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles 246311245Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::realview.ide 1679170514 # number of demand (read+write) miss cycles 246411245Sandreas.sandberg@arm.comsystem.iocache.demand_miss_latency::total 1684739014 # number of demand (read+write) miss cycles 246511201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles 246611245Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::realview.ide 1679170514 # number of overall miss cycles 246711245Sandreas.sandberg@arm.comsystem.iocache.overall_miss_latency::total 1684739014 # number of overall miss cycles 246810535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 246911245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) 247011245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) 247110535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 247210535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 247311245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 247411245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 247510535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 247611245Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses 247711245Sandreas.sandberg@arm.comsystem.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses 247810535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 247911245Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses 248011245Sandreas.sandberg@arm.comsystem.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses 248110535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 248210535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 248310535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 248410535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 248510535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 248611245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 0.999953 # miss rate for WriteLineReq accesses 248711245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_miss_rate::total 0.999953 # miss rate for WriteLineReq accesses 248810535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 248910535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 249010535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 249110535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 249210535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 249310535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 249411201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 249511245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 188628.455853 # average ReadReq miss latency 249611245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 188429.356080 # average ReadReq miss latency 249710726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 249810726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 249911245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 130941.731276 # average WriteLineReq miss latency 250011245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 130941.731276 # average WriteLineReq miss latency 250111201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 250211245Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency 250311245Sandreas.sandberg@arm.comsystem.iocache.demand_avg_miss_latency::total 188407.404831 # average overall miss latency 250411201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 250511245Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency 250611245Sandreas.sandberg@arm.comsystem.iocache.overall_avg_miss_latency::total 188407.404831 # average overall miss latency 250711245Sandreas.sandberg@arm.comsystem.iocache.blocked_cycles::no_mshrs 35755 # number of cycles access was blocked 250810535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 250911245Sandreas.sandberg@arm.comsystem.iocache.blocked::no_mshrs 3742 # number of cycles access was blocked 251010535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 251111245Sandreas.sandberg@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.555051 # average number of cycles each access was blocked 251210535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 251310585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 251410535SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 251511245Sandreas.sandberg@arm.comsystem.iocache.writebacks::writebacks 106695 # number of writebacks 251611245Sandreas.sandberg@arm.comsystem.iocache.writebacks::total 106695 # number of writebacks 251710535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 251811245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses 251911245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses 252010535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 252110535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 252211245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106723 # number of WriteLineReq MSHR misses 252311245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106723 # number of WriteLineReq MSHR misses 252410535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 252511245Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses 252611245Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses 252710535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 252811245Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses 252911245Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses 253011201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 253111245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1234070514 # number of ReadReq MSHR miss cycles 253211245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1237420014 # number of ReadReq MSHR miss cycles 253310892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 253410892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 253511245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8638344387 # number of WriteLineReq MSHR miss cycles 253611245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8638344387 # number of WriteLineReq MSHR miss cycles 253711201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles 253811245Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1234070514 # number of demand (read+write) MSHR miss cycles 253911245Sandreas.sandberg@arm.comsystem.iocache.demand_mshr_miss_latency::total 1237639014 # number of demand (read+write) MSHR miss cycles 254011201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles 254111245Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1234070514 # number of overall MSHR miss cycles 254211245Sandreas.sandberg@arm.comsystem.iocache.overall_mshr_miss_latency::total 1237639014 # number of overall MSHR miss cycles 254310535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 254410535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 254510535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 254610535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 254710535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 254811245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999953 # mshr miss rate for WriteLineReq accesses 254911245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 0.999953 # mshr miss rate for WriteLineReq accesses 255010535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 255110535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 255210535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 255310535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 255410535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 255510535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 255611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 255711245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138628.455853 # average ReadReq mshr miss latency 255811245Sandreas.sandberg@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 138429.356080 # average ReadReq mshr miss latency 255910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 256010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 256111245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80941.731276 # average WriteLineReq mshr miss latency 256211245Sandreas.sandberg@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 80941.731276 # average WriteLineReq mshr miss latency 256311201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 256411245Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency 256511245Sandreas.sandberg@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency 256611201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 256711245Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency 256811245Sandreas.sandberg@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency 256910535SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 257011245Sandreas.sandberg@arm.comsystem.l2c.tags.replacements 1201728 # number of replacements 257111245Sandreas.sandberg@arm.comsystem.l2c.tags.tagsinuse 62776.329461 # Cycle average of tags in use 257211245Sandreas.sandberg@arm.comsystem.l2c.tags.total_refs 5149298 # Total number of references to valid blocks. 257311245Sandreas.sandberg@arm.comsystem.l2c.tags.sampled_refs 1259663 # Sample count of references to valid blocks. 257411245Sandreas.sandberg@arm.comsystem.l2c.tags.avg_refs 4.087838 # Average number of references to valid blocks. 257510892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 257611245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::writebacks 23700.762045 # Average occupied blocks per requestor 257711245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 102.528322 # Average occupied blocks per requestor 257811245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 175.969290 # Average occupied blocks per requestor 257911245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4011.755779 # Average occupied blocks per requestor 258011245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 5217.555279 # Average occupied blocks per requestor 258111245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7227.978697 # Average occupied blocks per requestor 258211245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 166.263944 # Average occupied blocks per requestor 258311245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 281.111554 # Average occupied blocks per requestor 258411245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3722.000784 # Average occupied blocks per requestor 258511245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 8039.407020 # Average occupied blocks per requestor 258611245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10130.996747 # Average occupied blocks per requestor 258711245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::writebacks 0.361645 # Average percentage of cache occupancy 258811245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.001564 # Average percentage of cache occupancy 258911245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.002685 # Average percentage of cache occupancy 259011245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.061215 # Average percentage of cache occupancy 259111245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.079614 # Average percentage of cache occupancy 259211245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110290 # Average percentage of cache occupancy 259311245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.002537 # Average percentage of cache occupancy 259411245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.004289 # Average percentage of cache occupancy 259511245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.056793 # Average percentage of cache occupancy 259611245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.122672 # Average percentage of cache occupancy 259711245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.154587 # Average percentage of cache occupancy 259811245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::total 0.957891 # Average percentage of cache occupancy 259911245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 9737 # Occupied blocks per task id 260011245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 265 # Occupied blocks per task id 260111245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 47933 # Occupied blocks per task id 260211245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 59 # Occupied blocks per task id 260311245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 277 # Occupied blocks per task id 260411245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 9401 # Occupied blocks per task id 260511245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 260611245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 264 # Occupied blocks per task id 260711245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 260811245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id 260911245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1658 # Occupied blocks per task id 261011245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5230 # Occupied blocks per task id 261111245Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 40901 # Occupied blocks per task id 261211245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.148575 # Percentage of cache occupancy per task id 261311245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.004044 # Percentage of cache occupancy per task id 261411245Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.731400 # Percentage of cache occupancy per task id 261511245Sandreas.sandberg@arm.comsystem.l2c.tags.tag_accesses 66235328 # Number of tag accesses 261611245Sandreas.sandberg@arm.comsystem.l2c.tags.data_accesses 66235328 # Number of data accesses 261711245Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2474359 # number of WritebackDirty hits 261811245Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::total 2474359 # number of WritebackDirty hits 261911245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 150616 # number of UpgradeReq hits 262011245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 127305 # number of UpgradeReq hits 262111245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::total 277921 # number of UpgradeReq hits 262211245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 34718 # number of SCUpgradeReq hits 262311245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 37539 # number of SCUpgradeReq hits 262411245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::total 72257 # number of SCUpgradeReq hits 262511245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 146279 # number of ReadExReq hits 262611245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 167990 # number of ReadExReq hits 262711245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::total 314269 # number of ReadExReq hits 262811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4627 # number of ReadSharedReq hits 262911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3559 # number of ReadSharedReq hits 263011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 390104 # number of ReadSharedReq hits 263111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 513889 # number of ReadSharedReq hits 263211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 259608 # number of ReadSharedReq hits 263311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5392 # number of ReadSharedReq hits 263411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4493 # number of ReadSharedReq hits 263511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 410490 # number of ReadSharedReq hits 263611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 516454 # number of ReadSharedReq hits 263711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 291033 # number of ReadSharedReq hits 263811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::total 2399649 # number of ReadSharedReq hits 263911245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 4627 # number of demand (read+write) hits 264011245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3559 # number of demand (read+write) hits 264111245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.inst 390104 # number of demand (read+write) hits 264211245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.data 660168 # number of demand (read+write) hits 264311245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 259608 # number of demand (read+write) hits 264411245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5392 # number of demand (read+write) hits 264511245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4493 # number of demand (read+write) hits 264611245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.inst 410490 # number of demand (read+write) hits 264711245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.data 684444 # number of demand (read+write) hits 264811245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 291033 # number of demand (read+write) hits 264911245Sandreas.sandberg@arm.comsystem.l2c.demand_hits::total 2713918 # number of demand (read+write) hits 265011245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 4627 # number of overall hits 265111245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3559 # number of overall hits 265211245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.inst 390104 # number of overall hits 265311245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.data 660168 # number of overall hits 265411245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 259608 # number of overall hits 265511245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5392 # number of overall hits 265611245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4493 # number of overall hits 265711245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.inst 410490 # number of overall hits 265811245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.data 684444 # number of overall hits 265911245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 291033 # number of overall hits 266011245Sandreas.sandberg@arm.comsystem.l2c.overall_hits::total 2713918 # number of overall hits 266111245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 62469 # number of UpgradeReq misses 266211245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 57486 # number of UpgradeReq misses 266311245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::total 119955 # number of UpgradeReq misses 266411245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 13684 # number of SCUpgradeReq misses 266511245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 12909 # number of SCUpgradeReq misses 266611245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 26593 # number of SCUpgradeReq misses 266711245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 477377 # number of ReadExReq misses 266811245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 148178 # number of ReadExReq misses 266911245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::total 625555 # number of ReadExReq misses 267011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1085 # number of ReadSharedReq misses 267111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1066 # number of ReadSharedReq misses 267211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 45695 # number of ReadSharedReq misses 267311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 111052 # number of ReadSharedReq misses 267411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 202654 # number of ReadSharedReq misses 267511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1546 # number of ReadSharedReq misses 267611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1684 # number of ReadSharedReq misses 267711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 40203 # number of ReadSharedReq misses 267811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 92070 # number of ReadSharedReq misses 267911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 143125 # number of ReadSharedReq misses 268011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::total 640180 # number of ReadSharedReq misses 268111245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1085 # number of demand (read+write) misses 268211245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1066 # number of demand (read+write) misses 268311245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.inst 45695 # number of demand (read+write) misses 268411245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.data 588429 # number of demand (read+write) misses 268511245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 202654 # number of demand (read+write) misses 268611245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1546 # number of demand (read+write) misses 268711245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1684 # number of demand (read+write) misses 268811245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.inst 40203 # number of demand (read+write) misses 268911245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.data 240248 # number of demand (read+write) misses 269011245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 143125 # number of demand (read+write) misses 269111245Sandreas.sandberg@arm.comsystem.l2c.demand_misses::total 1265735 # number of demand (read+write) misses 269211245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1085 # number of overall misses 269311245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1066 # number of overall misses 269411245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.inst 45695 # number of overall misses 269511245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.data 588429 # number of overall misses 269611245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 202654 # number of overall misses 269711245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1546 # number of overall misses 269811245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1684 # number of overall misses 269911245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.inst 40203 # number of overall misses 270011245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.data 240248 # number of overall misses 270111245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 143125 # number of overall misses 270211245Sandreas.sandberg@arm.comsystem.l2c.overall_misses::total 1265735 # number of overall misses 270311245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 928670500 # number of UpgradeReq miss cycles 270411245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 1025251000 # number of UpgradeReq miss cycles 270511245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::total 1953921500 # number of UpgradeReq miss cycles 270611245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 178207000 # number of SCUpgradeReq miss cycles 270711245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 182538500 # number of SCUpgradeReq miss cycles 270811245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 360745500 # number of SCUpgradeReq miss cycles 270911245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 63116930500 # number of ReadExReq miss cycles 271011245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 19400961500 # number of ReadExReq miss cycles 271111245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_latency::total 82517892000 # number of ReadExReq miss cycles 271211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 153728000 # number of ReadSharedReq miss cycles 271311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 149604000 # number of ReadSharedReq miss cycles 271411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 6143069000 # number of ReadSharedReq miss cycles 271511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 15249907500 # number of ReadSharedReq miss cycles 271611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of ReadSharedReq miss cycles 271711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 212651500 # number of ReadSharedReq miss cycles 271811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 233752000 # number of ReadSharedReq miss cycles 271911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 5417778000 # number of ReadSharedReq miss cycles 272011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 12722216500 # number of ReadSharedReq miss cycles 272111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of ReadSharedReq miss cycles 272211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 96202750409 # number of ReadSharedReq miss cycles 272311245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 153728000 # number of demand (read+write) miss cycles 272411245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 149604000 # number of demand (read+write) miss cycles 272511245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 6143069000 # number of demand (read+write) miss cycles 272611245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.data 78366838000 # number of demand (read+write) miss cycles 272711245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of demand (read+write) miss cycles 272811245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 212651500 # number of demand (read+write) miss cycles 272911245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 233752000 # number of demand (read+write) miss cycles 273011245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 5417778000 # number of demand (read+write) miss cycles 273111245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.data 32123178000 # number of demand (read+write) miss cycles 273211245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of demand (read+write) miss cycles 273311245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_latency::total 178720642409 # number of demand (read+write) miss cycles 273411245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 153728000 # number of overall miss cycles 273511245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 149604000 # number of overall miss cycles 273611245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 6143069000 # number of overall miss cycles 273711245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.data 78366838000 # number of overall miss cycles 273811245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of overall miss cycles 273911245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 212651500 # number of overall miss cycles 274011245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 233752000 # number of overall miss cycles 274111245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 5417778000 # number of overall miss cycles 274211245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.data 32123178000 # number of overall miss cycles 274311245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of overall miss cycles 274411245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_latency::total 178720642409 # number of overall miss cycles 274511245Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2474359 # number of WritebackDirty accesses(hits+misses) 274611245Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::total 2474359 # number of WritebackDirty accesses(hits+misses) 274711245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 213085 # number of UpgradeReq accesses(hits+misses) 274811245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 184791 # number of UpgradeReq accesses(hits+misses) 274911245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::total 397876 # number of UpgradeReq accesses(hits+misses) 275011245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 48402 # number of SCUpgradeReq accesses(hits+misses) 275111245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 50448 # number of SCUpgradeReq accesses(hits+misses) 275211245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::total 98850 # number of SCUpgradeReq accesses(hits+misses) 275311245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 623656 # number of ReadExReq accesses(hits+misses) 275411245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 316168 # number of ReadExReq accesses(hits+misses) 275511245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::total 939824 # number of ReadExReq accesses(hits+misses) 275611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 5712 # number of ReadSharedReq accesses(hits+misses) 275711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4625 # number of ReadSharedReq accesses(hits+misses) 275811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 435799 # number of ReadSharedReq accesses(hits+misses) 275911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 624941 # number of ReadSharedReq accesses(hits+misses) 276011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 462262 # number of ReadSharedReq accesses(hits+misses) 276111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6938 # number of ReadSharedReq accesses(hits+misses) 276211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6177 # number of ReadSharedReq accesses(hits+misses) 276311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 450693 # number of ReadSharedReq accesses(hits+misses) 276411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 608524 # number of ReadSharedReq accesses(hits+misses) 276511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 434158 # number of ReadSharedReq accesses(hits+misses) 276611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::total 3039829 # number of ReadSharedReq accesses(hits+misses) 276711245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 5712 # number of demand (read+write) accesses 276811245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 4625 # number of demand (read+write) accesses 276911245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.inst 435799 # number of demand (read+write) accesses 277011245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.data 1248597 # number of demand (read+write) accesses 277111245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 462262 # number of demand (read+write) accesses 277211245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 6938 # number of demand (read+write) accesses 277311245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 6177 # number of demand (read+write) accesses 277411245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.inst 450693 # number of demand (read+write) accesses 277511245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.data 924692 # number of demand (read+write) accesses 277611245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 434158 # number of demand (read+write) accesses 277711245Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::total 3979653 # number of demand (read+write) accesses 277811245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 5712 # number of overall (read+write) accesses 277911245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 4625 # number of overall (read+write) accesses 278011245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.inst 435799 # number of overall (read+write) accesses 278111245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.data 1248597 # number of overall (read+write) accesses 278211245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 462262 # number of overall (read+write) accesses 278311245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 6938 # number of overall (read+write) accesses 278411245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 6177 # number of overall (read+write) accesses 278511245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.inst 450693 # number of overall (read+write) accesses 278611245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.data 924692 # number of overall (read+write) accesses 278711245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 434158 # number of overall (read+write) accesses 278811245Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::total 3979653 # number of overall (read+write) accesses 278911245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.293165 # miss rate for UpgradeReq accesses 279011245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.311087 # miss rate for UpgradeReq accesses 279111245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.301488 # miss rate for UpgradeReq accesses 279211245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.282716 # miss rate for SCUpgradeReq accesses 279311245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.255887 # miss rate for SCUpgradeReq accesses 279411245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.269024 # miss rate for SCUpgradeReq accesses 279511245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.765449 # miss rate for ReadExReq accesses 279611245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.468669 # miss rate for ReadExReq accesses 279711245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.665609 # miss rate for ReadExReq accesses 279811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.189951 # miss rate for ReadSharedReq accesses 279911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.230486 # miss rate for ReadSharedReq accesses 280011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.104853 # miss rate for ReadSharedReq accesses 280111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.177700 # miss rate for ReadSharedReq accesses 280211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.438396 # miss rate for ReadSharedReq accesses 280311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.222831 # miss rate for ReadSharedReq accesses 280411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.272624 # miss rate for ReadSharedReq accesses 280511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089203 # miss rate for ReadSharedReq accesses 280611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.151301 # miss rate for ReadSharedReq accesses 280711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.329661 # miss rate for ReadSharedReq accesses 280811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.210597 # miss rate for ReadSharedReq accesses 280911245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.189951 # miss rate for demand accesses 281011245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.230486 # miss rate for demand accesses 281111245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.104853 # miss rate for demand accesses 281211245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.471272 # miss rate for demand accesses 281311245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.438396 # miss rate for demand accesses 281411245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.222831 # miss rate for demand accesses 281511245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.272624 # miss rate for demand accesses 281611245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.089203 # miss rate for demand accesses 281711245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.259814 # miss rate for demand accesses 281811245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.329661 # miss rate for demand accesses 281911245Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::total 0.318052 # miss rate for demand accesses 282011245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.189951 # miss rate for overall accesses 282111245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.230486 # miss rate for overall accesses 282211245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.104853 # miss rate for overall accesses 282311245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.471272 # miss rate for overall accesses 282411245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.438396 # miss rate for overall accesses 282511245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.222831 # miss rate for overall accesses 282611245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.272624 # miss rate for overall accesses 282711245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.089203 # miss rate for overall accesses 282811245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.259814 # miss rate for overall accesses 282911245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.329661 # miss rate for overall accesses 283011245Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::total 0.318052 # miss rate for overall accesses 283111245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14866.101586 # average UpgradeReq miss latency 283211245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17834.794559 # average UpgradeReq miss latency 283311245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 16288.787462 # average UpgradeReq miss latency 283411245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13023.019585 # average SCUpgradeReq miss latency 283511245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14140.405918 # average SCUpgradeReq miss latency 283611245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 13565.430752 # average SCUpgradeReq miss latency 283711245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 132216.111166 # average ReadExReq miss latency 283811245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 130930.107708 # average ReadExReq miss latency 283911245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 131911.489797 # average ReadExReq miss latency 284011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141684.792627 # average ReadSharedReq miss latency 284111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140341.463415 # average ReadSharedReq miss latency 284211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134436.349710 # average ReadSharedReq miss latency 284311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137322.222923 # average ReadSharedReq miss latency 284411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888 # average ReadSharedReq miss latency 284511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 137549.482536 # average ReadSharedReq miss latency 284611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 138807.600950 # average ReadSharedReq miss latency 284711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134760.540258 # average ReadSharedReq miss latency 284811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138179.825133 # average ReadSharedReq miss latency 284911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093 # average ReadSharedReq miss latency 285011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 150274.532802 # average ReadSharedReq miss latency 285111245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141684.792627 # average overall miss latency 285211245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 140341.463415 # average overall miss latency 285311245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 134436.349710 # average overall miss latency 285411245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 133179.768502 # average overall miss latency 285511245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888 # average overall miss latency 285611245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137549.482536 # average overall miss latency 285711245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 138807.600950 # average overall miss latency 285811245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 134760.540258 # average overall miss latency 285911245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 133708.409643 # average overall miss latency 286011245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093 # average overall miss latency 286111245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_miss_latency::total 141199.099661 # average overall miss latency 286211245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141684.792627 # average overall miss latency 286311245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 140341.463415 # average overall miss latency 286411245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 134436.349710 # average overall miss latency 286511245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 133179.768502 # average overall miss latency 286611245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888 # average overall miss latency 286711245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137549.482536 # average overall miss latency 286811245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 138807.600950 # average overall miss latency 286911245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 134760.540258 # average overall miss latency 287011245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 133708.409643 # average overall miss latency 287111245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093 # average overall miss latency 287211245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_miss_latency::total 141199.099661 # average overall miss latency 287311245Sandreas.sandberg@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 287410515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 287511245Sandreas.sandberg@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 287610515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 287711245Sandreas.sandberg@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 287810515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 287910515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 288010515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 288111245Sandreas.sandberg@arm.comsystem.l2c.writebacks::writebacks 969294 # number of writebacks 288211245Sandreas.sandberg@arm.comsystem.l2c.writebacks::total 969294 # number of writebacks 288311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 118 # number of ReadSharedReq MSHR hits 288411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 27 # number of ReadSharedReq MSHR hits 288511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 91 # number of ReadSharedReq MSHR hits 288611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 23 # number of ReadSharedReq MSHR hits 288711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 259 # number of ReadSharedReq MSHR hits 288811245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 118 # number of demand (read+write) MSHR hits 288911245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 27 # number of demand (read+write) MSHR hits 289011245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 91 # number of demand (read+write) MSHR hits 289111245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits 289211245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits 289311245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 118 # number of overall MSHR hits 289411245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 27 # number of overall MSHR hits 289511245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 91 # number of overall MSHR hits 289611245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits 289711245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_hits::total 259 # number of overall MSHR hits 289811245Sandreas.sandberg@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 39496 # number of CleanEvict MSHR misses 289911245Sandreas.sandberg@arm.comsystem.l2c.CleanEvict_mshr_misses::total 39496 # number of CleanEvict MSHR misses 290011245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 62469 # number of UpgradeReq MSHR misses 290111245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 57486 # number of UpgradeReq MSHR misses 290211245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 119955 # number of UpgradeReq MSHR misses 290311245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13684 # number of SCUpgradeReq MSHR misses 290411245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12909 # number of SCUpgradeReq MSHR misses 290511245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 26593 # number of SCUpgradeReq MSHR misses 290611245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 477377 # number of ReadExReq MSHR misses 290711245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 148178 # number of ReadExReq MSHR misses 290811245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_misses::total 625555 # number of ReadExReq MSHR misses 290911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1085 # number of ReadSharedReq MSHR misses 291011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1066 # number of ReadSharedReq MSHR misses 291111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45577 # number of ReadSharedReq MSHR misses 291211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 111025 # number of ReadSharedReq MSHR misses 291311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 202654 # number of ReadSharedReq MSHR misses 291411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1546 # number of ReadSharedReq MSHR misses 291511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1684 # number of ReadSharedReq MSHR misses 291611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 40112 # number of ReadSharedReq MSHR misses 291711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 92047 # number of ReadSharedReq MSHR misses 291811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 143125 # number of ReadSharedReq MSHR misses 291911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 639921 # number of ReadSharedReq MSHR misses 292011245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1085 # number of demand (read+write) MSHR misses 292111245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1066 # number of demand (read+write) MSHR misses 292211245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 45577 # number of demand (read+write) MSHR misses 292311245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 588402 # number of demand (read+write) MSHR misses 292411245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 202654 # number of demand (read+write) MSHR misses 292511245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1546 # number of demand (read+write) MSHR misses 292611245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 1684 # number of demand (read+write) MSHR misses 292711245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 40112 # number of demand (read+write) MSHR misses 292811245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 240225 # number of demand (read+write) MSHR misses 292911245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 143125 # number of demand (read+write) MSHR misses 293011245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_misses::total 1265476 # number of demand (read+write) MSHR misses 293111245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1085 # number of overall MSHR misses 293211245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1066 # number of overall MSHR misses 293311245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 45577 # number of overall MSHR misses 293411245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 588402 # number of overall MSHR misses 293511245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 202654 # number of overall MSHR misses 293611245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 1546 # number of overall MSHR misses 293711245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 1684 # number of overall MSHR misses 293811245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 40112 # number of overall MSHR misses 293911245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 240225 # number of overall MSHR misses 294011245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 143125 # number of overall MSHR misses 294111245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_misses::total 1265476 # number of overall MSHR misses 294210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 294311245Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 16746 # number of ReadReq MSHR uncacheable 294410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 294511245Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 21791 # number of ReadReq MSHR uncacheable 294611245Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 81772 # number of ReadReq MSHR uncacheable 294711245Sandreas.sandberg@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 17968 # number of WriteReq MSHR uncacheable 294811245Sandreas.sandberg@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable 294911245Sandreas.sandberg@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38384 # number of WriteReq MSHR uncacheable 295010827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 295111245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 34714 # number of overall MSHR uncacheable misses 295210827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 295311245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 42207 # number of overall MSHR uncacheable misses 295411245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 120156 # number of overall MSHR uncacheable misses 295511245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4603464500 # number of UpgradeReq MSHR miss cycles 295611245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4224060500 # number of UpgradeReq MSHR miss cycles 295711245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_latency::total 8827525000 # number of UpgradeReq MSHR miss cycles 295811245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1048639500 # number of SCUpgradeReq MSHR miss cycles 295911245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 988070500 # number of SCUpgradeReq MSHR miss cycles 296011245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_latency::total 2036710000 # number of SCUpgradeReq MSHR miss cycles 296111245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu0.data 58343160500 # number of ReadExReq MSHR miss cycles 296211245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::cpu1.data 17919181500 # number of ReadExReq MSHR miss cycles 296311245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_latency::total 76262342000 # number of ReadExReq MSHR miss cycles 296411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 142878000 # number of ReadSharedReq MSHR miss cycles 296511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 138944000 # number of ReadSharedReq MSHR miss cycles 296611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5673195000 # number of ReadSharedReq MSHR miss cycles 296711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14136518000 # number of ReadSharedReq MSHR miss cycles 296811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30821758905 # number of ReadSharedReq MSHR miss cycles 296911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 197191500 # number of ReadSharedReq MSHR miss cycles 297011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 216912000 # number of ReadSharedReq MSHR miss cycles 297111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5007052000 # number of ReadSharedReq MSHR miss cycles 297211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11798625000 # number of ReadSharedReq MSHR miss cycles 297311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21640495004 # number of ReadSharedReq MSHR miss cycles 297411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_latency::total 89773569409 # number of ReadSharedReq MSHR miss cycles 297511245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 142878000 # number of demand (read+write) MSHR miss cycles 297611245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.itb.walker 138944000 # number of demand (read+write) MSHR miss cycles 297711245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.inst 5673195000 # number of demand (read+write) MSHR miss cycles 297811245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.data 72479678500 # number of demand (read+write) MSHR miss cycles 297911245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30821758905 # number of demand (read+write) MSHR miss cycles 298011245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197191500 # number of demand (read+write) MSHR miss cycles 298111245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.itb.walker 216912000 # number of demand (read+write) MSHR miss cycles 298211245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.inst 5007052000 # number of demand (read+write) MSHR miss cycles 298311245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.data 29717806500 # number of demand (read+write) MSHR miss cycles 298411245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21640495004 # number of demand (read+write) MSHR miss cycles 298511245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_latency::total 166035911409 # number of demand (read+write) MSHR miss cycles 298611245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 142878000 # number of overall MSHR miss cycles 298711245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.itb.walker 138944000 # number of overall MSHR miss cycles 298811245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.inst 5673195000 # number of overall MSHR miss cycles 298911245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.data 72479678500 # number of overall MSHR miss cycles 299011245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30821758905 # number of overall MSHR miss cycles 299111245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197191500 # number of overall MSHR miss cycles 299211245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.itb.walker 216912000 # number of overall MSHR miss cycles 299311245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.inst 5007052000 # number of overall MSHR miss cycles 299411245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.data 29717806500 # number of overall MSHR miss cycles 299511245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21640495004 # number of overall MSHR miss cycles 299611245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_latency::total 166035911409 # number of overall MSHR miss cycles 299711201Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles 299811245Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2461668000 # number of ReadReq MSHR uncacheable cycles 299911201Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11994000 # number of ReadReq MSHR uncacheable cycles 300011245Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3463851500 # number of ReadReq MSHR uncacheable cycles 300111245Sandreas.sandberg@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 10792034500 # number of ReadReq MSHR uncacheable cycles 300211245Sandreas.sandberg@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2661815500 # number of WriteReq MSHR uncacheable cycles 300311245Sandreas.sandberg@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3296062500 # number of WriteReq MSHR uncacheable cycles 300411245Sandreas.sandberg@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 5957878000 # number of WriteReq MSHR uncacheable cycles 300511201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles 300611245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 5123483500 # number of overall MSHR uncacheable cycles 300711201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11994000 # number of overall MSHR uncacheable cycles 300811245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 6759914000 # number of overall MSHR uncacheable cycles 300911245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 16749912500 # number of overall MSHR uncacheable cycles 301010892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 301110892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 301211245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.293165 # mshr miss rate for UpgradeReq accesses 301311245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.311087 # mshr miss rate for UpgradeReq accesses 301411245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.301488 # mshr miss rate for UpgradeReq accesses 301511245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.282716 # mshr miss rate for SCUpgradeReq accesses 301611245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.255887 # mshr miss rate for SCUpgradeReq accesses 301711245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.269024 # mshr miss rate for SCUpgradeReq accesses 301811245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.765449 # mshr miss rate for ReadExReq accesses 301911245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468669 # mshr miss rate for ReadExReq accesses 302011245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.665609 # mshr miss rate for ReadExReq accesses 302111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for ReadSharedReq accesses 302211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for ReadSharedReq accesses 302311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for ReadSharedReq accesses 302411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.177657 # mshr miss rate for ReadSharedReq accesses 302511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for ReadSharedReq accesses 302611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for ReadSharedReq accesses 302711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for ReadSharedReq accesses 302811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for ReadSharedReq accesses 302911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.151263 # mshr miss rate for ReadSharedReq accesses 303011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for ReadSharedReq accesses 303111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.210512 # mshr miss rate for ReadSharedReq accesses 303211245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for demand accesses 303311245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for demand accesses 303411245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for demand accesses 303511245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.471251 # mshr miss rate for demand accesses 303611245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for demand accesses 303711245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for demand accesses 303811245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for demand accesses 303911245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for demand accesses 304011245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.259789 # mshr miss rate for demand accesses 304111245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for demand accesses 304211245Sandreas.sandberg@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.317987 # mshr miss rate for demand accesses 304311245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for overall accesses 304411245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for overall accesses 304511245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for overall accesses 304611245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.471251 # mshr miss rate for overall accesses 304711245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for overall accesses 304811245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for overall accesses 304911245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for overall accesses 305011245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for overall accesses 305111245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.259789 # mshr miss rate for overall accesses 305211245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for overall accesses 305311245Sandreas.sandberg@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.317987 # mshr miss rate for overall accesses 305411245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73691.983224 # average UpgradeReq mshr miss latency 305511245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73479.812476 # average UpgradeReq mshr miss latency 305611245Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 73590.304698 # average UpgradeReq mshr miss latency 305711245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76632.527039 # average SCUpgradeReq mshr miss latency 305811245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76541.211558 # average SCUpgradeReq mshr miss latency 305911245Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76588.199902 # average SCUpgradeReq mshr miss latency 306011245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122216.111166 # average ReadExReq mshr miss latency 306111245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120930.107708 # average ReadExReq mshr miss latency 306211245Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 121911.489797 # average ReadExReq mshr miss latency 306311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average ReadSharedReq mshr miss latency 306411245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average ReadSharedReq mshr miss latency 306511245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average ReadSharedReq mshr miss latency 306611245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127327.340689 # average ReadSharedReq mshr miss latency 306711245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average ReadSharedReq mshr miss latency 306811245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average ReadSharedReq mshr miss latency 306911245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average ReadSharedReq mshr miss latency 307011245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average ReadSharedReq mshr miss latency 307111245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128180.440427 # average ReadSharedReq mshr miss latency 307211245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average ReadSharedReq mshr miss latency 307311245Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140288.519066 # average ReadSharedReq mshr miss latency 307411245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency 307511245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency 307611245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency 307711245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency 307811245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency 307911245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency 308011245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency 308111245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency 308211245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency 308311245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency 308411245Sandreas.sandberg@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency 308511245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency 308611245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency 308711245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency 308811245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency 308911245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency 309011245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency 309111245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency 309211245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency 309311245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency 309411245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency 309511245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency 309611201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency 309711245Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 147000.358295 # average ReadReq mshr uncacheable latency 309811201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average ReadReq mshr uncacheable latency 309911245Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158957.895461 # average ReadReq mshr uncacheable latency 310011245Sandreas.sandberg@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131977.137651 # average ReadReq mshr uncacheable latency 310111245Sandreas.sandberg@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148142.002449 # average WriteReq mshr uncacheable latency 310211245Sandreas.sandberg@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161445.067594 # average WriteReq mshr uncacheable latency 310311245Sandreas.sandberg@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155217.746978 # average WriteReq mshr uncacheable latency 310411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency 310511245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147591.274414 # average overall mshr uncacheable latency 310611201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average overall mshr uncacheable latency 310711245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160160.968560 # average overall mshr uncacheable latency 310811245Sandreas.sandberg@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 139401.382370 # average overall mshr uncacheable latency 310910515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 311011245Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadReq 81772 # Transaction distribution 311111245Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 730632 # Transaction distribution 311211245Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteReq 38384 # Transaction distribution 311311245Sandreas.sandberg@arm.comsystem.membus.trans_dist::WriteResp 38384 # Transaction distribution 311411245Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 1075989 # Transaction distribution 311511245Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 189758 # Transaction distribution 311611245Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 405662 # Transaction distribution 311711245Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeReq 313696 # Transaction distribution 311811245Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeResp 154281 # Transaction distribution 311911245Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 640388 # Transaction distribution 312011245Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 617827 # Transaction distribution 312111245Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 648860 # Transaction distribution 312211245Sandreas.sandberg@arm.comsystem.membus.trans_dist::InvalidateReq 106721 # Transaction distribution 312311245Sandreas.sandberg@arm.comsystem.membus.trans_dist::InvalidateResp 106721 # Transaction distribution 312411245Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122768 # Packet count per connected master and slave (bytes) 312510535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 312611245Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25854 # Packet count per connected master and slave (bytes) 312711245Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4655021 # Packet count per connected master and slave (bytes) 312811245Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4803735 # Packet count per connected master and slave (bytes) 312911245Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342369 # Packet count per connected master and slave (bytes) 313011245Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 342369 # Packet count per connected master and slave (bytes) 313111245Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 5146104 # Packet count per connected master and slave (bytes) 313211245Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155875 # Cumulative packet size per connected master and slave (bytes) 313310535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 313411245Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51708 # Cumulative packet size per connected master and slave (bytes) 313511245Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142678316 # Cumulative packet size per connected master and slave (bytes) 313611245Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 142886103 # Cumulative packet size per connected master and slave (bytes) 313711245Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257472 # Cumulative packet size per connected master and slave (bytes) 313811245Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7257472 # Cumulative packet size per connected master and slave (bytes) 313911245Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 150143575 # Cumulative packet size per connected master and slave (bytes) 314011245Sandreas.sandberg@arm.comsystem.membus.snoops 590609 # Total snoops (count) 314111245Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 3503595 # Request fanout histogram 314210535SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 314310535SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 314410535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 314510535SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 314611245Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::1 3503595 100.00% 100.00% # Request fanout histogram 314710535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 314810535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 314910535SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 315010535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 315111245Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 3503595 # Request fanout histogram 315211245Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 101306500 # Layer occupancy (ticks) 315310535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 315411138Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 315510535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 315611245Sandreas.sandberg@arm.comsystem.membus.reqLayer2.occupancy 21492499 # Layer occupancy (ticks) 315710535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 315811245Sandreas.sandberg@arm.comsystem.membus.reqLayer5.occupancy 7402591959 # Layer occupancy (ticks) 315910535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 316011245Sandreas.sandberg@arm.comsystem.membus.respLayer2.occupancy 7154332547 # Layer occupancy (ticks) 316110535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 316211245Sandreas.sandberg@arm.comsystem.membus.respLayer3.occupancy 228436684 # Layer occupancy (ticks) 316310535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 316411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 316511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 316611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 316711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 316811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 316911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 317010515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 317110515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 317210515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 317310515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 317410515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 317510515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 317610515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 317710515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 317810515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 317911201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) 318010515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 318110515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 318210515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 318311201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) 318410515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 318510515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 318610515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 318710515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 318810515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 318910515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 319010515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 319110515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 319210515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 319310515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 319410515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 319510515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 319610515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 319710515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 319810515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 319910515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 320010515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 320110515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 320210515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 320310515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 320410515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 320510515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 320610515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 320710515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 320810515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 320910515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 321010515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 321110515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 321211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 321311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 321411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 321511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 321611245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_requests 10356989 # Total number of requests made to the snoop filter. 321711245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5641244 # Number of requests hitting in the snoop filter with a single holder of the requested data. 321811245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1705825 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 321911245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 115755 # Total number of snoops made to the snoop filter. 322011245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 104698 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 322111245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 11057 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 322211245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadReq 81774 # Transaction distribution 322311245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadResp 3879147 # Transaction distribution 322411245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WriteReq 38384 # Transaction distribution 322511245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WriteResp 38384 # Transaction distribution 322611245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3550378 # Transaction distribution 322711245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1245199 # Transaction distribution 322811245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 675855 # Transaction distribution 322911245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 385953 # Transaction distribution 323011245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1061806 # Transaction distribution 323111245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution 323211245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 323311245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1071844 # Transaction distribution 323411245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1071844 # Transaction distribution 323511245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3804622 # Transaction distribution 323611245Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 106721 # Transaction distribution 323711245Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7596632 # Packet count per connected master and slave (bytes) 323811245Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6529428 # Packet count per connected master and slave (bytes) 323911245Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count::total 14126060 # Packet count per connected master and slave (bytes) 324011245Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 228502049 # Cumulative packet size per connected master and slave (bytes) 324111245Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185064310 # Cumulative packet size per connected master and slave (bytes) 324211245Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size::total 413566359 # Cumulative packet size per connected master and slave (bytes) 324311245Sandreas.sandberg@arm.comsystem.toL2Bus.snoops 2887820 # Total snoops (count) 324411245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::samples 7482662 # Request fanout histogram 324511245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::mean 0.359179 # Request fanout histogram 324611245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.482830 # Request fanout histogram 324710515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 324811245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::0 4806103 64.23% 64.23% # Request fanout histogram 324911245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::1 2665502 35.62% 99.85% # Request fanout histogram 325011245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::2 11057 0.15% 100.00% # Request fanout histogram 325110515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 325211138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 325310515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 325411245Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::total 7482662 # Request fanout histogram 325511245Sandreas.sandberg@arm.comsystem.toL2Bus.reqLayer0.occupancy 8118734038 # Layer occupancy (ticks) 325610515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 325711245Sandreas.sandberg@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2606433 # Layer occupancy (ticks) 325810515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 325911245Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer0.occupancy 4223747952 # Layer occupancy (ticks) 326010515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 326111245Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer1.occupancy 3725557524 # Layer occupancy (ticks) 326210515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 326310515SN/A 326410515SN/A---------- End Simulation Statistics ---------- 3265