stats.txt revision 11245
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.593744 # Number of seconds simulated 4sim_ticks 47593744171500 # Number of ticks simulated 5final_tick 47593744171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 618435 # Simulator instruction rate (inst/s) 8host_op_rate 727668 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34163076444 # Simulator tick rate (ticks/s) 10host_mem_usage 740160 # Number of bytes of host memory used 11host_seconds 1393.13 # Real time elapsed on the host 12sim_insts 861562684 # Number of instructions simulated 13sim_ops 1013739401 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 69440 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 68224 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3088500 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 37423496 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 12959872 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 98944 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 107776 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2567544 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 15084176 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 9154944 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory 27system.physmem.bytes_read::total 81051908 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 3088500 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2567544 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 5656044 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 68863296 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 68883880 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1085 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1066 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 88665 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 584755 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 202498 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1546 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1684 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 40206 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 235703 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 143046 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1306957 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1075989 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1078563 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 1459 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1433 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 64893 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 786311 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 272302 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 2079 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2264 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 53947 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 316936 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 192356 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9014 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1702995 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 64893 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 53947 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 118840 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1446898 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1447331 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1446898 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 1459 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1433 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 64893 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 786744 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 272302 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 2079 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2264 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 53947 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 316936 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 192356 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9014 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3150326 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1306957 # Number of read requests accepted 84system.physmem.writeReqs 1078563 # Number of write requests accepted 85system.physmem.readBursts 1306957 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1078563 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 83609728 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 35520 # Total number of bytes read from write queue 89system.physmem.bytesWritten 68881216 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 81051908 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 68883880 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2266 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 450744 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 74137 # Per bank write bursts 96system.physmem.perBankRdBursts::1 79440 # Per bank write bursts 97system.physmem.perBankRdBursts::2 74164 # Per bank write bursts 98system.physmem.perBankRdBursts::3 81483 # Per bank write bursts 99system.physmem.perBankRdBursts::4 82988 # Per bank write bursts 100system.physmem.perBankRdBursts::5 89928 # Per bank write bursts 101system.physmem.perBankRdBursts::6 78492 # Per bank write bursts 102system.physmem.perBankRdBursts::7 81076 # Per bank write bursts 103system.physmem.perBankRdBursts::8 74414 # Per bank write bursts 104system.physmem.perBankRdBursts::9 117966 # Per bank write bursts 105system.physmem.perBankRdBursts::10 72212 # Per bank write bursts 106system.physmem.perBankRdBursts::11 83486 # Per bank write bursts 107system.physmem.perBankRdBursts::12 77461 # Per bank write bursts 108system.physmem.perBankRdBursts::13 81836 # Per bank write bursts 109system.physmem.perBankRdBursts::14 80080 # Per bank write bursts 110system.physmem.perBankRdBursts::15 77239 # Per bank write bursts 111system.physmem.perBankWrBursts::0 62409 # Per bank write bursts 112system.physmem.perBankWrBursts::1 67459 # Per bank write bursts 113system.physmem.perBankWrBursts::2 64157 # Per bank write bursts 114system.physmem.perBankWrBursts::3 68996 # Per bank write bursts 115system.physmem.perBankWrBursts::4 69521 # Per bank write bursts 116system.physmem.perBankWrBursts::5 74527 # Per bank write bursts 117system.physmem.perBankWrBursts::6 66146 # Per bank write bursts 118system.physmem.perBankWrBursts::7 68657 # Per bank write bursts 119system.physmem.perBankWrBursts::8 63193 # Per bank write bursts 120system.physmem.perBankWrBursts::9 66730 # Per bank write bursts 121system.physmem.perBankWrBursts::10 63431 # Per bank write bursts 122system.physmem.perBankWrBursts::11 70210 # Per bank write bursts 123system.physmem.perBankWrBursts::12 65844 # Per bank write bursts 124system.physmem.perBankWrBursts::13 70148 # Per bank write bursts 125system.physmem.perBankWrBursts::14 68557 # Per bank write bursts 126system.physmem.perBankWrBursts::15 66284 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 30 # Number of times write queue was full causing retry 129system.physmem.totGap 47593740806000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 43195 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1263732 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1075989 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 1091015 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 68737 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 30330 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 25975 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 22184 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 19490 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 16927 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 14904 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 11891 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 1868 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 888 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 551 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 438 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 304 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 237 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 204 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 179 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 147 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 18318 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 20896 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 46603 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 53376 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 57792 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 60877 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 64132 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 65344 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 67196 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 67473 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 69715 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 73497 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 68447 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 68375 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 71528 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 66722 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 63618 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 62101 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1601 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1148 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 781 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 693 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 586 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 407 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 317 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 356 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 320 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 373 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 287 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 363 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 225 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 274 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 301 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 271 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 314 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 215 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 195 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 206 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 161 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 110 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 113 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 62 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 67 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 71 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 62 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 58 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 840117 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 181.511175 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 111.812729 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 240.875315 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 520248 61.93% 61.93% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 156423 18.62% 80.54% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 51977 6.19% 86.73% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 27385 3.26% 89.99% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 18542 2.21% 92.20% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 11713 1.39% 93.59% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 8913 1.06% 94.65% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 8910 1.06% 95.71% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 36006 4.29% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 840117 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 60330 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 21.654169 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 330.190002 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 60327 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 60330 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 60330 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 17.839698 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.269040 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 7.176072 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 56620 93.85% 93.85% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 1546 2.56% 96.41% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 276 0.46% 96.87% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 296 0.49% 97.36% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 110 0.18% 97.54% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 266 0.44% 97.98% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 180 0.30% 98.28% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 98 0.16% 98.45% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 97 0.16% 98.61% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 84 0.14% 98.75% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 48 0.08% 98.82% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 66 0.11% 98.93% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 398 0.66% 99.59% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 43 0.07% 99.67% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 35 0.06% 99.72% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 96 0.16% 99.88% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 19 0.03% 99.91% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::100-103 3 0.00% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::108-111 1 0.00% 99.92% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::128-131 24 0.04% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::140-143 3 0.00% 99.98% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::152-155 7 0.01% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::total 60330 # Writes before turning the bus around for reads 299system.physmem.totQLat 28430560155 # Total ticks spent queuing 300system.physmem.totMemAccLat 52925597655 # Total ticks spent from burst creation until serviced by the DRAM 301system.physmem.totBusLat 6532010000 # Total ticks spent in databus transfers 302system.physmem.avgQLat 21762.49 # Average queueing delay per DRAM burst 303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 304system.physmem.avgMemAccLat 40512.49 # Average memory access latency per DRAM burst 305system.physmem.avgRdBW 1.76 # Average DRAM read bandwidth in MiByte/s 306system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s 307system.physmem.avgRdBWSys 1.70 # Average system read bandwidth in MiByte/s 308system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 310system.physmem.busUtil 0.03 # Data bus utilization in percentage 311system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 312system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 313system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing 314system.physmem.avgWrQLen 26.65 # Average write queue length when enqueuing 315system.physmem.readRowHits 1047491 # Number of row buffer hits during reads 316system.physmem.writeRowHits 495062 # Number of row buffer hits during writes 317system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads 318system.physmem.writeRowHitRate 46.00 # Row buffer hit rate for writes 319system.physmem.avgGap 19951096.95 # Average gap between requests 320system.physmem.pageHitRate 64.74 # Row buffer hit rate, read and write combined 321system.physmem_0.actEnergy 3221134560 # Energy for activate commands per rank (pJ) 322system.physmem_0.preEnergy 1757563500 # Energy for precharge commands per rank (pJ) 323system.physmem_0.readEnergy 5005283400 # Energy for read commands per rank (pJ) 324system.physmem_0.writeEnergy 3511330560 # Energy for write commands per rank (pJ) 325system.physmem_0.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ) 326system.physmem_0.actBackEnergy 1216360497735 # Energy for active background per rank (pJ) 327system.physmem_0.preBackEnergy 27489261984750 # Energy for precharge background per rank (pJ) 328system.physmem_0.totalEnergy 31827709611225 # Total energy per rank (pJ) 329system.physmem_0.averagePower 668.737288 # Core power per rank (mW) 330system.physmem_0.memoryStateTime::IDLE 45730304477620 # Time in different power states 331system.physmem_0.memoryStateTime::REF 1589259620000 # Time in different power states 332system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 333system.physmem_0.memoryStateTime::ACT 274179379380 # Time in different power states 334system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 335system.physmem_1.actEnergy 3130149960 # Energy for activate commands per rank (pJ) 336system.physmem_1.preEnergy 1707919125 # Energy for precharge commands per rank (pJ) 337system.physmem_1.readEnergy 5184613200 # Energy for read commands per rank (pJ) 338system.physmem_1.writeEnergy 3462892560 # Energy for write commands per rank (pJ) 339system.physmem_1.refreshEnergy 3108591816720 # Energy for refresh commands per rank (pJ) 340system.physmem_1.actBackEnergy 1215861151230 # Energy for active background per rank (pJ) 341system.physmem_1.preBackEnergy 27489700008000 # Energy for precharge background per rank (pJ) 342system.physmem_1.totalEnergy 31827638550795 # Total energy per rank (pJ) 343system.physmem_1.averagePower 668.735795 # Core power per rank (mW) 344system.physmem_1.memoryStateTime::IDLE 45731003279682 # Time in different power states 345system.physmem_1.memoryStateTime::REF 1589259620000 # Time in different power states 346system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 347system.physmem_1.memoryStateTime::ACT 273478576568 # Time in different power states 348system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 349system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 357system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 362system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 375system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 376system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 377system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 378system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 379system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 380system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 381system.cpu_clk_domain.clock 500 # Clock period in ticks 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 391system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 392system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 393system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 394system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 395system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 396system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 398system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 400system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 401system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 402system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 403system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 404system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 405system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 406system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 407system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 408system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 409system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 410system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 411system.cpu0.dtb.walker.walks 93408 # Table walker walks requested 412system.cpu0.dtb.walker.walksLong 93408 # Table walker walks initiated with long descriptors 413system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 7983 # Level at which table walker walks with long descriptors terminate 414system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 70276 # Level at which table walker walks with long descriptors terminate 415system.cpu0.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting 416system.cpu0.dtb.walker.walkWaitTime::samples 93401 # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::mean 0.278370 # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::stdev 85.074143 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::0-2047 93400 100.00% 100.00% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::total 93401 # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkCompletionTime::samples 78266 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::mean 22499.341988 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::gmean 20923.382111 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::stdev 16650.912887 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::0-65535 77590 99.14% 99.14% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::65536-131071 164 0.21% 99.35% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::131072-196607 417 0.53% 99.88% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.91% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::262144-327679 25 0.03% 99.94% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.95% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::393216-458751 29 0.04% 99.99% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::total 78266 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walksPending::samples 5219685476 # Table walker pending requests distribution 437system.cpu0.dtb.walker.walksPending::mean 0.596746 # Table walker pending requests distribution 438system.cpu0.dtb.walker.walksPending::stdev 0.490551 # Table walker pending requests distribution 439system.cpu0.dtb.walker.walksPending::0 2104860204 40.33% 40.33% # Table walker pending requests distribution 440system.cpu0.dtb.walker.walksPending::1 3114825272 59.67% 100.00% # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::total 5219685476 # Table walker pending requests distribution 442system.cpu0.dtb.walker.walkPageSizes::4K 70276 89.80% 89.80% # Table walker page sizes translated 443system.cpu0.dtb.walker.walkPageSizes::2M 7983 10.20% 100.00% # Table walker page sizes translated 444system.cpu0.dtb.walker.walkPageSizes::total 78259 # Table walker page sizes translated 445system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 93408 # Table walker requests started/completed, data/inst 446system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 447system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 93408 # Table walker requests started/completed, data/inst 448system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78259 # Table walker requests started/completed, data/inst 449system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78259 # Table walker requests started/completed, data/inst 451system.cpu0.dtb.walker.walkRequestOrigin::total 171667 # Table walker requests started/completed, data/inst 452system.cpu0.dtb.inst_hits 0 # ITB inst hits 453system.cpu0.dtb.inst_misses 0 # ITB inst misses 454system.cpu0.dtb.read_hits 80327529 # DTB read hits 455system.cpu0.dtb.read_misses 69973 # DTB read misses 456system.cpu0.dtb.write_hits 72902451 # DTB write hits 457system.cpu0.dtb.write_misses 23435 # DTB write misses 458system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 459system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 460system.cpu0.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID 461system.cpu0.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID 462system.cpu0.dtb.flush_entries 34709 # Number of entries that have been flushed from TLB 463system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 464system.cpu0.dtb.prefetch_faults 4393 # Number of TLB faults due to prefetch 465system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 466system.cpu0.dtb.perms_faults 8867 # Number of TLB faults due to permissions restrictions 467system.cpu0.dtb.read_accesses 80397502 # DTB read accesses 468system.cpu0.dtb.write_accesses 72925886 # DTB write accesses 469system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 470system.cpu0.dtb.hits 153229980 # DTB hits 471system.cpu0.dtb.misses 93408 # DTB misses 472system.cpu0.dtb.accesses 153323388 # DTB accesses 473system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 475system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 482system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 483system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 484system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 485system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 486system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 487system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 488system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 489system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 491system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 492system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 493system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 494system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 495system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 496system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 497system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 498system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 499system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 500system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 501system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 502system.cpu0.itb.walker.walks 52417 # Table walker walks requested 503system.cpu0.itb.walker.walksLong 52417 # Table walker walks initiated with long descriptors 504system.cpu0.itb.walker.walksLongTerminationLevel::Level2 598 # Level at which table walker walks with long descriptors terminate 505system.cpu0.itb.walker.walksLongTerminationLevel::Level3 46386 # Level at which table walker walks with long descriptors terminate 506system.cpu0.itb.walker.walkWaitTime::samples 52417 # Table walker wait (enqueue to first request) latency 507system.cpu0.itb.walker.walkWaitTime::0 52417 100.00% 100.00% # Table walker wait (enqueue to first request) latency 508system.cpu0.itb.walker.walkWaitTime::total 52417 # Table walker wait (enqueue to first request) latency 509system.cpu0.itb.walker.walkCompletionTime::samples 46984 # Table walker service (enqueue to completion) latency 510system.cpu0.itb.walker.walkCompletionTime::mean 25232.568534 # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::gmean 22985.913240 # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::stdev 21269.412068 # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::0-65535 46328 98.60% 98.60% # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::65536-131071 41 0.09% 98.69% # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::131072-196607 530 1.13% 99.82% # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::196608-262143 16 0.03% 99.85% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::262144-327679 24 0.05% 99.90% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.04% 99.94% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::393216-458751 22 0.05% 99.99% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::total 46984 # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution 525system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution 526system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution 527system.cpu0.itb.walker.walkPageSizes::4K 46386 98.73% 98.73% # Table walker page sizes translated 528system.cpu0.itb.walker.walkPageSizes::2M 598 1.27% 100.00% # Table walker page sizes translated 529system.cpu0.itb.walker.walkPageSizes::total 46984 # Table walker page sizes translated 530system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 531system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52417 # Table walker requests started/completed, data/inst 532system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52417 # Table walker requests started/completed, data/inst 533system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 534system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 46984 # Table walker requests started/completed, data/inst 535system.cpu0.itb.walker.walkRequestOrigin_Completed::total 46984 # Table walker requests started/completed, data/inst 536system.cpu0.itb.walker.walkRequestOrigin::total 99401 # Table walker requests started/completed, data/inst 537system.cpu0.itb.inst_hits 426699171 # ITB inst hits 538system.cpu0.itb.inst_misses 52417 # ITB inst misses 539system.cpu0.itb.read_hits 0 # DTB read hits 540system.cpu0.itb.read_misses 0 # DTB read misses 541system.cpu0.itb.write_hits 0 # DTB write hits 542system.cpu0.itb.write_misses 0 # DTB write misses 543system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 544system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 545system.cpu0.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID 546system.cpu0.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID 547system.cpu0.itb.flush_entries 24801 # Number of entries that have been flushed from TLB 548system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 549system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 550system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 551system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 552system.cpu0.itb.read_accesses 0 # DTB read accesses 553system.cpu0.itb.write_accesses 0 # DTB write accesses 554system.cpu0.itb.inst_accesses 426751588 # ITB inst accesses 555system.cpu0.itb.hits 426699171 # DTB hits 556system.cpu0.itb.misses 52417 # DTB misses 557system.cpu0.itb.accesses 426751588 # DTB accesses 558system.cpu0.numCycles 95186924479 # number of cpu cycles simulated 559system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 560system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 561system.cpu0.kern.inst.arm 0 # number of arm instructions executed 562system.cpu0.kern.inst.quiesce 4674 # number of quiesce instructions executed 563system.cpu0.committedInsts 426454163 # Number of instructions committed 564system.cpu0.committedOps 501120280 # Number of ops (including micro ops) committed 565system.cpu0.num_int_alu_accesses 460758133 # Number of integer alu accesses 566system.cpu0.num_fp_alu_accesses 395268 # Number of float alu accesses 567system.cpu0.num_func_calls 25675920 # number of times a function call or return occured 568system.cpu0.num_conditional_control_insts 64224693 # number of instructions that are conditional controls 569system.cpu0.num_int_insts 460758133 # number of integer instructions 570system.cpu0.num_fp_insts 395268 # number of float instructions 571system.cpu0.num_int_register_reads 666544840 # number of times the integer registers were read 572system.cpu0.num_int_register_writes 365452769 # number of times the integer registers were written 573system.cpu0.num_fp_register_reads 661868 # number of times the floating registers were read 574system.cpu0.num_fp_register_writes 282064 # number of times the floating registers were written 575system.cpu0.num_cc_register_reads 110079606 # number of times the CC registers were read 576system.cpu0.num_cc_register_writes 109774743 # number of times the CC registers were written 577system.cpu0.num_mem_refs 153223313 # number of memory refs 578system.cpu0.num_load_insts 80324545 # Number of load instructions 579system.cpu0.num_store_insts 72898768 # Number of store instructions 580system.cpu0.num_idle_cycles 94023627088.560516 # Number of idle cycles 581system.cpu0.num_busy_cycles 1163297390.439485 # Number of busy cycles 582system.cpu0.not_idle_fraction 0.012221 # Percentage of non-idle cycles 583system.cpu0.idle_fraction 0.987779 # Percentage of idle cycles 584system.cpu0.Branches 94888903 # Number of branches fetched 585system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 586system.cpu0.op_class::IntAlu 346960051 69.20% 69.20% # Class of executed instruction 587system.cpu0.op_class::IntMult 1125201 0.22% 69.42% # Class of executed instruction 588system.cpu0.op_class::IntDiv 62694 0.01% 69.43% # Class of executed instruction 589system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction 590system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction 591system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction 592system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction 593system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction 594system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction 595system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction 596system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction 597system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction 598system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction 599system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction 600system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction 601system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction 602system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction 603system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction 604system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction 605system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction 606system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction 607system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction 608system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction 609system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction 610system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction 611system.cpu0.op_class::SimdFloatMisc 37154 0.01% 69.44% # Class of executed instruction 612system.cpu0.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction 613system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction 614system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction 615system.cpu0.op_class::MemRead 80324545 16.02% 85.46% # Class of executed instruction 616system.cpu0.op_class::MemWrite 72898768 14.54% 100.00% # Class of executed instruction 617system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 618system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 619system.cpu0.op_class::total 501408413 # Class of executed instruction 620system.cpu0.dcache.tags.replacements 5237512 # number of replacements 621system.cpu0.dcache.tags.tagsinuse 505.877232 # Cycle average of tags in use 622system.cpu0.dcache.tags.total_refs 147745204 # Total number of references to valid blocks. 623system.cpu0.dcache.tags.sampled_refs 5237891 # Sample count of references to valid blocks. 624system.cpu0.dcache.tags.avg_refs 28.207002 # Average number of references to valid blocks. 625system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. 626system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.877232 # Average occupied blocks per requestor 627system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988041 # Average percentage of cache occupancy 628system.cpu0.dcache.tags.occ_percent::total 0.988041 # Average percentage of cache occupancy 629system.cpu0.dcache.tags.occ_task_id_blocks::1024 379 # Occupied blocks per task id 630system.cpu0.dcache.tags.age_task_id_blocks_1024::2 370 # Occupied blocks per task id 631system.cpu0.dcache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 632system.cpu0.dcache.tags.occ_task_id_percent::1024 0.740234 # Percentage of cache occupancy per task id 633system.cpu0.dcache.tags.tag_accesses 311719457 # Number of tag accesses 634system.cpu0.dcache.tags.data_accesses 311719457 # Number of data accesses 635system.cpu0.dcache.ReadReq_hits::cpu0.data 74802484 # number of ReadReq hits 636system.cpu0.dcache.ReadReq_hits::total 74802484 # number of ReadReq hits 637system.cpu0.dcache.WriteReq_hits::cpu0.data 68840975 # number of WriteReq hits 638system.cpu0.dcache.WriteReq_hits::total 68840975 # number of WriteReq hits 639system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186514 # number of SoftPFReq hits 640system.cpu0.dcache.SoftPFReq_hits::total 186514 # number of SoftPFReq hits 641system.cpu0.dcache.WriteLineReq_hits::cpu0.data 133741 # number of WriteLineReq hits 642system.cpu0.dcache.WriteLineReq_hits::total 133741 # number of WriteLineReq hits 643system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1712983 # number of LoadLockedReq hits 644system.cpu0.dcache.LoadLockedReq_hits::total 1712983 # number of LoadLockedReq hits 645system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1673957 # number of StoreCondReq hits 646system.cpu0.dcache.StoreCondReq_hits::total 1673957 # number of StoreCondReq hits 647system.cpu0.dcache.demand_hits::cpu0.data 143643459 # number of demand (read+write) hits 648system.cpu0.dcache.demand_hits::total 143643459 # number of demand (read+write) hits 649system.cpu0.dcache.overall_hits::cpu0.data 143829973 # number of overall hits 650system.cpu0.dcache.overall_hits::total 143829973 # number of overall hits 651system.cpu0.dcache.ReadReq_misses::cpu0.data 2859232 # number of ReadReq misses 652system.cpu0.dcache.ReadReq_misses::total 2859232 # number of ReadReq misses 653system.cpu0.dcache.WriteReq_misses::cpu0.data 1316810 # number of WriteReq misses 654system.cpu0.dcache.WriteReq_misses::total 1316810 # number of WriteReq misses 655system.cpu0.dcache.SoftPFReq_misses::cpu0.data 596453 # number of SoftPFReq misses 656system.cpu0.dcache.SoftPFReq_misses::total 596453 # number of SoftPFReq misses 657system.cpu0.dcache.WriteLineReq_misses::cpu0.data 721743 # number of WriteLineReq misses 658system.cpu0.dcache.WriteLineReq_misses::total 721743 # number of WriteLineReq misses 659system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153137 # number of LoadLockedReq misses 660system.cpu0.dcache.LoadLockedReq_misses::total 153137 # number of LoadLockedReq misses 661system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190741 # number of StoreCondReq misses 662system.cpu0.dcache.StoreCondReq_misses::total 190741 # number of StoreCondReq misses 663system.cpu0.dcache.demand_misses::cpu0.data 4176042 # number of demand (read+write) misses 664system.cpu0.dcache.demand_misses::total 4176042 # number of demand (read+write) misses 665system.cpu0.dcache.overall_misses::cpu0.data 4772495 # number of overall misses 666system.cpu0.dcache.overall_misses::total 4772495 # number of overall misses 667system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45650819500 # number of ReadReq miss cycles 668system.cpu0.dcache.ReadReq_miss_latency::total 45650819500 # number of ReadReq miss cycles 669system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34330450500 # number of WriteReq miss cycles 670system.cpu0.dcache.WriteReq_miss_latency::total 34330450500 # number of WriteReq miss cycles 671system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65187396500 # number of WriteLineReq miss cycles 672system.cpu0.dcache.WriteLineReq_miss_latency::total 65187396500 # number of WriteLineReq miss cycles 673system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2390631500 # number of LoadLockedReq miss cycles 674system.cpu0.dcache.LoadLockedReq_miss_latency::total 2390631500 # number of LoadLockedReq miss cycles 675system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5489081000 # number of StoreCondReq miss cycles 676system.cpu0.dcache.StoreCondReq_miss_latency::total 5489081000 # number of StoreCondReq miss cycles 677system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7149000 # number of StoreCondFailReq miss cycles 678system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7149000 # number of StoreCondFailReq miss cycles 679system.cpu0.dcache.demand_miss_latency::cpu0.data 79981270000 # number of demand (read+write) miss cycles 680system.cpu0.dcache.demand_miss_latency::total 79981270000 # number of demand (read+write) miss cycles 681system.cpu0.dcache.overall_miss_latency::cpu0.data 79981270000 # number of overall miss cycles 682system.cpu0.dcache.overall_miss_latency::total 79981270000 # number of overall miss cycles 683system.cpu0.dcache.ReadReq_accesses::cpu0.data 77661716 # number of ReadReq accesses(hits+misses) 684system.cpu0.dcache.ReadReq_accesses::total 77661716 # number of ReadReq accesses(hits+misses) 685system.cpu0.dcache.WriteReq_accesses::cpu0.data 70157785 # number of WriteReq accesses(hits+misses) 686system.cpu0.dcache.WriteReq_accesses::total 70157785 # number of WriteReq accesses(hits+misses) 687system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 782967 # number of SoftPFReq accesses(hits+misses) 688system.cpu0.dcache.SoftPFReq_accesses::total 782967 # number of SoftPFReq accesses(hits+misses) 689system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 855484 # number of WriteLineReq accesses(hits+misses) 690system.cpu0.dcache.WriteLineReq_accesses::total 855484 # number of WriteLineReq accesses(hits+misses) 691system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1866120 # number of LoadLockedReq accesses(hits+misses) 692system.cpu0.dcache.LoadLockedReq_accesses::total 1866120 # number of LoadLockedReq accesses(hits+misses) 693system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1864698 # number of StoreCondReq accesses(hits+misses) 694system.cpu0.dcache.StoreCondReq_accesses::total 1864698 # number of StoreCondReq accesses(hits+misses) 695system.cpu0.dcache.demand_accesses::cpu0.data 147819501 # number of demand (read+write) accesses 696system.cpu0.dcache.demand_accesses::total 147819501 # number of demand (read+write) accesses 697system.cpu0.dcache.overall_accesses::cpu0.data 148602468 # number of overall (read+write) accesses 698system.cpu0.dcache.overall_accesses::total 148602468 # number of overall (read+write) accesses 699system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036816 # miss rate for ReadReq accesses 700system.cpu0.dcache.ReadReq_miss_rate::total 0.036816 # miss rate for ReadReq accesses 701system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018769 # miss rate for WriteReq accesses 702system.cpu0.dcache.WriteReq_miss_rate::total 0.018769 # miss rate for WriteReq accesses 703system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761786 # miss rate for SoftPFReq accesses 704system.cpu0.dcache.SoftPFReq_miss_rate::total 0.761786 # miss rate for SoftPFReq accesses 705system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843666 # miss rate for WriteLineReq accesses 706system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843666 # miss rate for WriteLineReq accesses 707system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.082062 # miss rate for LoadLockedReq accesses 708system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.082062 # miss rate for LoadLockedReq accesses 709system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.102291 # miss rate for StoreCondReq accesses 710system.cpu0.dcache.StoreCondReq_miss_rate::total 0.102291 # miss rate for StoreCondReq accesses 711system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028251 # miss rate for demand accesses 712system.cpu0.dcache.demand_miss_rate::total 0.028251 # miss rate for demand accesses 713system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032116 # miss rate for overall accesses 714system.cpu0.dcache.overall_miss_rate::total 0.032116 # miss rate for overall accesses 715system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15966.112404 # average ReadReq miss latency 716system.cpu0.dcache.ReadReq_avg_miss_latency::total 15966.112404 # average ReadReq miss latency 717system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 26070.921773 # average WriteReq miss latency 718system.cpu0.dcache.WriteReq_avg_miss_latency::total 26070.921773 # average WriteReq miss latency 719system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90319.402474 # average WriteLineReq miss latency 720system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90319.402474 # average WriteLineReq miss latency 721system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15611.063949 # average LoadLockedReq miss latency 722system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15611.063949 # average LoadLockedReq miss latency 723system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28777.667098 # average StoreCondReq miss latency 724system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28777.667098 # average StoreCondReq miss latency 725system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 726system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 727system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19152.410345 # average overall miss latency 728system.cpu0.dcache.demand_avg_miss_latency::total 19152.410345 # average overall miss latency 729system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16758.795976 # average overall miss latency 730system.cpu0.dcache.overall_avg_miss_latency::total 16758.795976 # average overall miss latency 731system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 732system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 733system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 734system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 735system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 736system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 737system.cpu0.dcache.fast_writes 0 # number of fast writes performed 738system.cpu0.dcache.cache_copies 0 # number of cache copies performed 739system.cpu0.dcache.writebacks::writebacks 5237512 # number of writebacks 740system.cpu0.dcache.writebacks::total 5237512 # number of writebacks 741system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25341 # number of ReadReq MSHR hits 742system.cpu0.dcache.ReadReq_mshr_hits::total 25341 # number of ReadReq MSHR hits 743system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21295 # number of WriteReq MSHR hits 744system.cpu0.dcache.WriteReq_mshr_hits::total 21295 # number of WriteReq MSHR hits 745system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 39838 # number of LoadLockedReq MSHR hits 746system.cpu0.dcache.LoadLockedReq_mshr_hits::total 39838 # number of LoadLockedReq MSHR hits 747system.cpu0.dcache.demand_mshr_hits::cpu0.data 46636 # number of demand (read+write) MSHR hits 748system.cpu0.dcache.demand_mshr_hits::total 46636 # number of demand (read+write) MSHR hits 749system.cpu0.dcache.overall_mshr_hits::cpu0.data 46636 # number of overall MSHR hits 750system.cpu0.dcache.overall_mshr_hits::total 46636 # number of overall MSHR hits 751system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2833891 # number of ReadReq MSHR misses 752system.cpu0.dcache.ReadReq_mshr_misses::total 2833891 # number of ReadReq MSHR misses 753system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1295515 # number of WriteReq MSHR misses 754system.cpu0.dcache.WriteReq_mshr_misses::total 1295515 # number of WriteReq MSHR misses 755system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 595169 # number of SoftPFReq MSHR misses 756system.cpu0.dcache.SoftPFReq_mshr_misses::total 595169 # number of SoftPFReq MSHR misses 757system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 721743 # number of WriteLineReq MSHR misses 758system.cpu0.dcache.WriteLineReq_mshr_misses::total 721743 # number of WriteLineReq MSHR misses 759system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113299 # number of LoadLockedReq MSHR misses 760system.cpu0.dcache.LoadLockedReq_mshr_misses::total 113299 # number of LoadLockedReq MSHR misses 761system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190741 # number of StoreCondReq MSHR misses 762system.cpu0.dcache.StoreCondReq_mshr_misses::total 190741 # number of StoreCondReq MSHR misses 763system.cpu0.dcache.demand_mshr_misses::cpu0.data 4129406 # number of demand (read+write) MSHR misses 764system.cpu0.dcache.demand_mshr_misses::total 4129406 # number of demand (read+write) MSHR misses 765system.cpu0.dcache.overall_mshr_misses::cpu0.data 4724575 # number of overall MSHR misses 766system.cpu0.dcache.overall_mshr_misses::total 4724575 # number of overall MSHR misses 767system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16746 # number of ReadReq MSHR uncacheable 768system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16746 # number of ReadReq MSHR uncacheable 769system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17968 # number of WriteReq MSHR uncacheable 770system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17968 # number of WriteReq MSHR uncacheable 771system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34714 # number of overall MSHR uncacheable misses 772system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34714 # number of overall MSHR uncacheable misses 773system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41050881000 # number of ReadReq MSHR miss cycles 774system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41050881000 # number of ReadReq MSHR miss cycles 775system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32444395000 # number of WriteReq MSHR miss cycles 776system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32444395000 # number of WriteReq MSHR miss cycles 777system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14818032000 # number of SoftPFReq MSHR miss cycles 778system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14818032000 # number of SoftPFReq MSHR miss cycles 779system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 64465653500 # number of WriteLineReq MSHR miss cycles 780system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 64465653500 # number of WriteLineReq MSHR miss cycles 781system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564895500 # number of LoadLockedReq MSHR miss cycles 782system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564895500 # number of LoadLockedReq MSHR miss cycles 783system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5298419000 # number of StoreCondReq MSHR miss cycles 784system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5298419000 # number of StoreCondReq MSHR miss cycles 785system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7070000 # number of StoreCondFailReq MSHR miss cycles 786system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7070000 # number of StoreCondFailReq MSHR miss cycles 787system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73495276000 # number of demand (read+write) MSHR miss cycles 788system.cpu0.dcache.demand_mshr_miss_latency::total 73495276000 # number of demand (read+write) MSHR miss cycles 789system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 88313308000 # number of overall MSHR miss cycles 790system.cpu0.dcache.overall_mshr_miss_latency::total 88313308000 # number of overall MSHR miss cycles 791system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897717500 # number of ReadReq MSHR uncacheable cycles 792system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897717500 # number of ReadReq MSHR uncacheable cycles 793system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3102799000 # number of WriteReq MSHR uncacheable cycles 794system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3102799000 # number of WriteReq MSHR uncacheable cycles 795system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6000516500 # number of overall MSHR uncacheable cycles 796system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6000516500 # number of overall MSHR uncacheable cycles 797system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036490 # mshr miss rate for ReadReq accesses 798system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036490 # mshr miss rate for ReadReq accesses 799system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018466 # mshr miss rate for WriteReq accesses 800system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses 801system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.760146 # mshr miss rate for SoftPFReq accesses 802system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760146 # mshr miss rate for SoftPFReq accesses 803system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.843666 # mshr miss rate for WriteLineReq accesses 804system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.843666 # mshr miss rate for WriteLineReq accesses 805system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060714 # mshr miss rate for LoadLockedReq accesses 806system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060714 # mshr miss rate for LoadLockedReq accesses 807system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.102291 # mshr miss rate for StoreCondReq accesses 808system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.102291 # mshr miss rate for StoreCondReq accesses 809system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027935 # mshr miss rate for demand accesses 810system.cpu0.dcache.demand_mshr_miss_rate::total 0.027935 # mshr miss rate for demand accesses 811system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031793 # mshr miss rate for overall accesses 812system.cpu0.dcache.overall_mshr_miss_rate::total 0.031793 # mshr miss rate for overall accesses 813system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14485.695110 # average ReadReq mshr miss latency 814system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14485.695110 # average ReadReq mshr miss latency 815system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25043.627438 # average WriteReq mshr miss latency 816system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25043.627438 # average WriteReq mshr miss latency 817system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24897.183825 # average SoftPFReq mshr miss latency 818system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24897.183825 # average SoftPFReq mshr miss latency 819system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89319.402474 # average WriteLineReq mshr miss latency 820system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89319.402474 # average WriteLineReq mshr miss latency 821system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13812.085720 # average LoadLockedReq mshr miss latency 822system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13812.085720 # average LoadLockedReq mshr miss latency 823system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27778.081273 # average StoreCondReq mshr miss latency 824system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27778.081273 # average StoreCondReq mshr miss latency 825system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 826system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 827system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17798.026157 # average overall mshr miss latency 828system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17798.026157 # average overall mshr miss latency 829system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18692.328516 # average overall mshr miss latency 830system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18692.328516 # average overall mshr miss latency 831system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173039.382539 # average ReadReq mshr uncacheable latency 832system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173039.382539 # average ReadReq mshr uncacheable latency 833system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172684.717275 # average WriteReq mshr uncacheable latency 834system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172684.717275 # average WriteReq mshr uncacheable latency 835system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 172855.807455 # average overall mshr uncacheable latency 836system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 172855.807455 # average overall mshr uncacheable latency 837system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 838system.cpu0.icache.tags.replacements 4772370 # number of replacements 839system.cpu0.icache.tags.tagsinuse 511.827216 # Cycle average of tags in use 840system.cpu0.icache.tags.total_refs 421926289 # Total number of references to valid blocks. 841system.cpu0.icache.tags.sampled_refs 4772882 # Sample count of references to valid blocks. 842system.cpu0.icache.tags.avg_refs 88.400738 # Average number of references to valid blocks. 843system.cpu0.icache.tags.warmup_cycle 59167640000 # Cycle when the warmup percentage was hit. 844system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827216 # Average occupied blocks per requestor 845system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999663 # Average percentage of cache occupancy 846system.cpu0.icache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy 847system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 848system.cpu0.icache.tags.age_task_id_blocks_1024::2 395 # Occupied blocks per task id 849system.cpu0.icache.tags.age_task_id_blocks_1024::3 117 # Occupied blocks per task id 850system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 851system.cpu0.icache.tags.tag_accesses 858171224 # Number of tag accesses 852system.cpu0.icache.tags.data_accesses 858171224 # Number of data accesses 853system.cpu0.icache.ReadReq_hits::cpu0.inst 421926289 # number of ReadReq hits 854system.cpu0.icache.ReadReq_hits::total 421926289 # number of ReadReq hits 855system.cpu0.icache.demand_hits::cpu0.inst 421926289 # number of demand (read+write) hits 856system.cpu0.icache.demand_hits::total 421926289 # number of demand (read+write) hits 857system.cpu0.icache.overall_hits::cpu0.inst 421926289 # number of overall hits 858system.cpu0.icache.overall_hits::total 421926289 # number of overall hits 859system.cpu0.icache.ReadReq_misses::cpu0.inst 4772882 # number of ReadReq misses 860system.cpu0.icache.ReadReq_misses::total 4772882 # number of ReadReq misses 861system.cpu0.icache.demand_misses::cpu0.inst 4772882 # number of demand (read+write) misses 862system.cpu0.icache.demand_misses::total 4772882 # number of demand (read+write) misses 863system.cpu0.icache.overall_misses::cpu0.inst 4772882 # number of overall misses 864system.cpu0.icache.overall_misses::total 4772882 # number of overall misses 865system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52975952000 # number of ReadReq miss cycles 866system.cpu0.icache.ReadReq_miss_latency::total 52975952000 # number of ReadReq miss cycles 867system.cpu0.icache.demand_miss_latency::cpu0.inst 52975952000 # number of demand (read+write) miss cycles 868system.cpu0.icache.demand_miss_latency::total 52975952000 # number of demand (read+write) miss cycles 869system.cpu0.icache.overall_miss_latency::cpu0.inst 52975952000 # number of overall miss cycles 870system.cpu0.icache.overall_miss_latency::total 52975952000 # number of overall miss cycles 871system.cpu0.icache.ReadReq_accesses::cpu0.inst 426699171 # number of ReadReq accesses(hits+misses) 872system.cpu0.icache.ReadReq_accesses::total 426699171 # number of ReadReq accesses(hits+misses) 873system.cpu0.icache.demand_accesses::cpu0.inst 426699171 # number of demand (read+write) accesses 874system.cpu0.icache.demand_accesses::total 426699171 # number of demand (read+write) accesses 875system.cpu0.icache.overall_accesses::cpu0.inst 426699171 # number of overall (read+write) accesses 876system.cpu0.icache.overall_accesses::total 426699171 # number of overall (read+write) accesses 877system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011186 # miss rate for ReadReq accesses 878system.cpu0.icache.ReadReq_miss_rate::total 0.011186 # miss rate for ReadReq accesses 879system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011186 # miss rate for demand accesses 880system.cpu0.icache.demand_miss_rate::total 0.011186 # miss rate for demand accesses 881system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011186 # miss rate for overall accesses 882system.cpu0.icache.overall_miss_rate::total 0.011186 # miss rate for overall accesses 883system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11099.363445 # average ReadReq miss latency 884system.cpu0.icache.ReadReq_avg_miss_latency::total 11099.363445 # average ReadReq miss latency 885system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency 886system.cpu0.icache.demand_avg_miss_latency::total 11099.363445 # average overall miss latency 887system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11099.363445 # average overall miss latency 888system.cpu0.icache.overall_avg_miss_latency::total 11099.363445 # average overall miss latency 889system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 890system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 892system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 893system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 894system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu0.icache.fast_writes 0 # number of fast writes performed 896system.cpu0.icache.cache_copies 0 # number of cache copies performed 897system.cpu0.icache.writebacks::writebacks 4772370 # number of writebacks 898system.cpu0.icache.writebacks::total 4772370 # number of writebacks 899system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4772882 # number of ReadReq MSHR misses 900system.cpu0.icache.ReadReq_mshr_misses::total 4772882 # number of ReadReq MSHR misses 901system.cpu0.icache.demand_mshr_misses::cpu0.inst 4772882 # number of demand (read+write) MSHR misses 902system.cpu0.icache.demand_mshr_misses::total 4772882 # number of demand (read+write) MSHR misses 903system.cpu0.icache.overall_mshr_misses::cpu0.inst 4772882 # number of overall MSHR misses 904system.cpu0.icache.overall_mshr_misses::total 4772882 # number of overall MSHR misses 905system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 906system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 907system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 908system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 909system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 50589511000 # number of ReadReq MSHR miss cycles 910system.cpu0.icache.ReadReq_mshr_miss_latency::total 50589511000 # number of ReadReq MSHR miss cycles 911system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 50589511000 # number of demand (read+write) MSHR miss cycles 912system.cpu0.icache.demand_mshr_miss_latency::total 50589511000 # number of demand (read+write) MSHR miss cycles 913system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 50589511000 # number of overall MSHR miss cycles 914system.cpu0.icache.overall_mshr_miss_latency::total 50589511000 # number of overall MSHR miss cycles 915system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles 916system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles 917system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles 918system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles 919system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for ReadReq accesses 920system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011186 # mshr miss rate for ReadReq accesses 921system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for demand accesses 922system.cpu0.icache.demand_mshr_miss_rate::total 0.011186 # mshr miss rate for demand accesses 923system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011186 # mshr miss rate for overall accesses 924system.cpu0.icache.overall_mshr_miss_rate::total 0.011186 # mshr miss rate for overall accesses 925system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average ReadReq mshr miss latency 926system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10599.363445 # average ReadReq mshr miss latency 927system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency 928system.cpu0.icache.demand_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency 929system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10599.363445 # average overall mshr miss latency 930system.cpu0.icache.overall_avg_mshr_miss_latency::total 10599.363445 # average overall mshr miss latency 931system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency 932system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency 933system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency 934system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency 935system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 936system.cpu0.l2cache.prefetcher.num_hwpf_issued 7230591 # number of hwpf issued 937system.cpu0.l2cache.prefetcher.pfIdentified 7230639 # number of prefetch candidates identified 938system.cpu0.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue 939system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 940system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 941system.cpu0.l2cache.prefetcher.pfSpanPage 940745 # number of prefetches not generated due to page crossing 942system.cpu0.l2cache.tags.replacements 2188465 # number of replacements 943system.cpu0.l2cache.tags.tagsinuse 16163.582102 # Cycle average of tags in use 944system.cpu0.l2cache.tags.total_refs 14109503 # Total number of references to valid blocks. 945system.cpu0.l2cache.tags.sampled_refs 2203636 # Sample count of references to valid blocks. 946system.cpu0.l2cache.tags.avg_refs 6.402828 # Average number of references to valid blocks. 947system.cpu0.l2cache.tags.warmup_cycle 8764179000 # Cycle when the warmup percentage was hit. 948system.cpu0.l2cache.tags.occ_blocks::writebacks 15163.258465 # Average occupied blocks per requestor 949system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 49.967950 # Average occupied blocks per requestor 950system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 74.840251 # Average occupied blocks per requestor 951system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 875.515436 # Average occupied blocks per requestor 952system.cpu0.l2cache.tags.occ_percent::writebacks 0.925492 # Average percentage of cache occupancy 953system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003050 # Average percentage of cache occupancy 954system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004568 # Average percentage of cache occupancy 955system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.053437 # Average percentage of cache occupancy 956system.cpu0.l2cache.tags.occ_percent::total 0.986547 # Average percentage of cache occupancy 957system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1542 # Occupied blocks per task id 958system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 959system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13561 # Occupied blocks per task id 960system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 58 # Occupied blocks per task id 961system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 726 # Occupied blocks per task id 962system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 758 # Occupied blocks per task id 963system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 36 # Occupied blocks per task id 964system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id 965system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 590 # Occupied blocks per task id 966system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6261 # Occupied blocks per task id 967system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 6710 # Occupied blocks per task id 968system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.094116 # Percentage of cache occupancy per task id 969system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 970system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.827698 # Percentage of cache occupancy per task id 971system.cpu0.l2cache.tags.tag_accesses 339677714 # Number of tag accesses 972system.cpu0.l2cache.tags.data_accesses 339677714 # Number of data accesses 973system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 214201 # number of ReadReq hits 974system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 132495 # number of ReadReq hits 975system.cpu0.l2cache.ReadReq_hits::total 346696 # number of ReadReq hits 976system.cpu0.l2cache.WritebackDirty_hits::writebacks 3462500 # number of WritebackDirty hits 977system.cpu0.l2cache.WritebackDirty_hits::total 3462500 # number of WritebackDirty hits 978system.cpu0.l2cache.WritebackClean_hits::writebacks 6546722 # number of WritebackClean hits 979system.cpu0.l2cache.WritebackClean_hits::total 6546722 # number of WritebackClean hits 980system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 323 # number of UpgradeReq hits 981system.cpu0.l2cache.UpgradeReq_hits::total 323 # number of UpgradeReq hits 982system.cpu0.l2cache.ReadExReq_hits::cpu0.data 835467 # number of ReadExReq hits 983system.cpu0.l2cache.ReadExReq_hits::total 835467 # number of ReadExReq hits 984system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4337083 # number of ReadCleanReq hits 985system.cpu0.l2cache.ReadCleanReq_hits::total 4337083 # number of ReadCleanReq hits 986system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2670834 # number of ReadSharedReq hits 987system.cpu0.l2cache.ReadSharedReq_hits::total 2670834 # number of ReadSharedReq hits 988system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 164201 # number of InvalidateReq hits 989system.cpu0.l2cache.InvalidateReq_hits::total 164201 # number of InvalidateReq hits 990system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 214201 # number of demand (read+write) hits 991system.cpu0.l2cache.demand_hits::cpu0.itb.walker 132495 # number of demand (read+write) hits 992system.cpu0.l2cache.demand_hits::cpu0.inst 4337083 # number of demand (read+write) hits 993system.cpu0.l2cache.demand_hits::cpu0.data 3506301 # number of demand (read+write) hits 994system.cpu0.l2cache.demand_hits::total 8190080 # number of demand (read+write) hits 995system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 214201 # number of overall hits 996system.cpu0.l2cache.overall_hits::cpu0.itb.walker 132495 # number of overall hits 997system.cpu0.l2cache.overall_hits::cpu0.inst 4337083 # number of overall hits 998system.cpu0.l2cache.overall_hits::cpu0.data 3506301 # number of overall hits 999system.cpu0.l2cache.overall_hits::total 8190080 # number of overall hits 1000system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 9167 # number of ReadReq misses 1001system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7221 # number of ReadReq misses 1002system.cpu0.l2cache.ReadReq_misses::total 16388 # number of ReadReq misses 1003system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 234409 # number of UpgradeReq misses 1004system.cpu0.l2cache.UpgradeReq_misses::total 234409 # number of UpgradeReq misses 1005system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190710 # number of SCUpgradeReq misses 1006system.cpu0.l2cache.SCUpgradeReq_misses::total 190710 # number of SCUpgradeReq misses 1007system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 31 # number of SCUpgradeFailReq misses 1008system.cpu0.l2cache.SCUpgradeFailReq_misses::total 31 # number of SCUpgradeFailReq misses 1009system.cpu0.l2cache.ReadExReq_misses::cpu0.data 244449 # number of ReadExReq misses 1010system.cpu0.l2cache.ReadExReq_misses::total 244449 # number of ReadExReq misses 1011system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 435799 # number of ReadCleanReq misses 1012system.cpu0.l2cache.ReadCleanReq_misses::total 435799 # number of ReadCleanReq misses 1013system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 871525 # number of ReadSharedReq misses 1014system.cpu0.l2cache.ReadSharedReq_misses::total 871525 # number of ReadSharedReq misses 1015system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 555346 # number of InvalidateReq misses 1016system.cpu0.l2cache.InvalidateReq_misses::total 555346 # number of InvalidateReq misses 1017system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 9167 # number of demand (read+write) misses 1018system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7221 # number of demand (read+write) misses 1019system.cpu0.l2cache.demand_misses::cpu0.inst 435799 # number of demand (read+write) misses 1020system.cpu0.l2cache.demand_misses::cpu0.data 1115974 # number of demand (read+write) misses 1021system.cpu0.l2cache.demand_misses::total 1568161 # number of demand (read+write) misses 1022system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 9167 # number of overall misses 1023system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7221 # number of overall misses 1024system.cpu0.l2cache.overall_misses::cpu0.inst 435799 # number of overall misses 1025system.cpu0.l2cache.overall_misses::cpu0.data 1115974 # number of overall misses 1026system.cpu0.l2cache.overall_misses::total 1568161 # number of overall misses 1027system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 351604000 # number of ReadReq miss cycles 1028system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 298997000 # number of ReadReq miss cycles 1029system.cpu0.l2cache.ReadReq_miss_latency::total 650601000 # number of ReadReq miss cycles 1030system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3324963500 # number of UpgradeReq miss cycles 1031system.cpu0.l2cache.UpgradeReq_miss_latency::total 3324963500 # number of UpgradeReq miss cycles 1032system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1970779500 # number of SCUpgradeReq miss cycles 1033system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1970779500 # number of SCUpgradeReq miss cycles 1034system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 6951500 # number of SCUpgradeFailReq miss cycles 1035system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 6951500 # number of SCUpgradeFailReq miss cycles 1036system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15779075998 # number of ReadExReq miss cycles 1037system.cpu0.l2cache.ReadExReq_miss_latency::total 15779075998 # number of ReadExReq miss cycles 1038system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17377629000 # number of ReadCleanReq miss cycles 1039system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17377629000 # number of ReadCleanReq miss cycles 1040system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 34720917000 # number of ReadSharedReq miss cycles 1041system.cpu0.l2cache.ReadSharedReq_miss_latency::total 34720917000 # number of ReadSharedReq miss cycles 1042system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62263259000 # number of InvalidateReq miss cycles 1043system.cpu0.l2cache.InvalidateReq_miss_latency::total 62263259000 # number of InvalidateReq miss cycles 1044system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 351604000 # number of demand (read+write) miss cycles 1045system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 298997000 # number of demand (read+write) miss cycles 1046system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17377629000 # number of demand (read+write) miss cycles 1047system.cpu0.l2cache.demand_miss_latency::cpu0.data 50499992998 # number of demand (read+write) miss cycles 1048system.cpu0.l2cache.demand_miss_latency::total 68528222998 # number of demand (read+write) miss cycles 1049system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 351604000 # number of overall miss cycles 1050system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 298997000 # number of overall miss cycles 1051system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17377629000 # number of overall miss cycles 1052system.cpu0.l2cache.overall_miss_latency::cpu0.data 50499992998 # number of overall miss cycles 1053system.cpu0.l2cache.overall_miss_latency::total 68528222998 # number of overall miss cycles 1054system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 223368 # number of ReadReq accesses(hits+misses) 1055system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 139716 # number of ReadReq accesses(hits+misses) 1056system.cpu0.l2cache.ReadReq_accesses::total 363084 # number of ReadReq accesses(hits+misses) 1057system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3462500 # number of WritebackDirty accesses(hits+misses) 1058system.cpu0.l2cache.WritebackDirty_accesses::total 3462500 # number of WritebackDirty accesses(hits+misses) 1059system.cpu0.l2cache.WritebackClean_accesses::writebacks 6546722 # number of WritebackClean accesses(hits+misses) 1060system.cpu0.l2cache.WritebackClean_accesses::total 6546722 # number of WritebackClean accesses(hits+misses) 1061system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 234732 # number of UpgradeReq accesses(hits+misses) 1062system.cpu0.l2cache.UpgradeReq_accesses::total 234732 # number of UpgradeReq accesses(hits+misses) 1063system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190710 # number of SCUpgradeReq accesses(hits+misses) 1064system.cpu0.l2cache.SCUpgradeReq_accesses::total 190710 # number of SCUpgradeReq accesses(hits+misses) 1065system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 31 # number of SCUpgradeFailReq accesses(hits+misses) 1066system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 31 # number of SCUpgradeFailReq accesses(hits+misses) 1067system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1079916 # number of ReadExReq accesses(hits+misses) 1068system.cpu0.l2cache.ReadExReq_accesses::total 1079916 # number of ReadExReq accesses(hits+misses) 1069system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4772882 # number of ReadCleanReq accesses(hits+misses) 1070system.cpu0.l2cache.ReadCleanReq_accesses::total 4772882 # number of ReadCleanReq accesses(hits+misses) 1071system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3542359 # number of ReadSharedReq accesses(hits+misses) 1072system.cpu0.l2cache.ReadSharedReq_accesses::total 3542359 # number of ReadSharedReq accesses(hits+misses) 1073system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 719547 # number of InvalidateReq accesses(hits+misses) 1074system.cpu0.l2cache.InvalidateReq_accesses::total 719547 # number of InvalidateReq accesses(hits+misses) 1075system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 223368 # number of demand (read+write) accesses 1076system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 139716 # number of demand (read+write) accesses 1077system.cpu0.l2cache.demand_accesses::cpu0.inst 4772882 # number of demand (read+write) accesses 1078system.cpu0.l2cache.demand_accesses::cpu0.data 4622275 # number of demand (read+write) accesses 1079system.cpu0.l2cache.demand_accesses::total 9758241 # number of demand (read+write) accesses 1080system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 223368 # number of overall (read+write) accesses 1081system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 139716 # number of overall (read+write) accesses 1082system.cpu0.l2cache.overall_accesses::cpu0.inst 4772882 # number of overall (read+write) accesses 1083system.cpu0.l2cache.overall_accesses::cpu0.data 4622275 # number of overall (read+write) accesses 1084system.cpu0.l2cache.overall_accesses::total 9758241 # number of overall (read+write) accesses 1085system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.041040 # miss rate for ReadReq accesses 1086system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051683 # miss rate for ReadReq accesses 1087system.cpu0.l2cache.ReadReq_miss_rate::total 0.045136 # miss rate for ReadReq accesses 1088system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998624 # miss rate for UpgradeReq accesses 1089system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998624 # miss rate for UpgradeReq accesses 1090system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1091system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1092system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1093system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1094system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.226359 # miss rate for ReadExReq accesses 1095system.cpu0.l2cache.ReadExReq_miss_rate::total 0.226359 # miss rate for ReadExReq accesses 1096system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.091307 # miss rate for ReadCleanReq accesses 1097system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.091307 # miss rate for ReadCleanReq accesses 1098system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.246030 # miss rate for ReadSharedReq accesses 1099system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.246030 # miss rate for ReadSharedReq accesses 1100system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.771799 # miss rate for InvalidateReq accesses 1101system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.771799 # miss rate for InvalidateReq accesses 1102system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.041040 # miss rate for demand accesses 1103system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051683 # miss rate for demand accesses 1104system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.091307 # miss rate for demand accesses 1105system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241434 # miss rate for demand accesses 1106system.cpu0.l2cache.demand_miss_rate::total 0.160701 # miss rate for demand accesses 1107system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.041040 # miss rate for overall accesses 1108system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051683 # miss rate for overall accesses 1109system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.091307 # miss rate for overall accesses 1110system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241434 # miss rate for overall accesses 1111system.cpu0.l2cache.overall_miss_rate::total 0.160701 # miss rate for overall accesses 1112system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38355.405258 # average ReadReq miss latency 1113system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41406.591885 # average ReadReq miss latency 1114system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39699.841347 # average ReadReq miss latency 1115system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14184.453242 # average UpgradeReq miss latency 1116system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14184.453242 # average UpgradeReq miss latency 1117system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10333.907504 # average SCUpgradeReq miss latency 1118system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10333.907504 # average SCUpgradeReq miss latency 1119system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 224241.935484 # average SCUpgradeFailReq miss latency 1120system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 224241.935484 # average SCUpgradeFailReq miss latency 1121system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 64549.562477 # average ReadExReq miss latency 1122system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 64549.562477 # average ReadExReq miss latency 1123system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39875.330141 # average ReadCleanReq miss latency 1124system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39875.330141 # average ReadCleanReq miss latency 1125system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 39839.266802 # average ReadSharedReq miss latency 1126system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 39839.266802 # average ReadSharedReq miss latency 1127system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 112116.156414 # average InvalidateReq miss latency 1128system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 112116.156414 # average InvalidateReq miss latency 1129system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38355.405258 # average overall miss latency 1130system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41406.591885 # average overall miss latency 1131system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39875.330141 # average overall miss latency 1132system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45251.944040 # average overall miss latency 1133system.cpu0.l2cache.demand_avg_miss_latency::total 43699.736824 # average overall miss latency 1134system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38355.405258 # average overall miss latency 1135system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41406.591885 # average overall miss latency 1136system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39875.330141 # average overall miss latency 1137system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45251.944040 # average overall miss latency 1138system.cpu0.l2cache.overall_avg_miss_latency::total 43699.736824 # average overall miss latency 1139system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1140system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1141system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1142system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1143system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1144system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1145system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1146system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1147system.cpu0.l2cache.writebacks::writebacks 1408018 # number of writebacks 1148system.cpu0.l2cache.writebacks::total 1408018 # number of writebacks 1149system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5268 # number of ReadExReq MSHR hits 1150system.cpu0.l2cache.ReadExReq_mshr_hits::total 5268 # number of ReadExReq MSHR hits 1151system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 532 # number of ReadSharedReq MSHR hits 1152system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 532 # number of ReadSharedReq MSHR hits 1153system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5800 # number of demand (read+write) MSHR hits 1154system.cpu0.l2cache.demand_mshr_hits::total 5800 # number of demand (read+write) MSHR hits 1155system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5800 # number of overall MSHR hits 1156system.cpu0.l2cache.overall_mshr_hits::total 5800 # number of overall MSHR hits 1157system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 9167 # number of ReadReq MSHR misses 1158system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7221 # number of ReadReq MSHR misses 1159system.cpu0.l2cache.ReadReq_mshr_misses::total 16388 # number of ReadReq MSHR misses 1160system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 673244 # number of HardPFReq MSHR misses 1161system.cpu0.l2cache.HardPFReq_mshr_misses::total 673244 # number of HardPFReq MSHR misses 1162system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 234409 # number of UpgradeReq MSHR misses 1163system.cpu0.l2cache.UpgradeReq_mshr_misses::total 234409 # number of UpgradeReq MSHR misses 1164system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 190710 # number of SCUpgradeReq MSHR misses 1165system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 190710 # number of SCUpgradeReq MSHR misses 1166system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 31 # number of SCUpgradeFailReq MSHR misses 1167system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 31 # number of SCUpgradeFailReq MSHR misses 1168system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 239181 # number of ReadExReq MSHR misses 1169system.cpu0.l2cache.ReadExReq_mshr_misses::total 239181 # number of ReadExReq MSHR misses 1170system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 435799 # number of ReadCleanReq MSHR misses 1171system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 435799 # number of ReadCleanReq MSHR misses 1172system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 870993 # number of ReadSharedReq MSHR misses 1173system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 870993 # number of ReadSharedReq MSHR misses 1174system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 555346 # number of InvalidateReq MSHR misses 1175system.cpu0.l2cache.InvalidateReq_mshr_misses::total 555346 # number of InvalidateReq MSHR misses 1176system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 9167 # number of demand (read+write) MSHR misses 1177system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7221 # number of demand (read+write) MSHR misses 1178system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 435799 # number of demand (read+write) MSHR misses 1179system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1110174 # number of demand (read+write) MSHR misses 1180system.cpu0.l2cache.demand_mshr_misses::total 1562361 # number of demand (read+write) MSHR misses 1181system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 9167 # number of overall MSHR misses 1182system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7221 # number of overall MSHR misses 1183system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 435799 # number of overall MSHR misses 1184system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1110174 # number of overall MSHR misses 1185system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 673244 # number of overall MSHR misses 1186system.cpu0.l2cache.overall_mshr_misses::total 2235605 # number of overall MSHR misses 1187system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 1188system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16746 # number of ReadReq MSHR uncacheable 1189system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59871 # number of ReadReq MSHR uncacheable 1190system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17968 # number of WriteReq MSHR uncacheable 1191system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17968 # number of WriteReq MSHR uncacheable 1192system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 1193system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34714 # number of overall MSHR uncacheable misses 1194system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77839 # number of overall MSHR uncacheable misses 1195system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 296602000 # number of ReadReq MSHR miss cycles 1196system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 255671000 # number of ReadReq MSHR miss cycles 1197system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 552273000 # number of ReadReq MSHR miss cycles 1198system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 37620512818 # number of HardPFReq MSHR miss cycles 1199system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 37620512818 # number of HardPFReq MSHR miss cycles 1200system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7511827000 # number of UpgradeReq MSHR miss cycles 1201system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7511827000 # number of UpgradeReq MSHR miss cycles 1202system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3867075000 # number of SCUpgradeReq MSHR miss cycles 1203system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3867075000 # number of SCUpgradeReq MSHR miss cycles 1204system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6477500 # number of SCUpgradeFailReq MSHR miss cycles 1205system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6477500 # number of SCUpgradeFailReq MSHR miss cycles 1206system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13744375998 # number of ReadExReq MSHR miss cycles 1207system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13744375998 # number of ReadExReq MSHR miss cycles 1208system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 14762835000 # number of ReadCleanReq MSHR miss cycles 1209system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 14762835000 # number of ReadCleanReq MSHR miss cycles 1210system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 29450022000 # number of ReadSharedReq MSHR miss cycles 1211system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 29450022000 # number of ReadSharedReq MSHR miss cycles 1212system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 58931183000 # number of InvalidateReq MSHR miss cycles 1213system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 58931183000 # number of InvalidateReq MSHR miss cycles 1214system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 296602000 # number of demand (read+write) MSHR miss cycles 1215system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 255671000 # number of demand (read+write) MSHR miss cycles 1216system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 14762835000 # number of demand (read+write) MSHR miss cycles 1217system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43194397998 # number of demand (read+write) MSHR miss cycles 1218system.cpu0.l2cache.demand_mshr_miss_latency::total 58509505998 # number of demand (read+write) MSHR miss cycles 1219system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 296602000 # number of overall MSHR miss cycles 1220system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 255671000 # number of overall MSHR miss cycles 1221system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 14762835000 # number of overall MSHR miss cycles 1222system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43194397998 # number of overall MSHR miss cycles 1223system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 37620512818 # number of overall MSHR miss cycles 1224system.cpu0.l2cache.overall_mshr_miss_latency::total 96130018816 # number of overall MSHR miss cycles 1225system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles 1226system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2763179500 # number of ReadReq MSHR uncacheable cycles 1227system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8393951000 # number of ReadReq MSHR uncacheable cycles 1228system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2967633500 # number of WriteReq MSHR uncacheable cycles 1229system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2967633500 # number of WriteReq MSHR uncacheable cycles 1230system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles 1231system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5730813000 # number of overall MSHR uncacheable cycles 1232system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11361584500 # number of overall MSHR uncacheable cycles 1233system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for ReadReq accesses 1234system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for ReadReq accesses 1235system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.045136 # mshr miss rate for ReadReq accesses 1236system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1237system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1238system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998624 # mshr miss rate for UpgradeReq accesses 1239system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998624 # mshr miss rate for UpgradeReq accesses 1240system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1241system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1242system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1243system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1244system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221481 # mshr miss rate for ReadExReq accesses 1245system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221481 # mshr miss rate for ReadExReq accesses 1246system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for ReadCleanReq accesses 1247system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091307 # mshr miss rate for ReadCleanReq accesses 1248system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.245879 # mshr miss rate for ReadSharedReq accesses 1249system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245879 # mshr miss rate for ReadSharedReq accesses 1250system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771799 # mshr miss rate for InvalidateReq accesses 1251system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771799 # mshr miss rate for InvalidateReq accesses 1252system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for demand accesses 1253system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for demand accesses 1254system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for demand accesses 1255system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240179 # mshr miss rate for demand accesses 1256system.cpu0.l2cache.demand_mshr_miss_rate::total 0.160107 # mshr miss rate for demand accesses 1257system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.041040 # mshr miss rate for overall accesses 1258system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051683 # mshr miss rate for overall accesses 1259system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.091307 # mshr miss rate for overall accesses 1260system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240179 # mshr miss rate for overall accesses 1261system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1262system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229099 # mshr miss rate for overall accesses 1263system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average ReadReq mshr miss latency 1264system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average ReadReq mshr miss latency 1265system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33699.841347 # average ReadReq mshr miss latency 1266system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450 # average HardPFReq mshr miss latency 1267system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55879.462450 # average HardPFReq mshr miss latency 1268system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32045.813087 # average UpgradeReq mshr miss latency 1269system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32045.813087 # average UpgradeReq mshr miss latency 1270system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20277.253421 # average SCUpgradeReq mshr miss latency 1271system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20277.253421 # average SCUpgradeReq mshr miss latency 1272system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 208951.612903 # average SCUpgradeFailReq mshr miss latency 1273system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 208951.612903 # average SCUpgradeFailReq mshr miss latency 1274system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57464.330352 # average ReadExReq mshr miss latency 1275system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57464.330352 # average ReadExReq mshr miss latency 1276system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average ReadCleanReq mshr miss latency 1277system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33875.330141 # average ReadCleanReq mshr miss latency 1278system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33812.007674 # average ReadSharedReq mshr miss latency 1279system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33812.007674 # average ReadSharedReq mshr miss latency 1280system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 106116.156414 # average InvalidateReq mshr miss latency 1281system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 106116.156414 # average InvalidateReq mshr miss latency 1282system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency 1283system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency 1284system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency 1285system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency 1286system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37449.415339 # average overall mshr miss latency 1287system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32355.405258 # average overall mshr miss latency 1288system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35406.591885 # average overall mshr miss latency 1289system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33875.330141 # average overall mshr miss latency 1290system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38907.773014 # average overall mshr miss latency 1291system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55879.462450 # average overall mshr miss latency 1292system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42999.554401 # average overall mshr miss latency 1293system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency 1294system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165005.344560 # average ReadReq mshr uncacheable latency 1295system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 140200.614655 # average ReadReq mshr uncacheable latency 1296system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165162.149377 # average WriteReq mshr uncacheable latency 1297system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165162.149377 # average WriteReq mshr uncacheable latency 1298system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency 1299system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165086.506885 # average overall mshr uncacheable latency 1300system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 145962.621565 # average overall mshr uncacheable latency 1301system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1302system.cpu0.toL2Bus.snoop_filter.tot_requests 20776945 # Total number of requests made to the snoop filter. 1303system.cpu0.toL2Bus.snoop_filter.hit_single_requests 10662406 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1304system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 659 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1305system.cpu0.toL2Bus.snoop_filter.tot_snoops 1726264 # Total number of snoops made to the snoop filter. 1306system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1726085 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1307system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 179 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1308system.cpu0.toL2Bus.trans_dist::ReadReq 488069 # Transaction distribution 1309system.cpu0.toL2Bus.trans_dist::ReadResp 8911186 # Transaction distribution 1310system.cpu0.toL2Bus.trans_dist::WriteReq 17968 # Transaction distribution 1311system.cpu0.toL2Bus.trans_dist::WriteResp 17968 # Transaction distribution 1312system.cpu0.toL2Bus.trans_dist::WritebackDirty 4874700 # Transaction distribution 1313system.cpu0.toL2Bus.trans_dist::WritebackClean 6546722 # Transaction distribution 1314system.cpu0.toL2Bus.trans_dist::CleanEvict 2139143 # Transaction distribution 1315system.cpu0.toL2Bus.trans_dist::HardPFReq 829102 # Transaction distribution 1316system.cpu0.toL2Bus.trans_dist::UpgradeReq 434919 # Transaction distribution 1317system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 350602 # Transaction distribution 1318system.cpu0.toL2Bus.trans_dist::UpgradeResp 501065 # Transaction distribution 1319system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 90 # Transaction distribution 1320system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 1321system.cpu0.toL2Bus.trans_dist::ReadExReq 1159158 # Transaction distribution 1322system.cpu0.toL2Bus.trans_dist::ReadExResp 1092705 # Transaction distribution 1323system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4772882 # Transaction distribution 1324system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4419934 # Transaction distribution 1325system.cpu0.toL2Bus.trans_dist::InvalidateReq 726049 # Transaction distribution 1326system.cpu0.toL2Bus.trans_dist::InvalidateResp 719547 # Transaction distribution 1327system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14404114 # Packet count per connected master and slave (bytes) 1328system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17037537 # Packet count per connected master and slave (bytes) 1329system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296236 # Packet count per connected master and slave (bytes) 1330system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 495044 # Packet count per connected master and slave (bytes) 1331system.cpu0.toL2Bus.pkt_count::total 32232931 # Packet count per connected master and slave (bytes) 1332system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 611051348 # Cumulative packet size per connected master and slave (bytes) 1333system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 638823901 # Cumulative packet size per connected master and slave (bytes) 1334system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1117728 # Cumulative packet size per connected master and slave (bytes) 1335system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1786944 # Cumulative packet size per connected master and slave (bytes) 1336system.cpu0.toL2Bus.pkt_size::total 1252779921 # Cumulative packet size per connected master and slave (bytes) 1337system.cpu0.toL2Bus.snoops 5965413 # Total snoops (count) 1338system.cpu0.toL2Bus.snoop_fanout::samples 16750116 # Request fanout histogram 1339system.cpu0.toL2Bus.snoop_fanout::mean 0.116655 # Request fanout histogram 1340system.cpu0.toL2Bus.snoop_fanout::stdev 0.321042 # Request fanout histogram 1341system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1342system.cpu0.toL2Bus.snoop_fanout::0 14796306 88.34% 88.34% # Request fanout histogram 1343system.cpu0.toL2Bus.snoop_fanout::1 1953631 11.66% 100.00% # Request fanout histogram 1344system.cpu0.toL2Bus.snoop_fanout::2 179 0.00% 100.00% # Request fanout histogram 1345system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1346system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1347system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1348system.cpu0.toL2Bus.snoop_fanout::total 16750116 # Request fanout histogram 1349system.cpu0.toL2Bus.reqLayer0.occupancy 20546913496 # Layer occupancy (ticks) 1350system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1351system.cpu0.toL2Bus.snoopLayer0.occupancy 219185391 # Layer occupancy (ticks) 1352system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1353system.cpu0.toL2Bus.respLayer0.occupancy 7202448000 # Layer occupancy (ticks) 1354system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1355system.cpu0.toL2Bus.respLayer1.occupancy 7531952589 # Layer occupancy (ticks) 1356system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1357system.cpu0.toL2Bus.respLayer2.occupancy 156520499 # Layer occupancy (ticks) 1358system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1359system.cpu0.toL2Bus.respLayer3.occupancy 271676000 # Layer occupancy (ticks) 1360system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1361system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1362system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1363system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1364system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1365system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1366system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1367system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1368system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1369system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1370system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1371system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1372system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1373system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1374system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1375system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1376system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1377system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1378system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1379system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1380system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1381system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1382system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1383system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1384system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1385system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1386system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1387system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1388system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1389system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1390system.cpu1.dtb.walker.walks 101882 # Table walker walks requested 1391system.cpu1.dtb.walker.walksLong 101882 # Table walker walks initiated with long descriptors 1392system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8030 # Level at which table walker walks with long descriptors terminate 1393system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 79527 # Level at which table walker walks with long descriptors terminate 1394system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting 1395system.cpu1.dtb.walker.walkWaitTime::samples 101873 # Table walker wait (enqueue to first request) latency 1396system.cpu1.dtb.walker.walkWaitTime::mean 0.078529 # Table walker wait (enqueue to first request) latency 1397system.cpu1.dtb.walker.walkWaitTime::stdev 25.064580 # Table walker wait (enqueue to first request) latency 1398system.cpu1.dtb.walker.walkWaitTime::0-511 101872 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1399system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1400system.cpu1.dtb.walker.walkWaitTime::total 101873 # Table walker wait (enqueue to first request) latency 1401system.cpu1.dtb.walker.walkCompletionTime::samples 87566 # Table walker service (enqueue to completion) latency 1402system.cpu1.dtb.walker.walkCompletionTime::mean 23519.505287 # Table walker service (enqueue to completion) latency 1403system.cpu1.dtb.walker.walkCompletionTime::gmean 21365.105207 # Table walker service (enqueue to completion) latency 1404system.cpu1.dtb.walker.walkCompletionTime::stdev 20825.826742 # Table walker service (enqueue to completion) latency 1405system.cpu1.dtb.walker.walkCompletionTime::0-65535 86337 98.60% 98.60% # Table walker service (enqueue to completion) latency 1406system.cpu1.dtb.walker.walkCompletionTime::65536-131071 178 0.20% 98.80% # Table walker service (enqueue to completion) latency 1407system.cpu1.dtb.walker.walkCompletionTime::131072-196607 904 1.03% 99.83% # Table walker service (enqueue to completion) latency 1408system.cpu1.dtb.walker.walkCompletionTime::196608-262143 19 0.02% 99.85% # Table walker service (enqueue to completion) latency 1409system.cpu1.dtb.walker.walkCompletionTime::262144-327679 55 0.06% 99.92% # Table walker service (enqueue to completion) latency 1410system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.93% # Table walker service (enqueue to completion) latency 1411system.cpu1.dtb.walker.walkCompletionTime::393216-458751 42 0.05% 99.98% # Table walker service (enqueue to completion) latency 1412system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.01% 99.99% # Table walker service (enqueue to completion) latency 1413system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1414system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1415system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1416system.cpu1.dtb.walker.walkCompletionTime::total 87566 # Table walker service (enqueue to completion) latency 1417system.cpu1.dtb.walker.walksPending::samples 239339024 # Table walker pending requests distribution 1418system.cpu1.dtb.walker.walksPending::mean 9.661342 # Table walker pending requests distribution 1419system.cpu1.dtb.walker.walksPending::0 -2072997220 -866.13% -866.13% # Table walker pending requests distribution 1420system.cpu1.dtb.walker.walksPending::1 2312336244 966.13% 100.00% # Table walker pending requests distribution 1421system.cpu1.dtb.walker.walksPending::total 239339024 # Table walker pending requests distribution 1422system.cpu1.dtb.walker.walkPageSizes::4K 79528 90.83% 90.83% # Table walker page sizes translated 1423system.cpu1.dtb.walker.walkPageSizes::2M 8030 9.17% 100.00% # Table walker page sizes translated 1424system.cpu1.dtb.walker.walkPageSizes::total 87558 # Table walker page sizes translated 1425system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 101882 # Table walker requests started/completed, data/inst 1426system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1427system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 101882 # Table walker requests started/completed, data/inst 1428system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87558 # Table walker requests started/completed, data/inst 1429system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1430system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87558 # Table walker requests started/completed, data/inst 1431system.cpu1.dtb.walker.walkRequestOrigin::total 189440 # Table walker requests started/completed, data/inst 1432system.cpu1.dtb.inst_hits 0 # ITB inst hits 1433system.cpu1.dtb.inst_misses 0 # ITB inst misses 1434system.cpu1.dtb.read_hits 82176038 # DTB read hits 1435system.cpu1.dtb.read_misses 74927 # DTB read misses 1436system.cpu1.dtb.write_hits 74775352 # DTB write hits 1437system.cpu1.dtb.write_misses 26955 # DTB write misses 1438system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1439system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1440system.cpu1.dtb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID 1441system.cpu1.dtb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID 1442system.cpu1.dtb.flush_entries 37701 # Number of entries that have been flushed from TLB 1443system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1444system.cpu1.dtb.prefetch_faults 4186 # Number of TLB faults due to prefetch 1445system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1446system.cpu1.dtb.perms_faults 10277 # Number of TLB faults due to permissions restrictions 1447system.cpu1.dtb.read_accesses 82250965 # DTB read accesses 1448system.cpu1.dtb.write_accesses 74802307 # DTB write accesses 1449system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1450system.cpu1.dtb.hits 156951390 # DTB hits 1451system.cpu1.dtb.misses 101882 # DTB misses 1452system.cpu1.dtb.accesses 157053272 # DTB accesses 1453system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1454system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1455system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1456system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1457system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1458system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1459system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1460system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1461system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1462system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1463system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1464system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1465system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1466system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1467system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1468system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1469system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1470system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1471system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1472system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1473system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1474system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1475system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1476system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1477system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1478system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1479system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1480system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1481system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1482system.cpu1.itb.walker.walks 63786 # Table walker walks requested 1483system.cpu1.itb.walker.walksLong 63786 # Table walker walks initiated with long descriptors 1484system.cpu1.itb.walker.walksLongTerminationLevel::Level2 574 # Level at which table walker walks with long descriptors terminate 1485system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58046 # Level at which table walker walks with long descriptors terminate 1486system.cpu1.itb.walker.walkWaitTime::samples 63786 # Table walker wait (enqueue to first request) latency 1487system.cpu1.itb.walker.walkWaitTime::0 63786 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1488system.cpu1.itb.walker.walkWaitTime::total 63786 # Table walker wait (enqueue to first request) latency 1489system.cpu1.itb.walker.walkCompletionTime::samples 58620 # Table walker service (enqueue to completion) latency 1490system.cpu1.itb.walker.walkCompletionTime::mean 26694.208461 # Table walker service (enqueue to completion) latency 1491system.cpu1.itb.walker.walkCompletionTime::gmean 23680.273613 # Table walker service (enqueue to completion) latency 1492system.cpu1.itb.walker.walkCompletionTime::stdev 26398.773524 # Table walker service (enqueue to completion) latency 1493system.cpu1.itb.walker.walkCompletionTime::0-65535 57379 97.88% 97.88% # Table walker service (enqueue to completion) latency 1494system.cpu1.itb.walker.walkCompletionTime::65536-131071 45 0.08% 97.96% # Table walker service (enqueue to completion) latency 1495system.cpu1.itb.walker.walkCompletionTime::131072-196607 1025 1.75% 99.71% # Table walker service (enqueue to completion) latency 1496system.cpu1.itb.walker.walkCompletionTime::196608-262143 33 0.06% 99.76% # Table walker service (enqueue to completion) latency 1497system.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.85% # Table walker service (enqueue to completion) latency 1498system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.04% 99.89% # Table walker service (enqueue to completion) latency 1499system.cpu1.itb.walker.walkCompletionTime::393216-458751 49 0.08% 99.97% # Table walker service (enqueue to completion) latency 1500system.cpu1.itb.walker.walkCompletionTime::458752-524287 9 0.02% 99.99% # Table walker service (enqueue to completion) latency 1501system.cpu1.itb.walker.walkCompletionTime::524288-589823 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 1502system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1503system.cpu1.itb.walker.walkCompletionTime::total 58620 # Table walker service (enqueue to completion) latency 1504system.cpu1.itb.walker.walksPending::samples -2103779220 # Table walker pending requests distribution 1505system.cpu1.itb.walker.walksPending::0 -2103779220 100.00% 100.00% # Table walker pending requests distribution 1506system.cpu1.itb.walker.walksPending::total -2103779220 # Table walker pending requests distribution 1507system.cpu1.itb.walker.walkPageSizes::4K 58046 99.02% 99.02% # Table walker page sizes translated 1508system.cpu1.itb.walker.walkPageSizes::2M 574 0.98% 100.00% # Table walker page sizes translated 1509system.cpu1.itb.walker.walkPageSizes::total 58620 # Table walker page sizes translated 1510system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1511system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 63786 # Table walker requests started/completed, data/inst 1512system.cpu1.itb.walker.walkRequestOrigin_Requested::total 63786 # Table walker requests started/completed, data/inst 1513system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1514system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58620 # Table walker requests started/completed, data/inst 1515system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58620 # Table walker requests started/completed, data/inst 1516system.cpu1.itb.walker.walkRequestOrigin::total 122406 # Table walker requests started/completed, data/inst 1517system.cpu1.itb.inst_hits 435405767 # ITB inst hits 1518system.cpu1.itb.inst_misses 63786 # ITB inst misses 1519system.cpu1.itb.read_hits 0 # DTB read hits 1520system.cpu1.itb.read_misses 0 # DTB read misses 1521system.cpu1.itb.write_hits 0 # DTB write hits 1522system.cpu1.itb.write_misses 0 # DTB write misses 1523system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1524system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1525system.cpu1.itb.flush_tlb_mva_asid 39478 # Number of times TLB was flushed by MVA & ASID 1526system.cpu1.itb.flush_tlb_asid 1020 # Number of times TLB was flushed by ASID 1527system.cpu1.itb.flush_entries 26334 # Number of entries that have been flushed from TLB 1528system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1529system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1530system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1531system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1532system.cpu1.itb.read_accesses 0 # DTB read accesses 1533system.cpu1.itb.write_accesses 0 # DTB write accesses 1534system.cpu1.itb.inst_accesses 435469553 # ITB inst accesses 1535system.cpu1.itb.hits 435405767 # DTB hits 1536system.cpu1.itb.misses 63786 # DTB misses 1537system.cpu1.itb.accesses 435469553 # DTB accesses 1538system.cpu1.numCycles 95187488343 # number of cpu cycles simulated 1539system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1540system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1541system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1542system.cpu1.kern.inst.quiesce 14345 # number of quiesce instructions executed 1543system.cpu1.committedInsts 435108521 # Number of instructions committed 1544system.cpu1.committedOps 512619121 # Number of ops (including micro ops) committed 1545system.cpu1.num_int_alu_accesses 471360298 # Number of integer alu accesses 1546system.cpu1.num_fp_alu_accesses 517037 # Number of float alu accesses 1547system.cpu1.num_func_calls 26310177 # number of times a function call or return occured 1548system.cpu1.num_conditional_control_insts 66181606 # number of instructions that are conditional controls 1549system.cpu1.num_int_insts 471360298 # number of integer instructions 1550system.cpu1.num_fp_insts 517037 # number of float instructions 1551system.cpu1.num_int_register_reads 683625420 # number of times the integer registers were read 1552system.cpu1.num_int_register_writes 373659475 # number of times the integer registers were written 1553system.cpu1.num_fp_register_reads 819092 # number of times the floating registers were read 1554system.cpu1.num_fp_register_writes 470852 # number of times the floating registers were written 1555system.cpu1.num_cc_register_reads 112718016 # number of times the CC registers were read 1556system.cpu1.num_cc_register_writes 112414585 # number of times the CC registers were written 1557system.cpu1.num_mem_refs 156939308 # number of memory refs 1558system.cpu1.num_load_insts 82171340 # Number of load instructions 1559system.cpu1.num_store_insts 74767968 # Number of store instructions 1560system.cpu1.num_idle_cycles 94109373851.176025 # Number of idle cycles 1561system.cpu1.num_busy_cycles 1078114491.823977 # Number of busy cycles 1562system.cpu1.not_idle_fraction 0.011326 # Percentage of non-idle cycles 1563system.cpu1.idle_fraction 0.988674 # Percentage of idle cycles 1564system.cpu1.Branches 97258514 # Number of branches fetched 1565system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 1566system.cpu1.op_class::IntAlu 354775953 69.17% 69.17% # Class of executed instruction 1567system.cpu1.op_class::IntMult 1066461 0.21% 69.38% # Class of executed instruction 1568system.cpu1.op_class::IntDiv 59336 0.01% 69.39% # Class of executed instruction 1569system.cpu1.op_class::FloatAdd 0 0.00% 69.39% # Class of executed instruction 1570system.cpu1.op_class::FloatCmp 0 0.00% 69.39% # Class of executed instruction 1571system.cpu1.op_class::FloatCvt 0 0.00% 69.39% # Class of executed instruction 1572system.cpu1.op_class::FloatMult 0 0.00% 69.39% # Class of executed instruction 1573system.cpu1.op_class::FloatDiv 0 0.00% 69.39% # Class of executed instruction 1574system.cpu1.op_class::FloatSqrt 0 0.00% 69.39% # Class of executed instruction 1575system.cpu1.op_class::SimdAdd 0 0.00% 69.39% # Class of executed instruction 1576system.cpu1.op_class::SimdAddAcc 0 0.00% 69.39% # Class of executed instruction 1577system.cpu1.op_class::SimdAlu 0 0.00% 69.39% # Class of executed instruction 1578system.cpu1.op_class::SimdCmp 0 0.00% 69.39% # Class of executed instruction 1579system.cpu1.op_class::SimdCvt 0 0.00% 69.39% # Class of executed instruction 1580system.cpu1.op_class::SimdMisc 0 0.00% 69.39% # Class of executed instruction 1581system.cpu1.op_class::SimdMult 0 0.00% 69.39% # Class of executed instruction 1582system.cpu1.op_class::SimdMultAcc 0 0.00% 69.39% # Class of executed instruction 1583system.cpu1.op_class::SimdShift 0 0.00% 69.39% # Class of executed instruction 1584system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.39% # Class of executed instruction 1585system.cpu1.op_class::SimdSqrt 0 0.00% 69.39% # Class of executed instruction 1586system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.39% # Class of executed instruction 1587system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.39% # Class of executed instruction 1588system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.39% # Class of executed instruction 1589system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.39% # Class of executed instruction 1590system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.39% # Class of executed instruction 1591system.cpu1.op_class::SimdFloatMisc 75375 0.01% 69.40% # Class of executed instruction 1592system.cpu1.op_class::SimdFloatMult 0 0.00% 69.40% # Class of executed instruction 1593system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.40% # Class of executed instruction 1594system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.40% # Class of executed instruction 1595system.cpu1.op_class::MemRead 82171340 16.02% 85.42% # Class of executed instruction 1596system.cpu1.op_class::MemWrite 74767968 14.58% 100.00% # Class of executed instruction 1597system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1598system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1599system.cpu1.op_class::total 512916476 # Class of executed instruction 1600system.cpu1.dcache.tags.replacements 5113111 # number of replacements 1601system.cpu1.dcache.tags.tagsinuse 443.711015 # Cycle average of tags in use 1602system.cpu1.dcache.tags.total_refs 151630595 # Total number of references to valid blocks. 1603system.cpu1.dcache.tags.sampled_refs 5113623 # Sample count of references to valid blocks. 1604system.cpu1.dcache.tags.avg_refs 29.652283 # Average number of references to valid blocks. 1605system.cpu1.dcache.tags.warmup_cycle 8408412782000 # Cycle when the warmup percentage was hit. 1606system.cpu1.dcache.tags.occ_blocks::cpu1.data 443.711015 # Average occupied blocks per requestor 1607system.cpu1.dcache.tags.occ_percent::cpu1.data 0.866623 # Average percentage of cache occupancy 1608system.cpu1.dcache.tags.occ_percent::total 0.866623 # Average percentage of cache occupancy 1609system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1610system.cpu1.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 1611system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id 1612system.cpu1.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id 1613system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1614system.cpu1.dcache.tags.tag_accesses 319002554 # Number of tag accesses 1615system.cpu1.dcache.tags.data_accesses 319002554 # Number of data accesses 1616system.cpu1.dcache.ReadReq_hits::cpu1.data 76632055 # number of ReadReq hits 1617system.cpu1.dcache.ReadReq_hits::total 76632055 # number of ReadReq hits 1618system.cpu1.dcache.WriteReq_hits::cpu1.data 70902064 # number of WriteReq hits 1619system.cpu1.dcache.WriteReq_hits::total 70902064 # number of WriteReq hits 1620system.cpu1.dcache.SoftPFReq_hits::cpu1.data 183506 # number of SoftPFReq hits 1621system.cpu1.dcache.SoftPFReq_hits::total 183506 # number of SoftPFReq hits 1622system.cpu1.dcache.WriteLineReq_hits::cpu1.data 192465 # number of WriteLineReq hits 1623system.cpu1.dcache.WriteLineReq_hits::total 192465 # number of WriteLineReq hits 1624system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1673719 # number of LoadLockedReq hits 1625system.cpu1.dcache.LoadLockedReq_hits::total 1673719 # number of LoadLockedReq hits 1626system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1647145 # number of StoreCondReq hits 1627system.cpu1.dcache.StoreCondReq_hits::total 1647145 # number of StoreCondReq hits 1628system.cpu1.dcache.demand_hits::cpu1.data 147534119 # number of demand (read+write) hits 1629system.cpu1.dcache.demand_hits::total 147534119 # number of demand (read+write) hits 1630system.cpu1.dcache.overall_hits::cpu1.data 147717625 # number of overall hits 1631system.cpu1.dcache.overall_hits::total 147717625 # number of overall hits 1632system.cpu1.dcache.ReadReq_misses::cpu1.data 2895739 # number of ReadReq misses 1633system.cpu1.dcache.ReadReq_misses::total 2895739 # number of ReadReq misses 1634system.cpu1.dcache.WriteReq_misses::cpu1.data 1291835 # number of WriteReq misses 1635system.cpu1.dcache.WriteReq_misses::total 1291835 # number of WriteReq misses 1636system.cpu1.dcache.SoftPFReq_misses::cpu1.data 599128 # number of SoftPFReq misses 1637system.cpu1.dcache.SoftPFReq_misses::total 599128 # number of SoftPFReq misses 1638system.cpu1.dcache.WriteLineReq_misses::cpu1.data 515597 # number of WriteLineReq misses 1639system.cpu1.dcache.WriteLineReq_misses::total 515597 # number of WriteLineReq misses 1640system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170116 # number of LoadLockedReq misses 1641system.cpu1.dcache.LoadLockedReq_misses::total 170116 # number of LoadLockedReq misses 1642system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195350 # number of StoreCondReq misses 1643system.cpu1.dcache.StoreCondReq_misses::total 195350 # number of StoreCondReq misses 1644system.cpu1.dcache.demand_misses::cpu1.data 4187574 # number of demand (read+write) misses 1645system.cpu1.dcache.demand_misses::total 4187574 # number of demand (read+write) misses 1646system.cpu1.dcache.overall_misses::cpu1.data 4786702 # number of overall misses 1647system.cpu1.dcache.overall_misses::total 4786702 # number of overall misses 1648system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44430252500 # number of ReadReq miss cycles 1649system.cpu1.dcache.ReadReq_miss_latency::total 44430252500 # number of ReadReq miss cycles 1650system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 29275459500 # number of WriteReq miss cycles 1651system.cpu1.dcache.WriteReq_miss_latency::total 29275459500 # number of WriteReq miss cycles 1652system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 21176769000 # number of WriteLineReq miss cycles 1653system.cpu1.dcache.WriteLineReq_miss_latency::total 21176769000 # number of WriteLineReq miss cycles 1654system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2717509500 # number of LoadLockedReq miss cycles 1655system.cpu1.dcache.LoadLockedReq_miss_latency::total 2717509500 # number of LoadLockedReq miss cycles 1656system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5539928000 # number of StoreCondReq miss cycles 1657system.cpu1.dcache.StoreCondReq_miss_latency::total 5539928000 # number of StoreCondReq miss cycles 1658system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5730000 # number of StoreCondFailReq miss cycles 1659system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5730000 # number of StoreCondFailReq miss cycles 1660system.cpu1.dcache.demand_miss_latency::cpu1.data 73705712000 # number of demand (read+write) miss cycles 1661system.cpu1.dcache.demand_miss_latency::total 73705712000 # number of demand (read+write) miss cycles 1662system.cpu1.dcache.overall_miss_latency::cpu1.data 73705712000 # number of overall miss cycles 1663system.cpu1.dcache.overall_miss_latency::total 73705712000 # number of overall miss cycles 1664system.cpu1.dcache.ReadReq_accesses::cpu1.data 79527794 # number of ReadReq accesses(hits+misses) 1665system.cpu1.dcache.ReadReq_accesses::total 79527794 # number of ReadReq accesses(hits+misses) 1666system.cpu1.dcache.WriteReq_accesses::cpu1.data 72193899 # number of WriteReq accesses(hits+misses) 1667system.cpu1.dcache.WriteReq_accesses::total 72193899 # number of WriteReq accesses(hits+misses) 1668system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 782634 # number of SoftPFReq accesses(hits+misses) 1669system.cpu1.dcache.SoftPFReq_accesses::total 782634 # number of SoftPFReq accesses(hits+misses) 1670system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 708062 # number of WriteLineReq accesses(hits+misses) 1671system.cpu1.dcache.WriteLineReq_accesses::total 708062 # number of WriteLineReq accesses(hits+misses) 1672system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843835 # number of LoadLockedReq accesses(hits+misses) 1673system.cpu1.dcache.LoadLockedReq_accesses::total 1843835 # number of LoadLockedReq accesses(hits+misses) 1674system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1842495 # number of StoreCondReq accesses(hits+misses) 1675system.cpu1.dcache.StoreCondReq_accesses::total 1842495 # number of StoreCondReq accesses(hits+misses) 1676system.cpu1.dcache.demand_accesses::cpu1.data 151721693 # number of demand (read+write) accesses 1677system.cpu1.dcache.demand_accesses::total 151721693 # number of demand (read+write) accesses 1678system.cpu1.dcache.overall_accesses::cpu1.data 152504327 # number of overall (read+write) accesses 1679system.cpu1.dcache.overall_accesses::total 152504327 # number of overall (read+write) accesses 1680system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036412 # miss rate for ReadReq accesses 1681system.cpu1.dcache.ReadReq_miss_rate::total 0.036412 # miss rate for ReadReq accesses 1682system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.017894 # miss rate for WriteReq accesses 1683system.cpu1.dcache.WriteReq_miss_rate::total 0.017894 # miss rate for WriteReq accesses 1684system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.765528 # miss rate for SoftPFReq accesses 1685system.cpu1.dcache.SoftPFReq_miss_rate::total 0.765528 # miss rate for SoftPFReq accesses 1686system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.728181 # miss rate for WriteLineReq accesses 1687system.cpu1.dcache.WriteLineReq_miss_rate::total 0.728181 # miss rate for WriteLineReq accesses 1688system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092262 # miss rate for LoadLockedReq accesses 1689system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092262 # miss rate for LoadLockedReq accesses 1690system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106025 # miss rate for StoreCondReq accesses 1691system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106025 # miss rate for StoreCondReq accesses 1692system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027600 # miss rate for demand accesses 1693system.cpu1.dcache.demand_miss_rate::total 0.027600 # miss rate for demand accesses 1694system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031387 # miss rate for overall accesses 1695system.cpu1.dcache.overall_miss_rate::total 0.031387 # miss rate for overall accesses 1696system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15343.320824 # average ReadReq miss latency 1697system.cpu1.dcache.ReadReq_avg_miss_latency::total 15343.320824 # average ReadReq miss latency 1698system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22661.918511 # average WriteReq miss latency 1699system.cpu1.dcache.WriteReq_avg_miss_latency::total 22661.918511 # average WriteReq miss latency 1700system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41072.327806 # average WriteLineReq miss latency 1701system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41072.327806 # average WriteLineReq miss latency 1702system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.449787 # average LoadLockedReq miss latency 1703system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.449787 # average LoadLockedReq miss latency 1704system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28358.986435 # average StoreCondReq miss latency 1705system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28358.986435 # average StoreCondReq miss latency 1706system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1707system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1708system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17601.053020 # average overall miss latency 1709system.cpu1.dcache.demand_avg_miss_latency::total 17601.053020 # average overall miss latency 1710system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15398.015586 # average overall miss latency 1711system.cpu1.dcache.overall_avg_miss_latency::total 15398.015586 # average overall miss latency 1712system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1713system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1714system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1715system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1716system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1717system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1718system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1719system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1720system.cpu1.dcache.writebacks::writebacks 5113111 # number of writebacks 1721system.cpu1.dcache.writebacks::total 5113111 # number of writebacks 1722system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16657 # number of ReadReq MSHR hits 1723system.cpu1.dcache.ReadReq_mshr_hits::total 16657 # number of ReadReq MSHR hits 1724system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 402 # number of WriteReq MSHR hits 1725system.cpu1.dcache.WriteReq_mshr_hits::total 402 # number of WriteReq MSHR hits 1726system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46028 # number of LoadLockedReq MSHR hits 1727system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46028 # number of LoadLockedReq MSHR hits 1728system.cpu1.dcache.demand_mshr_hits::cpu1.data 17059 # number of demand (read+write) MSHR hits 1729system.cpu1.dcache.demand_mshr_hits::total 17059 # number of demand (read+write) MSHR hits 1730system.cpu1.dcache.overall_mshr_hits::cpu1.data 17059 # number of overall MSHR hits 1731system.cpu1.dcache.overall_mshr_hits::total 17059 # number of overall MSHR hits 1732system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2879082 # number of ReadReq MSHR misses 1733system.cpu1.dcache.ReadReq_mshr_misses::total 2879082 # number of ReadReq MSHR misses 1734system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1291433 # number of WriteReq MSHR misses 1735system.cpu1.dcache.WriteReq_mshr_misses::total 1291433 # number of WriteReq MSHR misses 1736system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 599128 # number of SoftPFReq MSHR misses 1737system.cpu1.dcache.SoftPFReq_mshr_misses::total 599128 # number of SoftPFReq MSHR misses 1738system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 515597 # number of WriteLineReq MSHR misses 1739system.cpu1.dcache.WriteLineReq_mshr_misses::total 515597 # number of WriteLineReq MSHR misses 1740system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 124088 # number of LoadLockedReq MSHR misses 1741system.cpu1.dcache.LoadLockedReq_mshr_misses::total 124088 # number of LoadLockedReq MSHR misses 1742system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195350 # number of StoreCondReq MSHR misses 1743system.cpu1.dcache.StoreCondReq_mshr_misses::total 195350 # number of StoreCondReq MSHR misses 1744system.cpu1.dcache.demand_mshr_misses::cpu1.data 4170515 # number of demand (read+write) MSHR misses 1745system.cpu1.dcache.demand_mshr_misses::total 4170515 # number of demand (read+write) MSHR misses 1746system.cpu1.dcache.overall_mshr_misses::cpu1.data 4769643 # number of overall MSHR misses 1747system.cpu1.dcache.overall_mshr_misses::total 4769643 # number of overall MSHR misses 1748system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21793 # number of ReadReq MSHR uncacheable 1749system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21793 # number of ReadReq MSHR uncacheable 1750system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable 1751system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20416 # number of WriteReq MSHR uncacheable 1752system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42209 # number of overall MSHR uncacheable misses 1753system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42209 # number of overall MSHR uncacheable misses 1754system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40268780500 # number of ReadReq MSHR miss cycles 1755system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40268780500 # number of ReadReq MSHR miss cycles 1756system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27960090500 # number of WriteReq MSHR miss cycles 1757system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27960090500 # number of WriteReq MSHR miss cycles 1758system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13604579000 # number of SoftPFReq MSHR miss cycles 1759system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13604579000 # number of SoftPFReq MSHR miss cycles 1760system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20661172000 # number of WriteLineReq MSHR miss cycles 1761system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20661172000 # number of WriteLineReq MSHR miss cycles 1762system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1751690500 # number of LoadLockedReq MSHR miss cycles 1763system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1751690500 # number of LoadLockedReq MSHR miss cycles 1764system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5344637000 # number of StoreCondReq MSHR miss cycles 1765system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5344637000 # number of StoreCondReq MSHR miss cycles 1766system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5671000 # number of StoreCondFailReq MSHR miss cycles 1767system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5671000 # number of StoreCondFailReq MSHR miss cycles 1768system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 68228871000 # number of demand (read+write) MSHR miss cycles 1769system.cpu1.dcache.demand_mshr_miss_latency::total 68228871000 # number of demand (read+write) MSHR miss cycles 1770system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81833450000 # number of overall MSHR miss cycles 1771system.cpu1.dcache.overall_mshr_miss_latency::total 81833450000 # number of overall MSHR miss cycles 1772system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4030825000 # number of ReadReq MSHR uncacheable cycles 1773system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4030825000 # number of ReadReq MSHR uncacheable cycles 1774system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3797015500 # number of WriteReq MSHR uncacheable cycles 1775system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3797015500 # number of WriteReq MSHR uncacheable cycles 1776system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7827840500 # number of overall MSHR uncacheable cycles 1777system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7827840500 # number of overall MSHR uncacheable cycles 1778system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036202 # mshr miss rate for ReadReq accesses 1779system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036202 # mshr miss rate for ReadReq accesses 1780system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for WriteReq accesses 1781system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017888 # mshr miss rate for WriteReq accesses 1782system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765528 # mshr miss rate for SoftPFReq accesses 1783system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.765528 # mshr miss rate for SoftPFReq accesses 1784system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.728181 # mshr miss rate for WriteLineReq accesses 1785system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.728181 # mshr miss rate for WriteLineReq accesses 1786system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067299 # mshr miss rate for LoadLockedReq accesses 1787system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067299 # mshr miss rate for LoadLockedReq accesses 1788system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106025 # mshr miss rate for StoreCondReq accesses 1789system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106025 # mshr miss rate for StoreCondReq accesses 1790system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027488 # mshr miss rate for demand accesses 1791system.cpu1.dcache.demand_mshr_miss_rate::total 0.027488 # mshr miss rate for demand accesses 1792system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031275 # mshr miss rate for overall accesses 1793system.cpu1.dcache.overall_mshr_miss_rate::total 0.031275 # mshr miss rate for overall accesses 1794system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.673704 # average ReadReq mshr miss latency 1795system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.673704 # average ReadReq mshr miss latency 1796system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21650.438312 # average WriteReq mshr miss latency 1797system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21650.438312 # average WriteReq mshr miss latency 1798system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22707.299609 # average SoftPFReq mshr miss latency 1799system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22707.299609 # average SoftPFReq mshr miss latency 1800system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40072.327806 # average WriteLineReq mshr miss latency 1801system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40072.327806 # average WriteLineReq mshr miss latency 1802system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14116.518116 # average LoadLockedReq mshr miss latency 1803system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14116.518116 # average LoadLockedReq mshr miss latency 1804system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27359.288457 # average StoreCondReq mshr miss latency 1805system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27359.288457 # average StoreCondReq mshr miss latency 1806system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1807system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1808system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16359.819111 # average overall mshr miss latency 1809system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16359.819111 # average overall mshr miss latency 1810system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17157.143627 # average overall mshr miss latency 1811system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17157.143627 # average overall mshr miss latency 1812system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184959.620061 # average ReadReq mshr uncacheable latency 1813system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184959.620061 # average ReadReq mshr uncacheable latency 1814system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 185982.342281 # average WriteReq mshr uncacheable latency 1815system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 185982.342281 # average WriteReq mshr uncacheable latency 1816system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 185454.298846 # average overall mshr uncacheable latency 1817system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 185454.298846 # average overall mshr uncacheable latency 1818system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1819system.cpu1.icache.tags.replacements 5153049 # number of replacements 1820system.cpu1.icache.tags.tagsinuse 495.966911 # Cycle average of tags in use 1821system.cpu1.icache.tags.total_refs 430252201 # Total number of references to valid blocks. 1822system.cpu1.icache.tags.sampled_refs 5153561 # Sample count of references to valid blocks. 1823system.cpu1.icache.tags.avg_refs 83.486390 # Average number of references to valid blocks. 1824system.cpu1.icache.tags.warmup_cycle 8408381586000 # Cycle when the warmup percentage was hit. 1825system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.966911 # Average occupied blocks per requestor 1826system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968685 # Average percentage of cache occupancy 1827system.cpu1.icache.tags.occ_percent::total 0.968685 # Average percentage of cache occupancy 1828system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1829system.cpu1.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1830system.cpu1.icache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id 1831system.cpu1.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id 1832system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1833system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1834system.cpu1.icache.tags.tag_accesses 875965100 # Number of tag accesses 1835system.cpu1.icache.tags.data_accesses 875965100 # Number of data accesses 1836system.cpu1.icache.ReadReq_hits::cpu1.inst 430252201 # number of ReadReq hits 1837system.cpu1.icache.ReadReq_hits::total 430252201 # number of ReadReq hits 1838system.cpu1.icache.demand_hits::cpu1.inst 430252201 # number of demand (read+write) hits 1839system.cpu1.icache.demand_hits::total 430252201 # number of demand (read+write) hits 1840system.cpu1.icache.overall_hits::cpu1.inst 430252201 # number of overall hits 1841system.cpu1.icache.overall_hits::total 430252201 # number of overall hits 1842system.cpu1.icache.ReadReq_misses::cpu1.inst 5153566 # number of ReadReq misses 1843system.cpu1.icache.ReadReq_misses::total 5153566 # number of ReadReq misses 1844system.cpu1.icache.demand_misses::cpu1.inst 5153566 # number of demand (read+write) misses 1845system.cpu1.icache.demand_misses::total 5153566 # number of demand (read+write) misses 1846system.cpu1.icache.overall_misses::cpu1.inst 5153566 # number of overall misses 1847system.cpu1.icache.overall_misses::total 5153566 # number of overall misses 1848system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 55699016000 # number of ReadReq miss cycles 1849system.cpu1.icache.ReadReq_miss_latency::total 55699016000 # number of ReadReq miss cycles 1850system.cpu1.icache.demand_miss_latency::cpu1.inst 55699016000 # number of demand (read+write) miss cycles 1851system.cpu1.icache.demand_miss_latency::total 55699016000 # number of demand (read+write) miss cycles 1852system.cpu1.icache.overall_miss_latency::cpu1.inst 55699016000 # number of overall miss cycles 1853system.cpu1.icache.overall_miss_latency::total 55699016000 # number of overall miss cycles 1854system.cpu1.icache.ReadReq_accesses::cpu1.inst 435405767 # number of ReadReq accesses(hits+misses) 1855system.cpu1.icache.ReadReq_accesses::total 435405767 # number of ReadReq accesses(hits+misses) 1856system.cpu1.icache.demand_accesses::cpu1.inst 435405767 # number of demand (read+write) accesses 1857system.cpu1.icache.demand_accesses::total 435405767 # number of demand (read+write) accesses 1858system.cpu1.icache.overall_accesses::cpu1.inst 435405767 # number of overall (read+write) accesses 1859system.cpu1.icache.overall_accesses::total 435405767 # number of overall (read+write) accesses 1860system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011836 # miss rate for ReadReq accesses 1861system.cpu1.icache.ReadReq_miss_rate::total 0.011836 # miss rate for ReadReq accesses 1862system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011836 # miss rate for demand accesses 1863system.cpu1.icache.demand_miss_rate::total 0.011836 # miss rate for demand accesses 1864system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011836 # miss rate for overall accesses 1865system.cpu1.icache.overall_miss_rate::total 0.011836 # miss rate for overall accesses 1866system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10807.859257 # average ReadReq miss latency 1867system.cpu1.icache.ReadReq_avg_miss_latency::total 10807.859257 # average ReadReq miss latency 1868system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10807.859257 # average overall miss latency 1869system.cpu1.icache.demand_avg_miss_latency::total 10807.859257 # average overall miss latency 1870system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10807.859257 # average overall miss latency 1871system.cpu1.icache.overall_avg_miss_latency::total 10807.859257 # average overall miss latency 1872system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1873system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1874system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1875system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1876system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1877system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1878system.cpu1.icache.fast_writes 0 # number of fast writes performed 1879system.cpu1.icache.cache_copies 0 # number of cache copies performed 1880system.cpu1.icache.writebacks::writebacks 5153049 # number of writebacks 1881system.cpu1.icache.writebacks::total 5153049 # number of writebacks 1882system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5153566 # number of ReadReq MSHR misses 1883system.cpu1.icache.ReadReq_mshr_misses::total 5153566 # number of ReadReq MSHR misses 1884system.cpu1.icache.demand_mshr_misses::cpu1.inst 5153566 # number of demand (read+write) MSHR misses 1885system.cpu1.icache.demand_mshr_misses::total 5153566 # number of demand (read+write) MSHR misses 1886system.cpu1.icache.overall_mshr_misses::cpu1.inst 5153566 # number of overall MSHR misses 1887system.cpu1.icache.overall_mshr_misses::total 5153566 # number of overall MSHR misses 1888system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1889system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1890system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1891system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1892system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 53122233000 # number of ReadReq MSHR miss cycles 1893system.cpu1.icache.ReadReq_mshr_miss_latency::total 53122233000 # number of ReadReq MSHR miss cycles 1894system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 53122233000 # number of demand (read+write) MSHR miss cycles 1895system.cpu1.icache.demand_mshr_miss_latency::total 53122233000 # number of demand (read+write) MSHR miss cycles 1896system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 53122233000 # number of overall MSHR miss cycles 1897system.cpu1.icache.overall_mshr_miss_latency::total 53122233000 # number of overall MSHR miss cycles 1898system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14799500 # number of ReadReq MSHR uncacheable cycles 1899system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14799500 # number of ReadReq MSHR uncacheable cycles 1900system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14799500 # number of overall MSHR uncacheable cycles 1901system.cpu1.icache.overall_mshr_uncacheable_latency::total 14799500 # number of overall MSHR uncacheable cycles 1902system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for ReadReq accesses 1903system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011836 # mshr miss rate for ReadReq accesses 1904system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for demand accesses 1905system.cpu1.icache.demand_mshr_miss_rate::total 0.011836 # mshr miss rate for demand accesses 1906system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011836 # mshr miss rate for overall accesses 1907system.cpu1.icache.overall_mshr_miss_rate::total 0.011836 # mshr miss rate for overall accesses 1908system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average ReadReq mshr miss latency 1909system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10307.859257 # average ReadReq mshr miss latency 1910system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency 1911system.cpu1.icache.demand_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency 1912system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10307.859257 # average overall mshr miss latency 1913system.cpu1.icache.overall_avg_mshr_miss_latency::total 10307.859257 # average overall mshr miss latency 1914system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average ReadReq mshr uncacheable latency 1915system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091 # average ReadReq mshr uncacheable latency 1916system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average overall mshr uncacheable latency 1917system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091 # average overall mshr uncacheable latency 1918system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1919system.cpu1.l2cache.prefetcher.num_hwpf_issued 6859303 # number of hwpf issued 1920system.cpu1.l2cache.prefetcher.pfIdentified 6859383 # number of prefetch candidates identified 1921system.cpu1.l2cache.prefetcher.pfBufferHit 70 # number of redundant prefetches already in prefetch queue 1922system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1923system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1924system.cpu1.l2cache.prefetcher.pfSpanPage 859985 # number of prefetches not generated due to page crossing 1925system.cpu1.l2cache.tags.replacements 1911702 # number of replacements 1926system.cpu1.l2cache.tags.tagsinuse 13239.490812 # Cycle average of tags in use 1927system.cpu1.l2cache.tags.total_refs 15125743 # Total number of references to valid blocks. 1928system.cpu1.l2cache.tags.sampled_refs 1927829 # Sample count of references to valid blocks. 1929system.cpu1.l2cache.tags.avg_refs 7.845998 # Average number of references to valid blocks. 1930system.cpu1.l2cache.tags.warmup_cycle 10087167671000 # Cycle when the warmup percentage was hit. 1931system.cpu1.l2cache.tags.occ_blocks::writebacks 12280.954827 # Average occupied blocks per requestor 1932system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.921711 # Average occupied blocks per requestor 1933system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.687685 # Average occupied blocks per requestor 1934system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 831.926589 # Average occupied blocks per requestor 1935system.cpu1.l2cache.tags.occ_percent::writebacks 0.749570 # Average percentage of cache occupancy 1936system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003230 # Average percentage of cache occupancy 1937system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004498 # Average percentage of cache occupancy 1938system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050777 # Average percentage of cache occupancy 1939system.cpu1.l2cache.tags.occ_percent::total 0.808074 # Average percentage of cache occupancy 1940system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1375 # Occupied blocks per task id 1941system.cpu1.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id 1942system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14698 # Occupied blocks per task id 1943system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id 1944system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id 1945system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 718 # Occupied blocks per task id 1946system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 459 # Occupied blocks per task id 1947system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id 1948system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 1949system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1950system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 1951system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1004 # Occupied blocks per task id 1952system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4268 # Occupied blocks per task id 1953system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6358 # Occupied blocks per task id 1954system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2989 # Occupied blocks per task id 1955system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.083923 # Percentage of cache occupancy per task id 1956system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id 1957system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897095 # Percentage of cache occupancy per task id 1958system.cpu1.l2cache.tags.tag_accesses 347994589 # Number of tag accesses 1959system.cpu1.l2cache.tags.data_accesses 347994589 # Number of data accesses 1960system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 237538 # number of ReadReq hits 1961system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 166264 # number of ReadReq hits 1962system.cpu1.l2cache.ReadReq_hits::total 403802 # number of ReadReq hits 1963system.cpu1.l2cache.WritebackDirty_hits::writebacks 3233759 # number of WritebackDirty hits 1964system.cpu1.l2cache.WritebackDirty_hits::total 3233759 # number of WritebackDirty hits 1965system.cpu1.l2cache.WritebackClean_hits::writebacks 7031230 # number of WritebackClean hits 1966system.cpu1.l2cache.WritebackClean_hits::total 7031230 # number of WritebackClean hits 1967system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 362 # number of UpgradeReq hits 1968system.cpu1.l2cache.UpgradeReq_hits::total 362 # number of UpgradeReq hits 1969system.cpu1.l2cache.ReadExReq_hits::cpu1.data 841313 # number of ReadExReq hits 1970system.cpu1.l2cache.ReadExReq_hits::total 841313 # number of ReadExReq hits 1971system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4702873 # number of ReadCleanReq hits 1972system.cpu1.l2cache.ReadCleanReq_hits::total 4702873 # number of ReadCleanReq hits 1973system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2730195 # number of ReadSharedReq hits 1974system.cpu1.l2cache.ReadSharedReq_hits::total 2730195 # number of ReadSharedReq hits 1975system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 242884 # number of InvalidateReq hits 1976system.cpu1.l2cache.InvalidateReq_hits::total 242884 # number of InvalidateReq hits 1977system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 237538 # number of demand (read+write) hits 1978system.cpu1.l2cache.demand_hits::cpu1.itb.walker 166264 # number of demand (read+write) hits 1979system.cpu1.l2cache.demand_hits::cpu1.inst 4702873 # number of demand (read+write) hits 1980system.cpu1.l2cache.demand_hits::cpu1.data 3571508 # number of demand (read+write) hits 1981system.cpu1.l2cache.demand_hits::total 8678183 # number of demand (read+write) hits 1982system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 237538 # number of overall hits 1983system.cpu1.l2cache.overall_hits::cpu1.itb.walker 166264 # number of overall hits 1984system.cpu1.l2cache.overall_hits::cpu1.inst 4702873 # number of overall hits 1985system.cpu1.l2cache.overall_hits::cpu1.data 3571508 # number of overall hits 1986system.cpu1.l2cache.overall_hits::total 8678183 # number of overall hits 1987system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9658 # number of ReadReq misses 1988system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8172 # number of ReadReq misses 1989system.cpu1.l2cache.ReadReq_misses::total 17830 # number of ReadReq misses 1990system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 204136 # number of UpgradeReq misses 1991system.cpu1.l2cache.UpgradeReq_misses::total 204136 # number of UpgradeReq misses 1992system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195335 # number of SCUpgradeReq misses 1993system.cpu1.l2cache.SCUpgradeReq_misses::total 195335 # number of SCUpgradeReq misses 1994system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 15 # number of SCUpgradeFailReq misses 1995system.cpu1.l2cache.SCUpgradeFailReq_misses::total 15 # number of SCUpgradeFailReq misses 1996system.cpu1.l2cache.ReadExReq_misses::cpu1.data 248244 # number of ReadExReq misses 1997system.cpu1.l2cache.ReadExReq_misses::total 248244 # number of ReadExReq misses 1998system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 450693 # number of ReadCleanReq misses 1999system.cpu1.l2cache.ReadCleanReq_misses::total 450693 # number of ReadCleanReq misses 2000system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 872103 # number of ReadSharedReq misses 2001system.cpu1.l2cache.ReadSharedReq_misses::total 872103 # number of ReadSharedReq misses 2002system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 270299 # number of InvalidateReq misses 2003system.cpu1.l2cache.InvalidateReq_misses::total 270299 # number of InvalidateReq misses 2004system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9658 # number of demand (read+write) misses 2005system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8172 # number of demand (read+write) misses 2006system.cpu1.l2cache.demand_misses::cpu1.inst 450693 # number of demand (read+write) misses 2007system.cpu1.l2cache.demand_misses::cpu1.data 1120347 # number of demand (read+write) misses 2008system.cpu1.l2cache.demand_misses::total 1588870 # number of demand (read+write) misses 2009system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9658 # number of overall misses 2010system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8172 # number of overall misses 2011system.cpu1.l2cache.overall_misses::cpu1.inst 450693 # number of overall misses 2012system.cpu1.l2cache.overall_misses::cpu1.data 1120347 # number of overall misses 2013system.cpu1.l2cache.overall_misses::total 1588870 # number of overall misses 2014system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 420391500 # number of ReadReq miss cycles 2015system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 400950500 # number of ReadReq miss cycles 2016system.cpu1.l2cache.ReadReq_miss_latency::total 821342000 # number of ReadReq miss cycles 2017system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3230006000 # number of UpgradeReq miss cycles 2018system.cpu1.l2cache.UpgradeReq_miss_latency::total 3230006000 # number of UpgradeReq miss cycles 2019system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1996070000 # number of SCUpgradeReq miss cycles 2020system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1996070000 # number of SCUpgradeReq miss cycles 2021system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5582500 # number of SCUpgradeFailReq miss cycles 2022system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5582500 # number of SCUpgradeFailReq miss cycles 2023system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12845706999 # number of ReadExReq miss cycles 2024system.cpu1.l2cache.ReadExReq_miss_latency::total 12845706999 # number of ReadExReq miss cycles 2025system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17128169000 # number of ReadCleanReq miss cycles 2026system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17128169000 # number of ReadCleanReq miss cycles 2027system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32431804500 # number of ReadSharedReq miss cycles 2028system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32431804500 # number of ReadSharedReq miss cycles 2029system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18248876500 # number of InvalidateReq miss cycles 2030system.cpu1.l2cache.InvalidateReq_miss_latency::total 18248876500 # number of InvalidateReq miss cycles 2031system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 420391500 # number of demand (read+write) miss cycles 2032system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 400950500 # number of demand (read+write) miss cycles 2033system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17128169000 # number of demand (read+write) miss cycles 2034system.cpu1.l2cache.demand_miss_latency::cpu1.data 45277511499 # number of demand (read+write) miss cycles 2035system.cpu1.l2cache.demand_miss_latency::total 63227022499 # number of demand (read+write) miss cycles 2036system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 420391500 # number of overall miss cycles 2037system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 400950500 # number of overall miss cycles 2038system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17128169000 # number of overall miss cycles 2039system.cpu1.l2cache.overall_miss_latency::cpu1.data 45277511499 # number of overall miss cycles 2040system.cpu1.l2cache.overall_miss_latency::total 63227022499 # number of overall miss cycles 2041system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 247196 # number of ReadReq accesses(hits+misses) 2042system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 174436 # number of ReadReq accesses(hits+misses) 2043system.cpu1.l2cache.ReadReq_accesses::total 421632 # number of ReadReq accesses(hits+misses) 2044system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3233759 # number of WritebackDirty accesses(hits+misses) 2045system.cpu1.l2cache.WritebackDirty_accesses::total 3233759 # number of WritebackDirty accesses(hits+misses) 2046system.cpu1.l2cache.WritebackClean_accesses::writebacks 7031230 # number of WritebackClean accesses(hits+misses) 2047system.cpu1.l2cache.WritebackClean_accesses::total 7031230 # number of WritebackClean accesses(hits+misses) 2048system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 204498 # number of UpgradeReq accesses(hits+misses) 2049system.cpu1.l2cache.UpgradeReq_accesses::total 204498 # number of UpgradeReq accesses(hits+misses) 2050system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195335 # number of SCUpgradeReq accesses(hits+misses) 2051system.cpu1.l2cache.SCUpgradeReq_accesses::total 195335 # number of SCUpgradeReq accesses(hits+misses) 2052system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 15 # number of SCUpgradeFailReq accesses(hits+misses) 2053system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 15 # number of SCUpgradeFailReq accesses(hits+misses) 2054system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1089557 # number of ReadExReq accesses(hits+misses) 2055system.cpu1.l2cache.ReadExReq_accesses::total 1089557 # number of ReadExReq accesses(hits+misses) 2056system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5153566 # number of ReadCleanReq accesses(hits+misses) 2057system.cpu1.l2cache.ReadCleanReq_accesses::total 5153566 # number of ReadCleanReq accesses(hits+misses) 2058system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3602298 # number of ReadSharedReq accesses(hits+misses) 2059system.cpu1.l2cache.ReadSharedReq_accesses::total 3602298 # number of ReadSharedReq accesses(hits+misses) 2060system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 513183 # number of InvalidateReq accesses(hits+misses) 2061system.cpu1.l2cache.InvalidateReq_accesses::total 513183 # number of InvalidateReq accesses(hits+misses) 2062system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 247196 # number of demand (read+write) accesses 2063system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 174436 # number of demand (read+write) accesses 2064system.cpu1.l2cache.demand_accesses::cpu1.inst 5153566 # number of demand (read+write) accesses 2065system.cpu1.l2cache.demand_accesses::cpu1.data 4691855 # number of demand (read+write) accesses 2066system.cpu1.l2cache.demand_accesses::total 10267053 # number of demand (read+write) accesses 2067system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 247196 # number of overall (read+write) accesses 2068system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 174436 # number of overall (read+write) accesses 2069system.cpu1.l2cache.overall_accesses::cpu1.inst 5153566 # number of overall (read+write) accesses 2070system.cpu1.l2cache.overall_accesses::cpu1.data 4691855 # number of overall (read+write) accesses 2071system.cpu1.l2cache.overall_accesses::total 10267053 # number of overall (read+write) accesses 2072system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.039070 # miss rate for ReadReq accesses 2073system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046848 # miss rate for ReadReq accesses 2074system.cpu1.l2cache.ReadReq_miss_rate::total 0.042288 # miss rate for ReadReq accesses 2075system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998230 # miss rate for UpgradeReq accesses 2076system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998230 # miss rate for UpgradeReq accesses 2077system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2078system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2079system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2080system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2081system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.227839 # miss rate for ReadExReq accesses 2082system.cpu1.l2cache.ReadExReq_miss_rate::total 0.227839 # miss rate for ReadExReq accesses 2083system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.087453 # miss rate for ReadCleanReq accesses 2084system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.087453 # miss rate for ReadCleanReq accesses 2085system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.242096 # miss rate for ReadSharedReq accesses 2086system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.242096 # miss rate for ReadSharedReq accesses 2087system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.526711 # miss rate for InvalidateReq accesses 2088system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.526711 # miss rate for InvalidateReq accesses 2089system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.039070 # miss rate for demand accesses 2090system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046848 # miss rate for demand accesses 2091system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.087453 # miss rate for demand accesses 2092system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.238786 # miss rate for demand accesses 2093system.cpu1.l2cache.demand_miss_rate::total 0.154754 # miss rate for demand accesses 2094system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.039070 # miss rate for overall accesses 2095system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046848 # miss rate for overall accesses 2096system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.087453 # miss rate for overall accesses 2097system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.238786 # miss rate for overall accesses 2098system.cpu1.l2cache.overall_miss_rate::total 0.154754 # miss rate for overall accesses 2099system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 43527.800787 # average ReadReq miss latency 2100system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 49063.937837 # average ReadReq miss latency 2101system.cpu1.l2cache.ReadReq_avg_miss_latency::total 46065.171060 # average ReadReq miss latency 2102system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15822.814202 # average UpgradeReq miss latency 2103system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15822.814202 # average UpgradeReq miss latency 2104system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10218.701206 # average SCUpgradeReq miss latency 2105system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10218.701206 # average SCUpgradeReq miss latency 2106system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 372166.666667 # average SCUpgradeFailReq miss latency 2107system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 372166.666667 # average SCUpgradeFailReq miss latency 2108system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51746.293965 # average ReadExReq miss latency 2109system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51746.293965 # average ReadExReq miss latency 2110system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38004.071508 # average ReadCleanReq miss latency 2111system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38004.071508 # average ReadCleanReq miss latency 2112system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37188.043729 # average ReadSharedReq miss latency 2113system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37188.043729 # average ReadSharedReq miss latency 2114system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 67513.666347 # average InvalidateReq miss latency 2115system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 67513.666347 # average InvalidateReq miss latency 2116system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 43527.800787 # average overall miss latency 2117system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 49063.937837 # average overall miss latency 2118system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38004.071508 # average overall miss latency 2119system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40413.828483 # average overall miss latency 2120system.cpu1.l2cache.demand_avg_miss_latency::total 39793.704015 # average overall miss latency 2121system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 43527.800787 # average overall miss latency 2122system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 49063.937837 # average overall miss latency 2123system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38004.071508 # average overall miss latency 2124system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40413.828483 # average overall miss latency 2125system.cpu1.l2cache.overall_avg_miss_latency::total 39793.704015 # average overall miss latency 2126system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2127system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2128system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2129system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2130system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2131system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2132system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2133system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2134system.cpu1.l2cache.writebacks::writebacks 1066343 # number of writebacks 2135system.cpu1.l2cache.writebacks::total 1066343 # number of writebacks 2136system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3931 # number of ReadExReq MSHR hits 2137system.cpu1.l2cache.ReadExReq_mshr_hits::total 3931 # number of ReadExReq MSHR hits 2138system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 513 # number of ReadSharedReq MSHR hits 2139system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 513 # number of ReadSharedReq MSHR hits 2140system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4444 # number of demand (read+write) MSHR hits 2141system.cpu1.l2cache.demand_mshr_hits::total 4444 # number of demand (read+write) MSHR hits 2142system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4444 # number of overall MSHR hits 2143system.cpu1.l2cache.overall_mshr_hits::total 4444 # number of overall MSHR hits 2144system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9658 # number of ReadReq MSHR misses 2145system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8172 # number of ReadReq MSHR misses 2146system.cpu1.l2cache.ReadReq_mshr_misses::total 17830 # number of ReadReq MSHR misses 2147system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 644489 # number of HardPFReq MSHR misses 2148system.cpu1.l2cache.HardPFReq_mshr_misses::total 644489 # number of HardPFReq MSHR misses 2149system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 204136 # number of UpgradeReq MSHR misses 2150system.cpu1.l2cache.UpgradeReq_mshr_misses::total 204136 # number of UpgradeReq MSHR misses 2151system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195335 # number of SCUpgradeReq MSHR misses 2152system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195335 # number of SCUpgradeReq MSHR misses 2153system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 15 # number of SCUpgradeFailReq MSHR misses 2154system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 15 # number of SCUpgradeFailReq MSHR misses 2155system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 244313 # number of ReadExReq MSHR misses 2156system.cpu1.l2cache.ReadExReq_mshr_misses::total 244313 # number of ReadExReq MSHR misses 2157system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 450693 # number of ReadCleanReq MSHR misses 2158system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 450693 # number of ReadCleanReq MSHR misses 2159system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 871590 # number of ReadSharedReq MSHR misses 2160system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 871590 # number of ReadSharedReq MSHR misses 2161system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 270299 # number of InvalidateReq MSHR misses 2162system.cpu1.l2cache.InvalidateReq_mshr_misses::total 270299 # number of InvalidateReq MSHR misses 2163system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9658 # number of demand (read+write) MSHR misses 2164system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8172 # number of demand (read+write) MSHR misses 2165system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 450693 # number of demand (read+write) MSHR misses 2166system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1115903 # number of demand (read+write) MSHR misses 2167system.cpu1.l2cache.demand_mshr_misses::total 1584426 # number of demand (read+write) MSHR misses 2168system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9658 # number of overall MSHR misses 2169system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8172 # number of overall MSHR misses 2170system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 450693 # number of overall MSHR misses 2171system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1115903 # number of overall MSHR misses 2172system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 644489 # number of overall MSHR misses 2173system.cpu1.l2cache.overall_mshr_misses::total 2228915 # number of overall MSHR misses 2174system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2175system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21793 # number of ReadReq MSHR uncacheable 2176system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21903 # number of ReadReq MSHR uncacheable 2177system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable 2178system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20416 # number of WriteReq MSHR uncacheable 2179system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2180system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 42209 # number of overall MSHR uncacheable misses 2181system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 42319 # number of overall MSHR uncacheable misses 2182system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 362443500 # number of ReadReq MSHR miss cycles 2183system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 351918500 # number of ReadReq MSHR miss cycles 2184system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 714362000 # number of ReadReq MSHR miss cycles 2185system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28219162309 # number of HardPFReq MSHR miss cycles 2186system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 28219162309 # number of HardPFReq MSHR miss cycles 2187system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6506833500 # number of UpgradeReq MSHR miss cycles 2188system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6506833500 # number of UpgradeReq MSHR miss cycles 2189system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3878333500 # number of SCUpgradeReq MSHR miss cycles 2190system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3878333500 # number of SCUpgradeReq MSHR miss cycles 2191system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5228500 # number of SCUpgradeFailReq MSHR miss cycles 2192system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5228500 # number of SCUpgradeFailReq MSHR miss cycles 2193system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10923389999 # number of ReadExReq MSHR miss cycles 2194system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10923389999 # number of ReadExReq MSHR miss cycles 2195system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14424011000 # number of ReadCleanReq MSHR miss cycles 2196system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14424011000 # number of ReadCleanReq MSHR miss cycles 2197system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27157045000 # number of ReadSharedReq MSHR miss cycles 2198system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27157045000 # number of ReadSharedReq MSHR miss cycles 2199system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16627082500 # number of InvalidateReq MSHR miss cycles 2200system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16627082500 # number of InvalidateReq MSHR miss cycles 2201system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 362443500 # number of demand (read+write) MSHR miss cycles 2202system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 351918500 # number of demand (read+write) MSHR miss cycles 2203system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14424011000 # number of demand (read+write) MSHR miss cycles 2204system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38080434999 # number of demand (read+write) MSHR miss cycles 2205system.cpu1.l2cache.demand_mshr_miss_latency::total 53218807999 # number of demand (read+write) MSHR miss cycles 2206system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 362443500 # number of overall MSHR miss cycles 2207system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 351918500 # number of overall MSHR miss cycles 2208system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14424011000 # number of overall MSHR miss cycles 2209system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38080434999 # number of overall MSHR miss cycles 2210system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28219162309 # number of overall MSHR miss cycles 2211system.cpu1.l2cache.overall_mshr_miss_latency::total 81437970308 # number of overall MSHR miss cycles 2212system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13974500 # number of ReadReq MSHR uncacheable cycles 2213system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3856157500 # number of ReadReq MSHR uncacheable cycles 2214system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3870132000 # number of ReadReq MSHR uncacheable cycles 2215system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3643453500 # number of WriteReq MSHR uncacheable cycles 2216system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3643453500 # number of WriteReq MSHR uncacheable cycles 2217system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13974500 # number of overall MSHR uncacheable cycles 2218system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7499611000 # number of overall MSHR uncacheable cycles 2219system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7513585500 # number of overall MSHR uncacheable cycles 2220system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for ReadReq accesses 2221system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for ReadReq accesses 2222system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.042288 # mshr miss rate for ReadReq accesses 2223system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2224system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2225system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998230 # mshr miss rate for UpgradeReq accesses 2226system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998230 # mshr miss rate for UpgradeReq accesses 2227system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2228system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2229system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2230system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2231system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.224231 # mshr miss rate for ReadExReq accesses 2232system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.224231 # mshr miss rate for ReadExReq accesses 2233system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for ReadCleanReq accesses 2234system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087453 # mshr miss rate for ReadCleanReq accesses 2235system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.241954 # mshr miss rate for ReadSharedReq accesses 2236system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241954 # mshr miss rate for ReadSharedReq accesses 2237system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.526711 # mshr miss rate for InvalidateReq accesses 2238system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.526711 # mshr miss rate for InvalidateReq accesses 2239system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for demand accesses 2240system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for demand accesses 2241system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for demand accesses 2242system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.237838 # mshr miss rate for demand accesses 2243system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154321 # mshr miss rate for demand accesses 2244system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.039070 # mshr miss rate for overall accesses 2245system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046848 # mshr miss rate for overall accesses 2246system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087453 # mshr miss rate for overall accesses 2247system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.237838 # mshr miss rate for overall accesses 2248system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2249system.cpu1.l2cache.overall_mshr_miss_rate::total 0.217094 # mshr miss rate for overall accesses 2250system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average ReadReq mshr miss latency 2251system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average ReadReq mshr miss latency 2252system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 40065.171060 # average ReadReq mshr miss latency 2253system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average HardPFReq mshr miss latency 2254system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43785.328080 # average HardPFReq mshr miss latency 2255system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31874.992652 # average UpgradeReq mshr miss latency 2256system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31874.992652 # average UpgradeReq mshr miss latency 2257system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19854.780249 # average SCUpgradeReq mshr miss latency 2258system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19854.780249 # average SCUpgradeReq mshr miss latency 2259system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 348566.666667 # average SCUpgradeFailReq mshr miss latency 2260system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 348566.666667 # average SCUpgradeFailReq mshr miss latency 2261system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44710.637580 # average ReadExReq mshr miss latency 2262system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44710.637580 # average ReadExReq mshr miss latency 2263system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average ReadCleanReq mshr miss latency 2264system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32004.071508 # average ReadCleanReq mshr miss latency 2265system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31158.050230 # average ReadSharedReq mshr miss latency 2266system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31158.050230 # average ReadSharedReq mshr miss latency 2267system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61513.666347 # average InvalidateReq mshr miss latency 2268system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61513.666347 # average InvalidateReq mshr miss latency 2269system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency 2270system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency 2271system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency 2272system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency 2273system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33588.698998 # average overall mshr miss latency 2274system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 37527.800787 # average overall mshr miss latency 2275system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 43063.937837 # average overall mshr miss latency 2276system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32004.071508 # average overall mshr miss latency 2277system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34125.219664 # average overall mshr miss latency 2278system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43785.328080 # average overall mshr miss latency 2279system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36537.046190 # average overall mshr miss latency 2280system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average ReadReq mshr uncacheable latency 2281system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176944.775845 # average ReadReq mshr uncacheable latency 2282system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 176694.151486 # average ReadReq mshr uncacheable latency 2283system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178460.692594 # average WriteReq mshr uncacheable latency 2284system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 178460.692594 # average WriteReq mshr uncacheable latency 2285system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average overall mshr uncacheable latency 2286system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 177678.007060 # average overall mshr uncacheable latency 2287system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 177546.385784 # average overall mshr uncacheable latency 2288system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2289system.cpu1.toL2Bus.snoop_filter.tot_requests 21257827 # Total number of requests made to the snoop filter. 2290system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10899393 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2291system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1168 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2292system.cpu1.toL2Bus.snoop_filter.tot_snoops 1702072 # Total number of snoops made to the snoop filter. 2293system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1701871 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2294system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2295system.cpu1.toL2Bus.trans_dist::ReadReq 509534 # Transaction distribution 2296system.cpu1.toL2Bus.trans_dist::ReadResp 9349922 # Transaction distribution 2297system.cpu1.toL2Bus.trans_dist::WriteReq 20416 # Transaction distribution 2298system.cpu1.toL2Bus.trans_dist::WriteResp 20416 # Transaction distribution 2299system.cpu1.toL2Bus.trans_dist::WritebackDirty 4305236 # Transaction distribution 2300system.cpu1.toL2Bus.trans_dist::WritebackClean 7031230 # Transaction distribution 2301system.cpu1.toL2Bus.trans_dist::CleanEvict 2216107 # Transaction distribution 2302system.cpu1.toL2Bus.trans_dist::HardPFReq 785182 # Transaction distribution 2303system.cpu1.toL2Bus.trans_dist::UpgradeReq 389899 # Transaction distribution 2304system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353464 # Transaction distribution 2305system.cpu1.toL2Bus.trans_dist::UpgradeResp 462412 # Transaction distribution 2306system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 94 # Transaction distribution 2307system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 2308system.cpu1.toL2Bus.trans_dist::ReadExReq 1157273 # Transaction distribution 2309system.cpu1.toL2Bus.trans_dist::ReadExResp 1096575 # Transaction distribution 2310system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5153566 # Transaction distribution 2311system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4436249 # Transaction distribution 2312system.cpu1.toL2Bus.trans_dist::InvalidateReq 522065 # Transaction distribution 2313system.cpu1.toL2Bus.trans_dist::InvalidateResp 513183 # Transaction distribution 2314system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15459725 # Packet count per connected master and slave (bytes) 2315system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16561050 # Packet count per connected master and slave (bytes) 2316system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 365076 # Packet count per connected master and slave (bytes) 2317system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544187 # Packet count per connected master and slave (bytes) 2318system.cpu1.toL2Bus.pkt_count::total 32930038 # Packet count per connected master and slave (bytes) 2319system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 659580536 # Cumulative packet size per connected master and slave (bytes) 2320system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 633491086 # Cumulative packet size per connected master and slave (bytes) 2321system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1395488 # Cumulative packet size per connected master and slave (bytes) 2322system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1977568 # Cumulative packet size per connected master and slave (bytes) 2323system.cpu1.toL2Bus.pkt_size::total 1296444678 # Cumulative packet size per connected master and slave (bytes) 2324system.cpu1.toL2Bus.snoops 5547167 # Total snoops (count) 2325system.cpu1.toL2Bus.snoop_fanout::samples 16615326 # Request fanout histogram 2326system.cpu1.toL2Bus.snoop_fanout::mean 0.116559 # Request fanout histogram 2327system.cpu1.toL2Bus.snoop_fanout::stdev 0.320932 # Request fanout histogram 2328system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2329system.cpu1.toL2Bus.snoop_fanout::0 14678862 88.35% 88.35% # Request fanout histogram 2330system.cpu1.toL2Bus.snoop_fanout::1 1936263 11.65% 100.00% # Request fanout histogram 2331system.cpu1.toL2Bus.snoop_fanout::2 201 0.00% 100.00% # Request fanout histogram 2332system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2333system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2334system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2335system.cpu1.toL2Bus.snoop_fanout::total 16615326 # Request fanout histogram 2336system.cpu1.toL2Bus.reqLayer0.occupancy 21053645498 # Layer occupancy (ticks) 2337system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2338system.cpu1.toL2Bus.snoopLayer0.occupancy 168856163 # Layer occupancy (ticks) 2339system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2340system.cpu1.toL2Bus.respLayer0.occupancy 7730459000 # Layer occupancy (ticks) 2341system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2342system.cpu1.toL2Bus.respLayer1.occupancy 7526670911 # Layer occupancy (ticks) 2343system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2344system.cpu1.toL2Bus.respLayer2.occupancy 190640499 # Layer occupancy (ticks) 2345system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2346system.cpu1.toL2Bus.respLayer3.occupancy 296991000 # Layer occupancy (ticks) 2347system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2348system.iobus.trans_dist::ReadReq 40402 # Transaction distribution 2349system.iobus.trans_dist::ReadResp 40402 # Transaction distribution 2350system.iobus.trans_dist::WriteReq 136652 # Transaction distribution 2351system.iobus.trans_dist::WriteResp 136652 # Transaction distribution 2352system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47834 # Packet count per connected master and slave (bytes) 2353system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2354system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2355system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2356system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2357system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2358system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2359system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2360system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2361system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2362system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2363system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2364system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2365system.iobus.pkt_count_system.bridge.master::total 122768 # Packet count per connected master and slave (bytes) 2366system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231260 # Packet count per connected master and slave (bytes) 2367system.iobus.pkt_count_system.realview.ide.dma::total 231260 # Packet count per connected master and slave (bytes) 2368system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2369system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2370system.iobus.pkt_count::total 354108 # Packet count per connected master and slave (bytes) 2371system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47854 # Cumulative packet size per connected master and slave (bytes) 2372system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2373system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2374system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2375system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2376system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2377system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2378system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2379system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2380system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2381system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2382system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2383system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2384system.iobus.pkt_size_system.bridge.master::total 155875 # Cumulative packet size per connected master and slave (bytes) 2385system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339056 # Cumulative packet size per connected master and slave (bytes) 2386system.iobus.pkt_size_system.realview.ide.dma::total 7339056 # Cumulative packet size per connected master and slave (bytes) 2387system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2388system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2389system.iobus.pkt_size::total 7497017 # Cumulative packet size per connected master and slave (bytes) 2390system.iobus.reqLayer0.occupancy 37033500 # Layer occupancy (ticks) 2391system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2392system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) 2393system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2394system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) 2395system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2396system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 2397system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2398system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) 2399system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2400system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2401system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2402system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) 2403system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2404system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2405system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2406system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2407system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2408system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 2409system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2410system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2411system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2412system.iobus.reqLayer23.occupancy 26450500 # Layer occupancy (ticks) 2413system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2414system.iobus.reqLayer24.occupancy 37419000 # Layer occupancy (ticks) 2415system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2416system.iobus.reqLayer25.occupancy 565570401 # Layer occupancy (ticks) 2417system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2418system.iobus.respLayer0.occupancy 92847000 # Layer occupancy (ticks) 2419system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2420system.iobus.respLayer3.occupancy 147956000 # Layer occupancy (ticks) 2421system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2422system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2423system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2424system.iocache.tags.replacements 115605 # number of replacements 2425system.iocache.tags.tagsinuse 11.294118 # Cycle average of tags in use 2426system.iocache.tags.total_refs 10 # Total number of references to valid blocks. 2427system.iocache.tags.sampled_refs 115621 # Sample count of references to valid blocks. 2428system.iocache.tags.avg_refs 0.000086 # Average number of references to valid blocks. 2429system.iocache.tags.warmup_cycle 9206098021000 # Cycle when the warmup percentage was hit. 2430system.iocache.tags.occ_blocks::realview.ethernet 3.822126 # Average occupied blocks per requestor 2431system.iocache.tags.occ_blocks::realview.ide 7.471992 # Average occupied blocks per requestor 2432system.iocache.tags.occ_percent::realview.ethernet 0.238883 # Average percentage of cache occupancy 2433system.iocache.tags.occ_percent::realview.ide 0.466999 # Average percentage of cache occupancy 2434system.iocache.tags.occ_percent::total 0.705882 # Average percentage of cache occupancy 2435system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2436system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2437system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2438system.iocache.tags.tag_accesses 1041013 # Number of tag accesses 2439system.iocache.tags.data_accesses 1041013 # Number of data accesses 2440system.iocache.WriteLineReq_hits::realview.ide 5 # number of WriteLineReq hits 2441system.iocache.WriteLineReq_hits::total 5 # number of WriteLineReq hits 2442system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2443system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses 2444system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses 2445system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2446system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2447system.iocache.WriteLineReq_misses::realview.ide 106723 # number of WriteLineReq misses 2448system.iocache.WriteLineReq_misses::total 106723 # number of WriteLineReq misses 2449system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2450system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses 2451system.iocache.demand_misses::total 8942 # number of demand (read+write) misses 2452system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2453system.iocache.overall_misses::realview.ide 8902 # number of overall misses 2454system.iocache.overall_misses::total 8942 # number of overall misses 2455system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 2456system.iocache.ReadReq_miss_latency::realview.ide 1679170514 # number of ReadReq miss cycles 2457system.iocache.ReadReq_miss_latency::total 1684370014 # number of ReadReq miss cycles 2458system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2459system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2460system.iocache.WriteLineReq_miss_latency::realview.ide 13974494387 # number of WriteLineReq miss cycles 2461system.iocache.WriteLineReq_miss_latency::total 13974494387 # number of WriteLineReq miss cycles 2462system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles 2463system.iocache.demand_miss_latency::realview.ide 1679170514 # number of demand (read+write) miss cycles 2464system.iocache.demand_miss_latency::total 1684739014 # number of demand (read+write) miss cycles 2465system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles 2466system.iocache.overall_miss_latency::realview.ide 1679170514 # number of overall miss cycles 2467system.iocache.overall_miss_latency::total 1684739014 # number of overall miss cycles 2468system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2469system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) 2470system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) 2471system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2472system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2473system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2474system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2475system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2476system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses 2477system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses 2478system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2479system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses 2480system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses 2481system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2482system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2483system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2484system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2485system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2486system.iocache.WriteLineReq_miss_rate::realview.ide 0.999953 # miss rate for WriteLineReq accesses 2487system.iocache.WriteLineReq_miss_rate::total 0.999953 # miss rate for WriteLineReq accesses 2488system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2489system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2490system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2491system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2492system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2493system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2494system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 2495system.iocache.ReadReq_avg_miss_latency::realview.ide 188628.455853 # average ReadReq miss latency 2496system.iocache.ReadReq_avg_miss_latency::total 188429.356080 # average ReadReq miss latency 2497system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2498system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2499system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130941.731276 # average WriteLineReq miss latency 2500system.iocache.WriteLineReq_avg_miss_latency::total 130941.731276 # average WriteLineReq miss latency 2501system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2502system.iocache.demand_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency 2503system.iocache.demand_avg_miss_latency::total 188407.404831 # average overall miss latency 2504system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2505system.iocache.overall_avg_miss_latency::realview.ide 188628.455853 # average overall miss latency 2506system.iocache.overall_avg_miss_latency::total 188407.404831 # average overall miss latency 2507system.iocache.blocked_cycles::no_mshrs 35755 # number of cycles access was blocked 2508system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2509system.iocache.blocked::no_mshrs 3742 # number of cycles access was blocked 2510system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2511system.iocache.avg_blocked_cycles::no_mshrs 9.555051 # average number of cycles each access was blocked 2512system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2513system.iocache.fast_writes 0 # number of fast writes performed 2514system.iocache.cache_copies 0 # number of cache copies performed 2515system.iocache.writebacks::writebacks 106695 # number of writebacks 2516system.iocache.writebacks::total 106695 # number of writebacks 2517system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2518system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses 2519system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses 2520system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2521system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2522system.iocache.WriteLineReq_mshr_misses::realview.ide 106723 # number of WriteLineReq MSHR misses 2523system.iocache.WriteLineReq_mshr_misses::total 106723 # number of WriteLineReq MSHR misses 2524system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2525system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses 2526system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses 2527system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2528system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses 2529system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses 2530system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 2531system.iocache.ReadReq_mshr_miss_latency::realview.ide 1234070514 # number of ReadReq MSHR miss cycles 2532system.iocache.ReadReq_mshr_miss_latency::total 1237420014 # number of ReadReq MSHR miss cycles 2533system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2534system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2535system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8638344387 # number of WriteLineReq MSHR miss cycles 2536system.iocache.WriteLineReq_mshr_miss_latency::total 8638344387 # number of WriteLineReq MSHR miss cycles 2537system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles 2538system.iocache.demand_mshr_miss_latency::realview.ide 1234070514 # number of demand (read+write) MSHR miss cycles 2539system.iocache.demand_mshr_miss_latency::total 1237639014 # number of demand (read+write) MSHR miss cycles 2540system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles 2541system.iocache.overall_mshr_miss_latency::realview.ide 1234070514 # number of overall MSHR miss cycles 2542system.iocache.overall_mshr_miss_latency::total 1237639014 # number of overall MSHR miss cycles 2543system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2544system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2545system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2546system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2547system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2548system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.999953 # mshr miss rate for WriteLineReq accesses 2549system.iocache.WriteLineReq_mshr_miss_rate::total 0.999953 # mshr miss rate for WriteLineReq accesses 2550system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2551system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2552system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2553system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2554system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2555system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2556system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 2557system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138628.455853 # average ReadReq mshr miss latency 2558system.iocache.ReadReq_avg_mshr_miss_latency::total 138429.356080 # average ReadReq mshr miss latency 2559system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2560system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2561system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80941.731276 # average WriteLineReq mshr miss latency 2562system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80941.731276 # average WriteLineReq mshr miss latency 2563system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2564system.iocache.demand_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency 2565system.iocache.demand_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency 2566system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2567system.iocache.overall_avg_mshr_miss_latency::realview.ide 138628.455853 # average overall mshr miss latency 2568system.iocache.overall_avg_mshr_miss_latency::total 138407.404831 # average overall mshr miss latency 2569system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2570system.l2c.tags.replacements 1201728 # number of replacements 2571system.l2c.tags.tagsinuse 62776.329461 # Cycle average of tags in use 2572system.l2c.tags.total_refs 5149298 # Total number of references to valid blocks. 2573system.l2c.tags.sampled_refs 1259663 # Sample count of references to valid blocks. 2574system.l2c.tags.avg_refs 4.087838 # Average number of references to valid blocks. 2575system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2576system.l2c.tags.occ_blocks::writebacks 23700.762045 # Average occupied blocks per requestor 2577system.l2c.tags.occ_blocks::cpu0.dtb.walker 102.528322 # Average occupied blocks per requestor 2578system.l2c.tags.occ_blocks::cpu0.itb.walker 175.969290 # Average occupied blocks per requestor 2579system.l2c.tags.occ_blocks::cpu0.inst 4011.755779 # Average occupied blocks per requestor 2580system.l2c.tags.occ_blocks::cpu0.data 5217.555279 # Average occupied blocks per requestor 2581system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7227.978697 # Average occupied blocks per requestor 2582system.l2c.tags.occ_blocks::cpu1.dtb.walker 166.263944 # Average occupied blocks per requestor 2583system.l2c.tags.occ_blocks::cpu1.itb.walker 281.111554 # Average occupied blocks per requestor 2584system.l2c.tags.occ_blocks::cpu1.inst 3722.000784 # Average occupied blocks per requestor 2585system.l2c.tags.occ_blocks::cpu1.data 8039.407020 # Average occupied blocks per requestor 2586system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10130.996747 # Average occupied blocks per requestor 2587system.l2c.tags.occ_percent::writebacks 0.361645 # Average percentage of cache occupancy 2588system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001564 # Average percentage of cache occupancy 2589system.l2c.tags.occ_percent::cpu0.itb.walker 0.002685 # Average percentage of cache occupancy 2590system.l2c.tags.occ_percent::cpu0.inst 0.061215 # Average percentage of cache occupancy 2591system.l2c.tags.occ_percent::cpu0.data 0.079614 # Average percentage of cache occupancy 2592system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110290 # Average percentage of cache occupancy 2593system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002537 # Average percentage of cache occupancy 2594system.l2c.tags.occ_percent::cpu1.itb.walker 0.004289 # Average percentage of cache occupancy 2595system.l2c.tags.occ_percent::cpu1.inst 0.056793 # Average percentage of cache occupancy 2596system.l2c.tags.occ_percent::cpu1.data 0.122672 # Average percentage of cache occupancy 2597system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.154587 # Average percentage of cache occupancy 2598system.l2c.tags.occ_percent::total 0.957891 # Average percentage of cache occupancy 2599system.l2c.tags.occ_task_id_blocks::1022 9737 # Occupied blocks per task id 2600system.l2c.tags.occ_task_id_blocks::1023 265 # Occupied blocks per task id 2601system.l2c.tags.occ_task_id_blocks::1024 47933 # Occupied blocks per task id 2602system.l2c.tags.age_task_id_blocks_1022::2 59 # Occupied blocks per task id 2603system.l2c.tags.age_task_id_blocks_1022::3 277 # Occupied blocks per task id 2604system.l2c.tags.age_task_id_blocks_1022::4 9401 # Occupied blocks per task id 2605system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2606system.l2c.tags.age_task_id_blocks_1023::4 264 # Occupied blocks per task id 2607system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id 2608system.l2c.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id 2609system.l2c.tags.age_task_id_blocks_1024::2 1658 # Occupied blocks per task id 2610system.l2c.tags.age_task_id_blocks_1024::3 5230 # Occupied blocks per task id 2611system.l2c.tags.age_task_id_blocks_1024::4 40901 # Occupied blocks per task id 2612system.l2c.tags.occ_task_id_percent::1022 0.148575 # Percentage of cache occupancy per task id 2613system.l2c.tags.occ_task_id_percent::1023 0.004044 # Percentage of cache occupancy per task id 2614system.l2c.tags.occ_task_id_percent::1024 0.731400 # Percentage of cache occupancy per task id 2615system.l2c.tags.tag_accesses 66235328 # Number of tag accesses 2616system.l2c.tags.data_accesses 66235328 # Number of data accesses 2617system.l2c.WritebackDirty_hits::writebacks 2474359 # number of WritebackDirty hits 2618system.l2c.WritebackDirty_hits::total 2474359 # number of WritebackDirty hits 2619system.l2c.UpgradeReq_hits::cpu0.data 150616 # number of UpgradeReq hits 2620system.l2c.UpgradeReq_hits::cpu1.data 127305 # number of UpgradeReq hits 2621system.l2c.UpgradeReq_hits::total 277921 # number of UpgradeReq hits 2622system.l2c.SCUpgradeReq_hits::cpu0.data 34718 # number of SCUpgradeReq hits 2623system.l2c.SCUpgradeReq_hits::cpu1.data 37539 # number of SCUpgradeReq hits 2624system.l2c.SCUpgradeReq_hits::total 72257 # number of SCUpgradeReq hits 2625system.l2c.ReadExReq_hits::cpu0.data 146279 # number of ReadExReq hits 2626system.l2c.ReadExReq_hits::cpu1.data 167990 # number of ReadExReq hits 2627system.l2c.ReadExReq_hits::total 314269 # number of ReadExReq hits 2628system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 4627 # number of ReadSharedReq hits 2629system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3559 # number of ReadSharedReq hits 2630system.l2c.ReadSharedReq_hits::cpu0.inst 390104 # number of ReadSharedReq hits 2631system.l2c.ReadSharedReq_hits::cpu0.data 513889 # number of ReadSharedReq hits 2632system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 259608 # number of ReadSharedReq hits 2633system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5392 # number of ReadSharedReq hits 2634system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4493 # number of ReadSharedReq hits 2635system.l2c.ReadSharedReq_hits::cpu1.inst 410490 # number of ReadSharedReq hits 2636system.l2c.ReadSharedReq_hits::cpu1.data 516454 # number of ReadSharedReq hits 2637system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 291033 # number of ReadSharedReq hits 2638system.l2c.ReadSharedReq_hits::total 2399649 # number of ReadSharedReq hits 2639system.l2c.demand_hits::cpu0.dtb.walker 4627 # number of demand (read+write) hits 2640system.l2c.demand_hits::cpu0.itb.walker 3559 # number of demand (read+write) hits 2641system.l2c.demand_hits::cpu0.inst 390104 # number of demand (read+write) hits 2642system.l2c.demand_hits::cpu0.data 660168 # number of demand (read+write) hits 2643system.l2c.demand_hits::cpu0.l2cache.prefetcher 259608 # number of demand (read+write) hits 2644system.l2c.demand_hits::cpu1.dtb.walker 5392 # number of demand (read+write) hits 2645system.l2c.demand_hits::cpu1.itb.walker 4493 # number of demand (read+write) hits 2646system.l2c.demand_hits::cpu1.inst 410490 # number of demand (read+write) hits 2647system.l2c.demand_hits::cpu1.data 684444 # number of demand (read+write) hits 2648system.l2c.demand_hits::cpu1.l2cache.prefetcher 291033 # number of demand (read+write) hits 2649system.l2c.demand_hits::total 2713918 # number of demand (read+write) hits 2650system.l2c.overall_hits::cpu0.dtb.walker 4627 # number of overall hits 2651system.l2c.overall_hits::cpu0.itb.walker 3559 # number of overall hits 2652system.l2c.overall_hits::cpu0.inst 390104 # number of overall hits 2653system.l2c.overall_hits::cpu0.data 660168 # number of overall hits 2654system.l2c.overall_hits::cpu0.l2cache.prefetcher 259608 # number of overall hits 2655system.l2c.overall_hits::cpu1.dtb.walker 5392 # number of overall hits 2656system.l2c.overall_hits::cpu1.itb.walker 4493 # number of overall hits 2657system.l2c.overall_hits::cpu1.inst 410490 # number of overall hits 2658system.l2c.overall_hits::cpu1.data 684444 # number of overall hits 2659system.l2c.overall_hits::cpu1.l2cache.prefetcher 291033 # number of overall hits 2660system.l2c.overall_hits::total 2713918 # number of overall hits 2661system.l2c.UpgradeReq_misses::cpu0.data 62469 # number of UpgradeReq misses 2662system.l2c.UpgradeReq_misses::cpu1.data 57486 # number of UpgradeReq misses 2663system.l2c.UpgradeReq_misses::total 119955 # number of UpgradeReq misses 2664system.l2c.SCUpgradeReq_misses::cpu0.data 13684 # number of SCUpgradeReq misses 2665system.l2c.SCUpgradeReq_misses::cpu1.data 12909 # number of SCUpgradeReq misses 2666system.l2c.SCUpgradeReq_misses::total 26593 # number of SCUpgradeReq misses 2667system.l2c.ReadExReq_misses::cpu0.data 477377 # number of ReadExReq misses 2668system.l2c.ReadExReq_misses::cpu1.data 148178 # number of ReadExReq misses 2669system.l2c.ReadExReq_misses::total 625555 # number of ReadExReq misses 2670system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1085 # number of ReadSharedReq misses 2671system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1066 # number of ReadSharedReq misses 2672system.l2c.ReadSharedReq_misses::cpu0.inst 45695 # number of ReadSharedReq misses 2673system.l2c.ReadSharedReq_misses::cpu0.data 111052 # number of ReadSharedReq misses 2674system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 202654 # number of ReadSharedReq misses 2675system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1546 # number of ReadSharedReq misses 2676system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1684 # number of ReadSharedReq misses 2677system.l2c.ReadSharedReq_misses::cpu1.inst 40203 # number of ReadSharedReq misses 2678system.l2c.ReadSharedReq_misses::cpu1.data 92070 # number of ReadSharedReq misses 2679system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 143125 # number of ReadSharedReq misses 2680system.l2c.ReadSharedReq_misses::total 640180 # number of ReadSharedReq misses 2681system.l2c.demand_misses::cpu0.dtb.walker 1085 # number of demand (read+write) misses 2682system.l2c.demand_misses::cpu0.itb.walker 1066 # number of demand (read+write) misses 2683system.l2c.demand_misses::cpu0.inst 45695 # number of demand (read+write) misses 2684system.l2c.demand_misses::cpu0.data 588429 # number of demand (read+write) misses 2685system.l2c.demand_misses::cpu0.l2cache.prefetcher 202654 # number of demand (read+write) misses 2686system.l2c.demand_misses::cpu1.dtb.walker 1546 # number of demand (read+write) misses 2687system.l2c.demand_misses::cpu1.itb.walker 1684 # number of demand (read+write) misses 2688system.l2c.demand_misses::cpu1.inst 40203 # number of demand (read+write) misses 2689system.l2c.demand_misses::cpu1.data 240248 # number of demand (read+write) misses 2690system.l2c.demand_misses::cpu1.l2cache.prefetcher 143125 # number of demand (read+write) misses 2691system.l2c.demand_misses::total 1265735 # number of demand (read+write) misses 2692system.l2c.overall_misses::cpu0.dtb.walker 1085 # number of overall misses 2693system.l2c.overall_misses::cpu0.itb.walker 1066 # number of overall misses 2694system.l2c.overall_misses::cpu0.inst 45695 # number of overall misses 2695system.l2c.overall_misses::cpu0.data 588429 # number of overall misses 2696system.l2c.overall_misses::cpu0.l2cache.prefetcher 202654 # number of overall misses 2697system.l2c.overall_misses::cpu1.dtb.walker 1546 # number of overall misses 2698system.l2c.overall_misses::cpu1.itb.walker 1684 # number of overall misses 2699system.l2c.overall_misses::cpu1.inst 40203 # number of overall misses 2700system.l2c.overall_misses::cpu1.data 240248 # number of overall misses 2701system.l2c.overall_misses::cpu1.l2cache.prefetcher 143125 # number of overall misses 2702system.l2c.overall_misses::total 1265735 # number of overall misses 2703system.l2c.UpgradeReq_miss_latency::cpu0.data 928670500 # number of UpgradeReq miss cycles 2704system.l2c.UpgradeReq_miss_latency::cpu1.data 1025251000 # number of UpgradeReq miss cycles 2705system.l2c.UpgradeReq_miss_latency::total 1953921500 # number of UpgradeReq miss cycles 2706system.l2c.SCUpgradeReq_miss_latency::cpu0.data 178207000 # number of SCUpgradeReq miss cycles 2707system.l2c.SCUpgradeReq_miss_latency::cpu1.data 182538500 # number of SCUpgradeReq miss cycles 2708system.l2c.SCUpgradeReq_miss_latency::total 360745500 # number of SCUpgradeReq miss cycles 2709system.l2c.ReadExReq_miss_latency::cpu0.data 63116930500 # number of ReadExReq miss cycles 2710system.l2c.ReadExReq_miss_latency::cpu1.data 19400961500 # number of ReadExReq miss cycles 2711system.l2c.ReadExReq_miss_latency::total 82517892000 # number of ReadExReq miss cycles 2712system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 153728000 # number of ReadSharedReq miss cycles 2713system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 149604000 # number of ReadSharedReq miss cycles 2714system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6143069000 # number of ReadSharedReq miss cycles 2715system.l2c.ReadSharedReq_miss_latency::cpu0.data 15249907500 # number of ReadSharedReq miss cycles 2716system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of ReadSharedReq miss cycles 2717system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 212651500 # number of ReadSharedReq miss cycles 2718system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 233752000 # number of ReadSharedReq miss cycles 2719system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5417778000 # number of ReadSharedReq miss cycles 2720system.l2c.ReadSharedReq_miss_latency::cpu1.data 12722216500 # number of ReadSharedReq miss cycles 2721system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of ReadSharedReq miss cycles 2722system.l2c.ReadSharedReq_miss_latency::total 96202750409 # number of ReadSharedReq miss cycles 2723system.l2c.demand_miss_latency::cpu0.dtb.walker 153728000 # number of demand (read+write) miss cycles 2724system.l2c.demand_miss_latency::cpu0.itb.walker 149604000 # number of demand (read+write) miss cycles 2725system.l2c.demand_miss_latency::cpu0.inst 6143069000 # number of demand (read+write) miss cycles 2726system.l2c.demand_miss_latency::cpu0.data 78366838000 # number of demand (read+write) miss cycles 2727system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of demand (read+write) miss cycles 2728system.l2c.demand_miss_latency::cpu1.dtb.walker 212651500 # number of demand (read+write) miss cycles 2729system.l2c.demand_miss_latency::cpu1.itb.walker 233752000 # number of demand (read+write) miss cycles 2730system.l2c.demand_miss_latency::cpu1.inst 5417778000 # number of demand (read+write) miss cycles 2731system.l2c.demand_miss_latency::cpu1.data 32123178000 # number of demand (read+write) miss cycles 2732system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of demand (read+write) miss cycles 2733system.l2c.demand_miss_latency::total 178720642409 # number of demand (read+write) miss cycles 2734system.l2c.overall_miss_latency::cpu0.dtb.walker 153728000 # number of overall miss cycles 2735system.l2c.overall_miss_latency::cpu0.itb.walker 149604000 # number of overall miss cycles 2736system.l2c.overall_miss_latency::cpu0.inst 6143069000 # number of overall miss cycles 2737system.l2c.overall_miss_latency::cpu0.data 78366838000 # number of overall miss cycles 2738system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32848298905 # number of overall miss cycles 2739system.l2c.overall_miss_latency::cpu1.dtb.walker 212651500 # number of overall miss cycles 2740system.l2c.overall_miss_latency::cpu1.itb.walker 233752000 # number of overall miss cycles 2741system.l2c.overall_miss_latency::cpu1.inst 5417778000 # number of overall miss cycles 2742system.l2c.overall_miss_latency::cpu1.data 32123178000 # number of overall miss cycles 2743system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 23071745004 # number of overall miss cycles 2744system.l2c.overall_miss_latency::total 178720642409 # number of overall miss cycles 2745system.l2c.WritebackDirty_accesses::writebacks 2474359 # number of WritebackDirty accesses(hits+misses) 2746system.l2c.WritebackDirty_accesses::total 2474359 # number of WritebackDirty accesses(hits+misses) 2747system.l2c.UpgradeReq_accesses::cpu0.data 213085 # number of UpgradeReq accesses(hits+misses) 2748system.l2c.UpgradeReq_accesses::cpu1.data 184791 # number of UpgradeReq accesses(hits+misses) 2749system.l2c.UpgradeReq_accesses::total 397876 # number of UpgradeReq accesses(hits+misses) 2750system.l2c.SCUpgradeReq_accesses::cpu0.data 48402 # number of SCUpgradeReq accesses(hits+misses) 2751system.l2c.SCUpgradeReq_accesses::cpu1.data 50448 # number of SCUpgradeReq accesses(hits+misses) 2752system.l2c.SCUpgradeReq_accesses::total 98850 # number of SCUpgradeReq accesses(hits+misses) 2753system.l2c.ReadExReq_accesses::cpu0.data 623656 # number of ReadExReq accesses(hits+misses) 2754system.l2c.ReadExReq_accesses::cpu1.data 316168 # number of ReadExReq accesses(hits+misses) 2755system.l2c.ReadExReq_accesses::total 939824 # number of ReadExReq accesses(hits+misses) 2756system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 5712 # number of ReadSharedReq accesses(hits+misses) 2757system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4625 # number of ReadSharedReq accesses(hits+misses) 2758system.l2c.ReadSharedReq_accesses::cpu0.inst 435799 # number of ReadSharedReq accesses(hits+misses) 2759system.l2c.ReadSharedReq_accesses::cpu0.data 624941 # number of ReadSharedReq accesses(hits+misses) 2760system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 462262 # number of ReadSharedReq accesses(hits+misses) 2761system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6938 # number of ReadSharedReq accesses(hits+misses) 2762system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6177 # number of ReadSharedReq accesses(hits+misses) 2763system.l2c.ReadSharedReq_accesses::cpu1.inst 450693 # number of ReadSharedReq accesses(hits+misses) 2764system.l2c.ReadSharedReq_accesses::cpu1.data 608524 # number of ReadSharedReq accesses(hits+misses) 2765system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 434158 # number of ReadSharedReq accesses(hits+misses) 2766system.l2c.ReadSharedReq_accesses::total 3039829 # number of ReadSharedReq accesses(hits+misses) 2767system.l2c.demand_accesses::cpu0.dtb.walker 5712 # number of demand (read+write) accesses 2768system.l2c.demand_accesses::cpu0.itb.walker 4625 # number of demand (read+write) accesses 2769system.l2c.demand_accesses::cpu0.inst 435799 # number of demand (read+write) accesses 2770system.l2c.demand_accesses::cpu0.data 1248597 # number of demand (read+write) accesses 2771system.l2c.demand_accesses::cpu0.l2cache.prefetcher 462262 # number of demand (read+write) accesses 2772system.l2c.demand_accesses::cpu1.dtb.walker 6938 # number of demand (read+write) accesses 2773system.l2c.demand_accesses::cpu1.itb.walker 6177 # number of demand (read+write) accesses 2774system.l2c.demand_accesses::cpu1.inst 450693 # number of demand (read+write) accesses 2775system.l2c.demand_accesses::cpu1.data 924692 # number of demand (read+write) accesses 2776system.l2c.demand_accesses::cpu1.l2cache.prefetcher 434158 # number of demand (read+write) accesses 2777system.l2c.demand_accesses::total 3979653 # number of demand (read+write) accesses 2778system.l2c.overall_accesses::cpu0.dtb.walker 5712 # number of overall (read+write) accesses 2779system.l2c.overall_accesses::cpu0.itb.walker 4625 # number of overall (read+write) accesses 2780system.l2c.overall_accesses::cpu0.inst 435799 # number of overall (read+write) accesses 2781system.l2c.overall_accesses::cpu0.data 1248597 # number of overall (read+write) accesses 2782system.l2c.overall_accesses::cpu0.l2cache.prefetcher 462262 # number of overall (read+write) accesses 2783system.l2c.overall_accesses::cpu1.dtb.walker 6938 # number of overall (read+write) accesses 2784system.l2c.overall_accesses::cpu1.itb.walker 6177 # number of overall (read+write) accesses 2785system.l2c.overall_accesses::cpu1.inst 450693 # number of overall (read+write) accesses 2786system.l2c.overall_accesses::cpu1.data 924692 # number of overall (read+write) accesses 2787system.l2c.overall_accesses::cpu1.l2cache.prefetcher 434158 # number of overall (read+write) accesses 2788system.l2c.overall_accesses::total 3979653 # number of overall (read+write) accesses 2789system.l2c.UpgradeReq_miss_rate::cpu0.data 0.293165 # miss rate for UpgradeReq accesses 2790system.l2c.UpgradeReq_miss_rate::cpu1.data 0.311087 # miss rate for UpgradeReq accesses 2791system.l2c.UpgradeReq_miss_rate::total 0.301488 # miss rate for UpgradeReq accesses 2792system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.282716 # miss rate for SCUpgradeReq accesses 2793system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.255887 # miss rate for SCUpgradeReq accesses 2794system.l2c.SCUpgradeReq_miss_rate::total 0.269024 # miss rate for SCUpgradeReq accesses 2795system.l2c.ReadExReq_miss_rate::cpu0.data 0.765449 # miss rate for ReadExReq accesses 2796system.l2c.ReadExReq_miss_rate::cpu1.data 0.468669 # miss rate for ReadExReq accesses 2797system.l2c.ReadExReq_miss_rate::total 0.665609 # miss rate for ReadExReq accesses 2798system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.189951 # miss rate for ReadSharedReq accesses 2799system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.230486 # miss rate for ReadSharedReq accesses 2800system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.104853 # miss rate for ReadSharedReq accesses 2801system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.177700 # miss rate for ReadSharedReq accesses 2802system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.438396 # miss rate for ReadSharedReq accesses 2803system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.222831 # miss rate for ReadSharedReq accesses 2804system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.272624 # miss rate for ReadSharedReq accesses 2805system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.089203 # miss rate for ReadSharedReq accesses 2806system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.151301 # miss rate for ReadSharedReq accesses 2807system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.329661 # miss rate for ReadSharedReq accesses 2808system.l2c.ReadSharedReq_miss_rate::total 0.210597 # miss rate for ReadSharedReq accesses 2809system.l2c.demand_miss_rate::cpu0.dtb.walker 0.189951 # miss rate for demand accesses 2810system.l2c.demand_miss_rate::cpu0.itb.walker 0.230486 # miss rate for demand accesses 2811system.l2c.demand_miss_rate::cpu0.inst 0.104853 # miss rate for demand accesses 2812system.l2c.demand_miss_rate::cpu0.data 0.471272 # miss rate for demand accesses 2813system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.438396 # miss rate for demand accesses 2814system.l2c.demand_miss_rate::cpu1.dtb.walker 0.222831 # miss rate for demand accesses 2815system.l2c.demand_miss_rate::cpu1.itb.walker 0.272624 # miss rate for demand accesses 2816system.l2c.demand_miss_rate::cpu1.inst 0.089203 # miss rate for demand accesses 2817system.l2c.demand_miss_rate::cpu1.data 0.259814 # miss rate for demand accesses 2818system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.329661 # miss rate for demand accesses 2819system.l2c.demand_miss_rate::total 0.318052 # miss rate for demand accesses 2820system.l2c.overall_miss_rate::cpu0.dtb.walker 0.189951 # miss rate for overall accesses 2821system.l2c.overall_miss_rate::cpu0.itb.walker 0.230486 # miss rate for overall accesses 2822system.l2c.overall_miss_rate::cpu0.inst 0.104853 # miss rate for overall accesses 2823system.l2c.overall_miss_rate::cpu0.data 0.471272 # miss rate for overall accesses 2824system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.438396 # miss rate for overall accesses 2825system.l2c.overall_miss_rate::cpu1.dtb.walker 0.222831 # miss rate for overall accesses 2826system.l2c.overall_miss_rate::cpu1.itb.walker 0.272624 # miss rate for overall accesses 2827system.l2c.overall_miss_rate::cpu1.inst 0.089203 # miss rate for overall accesses 2828system.l2c.overall_miss_rate::cpu1.data 0.259814 # miss rate for overall accesses 2829system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.329661 # miss rate for overall accesses 2830system.l2c.overall_miss_rate::total 0.318052 # miss rate for overall accesses 2831system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14866.101586 # average UpgradeReq miss latency 2832system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17834.794559 # average UpgradeReq miss latency 2833system.l2c.UpgradeReq_avg_miss_latency::total 16288.787462 # average UpgradeReq miss latency 2834system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13023.019585 # average SCUpgradeReq miss latency 2835system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14140.405918 # average SCUpgradeReq miss latency 2836system.l2c.SCUpgradeReq_avg_miss_latency::total 13565.430752 # average SCUpgradeReq miss latency 2837system.l2c.ReadExReq_avg_miss_latency::cpu0.data 132216.111166 # average ReadExReq miss latency 2838system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130930.107708 # average ReadExReq miss latency 2839system.l2c.ReadExReq_avg_miss_latency::total 131911.489797 # average ReadExReq miss latency 2840system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141684.792627 # average ReadSharedReq miss latency 2841system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140341.463415 # average ReadSharedReq miss latency 2842system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134436.349710 # average ReadSharedReq miss latency 2843system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 137322.222923 # average ReadSharedReq miss latency 2844system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888 # average ReadSharedReq miss latency 2845system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 137549.482536 # average ReadSharedReq miss latency 2846system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 138807.600950 # average ReadSharedReq miss latency 2847system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134760.540258 # average ReadSharedReq miss latency 2848system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138179.825133 # average ReadSharedReq miss latency 2849system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093 # average ReadSharedReq miss latency 2850system.l2c.ReadSharedReq_avg_miss_latency::total 150274.532802 # average ReadSharedReq miss latency 2851system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141684.792627 # average overall miss latency 2852system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140341.463415 # average overall miss latency 2853system.l2c.demand_avg_miss_latency::cpu0.inst 134436.349710 # average overall miss latency 2854system.l2c.demand_avg_miss_latency::cpu0.data 133179.768502 # average overall miss latency 2855system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888 # average overall miss latency 2856system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137549.482536 # average overall miss latency 2857system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138807.600950 # average overall miss latency 2858system.l2c.demand_avg_miss_latency::cpu1.inst 134760.540258 # average overall miss latency 2859system.l2c.demand_avg_miss_latency::cpu1.data 133708.409643 # average overall miss latency 2860system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093 # average overall miss latency 2861system.l2c.demand_avg_miss_latency::total 141199.099661 # average overall miss latency 2862system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141684.792627 # average overall miss latency 2863system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140341.463415 # average overall miss latency 2864system.l2c.overall_avg_miss_latency::cpu0.inst 134436.349710 # average overall miss latency 2865system.l2c.overall_avg_miss_latency::cpu0.data 133179.768502 # average overall miss latency 2866system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 162090.552888 # average overall miss latency 2867system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137549.482536 # average overall miss latency 2868system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138807.600950 # average overall miss latency 2869system.l2c.overall_avg_miss_latency::cpu1.inst 134760.540258 # average overall miss latency 2870system.l2c.overall_avg_miss_latency::cpu1.data 133708.409643 # average overall miss latency 2871system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 161199.965093 # average overall miss latency 2872system.l2c.overall_avg_miss_latency::total 141199.099661 # average overall miss latency 2873system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2874system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2875system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2876system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2877system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2878system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2879system.l2c.fast_writes 0 # number of fast writes performed 2880system.l2c.cache_copies 0 # number of cache copies performed 2881system.l2c.writebacks::writebacks 969294 # number of writebacks 2882system.l2c.writebacks::total 969294 # number of writebacks 2883system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 118 # number of ReadSharedReq MSHR hits 2884system.l2c.ReadSharedReq_mshr_hits::cpu0.data 27 # number of ReadSharedReq MSHR hits 2885system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 91 # number of ReadSharedReq MSHR hits 2886system.l2c.ReadSharedReq_mshr_hits::cpu1.data 23 # number of ReadSharedReq MSHR hits 2887system.l2c.ReadSharedReq_mshr_hits::total 259 # number of ReadSharedReq MSHR hits 2888system.l2c.demand_mshr_hits::cpu0.inst 118 # number of demand (read+write) MSHR hits 2889system.l2c.demand_mshr_hits::cpu0.data 27 # number of demand (read+write) MSHR hits 2890system.l2c.demand_mshr_hits::cpu1.inst 91 # number of demand (read+write) MSHR hits 2891system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits 2892system.l2c.demand_mshr_hits::total 259 # number of demand (read+write) MSHR hits 2893system.l2c.overall_mshr_hits::cpu0.inst 118 # number of overall MSHR hits 2894system.l2c.overall_mshr_hits::cpu0.data 27 # number of overall MSHR hits 2895system.l2c.overall_mshr_hits::cpu1.inst 91 # number of overall MSHR hits 2896system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits 2897system.l2c.overall_mshr_hits::total 259 # number of overall MSHR hits 2898system.l2c.CleanEvict_mshr_misses::writebacks 39496 # number of CleanEvict MSHR misses 2899system.l2c.CleanEvict_mshr_misses::total 39496 # number of CleanEvict MSHR misses 2900system.l2c.UpgradeReq_mshr_misses::cpu0.data 62469 # number of UpgradeReq MSHR misses 2901system.l2c.UpgradeReq_mshr_misses::cpu1.data 57486 # number of UpgradeReq MSHR misses 2902system.l2c.UpgradeReq_mshr_misses::total 119955 # number of UpgradeReq MSHR misses 2903system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13684 # number of SCUpgradeReq MSHR misses 2904system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 12909 # number of SCUpgradeReq MSHR misses 2905system.l2c.SCUpgradeReq_mshr_misses::total 26593 # number of SCUpgradeReq MSHR misses 2906system.l2c.ReadExReq_mshr_misses::cpu0.data 477377 # number of ReadExReq MSHR misses 2907system.l2c.ReadExReq_mshr_misses::cpu1.data 148178 # number of ReadExReq MSHR misses 2908system.l2c.ReadExReq_mshr_misses::total 625555 # number of ReadExReq MSHR misses 2909system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1085 # number of ReadSharedReq MSHR misses 2910system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1066 # number of ReadSharedReq MSHR misses 2911system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45577 # number of ReadSharedReq MSHR misses 2912system.l2c.ReadSharedReq_mshr_misses::cpu0.data 111025 # number of ReadSharedReq MSHR misses 2913system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 202654 # number of ReadSharedReq MSHR misses 2914system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1546 # number of ReadSharedReq MSHR misses 2915system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1684 # number of ReadSharedReq MSHR misses 2916system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 40112 # number of ReadSharedReq MSHR misses 2917system.l2c.ReadSharedReq_mshr_misses::cpu1.data 92047 # number of ReadSharedReq MSHR misses 2918system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 143125 # number of ReadSharedReq MSHR misses 2919system.l2c.ReadSharedReq_mshr_misses::total 639921 # number of ReadSharedReq MSHR misses 2920system.l2c.demand_mshr_misses::cpu0.dtb.walker 1085 # number of demand (read+write) MSHR misses 2921system.l2c.demand_mshr_misses::cpu0.itb.walker 1066 # number of demand (read+write) MSHR misses 2922system.l2c.demand_mshr_misses::cpu0.inst 45577 # number of demand (read+write) MSHR misses 2923system.l2c.demand_mshr_misses::cpu0.data 588402 # number of demand (read+write) MSHR misses 2924system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 202654 # number of demand (read+write) MSHR misses 2925system.l2c.demand_mshr_misses::cpu1.dtb.walker 1546 # number of demand (read+write) MSHR misses 2926system.l2c.demand_mshr_misses::cpu1.itb.walker 1684 # number of demand (read+write) MSHR misses 2927system.l2c.demand_mshr_misses::cpu1.inst 40112 # number of demand (read+write) MSHR misses 2928system.l2c.demand_mshr_misses::cpu1.data 240225 # number of demand (read+write) MSHR misses 2929system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 143125 # number of demand (read+write) MSHR misses 2930system.l2c.demand_mshr_misses::total 1265476 # number of demand (read+write) MSHR misses 2931system.l2c.overall_mshr_misses::cpu0.dtb.walker 1085 # number of overall MSHR misses 2932system.l2c.overall_mshr_misses::cpu0.itb.walker 1066 # number of overall MSHR misses 2933system.l2c.overall_mshr_misses::cpu0.inst 45577 # number of overall MSHR misses 2934system.l2c.overall_mshr_misses::cpu0.data 588402 # number of overall MSHR misses 2935system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 202654 # number of overall MSHR misses 2936system.l2c.overall_mshr_misses::cpu1.dtb.walker 1546 # number of overall MSHR misses 2937system.l2c.overall_mshr_misses::cpu1.itb.walker 1684 # number of overall MSHR misses 2938system.l2c.overall_mshr_misses::cpu1.inst 40112 # number of overall MSHR misses 2939system.l2c.overall_mshr_misses::cpu1.data 240225 # number of overall MSHR misses 2940system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 143125 # number of overall MSHR misses 2941system.l2c.overall_mshr_misses::total 1265476 # number of overall MSHR misses 2942system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 2943system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16746 # number of ReadReq MSHR uncacheable 2944system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2945system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21791 # number of ReadReq MSHR uncacheable 2946system.l2c.ReadReq_mshr_uncacheable::total 81772 # number of ReadReq MSHR uncacheable 2947system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17968 # number of WriteReq MSHR uncacheable 2948system.l2c.WriteReq_mshr_uncacheable::cpu1.data 20416 # number of WriteReq MSHR uncacheable 2949system.l2c.WriteReq_mshr_uncacheable::total 38384 # number of WriteReq MSHR uncacheable 2950system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 2951system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34714 # number of overall MSHR uncacheable misses 2952system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2953system.l2c.overall_mshr_uncacheable_misses::cpu1.data 42207 # number of overall MSHR uncacheable misses 2954system.l2c.overall_mshr_uncacheable_misses::total 120156 # number of overall MSHR uncacheable misses 2955system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4603464500 # number of UpgradeReq MSHR miss cycles 2956system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4224060500 # number of UpgradeReq MSHR miss cycles 2957system.l2c.UpgradeReq_mshr_miss_latency::total 8827525000 # number of UpgradeReq MSHR miss cycles 2958system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1048639500 # number of SCUpgradeReq MSHR miss cycles 2959system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 988070500 # number of SCUpgradeReq MSHR miss cycles 2960system.l2c.SCUpgradeReq_mshr_miss_latency::total 2036710000 # number of SCUpgradeReq MSHR miss cycles 2961system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 58343160500 # number of ReadExReq MSHR miss cycles 2962system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 17919181500 # number of ReadExReq MSHR miss cycles 2963system.l2c.ReadExReq_mshr_miss_latency::total 76262342000 # number of ReadExReq MSHR miss cycles 2964system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 142878000 # number of ReadSharedReq MSHR miss cycles 2965system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 138944000 # number of ReadSharedReq MSHR miss cycles 2966system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 5673195000 # number of ReadSharedReq MSHR miss cycles 2967system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14136518000 # number of ReadSharedReq MSHR miss cycles 2968system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 30821758905 # number of ReadSharedReq MSHR miss cycles 2969system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 197191500 # number of ReadSharedReq MSHR miss cycles 2970system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 216912000 # number of ReadSharedReq MSHR miss cycles 2971system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5007052000 # number of ReadSharedReq MSHR miss cycles 2972system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11798625000 # number of ReadSharedReq MSHR miss cycles 2973system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21640495004 # number of ReadSharedReq MSHR miss cycles 2974system.l2c.ReadSharedReq_mshr_miss_latency::total 89773569409 # number of ReadSharedReq MSHR miss cycles 2975system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 142878000 # number of demand (read+write) MSHR miss cycles 2976system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 138944000 # number of demand (read+write) MSHR miss cycles 2977system.l2c.demand_mshr_miss_latency::cpu0.inst 5673195000 # number of demand (read+write) MSHR miss cycles 2978system.l2c.demand_mshr_miss_latency::cpu0.data 72479678500 # number of demand (read+write) MSHR miss cycles 2979system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 30821758905 # number of demand (read+write) MSHR miss cycles 2980system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197191500 # number of demand (read+write) MSHR miss cycles 2981system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 216912000 # number of demand (read+write) MSHR miss cycles 2982system.l2c.demand_mshr_miss_latency::cpu1.inst 5007052000 # number of demand (read+write) MSHR miss cycles 2983system.l2c.demand_mshr_miss_latency::cpu1.data 29717806500 # number of demand (read+write) MSHR miss cycles 2984system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21640495004 # number of demand (read+write) MSHR miss cycles 2985system.l2c.demand_mshr_miss_latency::total 166035911409 # number of demand (read+write) MSHR miss cycles 2986system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 142878000 # number of overall MSHR miss cycles 2987system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 138944000 # number of overall MSHR miss cycles 2988system.l2c.overall_mshr_miss_latency::cpu0.inst 5673195000 # number of overall MSHR miss cycles 2989system.l2c.overall_mshr_miss_latency::cpu0.data 72479678500 # number of overall MSHR miss cycles 2990system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 30821758905 # number of overall MSHR miss cycles 2991system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197191500 # number of overall MSHR miss cycles 2992system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 216912000 # number of overall MSHR miss cycles 2993system.l2c.overall_mshr_miss_latency::cpu1.inst 5007052000 # number of overall MSHR miss cycles 2994system.l2c.overall_mshr_miss_latency::cpu1.data 29717806500 # number of overall MSHR miss cycles 2995system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21640495004 # number of overall MSHR miss cycles 2996system.l2c.overall_mshr_miss_latency::total 166035911409 # number of overall MSHR miss cycles 2997system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles 2998system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2461668000 # number of ReadReq MSHR uncacheable cycles 2999system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11994000 # number of ReadReq MSHR uncacheable cycles 3000system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3463851500 # number of ReadReq MSHR uncacheable cycles 3001system.l2c.ReadReq_mshr_uncacheable_latency::total 10792034500 # number of ReadReq MSHR uncacheable cycles 3002system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2661815500 # number of WriteReq MSHR uncacheable cycles 3003system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3296062500 # number of WriteReq MSHR uncacheable cycles 3004system.l2c.WriteReq_mshr_uncacheable_latency::total 5957878000 # number of WriteReq MSHR uncacheable cycles 3005system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles 3006system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5123483500 # number of overall MSHR uncacheable cycles 3007system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11994000 # number of overall MSHR uncacheable cycles 3008system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6759914000 # number of overall MSHR uncacheable cycles 3009system.l2c.overall_mshr_uncacheable_latency::total 16749912500 # number of overall MSHR uncacheable cycles 3010system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3011system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3012system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.293165 # mshr miss rate for UpgradeReq accesses 3013system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.311087 # mshr miss rate for UpgradeReq accesses 3014system.l2c.UpgradeReq_mshr_miss_rate::total 0.301488 # mshr miss rate for UpgradeReq accesses 3015system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.282716 # mshr miss rate for SCUpgradeReq accesses 3016system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.255887 # mshr miss rate for SCUpgradeReq accesses 3017system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.269024 # mshr miss rate for SCUpgradeReq accesses 3018system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.765449 # mshr miss rate for ReadExReq accesses 3019system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468669 # mshr miss rate for ReadExReq accesses 3020system.l2c.ReadExReq_mshr_miss_rate::total 0.665609 # mshr miss rate for ReadExReq accesses 3021system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for ReadSharedReq accesses 3022system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for ReadSharedReq accesses 3023system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for ReadSharedReq accesses 3024system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.177657 # mshr miss rate for ReadSharedReq accesses 3025system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for ReadSharedReq accesses 3026system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for ReadSharedReq accesses 3027system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for ReadSharedReq accesses 3028system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for ReadSharedReq accesses 3029system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.151263 # mshr miss rate for ReadSharedReq accesses 3030system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for ReadSharedReq accesses 3031system.l2c.ReadSharedReq_mshr_miss_rate::total 0.210512 # mshr miss rate for ReadSharedReq accesses 3032system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for demand accesses 3033system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for demand accesses 3034system.l2c.demand_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for demand accesses 3035system.l2c.demand_mshr_miss_rate::cpu0.data 0.471251 # mshr miss rate for demand accesses 3036system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for demand accesses 3037system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for demand accesses 3038system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for demand accesses 3039system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for demand accesses 3040system.l2c.demand_mshr_miss_rate::cpu1.data 0.259789 # mshr miss rate for demand accesses 3041system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for demand accesses 3042system.l2c.demand_mshr_miss_rate::total 0.317987 # mshr miss rate for demand accesses 3043system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.189951 # mshr miss rate for overall accesses 3044system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.230486 # mshr miss rate for overall accesses 3045system.l2c.overall_mshr_miss_rate::cpu0.inst 0.104583 # mshr miss rate for overall accesses 3046system.l2c.overall_mshr_miss_rate::cpu0.data 0.471251 # mshr miss rate for overall accesses 3047system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.438396 # mshr miss rate for overall accesses 3048system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222831 # mshr miss rate for overall accesses 3049system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272624 # mshr miss rate for overall accesses 3050system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089001 # mshr miss rate for overall accesses 3051system.l2c.overall_mshr_miss_rate::cpu1.data 0.259789 # mshr miss rate for overall accesses 3052system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.329661 # mshr miss rate for overall accesses 3053system.l2c.overall_mshr_miss_rate::total 0.317987 # mshr miss rate for overall accesses 3054system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73691.983224 # average UpgradeReq mshr miss latency 3055system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73479.812476 # average UpgradeReq mshr miss latency 3056system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73590.304698 # average UpgradeReq mshr miss latency 3057system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76632.527039 # average SCUpgradeReq mshr miss latency 3058system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76541.211558 # average SCUpgradeReq mshr miss latency 3059system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76588.199902 # average SCUpgradeReq mshr miss latency 3060system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122216.111166 # average ReadExReq mshr miss latency 3061system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120930.107708 # average ReadExReq mshr miss latency 3062system.l2c.ReadExReq_avg_mshr_miss_latency::total 121911.489797 # average ReadExReq mshr miss latency 3063system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average ReadSharedReq mshr miss latency 3064system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average ReadSharedReq mshr miss latency 3065system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average ReadSharedReq mshr miss latency 3066system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127327.340689 # average ReadSharedReq mshr miss latency 3067system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average ReadSharedReq mshr miss latency 3068system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average ReadSharedReq mshr miss latency 3069system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average ReadSharedReq mshr miss latency 3070system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average ReadSharedReq mshr miss latency 3071system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128180.440427 # average ReadSharedReq mshr miss latency 3072system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average ReadSharedReq mshr miss latency 3073system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140288.519066 # average ReadSharedReq mshr miss latency 3074system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency 3075system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency 3076system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency 3077system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency 3078system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency 3079system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency 3080system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency 3081system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency 3082system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency 3083system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency 3084system.l2c.demand_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency 3085system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131684.792627 # average overall mshr miss latency 3086system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130341.463415 # average overall mshr miss latency 3087system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124474.954473 # average overall mshr miss latency 3088system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123180.544084 # average overall mshr miss latency 3089system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 152090.552888 # average overall mshr miss latency 3090system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127549.482536 # average overall mshr miss latency 3091system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128807.600950 # average overall mshr miss latency 3092system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124826.785002 # average overall mshr miss latency 3093system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123708.217296 # average overall mshr miss latency 3094system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151199.965093 # average overall mshr miss latency 3095system.l2c.overall_avg_mshr_miss_latency::total 131204.314747 # average overall mshr miss latency 3096system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency 3097system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 147000.358295 # average ReadReq mshr uncacheable latency 3098system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average ReadReq mshr uncacheable latency 3099system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158957.895461 # average ReadReq mshr uncacheable latency 3100system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131977.137651 # average ReadReq mshr uncacheable latency 3101system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148142.002449 # average WriteReq mshr uncacheable latency 3102system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161445.067594 # average WriteReq mshr uncacheable latency 3103system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155217.746978 # average WriteReq mshr uncacheable latency 3104system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency 3105system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147591.274414 # average overall mshr uncacheable latency 3106system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average overall mshr uncacheable latency 3107system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160160.968560 # average overall mshr uncacheable latency 3108system.l2c.overall_avg_mshr_uncacheable_latency::total 139401.382370 # average overall mshr uncacheable latency 3109system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3110system.membus.trans_dist::ReadReq 81772 # Transaction distribution 3111system.membus.trans_dist::ReadResp 730632 # Transaction distribution 3112system.membus.trans_dist::WriteReq 38384 # Transaction distribution 3113system.membus.trans_dist::WriteResp 38384 # Transaction distribution 3114system.membus.trans_dist::WritebackDirty 1075989 # Transaction distribution 3115system.membus.trans_dist::CleanEvict 189758 # Transaction distribution 3116system.membus.trans_dist::UpgradeReq 405662 # Transaction distribution 3117system.membus.trans_dist::SCUpgradeReq 313696 # Transaction distribution 3118system.membus.trans_dist::UpgradeResp 154281 # Transaction distribution 3119system.membus.trans_dist::ReadExReq 640388 # Transaction distribution 3120system.membus.trans_dist::ReadExResp 617827 # Transaction distribution 3121system.membus.trans_dist::ReadSharedReq 648860 # Transaction distribution 3122system.membus.trans_dist::InvalidateReq 106721 # Transaction distribution 3123system.membus.trans_dist::InvalidateResp 106721 # Transaction distribution 3124system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122768 # Packet count per connected master and slave (bytes) 3125system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3126system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25854 # Packet count per connected master and slave (bytes) 3127system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4655021 # Packet count per connected master and slave (bytes) 3128system.membus.pkt_count_system.l2c.mem_side::total 4803735 # Packet count per connected master and slave (bytes) 3129system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342369 # Packet count per connected master and slave (bytes) 3130system.membus.pkt_count_system.iocache.mem_side::total 342369 # Packet count per connected master and slave (bytes) 3131system.membus.pkt_count::total 5146104 # Packet count per connected master and slave (bytes) 3132system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155875 # Cumulative packet size per connected master and slave (bytes) 3133system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3134system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51708 # Cumulative packet size per connected master and slave (bytes) 3135system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142678316 # Cumulative packet size per connected master and slave (bytes) 3136system.membus.pkt_size_system.l2c.mem_side::total 142886103 # Cumulative packet size per connected master and slave (bytes) 3137system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257472 # Cumulative packet size per connected master and slave (bytes) 3138system.membus.pkt_size_system.iocache.mem_side::total 7257472 # Cumulative packet size per connected master and slave (bytes) 3139system.membus.pkt_size::total 150143575 # Cumulative packet size per connected master and slave (bytes) 3140system.membus.snoops 590609 # Total snoops (count) 3141system.membus.snoop_fanout::samples 3503595 # Request fanout histogram 3142system.membus.snoop_fanout::mean 1 # Request fanout histogram 3143system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3144system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3145system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3146system.membus.snoop_fanout::1 3503595 100.00% 100.00% # Request fanout histogram 3147system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3148system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3149system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3150system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3151system.membus.snoop_fanout::total 3503595 # Request fanout histogram 3152system.membus.reqLayer0.occupancy 101306500 # Layer occupancy (ticks) 3153system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3154system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 3155system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3156system.membus.reqLayer2.occupancy 21492499 # Layer occupancy (ticks) 3157system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3158system.membus.reqLayer5.occupancy 7402591959 # Layer occupancy (ticks) 3159system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3160system.membus.respLayer2.occupancy 7154332547 # Layer occupancy (ticks) 3161system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3162system.membus.respLayer3.occupancy 228436684 # Layer occupancy (ticks) 3163system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3164system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3165system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3166system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3167system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3168system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3169system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3170system.realview.ethernet.txBytes 966 # Bytes Transmitted 3171system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3172system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3173system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3174system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3175system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3176system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3177system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3178system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3179system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) 3180system.realview.ethernet.totPackets 3 # Total Packets 3181system.realview.ethernet.totBytes 966 # Total Bytes 3182system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3183system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) 3184system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3185system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3186system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3187system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3188system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3189system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3190system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3191system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3192system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3193system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3194system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3195system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3196system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3197system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3198system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3199system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3200system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3201system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3202system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3203system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3204system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3205system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3206system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3207system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3208system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3209system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3210system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3211system.realview.ethernet.droppedPackets 0 # number of packets dropped 3212system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3213system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3214system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3215system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3216system.toL2Bus.snoop_filter.tot_requests 10356989 # Total number of requests made to the snoop filter. 3217system.toL2Bus.snoop_filter.hit_single_requests 5641244 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3218system.toL2Bus.snoop_filter.hit_multi_requests 1705825 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3219system.toL2Bus.snoop_filter.tot_snoops 115755 # Total number of snoops made to the snoop filter. 3220system.toL2Bus.snoop_filter.hit_single_snoops 104698 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3221system.toL2Bus.snoop_filter.hit_multi_snoops 11057 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3222system.toL2Bus.trans_dist::ReadReq 81774 # Transaction distribution 3223system.toL2Bus.trans_dist::ReadResp 3879147 # Transaction distribution 3224system.toL2Bus.trans_dist::WriteReq 38384 # Transaction distribution 3225system.toL2Bus.trans_dist::WriteResp 38384 # Transaction distribution 3226system.toL2Bus.trans_dist::WritebackDirty 3550378 # Transaction distribution 3227system.toL2Bus.trans_dist::CleanEvict 1245199 # Transaction distribution 3228system.toL2Bus.trans_dist::UpgradeReq 675855 # Transaction distribution 3229system.toL2Bus.trans_dist::SCUpgradeReq 385953 # Transaction distribution 3230system.toL2Bus.trans_dist::UpgradeResp 1061806 # Transaction distribution 3231system.toL2Bus.trans_dist::SCUpgradeFailReq 138 # Transaction distribution 3232system.toL2Bus.trans_dist::UpgradeFailResp 138 # Transaction distribution 3233system.toL2Bus.trans_dist::ReadExReq 1071844 # Transaction distribution 3234system.toL2Bus.trans_dist::ReadExResp 1071844 # Transaction distribution 3235system.toL2Bus.trans_dist::ReadSharedReq 3804622 # Transaction distribution 3236system.toL2Bus.trans_dist::InvalidateReq 106721 # Transaction distribution 3237system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7596632 # Packet count per connected master and slave (bytes) 3238system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6529428 # Packet count per connected master and slave (bytes) 3239system.toL2Bus.pkt_count::total 14126060 # Packet count per connected master and slave (bytes) 3240system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 228502049 # Cumulative packet size per connected master and slave (bytes) 3241system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 185064310 # Cumulative packet size per connected master and slave (bytes) 3242system.toL2Bus.pkt_size::total 413566359 # Cumulative packet size per connected master and slave (bytes) 3243system.toL2Bus.snoops 2887820 # Total snoops (count) 3244system.toL2Bus.snoop_fanout::samples 7482662 # Request fanout histogram 3245system.toL2Bus.snoop_fanout::mean 0.359179 # Request fanout histogram 3246system.toL2Bus.snoop_fanout::stdev 0.482830 # Request fanout histogram 3247system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3248system.toL2Bus.snoop_fanout::0 4806103 64.23% 64.23% # Request fanout histogram 3249system.toL2Bus.snoop_fanout::1 2665502 35.62% 99.85% # Request fanout histogram 3250system.toL2Bus.snoop_fanout::2 11057 0.15% 100.00% # Request fanout histogram 3251system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3252system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3253system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3254system.toL2Bus.snoop_fanout::total 7482662 # Request fanout histogram 3255system.toL2Bus.reqLayer0.occupancy 8118734038 # Layer occupancy (ticks) 3256system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3257system.toL2Bus.snoopLayer0.occupancy 2606433 # Layer occupancy (ticks) 3258system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3259system.toL2Bus.respLayer0.occupancy 4223747952 # Layer occupancy (ticks) 3260system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3261system.toL2Bus.respLayer1.occupancy 3725557524 # Layer occupancy (ticks) 3262system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3263 3264---------- End Simulation Statistics ---------- 3265