stats.txt revision 11201
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311201Sandreas.hansson@arm.comsim_seconds 47.602568 # Number of seconds simulated 411201Sandreas.hansson@arm.comsim_ticks 47602567962500 # Number of ticks simulated 511201Sandreas.hansson@arm.comfinal_tick 47602567962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711201Sandreas.hansson@arm.comhost_inst_rate 587112 # Simulator instruction rate (inst/s) 811201Sandreas.hansson@arm.comhost_op_rate 690746 # Simulator op (including micro ops) rate (op/s) 911201Sandreas.hansson@arm.comhost_tick_rate 32025707663 # Simulator tick rate (ticks/s) 1011201Sandreas.hansson@arm.comhost_mem_usage 784812 # Number of bytes of host memory used 1111201Sandreas.hansson@arm.comhost_seconds 1486.39 # Real time elapsed on the host 1211201Sandreas.hansson@arm.comsim_insts 872675802 # Number of instructions simulated 1311201Sandreas.hansson@arm.comsim_ops 1026715135 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 97216 # Number of bytes read from this memory 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 105280 # Number of bytes read from this memory 1811201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3176436 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 39189384 # Number of bytes read from this memory 2011201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 13261312 # Number of bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 67968 # Number of bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 64704 # Number of bytes read from this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2473528 # Number of bytes read from this memory 2411201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 13920528 # Number of bytes read from this memory 2511201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 8902656 # Number of bytes read from this memory 2611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 417088 # Number of bytes read from this memory 2711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 81676100 # Number of bytes read from this memory 2811201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3176436 # Number of instructions bytes read from this memory 2911201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2473528 # Number of instructions bytes read from this memory 3011201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 5649964 # Number of instructions bytes read from this memory 3111201Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 69006208 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411201Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 69026792 # Number of bytes written to this memory 3511201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1519 # Number of read requests responded to by this memory 3611201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1645 # Number of read requests responded to by this memory 3711201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 90039 # Number of read requests responded to by this memory 3811201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 612347 # Number of read requests responded to by this memory 3911201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 207208 # Number of read requests responded to by this memory 4011201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1062 # Number of read requests responded to by this memory 4111201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 1011 # Number of read requests responded to by this memory 4211201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 38737 # Number of read requests responded to by this memory 4311201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 217521 # Number of read requests responded to by this memory 4411201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 139104 # Number of read requests responded to by this memory 4511201Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6517 # Number of read requests responded to by this memory 4611201Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1316710 # Number of read requests responded to by this memory 4711201Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1078222 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011201Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1080796 # Number of write requests responded to by this memory 5111201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2042 # Total read bandwidth from this memory (bytes/s) 5211201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2212 # Total read bandwidth from this memory (bytes/s) 5311201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 66728 # Total read bandwidth from this memory (bytes/s) 5411201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 823262 # Total read bandwidth from this memory (bytes/s) 5511201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 278584 # Total read bandwidth from this memory (bytes/s) 5611201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 1428 # Total read bandwidth from this memory (bytes/s) 5711201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) 5811201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 51962 # Total read bandwidth from this memory (bytes/s) 5911201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 292432 # Total read bandwidth from this memory (bytes/s) 6011201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 187020 # Total read bandwidth from this memory (bytes/s) 6111201Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8762 # Total read bandwidth from this memory (bytes/s) 6211201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1715792 # Total read bandwidth from this memory (bytes/s) 6311201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 66728 # Instruction read bandwidth from this memory (bytes/s) 6411201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 51962 # Instruction read bandwidth from this memory (bytes/s) 6511201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 118690 # Instruction read bandwidth from this memory (bytes/s) 6611201Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1449632 # Write bandwidth from this memory (bytes/s) 6711201Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s) 6810585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911201Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1450064 # Write bandwidth from this memory (bytes/s) 7011201Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1449632 # Total bandwidth to/from this memory (bytes/s) 7111201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2042 # Total bandwidth to/from this memory (bytes/s) 7211201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2212 # Total bandwidth to/from this memory (bytes/s) 7311201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 66728 # Total bandwidth to/from this memory (bytes/s) 7411201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 823694 # Total bandwidth to/from this memory (bytes/s) 7511201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 278584 # Total bandwidth to/from this memory (bytes/s) 7611201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 1428 # Total bandwidth to/from this memory (bytes/s) 7711201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) 7811201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 51962 # Total bandwidth to/from this memory (bytes/s) 7911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 292432 # Total bandwidth to/from this memory (bytes/s) 8011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 187020 # Total bandwidth to/from this memory (bytes/s) 8111201Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8762 # Total bandwidth to/from this memory (bytes/s) 8211201Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3165856 # Total bandwidth to/from this memory (bytes/s) 8311201Sandreas.hansson@arm.comsystem.physmem.readReqs 1316710 # Number of read requests accepted 8411201Sandreas.hansson@arm.comsystem.physmem.writeReqs 1080796 # Number of write requests accepted 8511201Sandreas.hansson@arm.comsystem.physmem.readBursts 1316710 # Number of DRAM read bursts, including those serviced by the write queue 8611201Sandreas.hansson@arm.comsystem.physmem.writeBursts 1080796 # Number of DRAM write bursts, including those merged in the write queue 8711201Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 84239104 # Total number of bytes read from DRAM 8811201Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 30336 # Total number of bytes read from write queue 8911201Sandreas.hansson@arm.comsystem.physmem.bytesWritten 69025088 # Total number of bytes written to DRAM 9011201Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 81676100 # Total read bytes from the system interface side 9111201Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 69026792 # Total written bytes from the system interface side 9211201Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 474 # Number of DRAM read bursts serviced by the write queue 9311201Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one 9411201Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 461546 # Number of requests that are neither read nor write 9511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 74138 # Per bank write bursts 9611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 82827 # Per bank write bursts 9711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 74957 # Per bank write bursts 9811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 82122 # Per bank write bursts 9911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 83077 # Per bank write bursts 10011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 87558 # Per bank write bursts 10111201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 81167 # Per bank write bursts 10211201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 84127 # Per bank write bursts 10311201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 76730 # Per bank write bursts 10411201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 122410 # Per bank write bursts 10511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 70954 # Per bank write bursts 10611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 80684 # Per bank write bursts 10711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 75912 # Per bank write bursts 10811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 81292 # Per bank write bursts 10911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 78761 # Per bank write bursts 11011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 79520 # Per bank write bursts 11111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 61777 # Per bank write bursts 11211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 69166 # Per bank write bursts 11311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 64147 # Per bank write bursts 11411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 68304 # Per bank write bursts 11511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 69323 # Per bank write bursts 11611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 73404 # Per bank write bursts 11711201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 67894 # Per bank write bursts 11811201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 70420 # Per bank write bursts 11911201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 65275 # Per bank write bursts 12011201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 69986 # Per bank write bursts 12111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 62072 # Per bank write bursts 12211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 68038 # Per bank write bursts 12311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 64002 # Per bank write bursts 12411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 68951 # Per bank write bursts 12511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 67347 # Per bank write bursts 12611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 68411 # Per bank write bursts 12710515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811201Sandreas.hansson@arm.comsystem.physmem.numWrRetry 25 # Number of times write queue was full causing retry 12911201Sandreas.hansson@arm.comsystem.physmem.totGap 47602564597000 # Total gap between requests 13010515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611201Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1273485 # Read request sizes (log2) 13710515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311201Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1078222 # Write request sizes (log2) 14411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 1098528 # What read queue length does an incoming req see 14511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 69154 # What read queue length does an incoming req see 14611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 30759 # What read queue length does an incoming req see 14711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 26336 # What read queue length does an incoming req see 14811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 22457 # What read queue length does an incoming req see 14911201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 19787 # What read queue length does an incoming req see 15011201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 17170 # What read queue length does an incoming req see 15111201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 15034 # What read queue length does an incoming req see 15211201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 11894 # What read queue length does an incoming req see 15311201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1995 # What read queue length does an incoming req see 15411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 874 # What read queue length does an incoming req see 15511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 575 # What read queue length does an incoming req see 15611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see 15711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 323 # What read queue length does an incoming req see 15811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 240 # What read queue length does an incoming req see 15911201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 218 # What read queue length does an incoming req see 16011201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 164 # What read queue length does an incoming req see 16111201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 144 # What read queue length does an incoming req see 16211201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see 16311201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see 16411138Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 16511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 16611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16810628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 18244 # What write queue length does an incoming req see 19211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 20496 # What write queue length does an incoming req see 19311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 46518 # What write queue length does an incoming req see 19411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 53470 # What write queue length does an incoming req see 19511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 57648 # What write queue length does an incoming req see 19611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 60710 # What write queue length does an incoming req see 19711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 64016 # What write queue length does an incoming req see 19811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 65226 # What write queue length does an incoming req see 19911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 67393 # What write queue length does an incoming req see 20011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 67733 # What write queue length does an incoming req see 20111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 70106 # What write queue length does an incoming req see 20211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 73801 # What write queue length does an incoming req see 20311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 68996 # What write queue length does an incoming req see 20411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 68981 # What write queue length does an incoming req see 20511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 71721 # What write queue length does an incoming req see 20611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 66784 # What write queue length does an incoming req see 20711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 63773 # What write queue length does an incoming req see 20811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 62218 # What write queue length does an incoming req see 20911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 1690 # What write queue length does an incoming req see 21011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 1098 # What write queue length does an incoming req see 21111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 827 # What write queue length does an incoming req see 21211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 666 # What write queue length does an incoming req see 21311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 614 # What write queue length does an incoming req see 21411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 508 # What write queue length does an incoming req see 21511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 438 # What write queue length does an incoming req see 21611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 398 # What write queue length does an incoming req see 21711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 362 # What write queue length does an incoming req see 21811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 382 # What write queue length does an incoming req see 21911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 307 # What write queue length does an incoming req see 22011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see 22111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 298 # What write queue length does an incoming req see 22211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 278 # What write queue length does an incoming req see 22311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see 22411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see 22511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 321 # What write queue length does an incoming req see 22611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see 22711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see 22811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 138 # What write queue length does an incoming req see 22911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 165 # What write queue length does an incoming req see 23011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see 23111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see 23211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 99 # What write queue length does an incoming req see 23311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see 23411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 78 # What write queue length does an incoming req see 23511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see 23611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 84 # What write queue length does an incoming req see 23711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see 23811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see 23911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see 24011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 845861 # Bytes accessed per row activation 24111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 181.192513 # Bytes accessed per row activation 24211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 111.718720 # Bytes accessed per row activation 24311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 240.356894 # Bytes accessed per row activation 24411201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 524023 61.95% 61.95% # Bytes accessed per row activation 24511201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 157589 18.63% 80.58% # Bytes accessed per row activation 24611201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 52244 6.18% 86.76% # Bytes accessed per row activation 24711201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 27763 3.28% 90.04% # Bytes accessed per row activation 24811201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 18582 2.20% 92.24% # Bytes accessed per row activation 24911201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 11693 1.38% 93.62% # Bytes accessed per row activation 25011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 8942 1.06% 94.68% # Bytes accessed per row activation 25111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 9176 1.08% 95.76% # Bytes accessed per row activation 25211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 35849 4.24% 100.00% # Bytes accessed per row activation 25311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 845861 # Bytes accessed per row activation 25411201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 60416 # Reads before turning the bus around for writes 25511201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 21.786182 # Reads before turning the bus around for writes 25611201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 329.918437 # Reads before turning the bus around for writes 25711201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-4095 60413 100.00% 100.00% # Reads before turning the bus around for writes 25811201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 25910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 26010892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 26111201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 60416 # Reads before turning the bus around for writes 26211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 60416 # Writes before turning the bus around for reads 26311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.851513 # Writes before turning the bus around for reads 26411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.268088 # Writes before turning the bus around for reads 26511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 7.277078 # Writes before turning the bus around for reads 26611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 56734 93.91% 93.91% # Writes before turning the bus around for reads 26711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 1553 2.57% 96.48% # Writes before turning the bus around for reads 26811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 255 0.42% 96.90% # Writes before turning the bus around for reads 26911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 285 0.47% 97.37% # Writes before turning the bus around for reads 27011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 70 0.12% 97.49% # Writes before turning the bus around for reads 27111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 285 0.47% 97.96% # Writes before turning the bus around for reads 27211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 159 0.26% 98.22% # Writes before turning the bus around for reads 27311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 94 0.16% 98.38% # Writes before turning the bus around for reads 27411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 78 0.13% 98.51% # Writes before turning the bus around for reads 27511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 106 0.18% 98.68% # Writes before turning the bus around for reads 27611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 41 0.07% 98.75% # Writes before turning the bus around for reads 27711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 61 0.10% 98.85% # Writes before turning the bus around for reads 27811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 428 0.71% 99.56% # Writes before turning the bus around for reads 27911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 38 0.06% 99.62% # Writes before turning the bus around for reads 28011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 49 0.08% 99.70% # Writes before turning the bus around for reads 28111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 117 0.19% 99.90% # Writes before turning the bus around for reads 28211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 11 0.02% 99.91% # Writes before turning the bus around for reads 28311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads 28411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads 28511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads 28611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads 28711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads 28811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads 28911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads 29011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 24 0.04% 99.97% # Writes before turning the bus around for reads 29111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads 29211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads 29311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads 29411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 3 0.00% 99.99% # Writes before turning the bus around for reads 29511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 5 0.01% 100.00% # Writes before turning the bus around for reads 29611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads 29711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads 29811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 60416 # Writes before turning the bus around for reads 29911201Sandreas.hansson@arm.comsystem.physmem.totQLat 28673044871 # Total ticks spent queuing 30011201Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 53352469871 # Total ticks spent from burst creation until serviced by the DRAM 30111201Sandreas.hansson@arm.comsystem.physmem.totBusLat 6581180000 # Total ticks spent in databus transfers 30211201Sandreas.hansson@arm.comsystem.physmem.avgQLat 21784.12 # Average queueing delay per DRAM burst 30310515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 30411201Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 40534.12 # Average memory access latency per DRAM burst 30511201Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.77 # Average DRAM read bandwidth in MiByte/s 30611201Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s 30711201Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s 30811201Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s 30910515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31010827Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31111201Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 31210892Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31311201Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing 31411201Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing 31511201Sandreas.hansson@arm.comsystem.physmem.readRowHits 1054044 # Number of row buffer hits during reads 31611201Sandreas.hansson@arm.comsystem.physmem.writeRowHits 494841 # Number of row buffer hits during writes 31711201Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads 31811201Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 45.88 # Row buffer hit rate for writes 31911201Sandreas.hansson@arm.comsystem.physmem.avgGap 19855034.61 # Average gap between requests 32011201Sandreas.hansson@arm.comsystem.physmem.pageHitRate 64.68 # Row buffer hit rate, read and write combined 32111201Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 3265088400 # Energy for activate commands per rank (pJ) 32211201Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 1781546250 # Energy for precharge commands per rank (pJ) 32311201Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 5069789400 # Energy for read commands per rank (pJ) 32411201Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 3527867520 # Energy for write commands per rank (pJ) 32511201Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ) 32611201Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1219382745750 # Energy for active background per rank (pJ) 32711201Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27491903982750 # Energy for precharge background per rank (pJ) 32811201Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31834099035270 # Total energy per rank (pJ) 32911201Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.747581 # Core power per rank (mW) 33011201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45734675361714 # Time in different power states 33111201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1589554200000 # Time in different power states 33210628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33311201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 278338023286 # Time in different power states 33410628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 33511201Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3129537600 # Energy for activate commands per rank (pJ) 33611201Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 1707585000 # Energy for precharge commands per rank (pJ) 33711201Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 5196804600 # Energy for read commands per rank (pJ) 33811201Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 3460818960 # Energy for write commands per rank (pJ) 33911201Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ) 34011201Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1215349697925 # Energy for active background per rank (pJ) 34111201Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27495441752250 # Energy for precharge background per rank (pJ) 34211201Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31833454211535 # Total energy per rank (pJ) 34311201Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.734035 # Core power per rank (mW) 34411201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45740562014248 # Time in different power states 34511201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1589554200000 # Time in different power states 34610628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 34711201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 272450963752 # Time in different power states 34810628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 34910515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 35010515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35110515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 35210515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35310515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 35410515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 35510515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 35610515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 35710515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 35810515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 35910515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 36010515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36110515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 36210515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 36310515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 36410515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 36510515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 36610515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 36710515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 36810515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 36910515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 37010515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 37110515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37210515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 37410515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 37510535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 37610535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 37710535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 37811201Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 37911201Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 38011201Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1674 # Number of DMA write transactions. 38110515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 38210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 38910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 39410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 39510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 39610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 39710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 111926 # Table walker walks requested 41211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 111926 # Table walker walks initiated with long descriptors 41311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10169 # Level at which table walker walks with long descriptors terminate 41411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 86471 # Level at which table walker walks with long descriptors terminate 41511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 18 # Table walks squashed before starting 41611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 111908 # Table walker wait (enqueue to first request) latency 41711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.232334 # Table walker wait (enqueue to first request) latency 41811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 77.721788 # Table walker wait (enqueue to first request) latency 41911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-2047 111907 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 42111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 111908 # Table walker wait (enqueue to first request) latency 42211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 96658 # Table walker service (enqueue to completion) latency 42311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 23040.705374 # Table walker service (enqueue to completion) latency 42411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 21274.900589 # Table walker service (enqueue to completion) latency 42511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 18509.319790 # Table walker service (enqueue to completion) latency 42611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 95612 98.92% 98.92% # Table walker service (enqueue to completion) latency 42711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 152 0.16% 99.08% # Table walker service (enqueue to completion) latency 42811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 763 0.79% 99.86% # Table walker service (enqueue to completion) latency 42911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 18 0.02% 99.88% # Table walker service (enqueue to completion) latency 43011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.92% # Table walker service (enqueue to completion) latency 43111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 23 0.02% 99.95% # Table walker service (enqueue to completion) latency 43211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 37 0.04% 99.99% # Table walker service (enqueue to completion) latency 43311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 43411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 43511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 43611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 43711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 96658 # Table walker service (enqueue to completion) latency 43811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 444719432 # Table walker pending requests distribution 43911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::mean -3.785405 # Table walker pending requests distribution 44011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 2128162704 478.54% 478.54% # Table walker pending requests distribution 44111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::1 -1683443272 -378.54% 100.00% # Table walker pending requests distribution 44211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 444719432 # Table walker pending requests distribution 44311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 86471 89.48% 89.48% # Table walker page sizes translated 44411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10169 10.52% 100.00% # Table walker page sizes translated 44511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 96640 # Table walker page sizes translated 44611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111926 # Table walker requests started/completed, data/inst 44710628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 44811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111926 # Table walker requests started/completed, data/inst 44911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96640 # Table walker requests started/completed, data/inst 45010628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96640 # Table walker requests started/completed, data/inst 45211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 208566 # Table walker requests started/completed, data/inst 45310535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 45410535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 45511201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 87929647 # DTB read hits 45611201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 85158 # DTB read misses 45711201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 79744109 # DTB write hits 45811201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 26768 # DTB write misses 45910535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 46010535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46111201Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID 46211201Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 46311201Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 37859 # Number of entries that have been flushed from TLB 46410535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 46511201Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 3884 # Number of TLB faults due to prefetch 46610535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 46711201Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 10087 # Number of TLB faults due to permissions restrictions 46811201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 88014805 # DTB read accesses 46911201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 79770877 # DTB write accesses 47010535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47111201Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 167673756 # DTB hits 47211201Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 111926 # DTB misses 47311201Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 167785682 # DTB accesses 47410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 47510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 47610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 47810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 48410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 48510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 48710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 49310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 49410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 49510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 49610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 49710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 49810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 49910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 50311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 61252 # Table walker walks requested 50411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 61252 # Table walker walks initiated with long descriptors 50511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 842 # Level at which table walker walks with long descriptors terminate 50611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 54849 # Level at which table walker walks with long descriptors terminate 50711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 61252 # Table walker wait (enqueue to first request) latency 50811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 61252 100.00% 100.00% # Table walker wait (enqueue to first request) latency 50911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 61252 # Table walker wait (enqueue to first request) latency 51011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 55691 # Table walker service (enqueue to completion) latency 51111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 26308.021045 # Table walker service (enqueue to completion) latency 51211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 23499.981275 # Table walker service (enqueue to completion) latency 51311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 25689.449100 # Table walker service (enqueue to completion) latency 51411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 54619 98.08% 98.08% # Table walker service (enqueue to completion) latency 51511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 42 0.08% 98.15% # Table walker service (enqueue to completion) latency 51611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 884 1.59% 99.74% # Table walker service (enqueue to completion) latency 51711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 24 0.04% 99.78% # Table walker service (enqueue to completion) latency 51811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.09% 99.87% # Table walker service (enqueue to completion) latency 51911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.90% # Table walker service (enqueue to completion) latency 52011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 35 0.06% 99.96% # Table walker service (enqueue to completion) latency 52111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 52211138Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 52311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 52411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 52511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 55691 # Table walker service (enqueue to completion) latency 52611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution 52711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution 52811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution 52911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 54849 98.49% 98.49% # Table walker page sizes translated 53011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 842 1.51% 100.00% # Table walker page sizes translated 53111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 55691 # Table walker page sizes translated 53210628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 53311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61252 # Table walker requests started/completed, data/inst 53411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 61252 # Table walker requests started/completed, data/inst 53510628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 53611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55691 # Table walker requests started/completed, data/inst 53711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 55691 # Table walker requests started/completed, data/inst 53811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 116943 # Table walker requests started/completed, data/inst 53911201Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 467202921 # ITB inst hits 54011201Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 61252 # ITB inst misses 54110535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 54210535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 54310535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 54410535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 54510535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 54610535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 54711201Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID 54811201Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 54911201Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 27100 # Number of entries that have been flushed from TLB 55010535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55110535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55210535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 55310535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 55410535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 55510535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 55611201Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 467264173 # ITB inst accesses 55711201Sandreas.hansson@arm.comsystem.cpu0.itb.hits 467202921 # DTB hits 55811201Sandreas.hansson@arm.comsystem.cpu0.itb.misses 61252 # DTB misses 55911201Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 467264173 # DTB accesses 56011201Sandreas.hansson@arm.comsystem.cpu0.numCycles 95205135902 # number of cpu cycles simulated 56110535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 56210535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 56311167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 56411201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 5123 # number of quiesce instructions executed 56511201Sandreas.hansson@arm.comsystem.cpu0.committedInsts 466948479 # Number of instructions committed 56611201Sandreas.hansson@arm.comsystem.cpu0.committedOps 548389991 # Number of ops (including micro ops) committed 56711201Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 504092161 # Number of integer alu accesses 56811201Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 464416 # Number of float alu accesses 56911201Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 27983491 # number of times a function call or return occured 57011201Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 70438282 # number of instructions that are conditional controls 57111201Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 504092161 # number of integer instructions 57211201Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 464416 # number of float instructions 57311201Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 728885661 # number of times the integer registers were read 57411201Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 399652952 # number of times the integer registers were written 57511201Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 772857 # number of times the floating registers were read 57611201Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 344936 # number of times the floating registers were written 57711201Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 120908457 # number of times the CC registers were read 57811201Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 120465396 # number of times the CC registers were written 57911201Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 167663327 # number of memory refs 58011201Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 87924608 # Number of load instructions 58111201Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 79738719 # Number of store instructions 58211201Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93943889977.646729 # Number of idle cycles 58311201Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 1261245924.353277 # Number of busy cycles 58411201Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.013248 # Percentage of non-idle cycles 58511201Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.986752 # Percentage of idle cycles 58611201Sandreas.hansson@arm.comsystem.cpu0.Branches 104008564 # Number of branches fetched 58711201Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 58811201Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 379698158 69.20% 69.20% # Class of executed instruction 58911201Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1212773 0.22% 69.42% # Class of executed instruction 59011201Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 66852 0.01% 69.43% # Class of executed instruction 59111201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction 59211201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction 59311201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction 59411201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction 59511201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction 59611201Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction 59711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction 59811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction 59911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction 60011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction 60111201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction 60211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction 60311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction 60411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction 60511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction 60611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction 60711201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction 60811201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction 60911201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction 61011201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction 61111201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction 61211201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction 61311201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 46447 0.01% 69.44% # Class of executed instruction 61411201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction 61511201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction 61611201Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction 61711201Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 87924608 16.02% 85.47% # Class of executed instruction 61811201Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 79738719 14.53% 100.00% # Class of executed instruction 61910535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 62010535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 62111201Sandreas.hansson@arm.comsystem.cpu0.op_class::total 548687557 # Class of executed instruction 62211201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5767473 # number of replacements 62311201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 506.102777 # Cycle average of tags in use 62411201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 161665939 # Total number of references to valid blocks. 62511201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5767985 # Sample count of references to valid blocks. 62611201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 28.028148 # Average number of references to valid blocks. 62711201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. 62811201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 506.102777 # Average occupied blocks per requestor 62911201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.988482 # Average percentage of cache occupancy 63011201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.988482 # Average percentage of cache occupancy 63110892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 63211201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 63311201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 63411201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 63510892Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 63611201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 341141490 # Number of tag accesses 63711201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 341141490 # Number of data accesses 63811201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 81909684 # number of ReadReq hits 63911201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 81909684 # number of ReadReq hits 64011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 75364450 # number of WriteReq hits 64111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 75364450 # number of WriteReq hits 64211201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 195602 # number of SoftPFReq hits 64311201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 195602 # number of SoftPFReq hits 64411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 139312 # number of WriteLineReq hits 64511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 139312 # number of WriteLineReq hits 64611201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1827663 # number of LoadLockedReq hits 64711201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1827663 # number of LoadLockedReq hits 64811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798607 # number of StoreCondReq hits 64911201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1798607 # number of StoreCondReq hits 65011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 157274134 # number of demand (read+write) hits 65111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 157274134 # number of demand (read+write) hits 65211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 157469736 # number of overall hits 65311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 157469736 # number of overall hits 65411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3156555 # number of ReadReq misses 65511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3156555 # number of ReadReq misses 65611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1440320 # number of WriteReq misses 65711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1440320 # number of WriteReq misses 65811201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 651795 # number of SoftPFReq misses 65911201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 651795 # number of SoftPFReq misses 66011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 776738 # number of WriteLineReq misses 66111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 776738 # number of WriteLineReq misses 66211201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172749 # number of LoadLockedReq misses 66311201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 172749 # number of LoadLockedReq misses 66411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 200464 # number of StoreCondReq misses 66511201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 200464 # number of StoreCondReq misses 66611201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4596875 # number of demand (read+write) misses 66711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4596875 # number of demand (read+write) misses 66811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5248670 # number of overall misses 66911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5248670 # number of overall misses 67011201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52100226500 # number of ReadReq miss cycles 67111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 52100226500 # number of ReadReq miss cycles 67211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36687284500 # number of WriteReq miss cycles 67311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 36687284500 # number of WriteReq miss cycles 67411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65915448000 # number of WriteLineReq miss cycles 67511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 65915448000 # number of WriteLineReq miss cycles 67611201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2830376000 # number of LoadLockedReq miss cycles 67711201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2830376000 # number of LoadLockedReq miss cycles 67811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5792176500 # number of StoreCondReq miss cycles 67911201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 5792176500 # number of StoreCondReq miss cycles 68011201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4797000 # number of StoreCondFailReq miss cycles 68111201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 4797000 # number of StoreCondFailReq miss cycles 68211201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 88787511000 # number of demand (read+write) miss cycles 68311201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 88787511000 # number of demand (read+write) miss cycles 68411201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 88787511000 # number of overall miss cycles 68511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 88787511000 # number of overall miss cycles 68611201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 85066239 # number of ReadReq accesses(hits+misses) 68711201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 85066239 # number of ReadReq accesses(hits+misses) 68811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 76804770 # number of WriteReq accesses(hits+misses) 68911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 76804770 # number of WriteReq accesses(hits+misses) 69011201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 847397 # number of SoftPFReq accesses(hits+misses) 69111201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 847397 # number of SoftPFReq accesses(hits+misses) 69211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 916050 # number of WriteLineReq accesses(hits+misses) 69311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 916050 # number of WriteLineReq accesses(hits+misses) 69411201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2000412 # number of LoadLockedReq accesses(hits+misses) 69511201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2000412 # number of LoadLockedReq accesses(hits+misses) 69611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1999071 # number of StoreCondReq accesses(hits+misses) 69711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1999071 # number of StoreCondReq accesses(hits+misses) 69811201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 161871009 # number of demand (read+write) accesses 69911201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 161871009 # number of demand (read+write) accesses 70011201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 162718406 # number of overall (read+write) accesses 70111201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 162718406 # number of overall (read+write) accesses 70211201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037107 # miss rate for ReadReq accesses 70311201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.037107 # miss rate for ReadReq accesses 70411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018753 # miss rate for WriteReq accesses 70511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018753 # miss rate for WriteReq accesses 70611201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769173 # miss rate for SoftPFReq accesses 70711201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.769173 # miss rate for SoftPFReq accesses 70811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.847921 # miss rate for WriteLineReq accesses 70911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.847921 # miss rate for WriteLineReq accesses 71011201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086357 # miss rate for LoadLockedReq accesses 71111201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086357 # miss rate for LoadLockedReq accesses 71211201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100279 # miss rate for StoreCondReq accesses 71311201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.100279 # miss rate for StoreCondReq accesses 71411201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.028398 # miss rate for demand accesses 71511201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.028398 # miss rate for demand accesses 71611201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032256 # miss rate for overall accesses 71711201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.032256 # miss rate for overall accesses 71811201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16505.407477 # average ReadReq miss latency 71911201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 16505.407477 # average ReadReq miss latency 72011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25471.620543 # average WriteReq miss latency 72111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 25471.620543 # average WriteReq miss latency 72211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 84861.881355 # average WriteLineReq miss latency 72311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 84861.881355 # average WriteLineReq miss latency 72411201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16384.326393 # average LoadLockedReq miss latency 72511201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16384.326393 # average LoadLockedReq miss latency 72611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28893.848771 # average StoreCondReq miss latency 72711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28893.848771 # average StoreCondReq miss latency 72810535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 72910535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 73011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19314.754262 # average overall miss latency 73111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 19314.754262 # average overall miss latency 73211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16916.192293 # average overall miss latency 73311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 16916.192293 # average overall miss latency 73410535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 73510535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 73610535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 73710535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 73810535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 73910535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74010585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 74110535SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 74211201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 5767473 # number of writebacks 74311201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 5767473 # number of writebacks 74411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 27282 # number of ReadReq MSHR hits 74511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 27282 # number of ReadReq MSHR hits 74611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21266 # number of WriteReq MSHR hits 74711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21266 # number of WriteReq MSHR hits 74811201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44626 # number of LoadLockedReq MSHR hits 74911201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 44626 # number of LoadLockedReq MSHR hits 75011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 48548 # number of demand (read+write) MSHR hits 75111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 48548 # number of demand (read+write) MSHR hits 75211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 48548 # number of overall MSHR hits 75311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 48548 # number of overall MSHR hits 75411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3129273 # number of ReadReq MSHR misses 75511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3129273 # number of ReadReq MSHR misses 75611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1419054 # number of WriteReq MSHR misses 75711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1419054 # number of WriteReq MSHR misses 75811201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 650511 # number of SoftPFReq MSHR misses 75911201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 650511 # number of SoftPFReq MSHR misses 76011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 776738 # number of WriteLineReq MSHR misses 76111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 776738 # number of WriteLineReq MSHR misses 76211201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128123 # number of LoadLockedReq MSHR misses 76311201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 128123 # number of LoadLockedReq MSHR misses 76411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200464 # number of StoreCondReq MSHR misses 76511201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 200464 # number of StoreCondReq MSHR misses 76611201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4548327 # number of demand (read+write) MSHR misses 76711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4548327 # number of demand (read+write) MSHR misses 76811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5198838 # number of overall MSHR misses 76911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5198838 # number of overall MSHR misses 77011201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15619 # number of ReadReq MSHR uncacheable 77111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 15619 # number of ReadReq MSHR uncacheable 77211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16479 # number of WriteReq MSHR uncacheable 77311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 16479 # number of WriteReq MSHR uncacheable 77411201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32098 # number of overall MSHR uncacheable misses 77511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 32098 # number of overall MSHR uncacheable misses 77611201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47104061500 # number of ReadReq MSHR miss cycles 77711201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 47104061500 # number of ReadReq MSHR miss cycles 77811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34681725000 # number of WriteReq MSHR miss cycles 77911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 34681725000 # number of WriteReq MSHR miss cycles 78011201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15920895000 # number of SoftPFReq MSHR miss cycles 78111201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15920895000 # number of SoftPFReq MSHR miss cycles 78211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 65138711000 # number of WriteLineReq MSHR miss cycles 78311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 65138711000 # number of WriteLineReq MSHR miss cycles 78411201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1795303000 # number of LoadLockedReq MSHR miss cycles 78511201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1795303000 # number of LoadLockedReq MSHR miss cycles 78611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5591766500 # number of StoreCondReq MSHR miss cycles 78711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5591766500 # number of StoreCondReq MSHR miss cycles 78811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4743000 # number of StoreCondFailReq MSHR miss cycles 78911201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4743000 # number of StoreCondFailReq MSHR miss cycles 79011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 81785786500 # number of demand (read+write) MSHR miss cycles 79111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 81785786500 # number of demand (read+write) MSHR miss cycles 79211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97706681500 # number of overall MSHR miss cycles 79311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 97706681500 # number of overall MSHR miss cycles 79411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2690935500 # number of ReadReq MSHR uncacheable cycles 79511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2690935500 # number of ReadReq MSHR uncacheable cycles 79611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2795849000 # number of WriteReq MSHR uncacheable cycles 79711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2795849000 # number of WriteReq MSHR uncacheable cycles 79811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5486784500 # number of overall MSHR uncacheable cycles 79911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 5486784500 # number of overall MSHR uncacheable cycles 80011201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036786 # mshr miss rate for ReadReq accesses 80111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036786 # mshr miss rate for ReadReq accesses 80211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018476 # mshr miss rate for WriteReq accesses 80311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018476 # mshr miss rate for WriteReq accesses 80411201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767658 # mshr miss rate for SoftPFReq accesses 80511201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767658 # mshr miss rate for SoftPFReq accesses 80611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.847921 # mshr miss rate for WriteLineReq accesses 80711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.847921 # mshr miss rate for WriteLineReq accesses 80811201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064048 # mshr miss rate for LoadLockedReq accesses 80911201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064048 # mshr miss rate for LoadLockedReq accesses 81011201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100279 # mshr miss rate for StoreCondReq accesses 81111201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100279 # mshr miss rate for StoreCondReq accesses 81211201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028098 # mshr miss rate for demand accesses 81311201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.028098 # mshr miss rate for demand accesses 81411201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031950 # mshr miss rate for overall accesses 81511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031950 # mshr miss rate for overall accesses 81611201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15052.717197 # average ReadReq mshr miss latency 81711201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15052.717197 # average ReadReq mshr miss latency 81811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24440.031880 # average WriteReq mshr miss latency 81911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24440.031880 # average WriteReq mshr miss latency 82011201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24474.443937 # average SoftPFReq mshr miss latency 82111201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24474.443937 # average SoftPFReq mshr miss latency 82211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 83861.882643 # average WriteLineReq mshr miss latency 82311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 83861.882643 # average WriteLineReq mshr miss latency 82411201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14012.339705 # average LoadLockedReq mshr miss latency 82511201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14012.339705 # average LoadLockedReq mshr miss latency 82611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27894.118146 # average StoreCondReq mshr miss latency 82711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27894.118146 # average StoreCondReq mshr miss latency 82810535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 82910535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 83011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17981.509795 # average overall mshr miss latency 83111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 17981.509795 # average overall mshr miss latency 83211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18793.946166 # average overall mshr miss latency 83311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 18793.946166 # average overall mshr miss latency 83411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172286.029835 # average ReadReq mshr uncacheable latency 83511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172286.029835 # average ReadReq mshr uncacheable latency 83611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169661.326537 # average WriteReq mshr uncacheable latency 83711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169661.326537 # average WriteReq mshr uncacheable latency 83811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170938.516418 # average overall mshr uncacheable latency 83911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170938.516418 # average overall mshr uncacheable latency 84010535SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 84111201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5175196 # number of replacements 84211201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.827248 # Cycle average of tags in use 84311201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 462027213 # Total number of references to valid blocks. 84411201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5175708 # Sample count of references to valid blocks. 84511201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 89.268408 # Average number of references to valid blocks. 84611201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 59167640000 # Cycle when the warmup percentage was hit. 84711201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827248 # Average occupied blocks per requestor 84811201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999663 # Average percentage of cache occupancy 84911201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy 85010535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 85111201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 85211201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id 85311201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id 85411201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 85510535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 85611201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 939581550 # Number of tag accesses 85711201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 939581550 # Number of data accesses 85811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 462027213 # number of ReadReq hits 85911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 462027213 # number of ReadReq hits 86011201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 462027213 # number of demand (read+write) hits 86111201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 462027213 # number of demand (read+write) hits 86211201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 462027213 # number of overall hits 86311201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 462027213 # number of overall hits 86411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5175708 # number of ReadReq misses 86511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5175708 # number of ReadReq misses 86611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5175708 # number of demand (read+write) misses 86711201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 5175708 # number of demand (read+write) misses 86811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5175708 # number of overall misses 86911201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5175708 # number of overall misses 87011201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 57336545500 # number of ReadReq miss cycles 87111201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 57336545500 # number of ReadReq miss cycles 87211201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 57336545500 # number of demand (read+write) miss cycles 87311201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 57336545500 # number of demand (read+write) miss cycles 87411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 57336545500 # number of overall miss cycles 87511201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 57336545500 # number of overall miss cycles 87611201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 467202921 # number of ReadReq accesses(hits+misses) 87711201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 467202921 # number of ReadReq accesses(hits+misses) 87811201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 467202921 # number of demand (read+write) accesses 87911201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 467202921 # number of demand (read+write) accesses 88011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 467202921 # number of overall (read+write) accesses 88111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 467202921 # number of overall (read+write) accesses 88211201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011078 # miss rate for ReadReq accesses 88311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011078 # miss rate for ReadReq accesses 88411201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011078 # miss rate for demand accesses 88511201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011078 # miss rate for demand accesses 88611201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011078 # miss rate for overall accesses 88711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011078 # miss rate for overall accesses 88811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11078.010100 # average ReadReq miss latency 88911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 11078.010100 # average ReadReq miss latency 89011201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11078.010100 # average overall miss latency 89111201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 11078.010100 # average overall miss latency 89211201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11078.010100 # average overall miss latency 89311201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 11078.010100 # average overall miss latency 89410535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89510535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89610535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 89710535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 89810535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 89910535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90010535SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 90110535SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 90211201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 5175196 # number of writebacks 90311201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 5175196 # number of writebacks 90411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5175708 # number of ReadReq MSHR misses 90511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 5175708 # number of ReadReq MSHR misses 90611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 5175708 # number of demand (read+write) MSHR misses 90711201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 5175708 # number of demand (read+write) MSHR misses 90811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 5175708 # number of overall MSHR misses 90911201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 5175708 # number of overall MSHR misses 91010827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 91110827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 91210827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 91310827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 91411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 54748691500 # number of ReadReq MSHR miss cycles 91511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 54748691500 # number of ReadReq MSHR miss cycles 91611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 54748691500 # number of demand (read+write) MSHR miss cycles 91711201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 54748691500 # number of demand (read+write) MSHR miss cycles 91811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 54748691500 # number of overall MSHR miss cycles 91911201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 54748691500 # number of overall MSHR miss cycles 92011201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles 92111201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles 92211201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles 92311201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles 92411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for ReadReq accesses 92511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011078 # mshr miss rate for ReadReq accesses 92611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for demand accesses 92711201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.011078 # mshr miss rate for demand accesses 92811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for overall accesses 92911201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.011078 # mshr miss rate for overall accesses 93011201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average ReadReq mshr miss latency 93111201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10578.010100 # average ReadReq mshr miss latency 93211201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency 93311201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency 93411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency 93511201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency 93611201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency 93711201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency 93811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency 93911201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency 94010535SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 94111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7857654 # number of hwpf issued 94211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7857701 # number of prefetch candidates identified 94311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue 94410628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 94510628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 94611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1019611 # number of prefetches not generated due to page crossing 94711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2391891 # number of replacements 94811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16167.019190 # Cycle average of tags in use 94911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 15476667 # Total number of references to valid blocks. 95011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2407580 # Sample count of references to valid blocks. 95111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 6.428309 # Average number of references to valid blocks. 95211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 8764179000 # Cycle when the warmup percentage was hit. 95311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15278.445219 # Average occupied blocks per requestor 95411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.058428 # Average occupied blocks per requestor 95511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.612606 # Average occupied blocks per requestor 95611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 747.902937 # Average occupied blocks per requestor 95711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.932522 # Average percentage of cache occupancy 95811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003727 # Average percentage of cache occupancy 95911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004859 # Average percentage of cache occupancy 96011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.045648 # Average percentage of cache occupancy 96111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.986757 # Average percentage of cache occupancy 96211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1309 # Occupied blocks per task id 96311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 96411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14303 # Occupied blocks per task id 96511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 143 # Occupied blocks per task id 96611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 161 # Occupied blocks per task id 96711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id 96811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 356 # Occupied blocks per task id 96911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 28 # Occupied blocks per task id 97011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id 97111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 97211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 97311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 827 # Occupied blocks per task id 97411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4392 # Occupied blocks per task id 97511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6793 # Occupied blocks per task id 97611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2165 # Occupied blocks per task id 97711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079895 # Percentage of cache occupancy per task id 97811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 97911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.872986 # Percentage of cache occupancy per task id 98011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 371635811 # Number of tag accesses 98111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 371635811 # Number of data accesses 98211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 264720 # number of ReadReq hits 98311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157843 # number of ReadReq hits 98411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 422563 # number of ReadReq hits 98511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3807067 # number of WritebackDirty hits 98611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3807067 # number of WritebackDirty hits 98711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 7134877 # number of WritebackClean hits 98811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 7134877 # number of WritebackClean hits 98911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 457 # number of UpgradeReq hits 99011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 457 # number of UpgradeReq hits 99111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 928109 # number of ReadExReq hits 99211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 928109 # number of ReadExReq hits 99311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4693228 # number of ReadCleanReq hits 99411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4693228 # number of ReadCleanReq hits 99511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2960524 # number of ReadSharedReq hits 99611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2960524 # number of ReadSharedReq hits 99711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 208597 # number of InvalidateReq hits 99811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 208597 # number of InvalidateReq hits 99911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 264720 # number of demand (read+write) hits 100011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 157843 # number of demand (read+write) hits 100111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4693228 # number of demand (read+write) hits 100211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3888633 # number of demand (read+write) hits 100311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 9004424 # number of demand (read+write) hits 100411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 264720 # number of overall hits 100511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 157843 # number of overall hits 100611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4693228 # number of overall hits 100711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3888633 # number of overall hits 100811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 9004424 # number of overall hits 100911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10067 # number of ReadReq misses 101011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8203 # number of ReadReq misses 101111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 18270 # number of ReadReq misses 101211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 246628 # number of UpgradeReq misses 101311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 246628 # number of UpgradeReq misses 101411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200453 # number of SCUpgradeReq misses 101511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 200453 # number of SCUpgradeReq misses 101611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses 101711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses 101811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 262909 # number of ReadExReq misses 101911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 262909 # number of ReadExReq misses 102011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 482480 # number of ReadCleanReq misses 102111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 482480 # number of ReadCleanReq misses 102211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 947383 # number of ReadSharedReq misses 102311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 947383 # number of ReadSharedReq misses 102411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 566022 # number of InvalidateReq misses 102511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 566022 # number of InvalidateReq misses 102611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10067 # number of demand (read+write) misses 102711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8203 # number of demand (read+write) misses 102811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 482480 # number of demand (read+write) misses 102911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1210292 # number of demand (read+write) misses 103011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1711042 # number of demand (read+write) misses 103111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10067 # number of overall misses 103211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8203 # number of overall misses 103311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 482480 # number of overall misses 103411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1210292 # number of overall misses 103511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1711042 # number of overall misses 103611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 425309500 # number of ReadReq miss cycles 103711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 392962000 # number of ReadReq miss cycles 103811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 818271500 # number of ReadReq miss cycles 103911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3546049000 # number of UpgradeReq miss cycles 104011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 3546049000 # number of UpgradeReq miss cycles 104111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2066053000 # number of SCUpgradeReq miss cycles 104211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2066053000 # number of SCUpgradeReq miss cycles 104311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4661500 # number of SCUpgradeFailReq miss cycles 104411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4661500 # number of SCUpgradeFailReq miss cycles 104511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16748515499 # number of ReadExReq miss cycles 104611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 16748515499 # number of ReadExReq miss cycles 104711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 18800277000 # number of ReadCleanReq miss cycles 104811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 18800277000 # number of ReadCleanReq miss cycles 104911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 39672427000 # number of ReadSharedReq miss cycles 105011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 39672427000 # number of ReadSharedReq miss cycles 105111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62566205500 # number of InvalidateReq miss cycles 105211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 62566205500 # number of InvalidateReq miss cycles 105311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 425309500 # number of demand (read+write) miss cycles 105411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 392962000 # number of demand (read+write) miss cycles 105511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 18800277000 # number of demand (read+write) miss cycles 105611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 56420942499 # number of demand (read+write) miss cycles 105711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 76039490999 # number of demand (read+write) miss cycles 105811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 425309500 # number of overall miss cycles 105911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 392962000 # number of overall miss cycles 106011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 18800277000 # number of overall miss cycles 106111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 56420942499 # number of overall miss cycles 106211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 76039490999 # number of overall miss cycles 106311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 274787 # number of ReadReq accesses(hits+misses) 106411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 166046 # number of ReadReq accesses(hits+misses) 106511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 440833 # number of ReadReq accesses(hits+misses) 106611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3807067 # number of WritebackDirty accesses(hits+misses) 106711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3807067 # number of WritebackDirty accesses(hits+misses) 106811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 7134877 # number of WritebackClean accesses(hits+misses) 106911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 7134877 # number of WritebackClean accesses(hits+misses) 107011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 247085 # number of UpgradeReq accesses(hits+misses) 107111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 247085 # number of UpgradeReq accesses(hits+misses) 107211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200453 # number of SCUpgradeReq accesses(hits+misses) 107311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 200453 # number of SCUpgradeReq accesses(hits+misses) 107411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) 107511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) 107611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1191018 # number of ReadExReq accesses(hits+misses) 107711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1191018 # number of ReadExReq accesses(hits+misses) 107811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5175708 # number of ReadCleanReq accesses(hits+misses) 107911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5175708 # number of ReadCleanReq accesses(hits+misses) 108011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3907907 # number of ReadSharedReq accesses(hits+misses) 108111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3907907 # number of ReadSharedReq accesses(hits+misses) 108211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 774619 # number of InvalidateReq accesses(hits+misses) 108311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 774619 # number of InvalidateReq accesses(hits+misses) 108411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 274787 # number of demand (read+write) accesses 108511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 166046 # number of demand (read+write) accesses 108611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5175708 # number of demand (read+write) accesses 108711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5098925 # number of demand (read+write) accesses 108811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 10715466 # number of demand (read+write) accesses 108911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 274787 # number of overall (read+write) accesses 109011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 166046 # number of overall (read+write) accesses 109111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5175708 # number of overall (read+write) accesses 109211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5098925 # number of overall (read+write) accesses 109311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 10715466 # number of overall (read+write) accesses 109411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036636 # miss rate for ReadReq accesses 109511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049402 # miss rate for ReadReq accesses 109611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.041444 # miss rate for ReadReq accesses 109711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998150 # miss rate for UpgradeReq accesses 109811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998150 # miss rate for UpgradeReq accesses 109911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 110011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 110110535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 110210535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 110311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.220743 # miss rate for ReadExReq accesses 110411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.220743 # miss rate for ReadExReq accesses 110511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.093220 # miss rate for ReadCleanReq accesses 110611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.093220 # miss rate for ReadCleanReq accesses 110711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242427 # miss rate for ReadSharedReq accesses 110811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242427 # miss rate for ReadSharedReq accesses 110911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730710 # miss rate for InvalidateReq accesses 111011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730710 # miss rate for InvalidateReq accesses 111111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036636 # miss rate for demand accesses 111211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049402 # miss rate for demand accesses 111311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.093220 # miss rate for demand accesses 111411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237362 # miss rate for demand accesses 111511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.159680 # miss rate for demand accesses 111611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036636 # miss rate for overall accesses 111711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049402 # miss rate for overall accesses 111811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.093220 # miss rate for overall accesses 111911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237362 # miss rate for overall accesses 112011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.159680 # miss rate for overall accesses 112111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42247.889143 # average ReadReq miss latency 112211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47904.669024 # average ReadReq miss latency 112311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 44787.712096 # average ReadReq miss latency 112411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14378.128193 # average UpgradeReq miss latency 112511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14378.128193 # average UpgradeReq miss latency 112611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10306.919827 # average SCUpgradeReq miss latency 112711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10306.919827 # average SCUpgradeReq miss latency 112811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 423772.727273 # average SCUpgradeFailReq miss latency 112911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 423772.727273 # average SCUpgradeFailReq miss latency 113011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63704.610717 # average ReadExReq miss latency 113111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63704.610717 # average ReadExReq miss latency 113211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38965.919831 # average ReadCleanReq miss latency 113311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38965.919831 # average ReadCleanReq miss latency 113411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41875.806300 # average ReadSharedReq miss latency 113511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41875.806300 # average ReadSharedReq miss latency 113611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 110536.702637 # average InvalidateReq miss latency 113711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 110536.702637 # average InvalidateReq miss latency 113811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42247.889143 # average overall miss latency 113911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47904.669024 # average overall miss latency 114011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38965.919831 # average overall miss latency 114111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46617.628224 # average overall miss latency 114211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 44440.458504 # average overall miss latency 114311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42247.889143 # average overall miss latency 114411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47904.669024 # average overall miss latency 114511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38965.919831 # average overall miss latency 114611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46617.628224 # average overall miss latency 114711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 44440.458504 # average overall miss latency 114810628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 114910535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 115010628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 115110535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 115210628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 115310535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 115410535SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 115510535SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 115611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1521426 # number of writebacks 115711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1521426 # number of writebacks 115811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5411 # number of ReadExReq MSHR hits 115911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 5411 # number of ReadExReq MSHR hits 116011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 533 # number of ReadSharedReq MSHR hits 116111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 533 # number of ReadSharedReq MSHR hits 116211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 5944 # number of demand (read+write) MSHR hits 116311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 5944 # number of demand (read+write) MSHR hits 116411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 5944 # number of overall MSHR hits 116511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 5944 # number of overall MSHR hits 116611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10067 # number of ReadReq MSHR misses 116711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8203 # number of ReadReq MSHR misses 116811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 18270 # number of ReadReq MSHR misses 116911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 721686 # number of HardPFReq MSHR misses 117011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 721686 # number of HardPFReq MSHR misses 117111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 246628 # number of UpgradeReq MSHR misses 117211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 246628 # number of UpgradeReq MSHR misses 117311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 200453 # number of SCUpgradeReq MSHR misses 117411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 200453 # number of SCUpgradeReq MSHR misses 117511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses 117611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses 117711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 257498 # number of ReadExReq MSHR misses 117811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 257498 # number of ReadExReq MSHR misses 117911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 482480 # number of ReadCleanReq MSHR misses 118011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 482480 # number of ReadCleanReq MSHR misses 118111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 946850 # number of ReadSharedReq MSHR misses 118211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 946850 # number of ReadSharedReq MSHR misses 118311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 566022 # number of InvalidateReq MSHR misses 118411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 566022 # number of InvalidateReq MSHR misses 118511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10067 # number of demand (read+write) MSHR misses 118611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8203 # number of demand (read+write) MSHR misses 118711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 482480 # number of demand (read+write) MSHR misses 118811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1204348 # number of demand (read+write) MSHR misses 118911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1705098 # number of demand (read+write) MSHR misses 119011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10067 # number of overall MSHR misses 119111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8203 # number of overall MSHR misses 119211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 482480 # number of overall MSHR misses 119311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1204348 # number of overall MSHR misses 119411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 721686 # number of overall MSHR misses 119511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2426784 # number of overall MSHR misses 119610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 119711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15619 # number of ReadReq MSHR uncacheable 119811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 58744 # number of ReadReq MSHR uncacheable 119911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16479 # number of WriteReq MSHR uncacheable 120011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16479 # number of WriteReq MSHR uncacheable 120110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 120211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 32098 # number of overall MSHR uncacheable misses 120311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 75223 # number of overall MSHR uncacheable misses 120411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 364907500 # number of ReadReq MSHR miss cycles 120511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 343744000 # number of ReadReq MSHR miss cycles 120611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 708651500 # number of ReadReq MSHR miss cycles 120711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38668799279 # number of HardPFReq MSHR miss cycles 120811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38668799279 # number of HardPFReq MSHR miss cycles 120911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7913903000 # number of UpgradeReq MSHR miss cycles 121011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7913903000 # number of UpgradeReq MSHR miss cycles 121111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4087252500 # number of SCUpgradeReq MSHR miss cycles 121211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4087252500 # number of SCUpgradeReq MSHR miss cycles 121311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4337500 # number of SCUpgradeFailReq MSHR miss cycles 121411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4337500 # number of SCUpgradeFailReq MSHR miss cycles 121511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14600636999 # number of ReadExReq MSHR miss cycles 121611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14600636999 # number of ReadExReq MSHR miss cycles 121711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 15905397000 # number of ReadCleanReq MSHR miss cycles 121811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 15905397000 # number of ReadCleanReq MSHR miss cycles 121911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 33944380000 # number of ReadSharedReq MSHR miss cycles 122011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 33944380000 # number of ReadSharedReq MSHR miss cycles 122111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 59170079500 # number of InvalidateReq MSHR miss cycles 122211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 59170079500 # number of InvalidateReq MSHR miss cycles 122311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 364907500 # number of demand (read+write) MSHR miss cycles 122411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 343744000 # number of demand (read+write) MSHR miss cycles 122511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15905397000 # number of demand (read+write) MSHR miss cycles 122611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 48545016999 # number of demand (read+write) MSHR miss cycles 122711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 65159065499 # number of demand (read+write) MSHR miss cycles 122811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 364907500 # number of overall MSHR miss cycles 122911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 343744000 # number of overall MSHR miss cycles 123011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15905397000 # number of overall MSHR miss cycles 123111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 48545016999 # number of overall MSHR miss cycles 123211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38668799279 # number of overall MSHR miss cycles 123311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 103827864778 # number of overall MSHR miss cycles 123411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles 123511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2565627500 # number of ReadReq MSHR uncacheable cycles 123611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8196399000 # number of ReadReq MSHR uncacheable cycles 123711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2671857000 # number of WriteReq MSHR uncacheable cycles 123811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2671857000 # number of WriteReq MSHR uncacheable cycles 123911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles 124011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5237484500 # number of overall MSHR uncacheable cycles 124111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10868256000 # number of overall MSHR uncacheable cycles 124211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036636 # mshr miss rate for ReadReq accesses 124311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049402 # mshr miss rate for ReadReq accesses 124411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.041444 # mshr miss rate for ReadReq accesses 124510535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 124610535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 124711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998150 # mshr miss rate for UpgradeReq accesses 124811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998150 # mshr miss rate for UpgradeReq accesses 124911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 125011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 125110535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 125210535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 125311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216200 # mshr miss rate for ReadExReq accesses 125411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216200 # mshr miss rate for ReadExReq accesses 125511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.093220 # mshr miss rate for ReadCleanReq accesses 125611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093220 # mshr miss rate for ReadCleanReq accesses 125711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242291 # mshr miss rate for ReadSharedReq accesses 125811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242291 # mshr miss rate for ReadSharedReq accesses 125911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.730710 # mshr miss rate for InvalidateReq accesses 126011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.730710 # mshr miss rate for InvalidateReq accesses 126111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036636 # mshr miss rate for demand accesses 126211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049402 # mshr miss rate for demand accesses 126311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.093220 # mshr miss rate for demand accesses 126411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.236196 # mshr miss rate for demand accesses 126511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.159125 # mshr miss rate for demand accesses 126611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036636 # mshr miss rate for overall accesses 126711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049402 # mshr miss rate for overall accesses 126811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.093220 # mshr miss rate for overall accesses 126911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.236196 # mshr miss rate for overall accesses 127010535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 127111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.226475 # mshr miss rate for overall accesses 127211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average ReadReq mshr miss latency 127311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average ReadReq mshr miss latency 127411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38787.712096 # average ReadReq mshr miss latency 127511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average HardPFReq mshr miss latency 127611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53581.196364 # average HardPFReq mshr miss latency 127711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32088.420617 # average UpgradeReq mshr miss latency 127811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32088.420617 # average UpgradeReq mshr miss latency 127911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.078971 # average SCUpgradeReq mshr miss latency 128011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20390.078971 # average SCUpgradeReq mshr miss latency 128111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 394318.181818 # average SCUpgradeFailReq mshr miss latency 128211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 394318.181818 # average SCUpgradeFailReq mshr miss latency 128311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56701.943312 # average ReadExReq mshr miss latency 128411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56701.943312 # average ReadExReq mshr miss latency 128511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average ReadCleanReq mshr miss latency 128611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32965.919831 # average ReadCleanReq mshr miss latency 128711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35849.796694 # average ReadSharedReq mshr miss latency 128811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35849.796694 # average ReadSharedReq mshr miss latency 128911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 104536.713237 # average InvalidateReq mshr miss latency 129011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 104536.713237 # average InvalidateReq mshr miss latency 129111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency 129211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency 129311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency 129411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency 129511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38214.264224 # average overall mshr miss latency 129611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency 129711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency 129811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency 129911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency 130011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average overall mshr miss latency 130111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42784.139329 # average overall mshr miss latency 130211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency 130311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164263.237083 # average ReadReq mshr uncacheable latency 130411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139527.424077 # average ReadReq mshr uncacheable latency 130511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162137.083561 # average WriteReq mshr uncacheable latency 130611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162137.083561 # average WriteReq mshr uncacheable latency 130711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency 130811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 163171.677363 # average overall mshr uncacheable latency 130911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144480.491339 # average overall mshr uncacheable latency 131010535SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 131111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 22685684 # Total number of requests made to the snoop filter. 131211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 11636633 # Number of requests hitting in the snoop filter with a single holder of the requested data. 131311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 725 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 131411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 1868386 # Total number of snoops made to the snoop filter. 131511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1868205 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 131611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 181 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 131711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 566458 # Transaction distribution 131811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 9760546 # Transaction distribution 131911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 16479 # Transaction distribution 132011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 16479 # Transaction distribution 132111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5331858 # Transaction distribution 132211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 7134877 # Transaction distribution 132311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 2347214 # Transaction distribution 132411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 886122 # Transaction distribution 132511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 438453 # Transaction distribution 132611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361903 # Transaction distribution 132711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 524601 # Transaction distribution 132811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution 132911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution 133011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1264261 # Transaction distribution 133111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1203854 # Transaction distribution 133211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5175708 # Transaction distribution 133311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4797612 # Transaction distribution 133411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 779730 # Transaction distribution 133511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 774618 # Transaction distribution 133611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15612584 # Packet count per connected master and slave (bytes) 133711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18673898 # Packet count per connected master and slave (bytes) 133811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 348811 # Packet count per connected master and slave (bytes) 133911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 599734 # Packet count per connected master and slave (bytes) 134011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 35235027 # Packet count per connected master and slave (bytes) 134111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662612564 # Cumulative packet size per connected master and slave (bytes) 134211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 703409885 # Cumulative packet size per connected master and slave (bytes) 134311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328368 # Cumulative packet size per connected master and slave (bytes) 134411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2198296 # Cumulative packet size per connected master and slave (bytes) 134511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1369549113 # Cumulative packet size per connected master and slave (bytes) 134611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 6346450 # Total snoops (count) 134711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 18158816 # Request fanout histogram 134811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.116500 # Request fanout histogram 134911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.320855 # Request fanout histogram 135010535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 135111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 16043491 88.35% 88.35% # Request fanout histogram 135211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2115144 11.65% 100.00% # Request fanout histogram 135311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 181 0.00% 100.00% # Request fanout histogram 135410535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 135511138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 135610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 135711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 18158816 # Request fanout histogram 135811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 22462112497 # Layer occupancy (ticks) 135910535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 136011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 223807892 # Layer occupancy (ticks) 136110535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 136211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7806687000 # Layer occupancy (ticks) 136310535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 136411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8283648998 # Layer occupancy (ticks) 136510535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 136611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 182765499 # Layer occupancy (ticks) 136710535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 136811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 324947000 # Layer occupancy (ticks) 136910535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 137010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 137110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 137210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 137310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 137410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 137710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 137810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 137910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 138010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 138110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 138210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 138310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 138410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 138510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 138610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 138710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 138910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 139010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 139110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 139210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 139310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 139410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 139510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 139610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 139710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 139810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 139911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 92112 # Table walker walks requested 140011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 92112 # Table walker walks initiated with long descriptors 140111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7185 # Level at which table walker walks with long descriptors terminate 140211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 70441 # Level at which table walker walks with long descriptors terminate 140311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting 140411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 92107 # Table walker wait (enqueue to first request) latency 140511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.086856 # Table walker wait (enqueue to first request) latency 140611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 26.359895 # Table walker wait (enqueue to first request) latency 140711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-511 92106 100.00% 100.00% # Table walker wait (enqueue to first request) latency 140811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 140911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 92107 # Table walker wait (enqueue to first request) latency 141011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 77631 # Table walker service (enqueue to completion) latency 141111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 22794.154397 # Table walker service (enqueue to completion) latency 141211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 21108.718713 # Table walker service (enqueue to completion) latency 141311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 17037.529740 # Table walker service (enqueue to completion) latency 141411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 76846 98.99% 98.99% # Table walker service (enqueue to completion) latency 141511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 174 0.22% 99.21% # Table walker service (enqueue to completion) latency 141611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 527 0.68% 99.89% # Table walker service (enqueue to completion) latency 141711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.91% # Table walker service (enqueue to completion) latency 141811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.95% # Table walker service (enqueue to completion) latency 141911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.96% # Table walker service (enqueue to completion) latency 142011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.02% 99.99% # Table walker service (enqueue to completion) latency 142111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 142211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 142310944Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 142411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 77631 # Table walker service (enqueue to completion) latency 142511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -5456316576 # Table walker pending requests distribution 142611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::mean 0.616394 # Table walker pending requests distribution 142711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::stdev 0.486264 # Table walker pending requests distribution 142811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -2093077220 38.36% 38.36% # Table walker pending requests distribution 142911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::1 -3363239356 61.64% 100.00% # Table walker pending requests distribution 143011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -5456316576 # Table walker pending requests distribution 143111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 70442 90.74% 90.74% # Table walker page sizes translated 143211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 7185 9.26% 100.00% # Table walker page sizes translated 143311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 77627 # Table walker page sizes translated 143411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92112 # Table walker requests started/completed, data/inst 143510628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 143611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92112 # Table walker requests started/completed, data/inst 143711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77627 # Table walker requests started/completed, data/inst 143810628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 143911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77627 # Table walker requests started/completed, data/inst 144011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 169739 # Table walker requests started/completed, data/inst 144110535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 144210535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 144311201Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 76812549 # DTB read hits 144411201Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 67403 # DTB read misses 144511201Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 69811450 # DTB write hits 144611201Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 24709 # DTB write misses 144710535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 144810535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 144911201Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID 145011201Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 145111201Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 34729 # Number of entries that have been flushed from TLB 145210535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 145311201Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 4304 # Number of TLB faults due to prefetch 145410535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 145511201Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 9295 # Number of TLB faults due to permissions restrictions 145611201Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 76879952 # DTB read accesses 145711201Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 69836159 # DTB write accesses 145810535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 145911201Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 146623999 # DTB hits 146011201Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 92112 # DTB misses 146111201Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 146716111 # DTB accesses 146210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 146310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 146410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 146510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 146610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 146710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 146810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 146910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 147010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 147110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 147210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 147310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 147410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 147510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 147610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 147710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 147810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 147910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 148010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 148110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 148210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 148310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 148410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 148510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 148610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 148710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 148810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 148910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 149010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 149111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 54749 # Table walker walks requested 149211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 54749 # Table walker walks initiated with long descriptors 149311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 360 # Level at which table walker walks with long descriptors terminate 149411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate 149511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 54749 # Table walker wait (enqueue to first request) latency 149611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 54749 100.00% 100.00% # Table walker wait (enqueue to first request) latency 149711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 54749 # Table walker wait (enqueue to first request) latency 149811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 49571 # Table walker service (enqueue to completion) latency 149911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 25509.592302 # Table walker service (enqueue to completion) latency 150011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 23251.815503 # Table walker service (enqueue to completion) latency 150111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 21686.807401 # Table walker service (enqueue to completion) latency 150211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 48865 98.58% 98.58% # Table walker service (enqueue to completion) latency 150311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 34 0.07% 98.64% # Table walker service (enqueue to completion) latency 150411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 581 1.17% 99.82% # Table walker service (enqueue to completion) latency 150511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 14 0.03% 99.84% # Table walker service (enqueue to completion) latency 150611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 29 0.06% 99.90% # Table walker service (enqueue to completion) latency 150711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.94% # Table walker service (enqueue to completion) latency 150811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 25 0.05% 99.99% # Table walker service (enqueue to completion) latency 150911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 151011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 151111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 151211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 49571 # Table walker service (enqueue to completion) latency 151311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -2103779220 # Table walker pending requests distribution 151411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -2103779220 100.00% 100.00% # Table walker pending requests distribution 151511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -2103779220 # Table walker pending requests distribution 151611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 49211 99.27% 99.27% # Table walker page sizes translated 151711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 360 0.73% 100.00% # Table walker page sizes translated 151811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 49571 # Table walker page sizes translated 151910628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 152011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54749 # Table walker requests started/completed, data/inst 152111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 54749 # Table walker requests started/completed, data/inst 152210628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 152311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49571 # Table walker requests started/completed, data/inst 152411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 49571 # Table walker requests started/completed, data/inst 152511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 104320 # Table walker requests started/completed, data/inst 152611201Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 406021553 # ITB inst hits 152711201Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 54749 # ITB inst misses 152810535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 152910535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 153010535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 153110535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 153210535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 153310535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 153411201Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID 153511201Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 153611201Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 24319 # Number of entries that have been flushed from TLB 153710535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 153810535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153910535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154010535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 154110535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 154210535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 154311201Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 406076302 # ITB inst accesses 154411201Sandreas.hansson@arm.comsystem.cpu1.itb.hits 406021553 # DTB hits 154511201Sandreas.hansson@arm.comsystem.cpu1.itb.misses 54749 # DTB misses 154611201Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 406076302 # DTB accesses 154711201Sandreas.hansson@arm.comsystem.cpu1.numCycles 95205135925 # number of cpu cycles simulated 154810535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 154910535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 155011167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 155111201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 14029 # number of quiesce instructions executed 155211201Sandreas.hansson@arm.comsystem.cpu1.committedInsts 405727323 # Number of instructions committed 155311201Sandreas.hansson@arm.comsystem.cpu1.committedOps 478325144 # Number of ops (including micro ops) committed 155411201Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 439907771 # Number of integer alu accesses 155511201Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 446670 # Number of float alu accesses 155611201Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 24605699 # number of times a function call or return occured 155711201Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 61596178 # number of instructions that are conditional controls 155811201Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 439907771 # number of integer instructions 155911201Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 446670 # number of float instructions 156011201Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 637924838 # number of times the integer registers were read 156111201Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 348926241 # number of times the integer registers were written 156211201Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 708486 # number of times the floating registers were read 156311201Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 403472 # number of times the floating registers were written 156411201Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 104772444 # number of times the CC registers were read 156511201Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 104573998 # number of times the CC registers were written 156611201Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 146614371 # number of memory refs 156711201Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 76808885 # Number of load instructions 156811201Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 69805486 # Number of store instructions 156911201Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 94195407146.248016 # Number of idle cycles 157011201Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 1009728778.751979 # Number of busy cycles 157111201Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.010606 # Percentage of non-idle cycles 157211201Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.989394 # Percentage of idle cycles 157311201Sandreas.hansson@arm.comsystem.cpu1.Branches 90553045 # Number of branches fetched 157411201Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 157511201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 330876771 69.13% 69.13% # Class of executed instruction 157611201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 1002715 0.21% 69.34% # Class of executed instruction 157711201Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 57816 0.01% 69.35% # Class of executed instruction 157811201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction 157911201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction 158011201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction 158111201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction 158211201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction 158311201Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction 158411201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction 158511201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction 158611201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction 158711201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction 158811201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction 158911201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction 159011201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction 159111201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction 159211201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction 159311201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction 159411201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction 159511201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction 159611201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction 159711201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction 159811201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction 159911201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction 160011201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 67767 0.01% 69.37% # Class of executed instruction 160111201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.37% # Class of executed instruction 160211201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.37% # Class of executed instruction 160311201Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.37% # Class of executed instruction 160411201Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 76808885 16.05% 85.42% # Class of executed instruction 160511201Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 69805486 14.58% 100.00% # Class of executed instruction 160610535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 160710535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 160811201Sandreas.hansson@arm.comsystem.cpu1.op_class::total 478619483 # Class of executed instruction 160911201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 4731492 # number of replacements 161011201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 440.215275 # Cycle average of tags in use 161111201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 141682703 # Total number of references to valid blocks. 161211201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 4732003 # Sample count of references to valid blocks. 161311201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 29.941381 # Average number of references to valid blocks. 161411201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8408412782000 # Cycle when the warmup percentage was hit. 161511201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 440.215275 # Average occupied blocks per requestor 161611201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.859795 # Average percentage of cache occupancy 161711201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.859795 # Average percentage of cache occupancy 161811201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 161911201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 162011201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id 162111201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 162211201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 162311201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 297963795 # Number of tag accesses 162411201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 297963795 # Number of data accesses 162511201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 71617652 # number of ReadReq hits 162611201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 71617652 # number of ReadReq hits 162711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 66171444 # number of WriteReq hits 162811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 66171444 # number of WriteReq hits 162911201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 174206 # number of SoftPFReq hits 163011201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 174206 # number of SoftPFReq hits 163111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 185116 # number of WriteLineReq hits 163211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 185116 # number of WriteLineReq hits 163311201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1590024 # number of LoadLockedReq hits 163411201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1590024 # number of LoadLockedReq hits 163511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1548743 # number of StoreCondReq hits 163611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1548743 # number of StoreCondReq hits 163711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 137789096 # number of demand (read+write) hits 163811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 137789096 # number of demand (read+write) hits 163911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 137963302 # number of overall hits 164011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 137963302 # number of overall hits 164111201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 2694357 # number of ReadReq misses 164211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 2694357 # number of ReadReq misses 164311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1213090 # number of WriteReq misses 164411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1213090 # number of WriteReq misses 164511201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 558664 # number of SoftPFReq misses 164611201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 558664 # number of SoftPFReq misses 164711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 466794 # number of WriteLineReq misses 164811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 466794 # number of WriteLineReq misses 164911201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 154053 # number of LoadLockedReq misses 165011201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 154053 # number of LoadLockedReq misses 165111201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 194127 # number of StoreCondReq misses 165211201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 194127 # number of StoreCondReq misses 165311201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 3907447 # number of demand (read+write) misses 165411201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 3907447 # number of demand (read+write) misses 165511201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 4466111 # number of overall misses 165611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 4466111 # number of overall misses 165711201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40157954500 # number of ReadReq miss cycles 165811201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 40157954500 # number of ReadReq miss cycles 165911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 28157091500 # number of WriteReq miss cycles 166011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 28157091500 # number of WriteReq miss cycles 166111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20750751000 # number of WriteLineReq miss cycles 166211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 20750751000 # number of WriteLineReq miss cycles 166311201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2380134500 # number of LoadLockedReq miss cycles 166411201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2380134500 # number of LoadLockedReq miss cycles 166511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5345117000 # number of StoreCondReq miss cycles 166611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 5345117000 # number of StoreCondReq miss cycles 166711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6929500 # number of StoreCondFailReq miss cycles 166811201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 6929500 # number of StoreCondFailReq miss cycles 166911201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 68315046000 # number of demand (read+write) miss cycles 167011201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 68315046000 # number of demand (read+write) miss cycles 167111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 68315046000 # number of overall miss cycles 167211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 68315046000 # number of overall miss cycles 167311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 74312009 # number of ReadReq accesses(hits+misses) 167411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 74312009 # number of ReadReq accesses(hits+misses) 167511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 67384534 # number of WriteReq accesses(hits+misses) 167611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 67384534 # number of WriteReq accesses(hits+misses) 167711201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 732870 # number of SoftPFReq accesses(hits+misses) 167811201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 732870 # number of SoftPFReq accesses(hits+misses) 167911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 651910 # number of WriteLineReq accesses(hits+misses) 168011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 651910 # number of WriteLineReq accesses(hits+misses) 168111201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1744077 # number of LoadLockedReq accesses(hits+misses) 168211201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1744077 # number of LoadLockedReq accesses(hits+misses) 168311201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1742870 # number of StoreCondReq accesses(hits+misses) 168411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1742870 # number of StoreCondReq accesses(hits+misses) 168511201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 141696543 # number of demand (read+write) accesses 168611201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 141696543 # number of demand (read+write) accesses 168711201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 142429413 # number of overall (read+write) accesses 168811201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 142429413 # number of overall (read+write) accesses 168911201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036257 # miss rate for ReadReq accesses 169011201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.036257 # miss rate for ReadReq accesses 169111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018002 # miss rate for WriteReq accesses 169211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018002 # miss rate for WriteReq accesses 169311201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.762296 # miss rate for SoftPFReq accesses 169411201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.762296 # miss rate for SoftPFReq accesses 169511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.716041 # miss rate for WriteLineReq accesses 169611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.716041 # miss rate for WriteLineReq accesses 169711201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088329 # miss rate for LoadLockedReq accesses 169811201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088329 # miss rate for LoadLockedReq accesses 169911201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111384 # miss rate for StoreCondReq accesses 170011201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.111384 # miss rate for StoreCondReq accesses 170111201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.027576 # miss rate for demand accesses 170211201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.027576 # miss rate for demand accesses 170311201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.031357 # miss rate for overall accesses 170411201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.031357 # miss rate for overall accesses 170511201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14904.466817 # average ReadReq miss latency 170611201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14904.466817 # average ReadReq miss latency 170711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23211.049057 # average WriteReq miss latency 170811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 23211.049057 # average WriteReq miss latency 170911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 44453.765473 # average WriteLineReq miss latency 171011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 44453.765473 # average WriteLineReq miss latency 171111201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15450.101588 # average LoadLockedReq miss latency 171211201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15450.101588 # average LoadLockedReq miss latency 171311201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27534.124568 # average StoreCondReq miss latency 171411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27534.124568 # average StoreCondReq miss latency 171510535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 171610535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 171711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17483.294335 # average overall miss latency 171811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 17483.294335 # average overall miss latency 171911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.316191 # average overall miss latency 172011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15296.316191 # average overall miss latency 172110535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172210535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 172310535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 172410535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 172510535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 172610535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 172710585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 172810535SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 172911201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 4731492 # number of writebacks 173011201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 4731492 # number of writebacks 173111201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13909 # number of ReadReq MSHR hits 173211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 13909 # number of ReadReq MSHR hits 173311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 323 # number of WriteReq MSHR hits 173411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 323 # number of WriteReq MSHR hits 173511201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44168 # number of LoadLockedReq MSHR hits 173611201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 44168 # number of LoadLockedReq MSHR hits 173711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 14232 # number of demand (read+write) MSHR hits 173811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 14232 # number of demand (read+write) MSHR hits 173911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 14232 # number of overall MSHR hits 174011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 14232 # number of overall MSHR hits 174111201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2680448 # number of ReadReq MSHR misses 174211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 2680448 # number of ReadReq MSHR misses 174311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1212767 # number of WriteReq MSHR misses 174411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1212767 # number of WriteReq MSHR misses 174511201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 558664 # number of SoftPFReq MSHR misses 174611201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 558664 # number of SoftPFReq MSHR misses 174711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466794 # number of WriteLineReq MSHR misses 174811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 466794 # number of WriteLineReq MSHR misses 174911201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109885 # number of LoadLockedReq MSHR misses 175011201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 109885 # number of LoadLockedReq MSHR misses 175111201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194127 # number of StoreCondReq MSHR misses 175211201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 194127 # number of StoreCondReq MSHR misses 175311201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 3893215 # number of demand (read+write) MSHR misses 175411201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 3893215 # number of demand (read+write) MSHR misses 175511201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 4451879 # number of overall MSHR misses 175611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 4451879 # number of overall MSHR misses 175711201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23611 # number of ReadReq MSHR uncacheable 175811201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 23611 # number of ReadReq MSHR uncacheable 175911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22620 # number of WriteReq MSHR uncacheable 176011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 22620 # number of WriteReq MSHR uncacheable 176111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46231 # number of overall MSHR uncacheable misses 176211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 46231 # number of overall MSHR uncacheable misses 176311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36382655000 # number of ReadReq MSHR miss cycles 176411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 36382655000 # number of ReadReq MSHR miss cycles 176511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26928760500 # number of WriteReq MSHR miss cycles 176611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 26928760500 # number of WriteReq MSHR miss cycles 176711201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12609688500 # number of SoftPFReq MSHR miss cycles 176811201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12609688500 # number of SoftPFReq MSHR miss cycles 176911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20283957000 # number of WriteLineReq MSHR miss cycles 177011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20283957000 # number of WriteLineReq MSHR miss cycles 177111201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1540230500 # number of LoadLockedReq MSHR miss cycles 177211201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1540230500 # number of LoadLockedReq MSHR miss cycles 177311201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5151064000 # number of StoreCondReq MSHR miss cycles 177411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5151064000 # number of StoreCondReq MSHR miss cycles 177511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6855500 # number of StoreCondFailReq MSHR miss cycles 177611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6855500 # number of StoreCondFailReq MSHR miss cycles 177711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63311415500 # number of demand (read+write) MSHR miss cycles 177811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 63311415500 # number of demand (read+write) MSHR miss cycles 177911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75921104000 # number of overall MSHR miss cycles 178011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 75921104000 # number of overall MSHR miss cycles 178111201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4287453000 # number of ReadReq MSHR uncacheable cycles 178211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4287453000 # number of ReadReq MSHR uncacheable cycles 178311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4160988000 # number of WriteReq MSHR uncacheable cycles 178411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4160988000 # number of WriteReq MSHR uncacheable cycles 178511201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8448441000 # number of overall MSHR uncacheable cycles 178611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 8448441000 # number of overall MSHR uncacheable cycles 178711201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036070 # mshr miss rate for ReadReq accesses 178811201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036070 # mshr miss rate for ReadReq accesses 178911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017998 # mshr miss rate for WriteReq accesses 179011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017998 # mshr miss rate for WriteReq accesses 179111201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762296 # mshr miss rate for SoftPFReq accesses 179211201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762296 # mshr miss rate for SoftPFReq accesses 179311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716041 # mshr miss rate for WriteLineReq accesses 179411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.716041 # mshr miss rate for WriteLineReq accesses 179511201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063005 # mshr miss rate for LoadLockedReq accesses 179611201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063005 # mshr miss rate for LoadLockedReq accesses 179711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111384 # mshr miss rate for StoreCondReq accesses 179811201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111384 # mshr miss rate for StoreCondReq accesses 179911201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027476 # mshr miss rate for demand accesses 180011201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.027476 # mshr miss rate for demand accesses 180111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031257 # mshr miss rate for overall accesses 180211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.031257 # mshr miss rate for overall accesses 180311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13573.348560 # average ReadReq mshr miss latency 180411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13573.348560 # average ReadReq mshr miss latency 180511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22204.397465 # average WriteReq mshr miss latency 180611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22204.397465 # average WriteReq mshr miss latency 180711201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22571.149206 # average SoftPFReq mshr miss latency 180811201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22571.149206 # average SoftPFReq mshr miss latency 180911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 43453.765473 # average WriteLineReq mshr miss latency 181011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 43453.765473 # average WriteLineReq mshr miss latency 181111201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14016.749329 # average LoadLockedReq mshr miss latency 181211201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14016.749329 # average LoadLockedReq mshr miss latency 181311201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26534.505762 # average StoreCondReq mshr miss latency 181411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26534.505762 # average StoreCondReq mshr miss latency 181510535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 181610535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 181711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16261.987971 # average overall mshr miss latency 181811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 16261.987971 # average overall mshr miss latency 181911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17053.721361 # average overall mshr miss latency 182011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 17053.721361 # average overall mshr miss latency 182111201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181587.099233 # average ReadReq mshr uncacheable latency 182211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181587.099233 # average ReadReq mshr uncacheable latency 182311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183951.724138 # average WriteReq mshr uncacheable latency 182411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183951.724138 # average WriteReq mshr uncacheable latency 182511201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182744.067833 # average overall mshr uncacheable latency 182611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182744.067833 # average overall mshr uncacheable latency 182710535SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 182811201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 4831573 # number of replacements 182911201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 495.969883 # Cycle average of tags in use 183011201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 401189463 # Total number of references to valid blocks. 183111201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 4832085 # Sample count of references to valid blocks. 183211201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 83.026160 # Average number of references to valid blocks. 183311201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8408381586000 # Cycle when the warmup percentage was hit. 183411201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 495.969883 # Average occupied blocks per requestor 183511201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.968691 # Average percentage of cache occupancy 183611201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.968691 # Average percentage of cache occupancy 183710535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 183811201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 183911201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id 184011201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id 184110535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 184211201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 816875196 # Number of tag accesses 184311201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 816875196 # Number of data accesses 184411201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 401189463 # number of ReadReq hits 184511201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 401189463 # number of ReadReq hits 184611201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 401189463 # number of demand (read+write) hits 184711201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 401189463 # number of demand (read+write) hits 184811201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 401189463 # number of overall hits 184911201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 401189463 # number of overall hits 185011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4832090 # number of ReadReq misses 185111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 4832090 # number of ReadReq misses 185211201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4832090 # number of demand (read+write) misses 185311201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 4832090 # number of demand (read+write) misses 185411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4832090 # number of overall misses 185511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 4832090 # number of overall misses 185611201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52408341000 # number of ReadReq miss cycles 185711201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 52408341000 # number of ReadReq miss cycles 185811201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 52408341000 # number of demand (read+write) miss cycles 185911201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 52408341000 # number of demand (read+write) miss cycles 186011201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 52408341000 # number of overall miss cycles 186111201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 52408341000 # number of overall miss cycles 186211201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 406021553 # number of ReadReq accesses(hits+misses) 186311201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 406021553 # number of ReadReq accesses(hits+misses) 186411201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 406021553 # number of demand (read+write) accesses 186511201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 406021553 # number of demand (read+write) accesses 186611201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 406021553 # number of overall (read+write) accesses 186711201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 406021553 # number of overall (read+write) accesses 186811201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011901 # miss rate for ReadReq accesses 186911201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.011901 # miss rate for ReadReq accesses 187011201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.011901 # miss rate for demand accesses 187111201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.011901 # miss rate for demand accesses 187211201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.011901 # miss rate for overall accesses 187311201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.011901 # miss rate for overall accesses 187411201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10845.895047 # average ReadReq miss latency 187511201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10845.895047 # average ReadReq miss latency 187611201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency 187711201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10845.895047 # average overall miss latency 187811201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency 187911201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10845.895047 # average overall miss latency 188010535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 188110535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 188210535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 188310535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 188410535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 188510535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 188610535SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 188710535SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 188811201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 4831573 # number of writebacks 188911201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 4831573 # number of writebacks 189011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4832090 # number of ReadReq MSHR misses 189111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 4832090 # number of ReadReq MSHR misses 189211201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 4832090 # number of demand (read+write) MSHR misses 189311201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 4832090 # number of demand (read+write) MSHR misses 189411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 4832090 # number of overall MSHR misses 189511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 4832090 # number of overall MSHR misses 189610827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 189710827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 189810827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 189910827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 190011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49992296000 # number of ReadReq MSHR miss cycles 190111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 49992296000 # number of ReadReq MSHR miss cycles 190211201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49992296000 # number of demand (read+write) MSHR miss cycles 190311201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 49992296000 # number of demand (read+write) MSHR miss cycles 190411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49992296000 # number of overall MSHR miss cycles 190511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 49992296000 # number of overall MSHR miss cycles 190611201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14799500 # number of ReadReq MSHR uncacheable cycles 190711201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14799500 # number of ReadReq MSHR uncacheable cycles 190811201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14799500 # number of overall MSHR uncacheable cycles 190911201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 14799500 # number of overall MSHR uncacheable cycles 191011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for ReadReq accesses 191111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011901 # mshr miss rate for ReadReq accesses 191211201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for demand accesses 191311201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.011901 # mshr miss rate for demand accesses 191411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for overall accesses 191511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.011901 # mshr miss rate for overall accesses 191611201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average ReadReq mshr miss latency 191711201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10345.895047 # average ReadReq mshr miss latency 191811201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average overall mshr miss latency 191911201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10345.895047 # average overall mshr miss latency 192011201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average overall mshr miss latency 192111201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10345.895047 # average overall mshr miss latency 192211201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average ReadReq mshr uncacheable latency 192311201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091 # average ReadReq mshr uncacheable latency 192411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average overall mshr uncacheable latency 192511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091 # average overall mshr uncacheable latency 192610535SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 192711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 6380299 # number of hwpf issued 192811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 6380331 # number of prefetch candidates identified 192911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue 193010628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 193110628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 193211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 802101 # number of prefetches not generated due to page crossing 193311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 1778912 # number of replacements 193411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13269.685648 # Cycle average of tags in use 193511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 14051315 # Total number of references to valid blocks. 193611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 1794926 # Sample count of references to valid blocks. 193711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 7.828353 # Average number of references to valid blocks. 193811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 10084696105000 # Cycle when the warmup percentage was hit. 193911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12213.003078 # Average occupied blocks per requestor 194011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 33.894206 # Average occupied blocks per requestor 194111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 34.650770 # Average occupied blocks per requestor 194211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 988.137594 # Average occupied blocks per requestor 194311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.745423 # Average percentage of cache occupancy 194411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002069 # Average percentage of cache occupancy 194511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002115 # Average percentage of cache occupancy 194611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060311 # Average percentage of cache occupancy 194711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.809917 # Average percentage of cache occupancy 194811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1110 # Occupied blocks per task id 194911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id 195011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14818 # Occupied blocks per task id 195111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 195211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id 195311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 669 # Occupied blocks per task id 195411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 184 # Occupied blocks per task id 195511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 195611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 72 # Occupied blocks per task id 195711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 195811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 195911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 972 # Occupied blocks per task id 196011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4464 # Occupied blocks per task id 196111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8114 # Occupied blocks per task id 196211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1200 # Occupied blocks per task id 196311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.067749 # Percentage of cache occupancy per task id 196411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id 196511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.904419 # Percentage of cache occupancy per task id 196611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 324313053 # Number of tag accesses 196711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 324313053 # Number of data accesses 196811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 211999 # number of ReadReq hits 196911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140481 # number of ReadReq hits 197011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 352480 # number of ReadReq hits 197111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 2988895 # number of WritebackDirty hits 197211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 2988895 # number of WritebackDirty hits 197311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6573071 # number of WritebackClean hits 197411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6573071 # number of WritebackClean hits 197511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 239 # number of UpgradeReq hits 197611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 239 # number of UpgradeReq hits 197711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 778234 # number of ReadExReq hits 197811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 778234 # number of ReadExReq hits 197911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4410501 # number of ReadCleanReq hits 198011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4410501 # number of ReadCleanReq hits 198111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2517428 # number of ReadSharedReq hits 198211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 2517428 # number of ReadSharedReq hits 198311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 200602 # number of InvalidateReq hits 198411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 200602 # number of InvalidateReq hits 198511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 211999 # number of demand (read+write) hits 198611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 140481 # number of demand (read+write) hits 198711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4410501 # number of demand (read+write) hits 198811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3295662 # number of demand (read+write) hits 198911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8058643 # number of demand (read+write) hits 199011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 211999 # number of overall hits 199111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 140481 # number of overall hits 199211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4410501 # number of overall hits 199311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3295662 # number of overall hits 199411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8058643 # number of overall hits 199511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9285 # number of ReadReq misses 199611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7506 # number of ReadReq misses 199711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 16791 # number of ReadReq misses 199811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 201343 # number of UpgradeReq misses 199911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 201343 # number of UpgradeReq misses 200011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194101 # number of SCUpgradeReq misses 200111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 194101 # number of SCUpgradeReq misses 200211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 26 # number of SCUpgradeFailReq misses 200311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 26 # number of SCUpgradeFailReq misses 200411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 235513 # number of ReadExReq misses 200511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 235513 # number of ReadExReq misses 200611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 421589 # number of ReadCleanReq misses 200711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 421589 # number of ReadCleanReq misses 200811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 831569 # number of ReadSharedReq misses 200911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 831569 # number of ReadSharedReq misses 201011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 263822 # number of InvalidateReq misses 201111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 263822 # number of InvalidateReq misses 201211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9285 # number of demand (read+write) misses 201311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 7506 # number of demand (read+write) misses 201411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 421589 # number of demand (read+write) misses 201511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1067082 # number of demand (read+write) misses 201611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1505462 # number of demand (read+write) misses 201711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9285 # number of overall misses 201811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 7506 # number of overall misses 201911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 421589 # number of overall misses 202011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1067082 # number of overall misses 202111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1505462 # number of overall misses 202211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 349092500 # number of ReadReq miss cycles 202311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 301051000 # number of ReadReq miss cycles 202411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 650143500 # number of ReadReq miss cycles 202511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3162483500 # number of UpgradeReq miss cycles 202611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 3162483500 # number of UpgradeReq miss cycles 202711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1860693500 # number of SCUpgradeReq miss cycles 202811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1860693500 # number of SCUpgradeReq miss cycles 202911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6744500 # number of SCUpgradeFailReq miss cycles 203011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6744500 # number of SCUpgradeFailReq miss cycles 203111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12440298999 # number of ReadExReq miss cycles 203211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 12440298999 # number of ReadExReq miss cycles 203311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16234081000 # number of ReadCleanReq miss cycles 203411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 16234081000 # number of ReadCleanReq miss cycles 203511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29105216000 # number of ReadSharedReq miss cycles 203611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 29105216000 # number of ReadSharedReq miss cycles 203711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18219271500 # number of InvalidateReq miss cycles 203811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 18219271500 # number of InvalidateReq miss cycles 203911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 349092500 # number of demand (read+write) miss cycles 204011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 301051000 # number of demand (read+write) miss cycles 204111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 16234081000 # number of demand (read+write) miss cycles 204211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 41545514999 # number of demand (read+write) miss cycles 204311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 58429739499 # number of demand (read+write) miss cycles 204411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 349092500 # number of overall miss cycles 204511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 301051000 # number of overall miss cycles 204611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 16234081000 # number of overall miss cycles 204711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 41545514999 # number of overall miss cycles 204811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 58429739499 # number of overall miss cycles 204911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 221284 # number of ReadReq accesses(hits+misses) 205011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 147987 # number of ReadReq accesses(hits+misses) 205111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 369271 # number of ReadReq accesses(hits+misses) 205211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 2988895 # number of WritebackDirty accesses(hits+misses) 205311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 2988895 # number of WritebackDirty accesses(hits+misses) 205411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6573071 # number of WritebackClean accesses(hits+misses) 205511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6573071 # number of WritebackClean accesses(hits+misses) 205611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 201582 # number of UpgradeReq accesses(hits+misses) 205711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 201582 # number of UpgradeReq accesses(hits+misses) 205811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194101 # number of SCUpgradeReq accesses(hits+misses) 205911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 194101 # number of SCUpgradeReq accesses(hits+misses) 206011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 26 # number of SCUpgradeFailReq accesses(hits+misses) 206111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 26 # number of SCUpgradeFailReq accesses(hits+misses) 206211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1013747 # number of ReadExReq accesses(hits+misses) 206311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1013747 # number of ReadExReq accesses(hits+misses) 206411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4832090 # number of ReadCleanReq accesses(hits+misses) 206511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4832090 # number of ReadCleanReq accesses(hits+misses) 206611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3348997 # number of ReadSharedReq accesses(hits+misses) 206711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 3348997 # number of ReadSharedReq accesses(hits+misses) 206811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 464424 # number of InvalidateReq accesses(hits+misses) 206911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 464424 # number of InvalidateReq accesses(hits+misses) 207011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 221284 # number of demand (read+write) accesses 207111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 147987 # number of demand (read+write) accesses 207211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4832090 # number of demand (read+write) accesses 207311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 4362744 # number of demand (read+write) accesses 207411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 9564105 # number of demand (read+write) accesses 207511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 221284 # number of overall (read+write) accesses 207611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 147987 # number of overall (read+write) accesses 207711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4832090 # number of overall (read+write) accesses 207811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 4362744 # number of overall (read+write) accesses 207911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 9564105 # number of overall (read+write) accesses 208011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041960 # miss rate for ReadReq accesses 208111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050721 # miss rate for ReadReq accesses 208211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.045471 # miss rate for ReadReq accesses 208311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998814 # miss rate for UpgradeReq accesses 208411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998814 # miss rate for UpgradeReq accesses 208511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 208611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 208710535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 208810535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 208911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.232319 # miss rate for ReadExReq accesses 209011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.232319 # miss rate for ReadExReq accesses 209111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.087248 # miss rate for ReadCleanReq accesses 209211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.087248 # miss rate for ReadCleanReq accesses 209311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.248304 # miss rate for ReadSharedReq accesses 209411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.248304 # miss rate for ReadSharedReq accesses 209511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.568063 # miss rate for InvalidateReq accesses 209611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.568063 # miss rate for InvalidateReq accesses 209711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.041960 # miss rate for demand accesses 209811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050721 # miss rate for demand accesses 209911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.087248 # miss rate for demand accesses 210011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244590 # miss rate for demand accesses 210111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.157408 # miss rate for demand accesses 210211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.041960 # miss rate for overall accesses 210311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050721 # miss rate for overall accesses 210411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.087248 # miss rate for overall accesses 210511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244590 # miss rate for overall accesses 210611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.157408 # miss rate for overall accesses 210711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37597.469036 # average ReadReq miss latency 210811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40108.046896 # average ReadReq miss latency 210911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 38719.760586 # average ReadReq miss latency 211011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15706.945362 # average UpgradeReq miss latency 211111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15706.945362 # average UpgradeReq miss latency 211211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9586.212848 # average SCUpgradeReq miss latency 211311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9586.212848 # average SCUpgradeReq miss latency 211411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 259403.846154 # average SCUpgradeFailReq miss latency 211511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 259403.846154 # average SCUpgradeFailReq miss latency 211611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52822.132957 # average ReadExReq miss latency 211711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52822.132957 # average ReadExReq miss latency 211811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38506.889411 # average ReadCleanReq miss latency 211911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38506.889411 # average ReadCleanReq miss latency 212011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35000.361966 # average ReadSharedReq miss latency 212111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35000.361966 # average ReadSharedReq miss latency 212211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69058.954522 # average InvalidateReq miss latency 212311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69058.954522 # average InvalidateReq miss latency 212411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37597.469036 # average overall miss latency 212511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40108.046896 # average overall miss latency 212611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38506.889411 # average overall miss latency 212711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38933.760479 # average overall miss latency 212811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 38811.832845 # average overall miss latency 212911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37597.469036 # average overall miss latency 213011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40108.046896 # average overall miss latency 213111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38506.889411 # average overall miss latency 213211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38933.760479 # average overall miss latency 213311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 38811.832845 # average overall miss latency 213410628SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 213510535SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 213610628SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 213710535SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 213810628SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 213910535SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 214010535SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 214110535SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 214211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 983057 # number of writebacks 214311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 983057 # number of writebacks 214411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3912 # number of ReadExReq MSHR hits 214511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 3912 # number of ReadExReq MSHR hits 214611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 475 # number of ReadSharedReq MSHR hits 214711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 475 # number of ReadSharedReq MSHR hits 214811138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 214911138Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 215011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 4387 # number of demand (read+write) MSHR hits 215111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 4387 # number of demand (read+write) MSHR hits 215211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 4387 # number of overall MSHR hits 215311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 4387 # number of overall MSHR hits 215411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9285 # number of ReadReq MSHR misses 215511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7506 # number of ReadReq MSHR misses 215611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 16791 # number of ReadReq MSHR misses 215711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 603476 # number of HardPFReq MSHR misses 215811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 603476 # number of HardPFReq MSHR misses 215911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 201343 # number of UpgradeReq MSHR misses 216011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 201343 # number of UpgradeReq MSHR misses 216111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194101 # number of SCUpgradeReq MSHR misses 216211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194101 # number of SCUpgradeReq MSHR misses 216311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 26 # number of SCUpgradeFailReq MSHR misses 216411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 26 # number of SCUpgradeFailReq MSHR misses 216511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 231601 # number of ReadExReq MSHR misses 216611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 231601 # number of ReadExReq MSHR misses 216711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 421589 # number of ReadCleanReq MSHR misses 216811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 421589 # number of ReadCleanReq MSHR misses 216911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 831094 # number of ReadSharedReq MSHR misses 217011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 831094 # number of ReadSharedReq MSHR misses 217111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 263821 # number of InvalidateReq MSHR misses 217211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 263821 # number of InvalidateReq MSHR misses 217311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9285 # number of demand (read+write) MSHR misses 217411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7506 # number of demand (read+write) MSHR misses 217511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 421589 # number of demand (read+write) MSHR misses 217611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1062695 # number of demand (read+write) MSHR misses 217711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1501075 # number of demand (read+write) MSHR misses 217811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9285 # number of overall MSHR misses 217911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7506 # number of overall MSHR misses 218011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 421589 # number of overall MSHR misses 218111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1062695 # number of overall MSHR misses 218211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 603476 # number of overall MSHR misses 218311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2104551 # number of overall MSHR misses 218410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 218511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23611 # number of ReadReq MSHR uncacheable 218611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23721 # number of ReadReq MSHR uncacheable 218711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22620 # number of WriteReq MSHR uncacheable 218811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22620 # number of WriteReq MSHR uncacheable 218910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 219011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 46231 # number of overall MSHR uncacheable misses 219111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 46341 # number of overall MSHR uncacheable misses 219211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 293382500 # number of ReadReq MSHR miss cycles 219311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 256015000 # number of ReadReq MSHR miss cycles 219411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 549397500 # number of ReadReq MSHR miss cycles 219511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27540952434 # number of HardPFReq MSHR miss cycles 219611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27540952434 # number of HardPFReq MSHR miss cycles 219711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6429356000 # number of UpgradeReq MSHR miss cycles 219811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6429356000 # number of UpgradeReq MSHR miss cycles 219911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3693933999 # number of SCUpgradeReq MSHR miss cycles 220011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3693933999 # number of SCUpgradeReq MSHR miss cycles 220111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6300500 # number of SCUpgradeFailReq MSHR miss cycles 220211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6300500 # number of SCUpgradeFailReq MSHR miss cycles 220311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10580800999 # number of ReadExReq MSHR miss cycles 220411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10580800999 # number of ReadExReq MSHR miss cycles 220511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13704547000 # number of ReadCleanReq MSHR miss cycles 220611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13704547000 # number of ReadCleanReq MSHR miss cycles 220711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24076200000 # number of ReadSharedReq MSHR miss cycles 220811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24076200000 # number of ReadSharedReq MSHR miss cycles 220911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16636263000 # number of InvalidateReq MSHR miss cycles 221011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16636263000 # number of InvalidateReq MSHR miss cycles 221111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 293382500 # number of demand (read+write) MSHR miss cycles 221211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 256015000 # number of demand (read+write) MSHR miss cycles 221311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13704547000 # number of demand (read+write) MSHR miss cycles 221411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34657000999 # number of demand (read+write) MSHR miss cycles 221511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 48910945499 # number of demand (read+write) MSHR miss cycles 221611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 293382500 # number of overall MSHR miss cycles 221711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 256015000 # number of overall MSHR miss cycles 221811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13704547000 # number of overall MSHR miss cycles 221911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34657000999 # number of overall MSHR miss cycles 222011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27540952434 # number of overall MSHR miss cycles 222111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 76451897933 # number of overall MSHR miss cycles 222211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13974500 # number of ReadReq MSHR uncacheable cycles 222311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 4098070000 # number of ReadReq MSHR uncacheable cycles 222411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 4112044500 # number of ReadReq MSHR uncacheable cycles 222511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3990752000 # number of WriteReq MSHR uncacheable cycles 222611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3990752000 # number of WriteReq MSHR uncacheable cycles 222711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13974500 # number of overall MSHR uncacheable cycles 222811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 8088822000 # number of overall MSHR uncacheable cycles 222911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 8102796500 # number of overall MSHR uncacheable cycles 223011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for ReadReq accesses 223111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for ReadReq accesses 223211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.045471 # mshr miss rate for ReadReq accesses 223310535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 223410535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 223511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998814 # mshr miss rate for UpgradeReq accesses 223611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998814 # mshr miss rate for UpgradeReq accesses 223711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 223811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 223910535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 224010535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 224111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.228460 # mshr miss rate for ReadExReq accesses 224211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.228460 # mshr miss rate for ReadExReq accesses 224311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for ReadCleanReq accesses 224411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087248 # mshr miss rate for ReadCleanReq accesses 224511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248162 # mshr miss rate for ReadSharedReq accesses 224611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248162 # mshr miss rate for ReadSharedReq accesses 224711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.568061 # mshr miss rate for InvalidateReq accesses 224811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.568061 # mshr miss rate for InvalidateReq accesses 224911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for demand accesses 225011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for demand accesses 225111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for demand accesses 225211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243584 # mshr miss rate for demand accesses 225311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.156949 # mshr miss rate for demand accesses 225411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for overall accesses 225511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for overall accesses 225611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for overall accesses 225711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243584 # mshr miss rate for overall accesses 225810535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 225911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.220047 # mshr miss rate for overall accesses 226011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average ReadReq mshr miss latency 226111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average ReadReq mshr miss latency 226211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.760586 # average ReadReq mshr miss latency 226311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average HardPFReq mshr miss latency 226411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45637.195902 # average HardPFReq mshr miss latency 226511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31932.354241 # average UpgradeReq mshr miss latency 226611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31932.354241 # average UpgradeReq mshr miss latency 226711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19030.989016 # average SCUpgradeReq mshr miss latency 226811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19030.989016 # average SCUpgradeReq mshr miss latency 226911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242326.923077 # average SCUpgradeFailReq mshr miss latency 227011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242326.923077 # average SCUpgradeFailReq mshr miss latency 227111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.471993 # average ReadExReq mshr miss latency 227211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.471993 # average ReadExReq mshr miss latency 227311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average ReadCleanReq mshr miss latency 227411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32506.889411 # average ReadCleanReq mshr miss latency 227511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28969.286266 # average ReadSharedReq mshr miss latency 227611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28969.286266 # average ReadSharedReq mshr miss latency 227711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63058.903575 # average InvalidateReq mshr miss latency 227811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63058.903575 # average InvalidateReq mshr miss latency 227911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency 228011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency 228111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency 228211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency 228311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32583.945172 # average overall mshr miss latency 228411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency 228511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency 228611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency 228711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency 228811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average overall mshr miss latency 228911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36326.940014 # average overall mshr miss latency 229011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average ReadReq mshr uncacheable latency 229111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173566.134429 # average ReadReq mshr uncacheable latency 229211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173350.385734 # average ReadReq mshr uncacheable latency 229311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176425.817860 # average WriteReq mshr uncacheable latency 229411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176425.817860 # average WriteReq mshr uncacheable latency 229511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average overall mshr uncacheable latency 229611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174965.326296 # average overall mshr uncacheable latency 229711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174851.567726 # average overall mshr uncacheable latency 229810535SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 229911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 19832170 # Total number of requests made to the snoop filter. 230011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 10173061 # Number of requests hitting in the snoop filter with a single holder of the requested data. 230111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1095 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 230211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 1632026 # Total number of snoops made to the snoop filter. 230311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1631848 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 230411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 178 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 230511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 456067 # Transaction distribution 230611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 8724452 # Transaction distribution 230711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 22620 # Transaction distribution 230811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 22620 # Transaction distribution 230911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 3978006 # Transaction distribution 231011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6573071 # Transaction distribution 231111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2099842 # Transaction distribution 231211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 741149 # Transaction distribution 231311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 395876 # Transaction distribution 231411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358205 # Transaction distribution 231511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 460652 # Transaction distribution 231611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution 231711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution 231811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1084167 # Transaction distribution 231911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1021480 # Transaction distribution 232011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4832090 # Transaction distribution 232111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4231593 # Transaction distribution 232211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 474723 # Transaction distribution 232311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 464424 # Transaction distribution 232411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14495311 # Packet count per connected master and slave (bytes) 232511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15429373 # Packet count per connected master and slave (bytes) 232611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 311743 # Packet count per connected master and slave (bytes) 232711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 489874 # Packet count per connected master and slave (bytes) 232811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 30726301 # Packet count per connected master and slave (bytes) 232911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 618432504 # Cumulative packet size per connected master and slave (bytes) 233011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588237954 # Cumulative packet size per connected master and slave (bytes) 233111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1183896 # Cumulative packet size per connected master and slave (bytes) 233211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1770272 # Cumulative packet size per connected master and slave (bytes) 233311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1209624626 # Cumulative packet size per connected master and slave (bytes) 233411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 5375046 # Total snoops (count) 233511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 15685523 # Request fanout histogram 233611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.117781 # Request fanout histogram 233711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.322383 # Request fanout histogram 233810535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 233911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 13838252 88.22% 88.22% # Request fanout histogram 234011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 1847093 11.78% 100.00% # Request fanout histogram 234111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 178 0.00% 100.00% # Request fanout histogram 234210535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 234311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 234410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 234511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 15685523 # Request fanout histogram 234611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 19622729498 # Layer occupancy (ticks) 234710535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 234811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 175341179 # Layer occupancy (ticks) 234910535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 235011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7248245000 # Layer occupancy (ticks) 235110535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 235211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 7009474930 # Layer occupancy (ticks) 235310535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 235411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 163756499 # Layer occupancy (ticks) 235510535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 235611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 268590000 # Layer occupancy (ticks) 235710535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 235811201Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40469 # Transaction distribution 235911201Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40469 # Transaction distribution 236011201Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 137017 # Transaction distribution 236111201Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 137017 # Transaction distribution 236211201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47986 # Packet count per connected master and slave (bytes) 236310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 236410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 236510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 236610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 236710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 236810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 236910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 237010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 237110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 237211201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 237310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 237410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 237510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 237610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 237711201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 123128 # Packet count per connected master and slave (bytes) 237811201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231764 # Packet count per connected master and slave (bytes) 237911201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231764 # Packet count per connected master and slave (bytes) 238010535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 238110535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 238211201Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354972 # Packet count per connected master and slave (bytes) 238311201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48006 # Cumulative packet size per connected master and slave (bytes) 238410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 238510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 238610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 238710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 238810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 238910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 239210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 239311201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 239410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 239510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 239610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 239710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 239811201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 156143 # Cumulative packet size per connected master and slave (bytes) 239911201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355408 # Cumulative packet size per connected master and slave (bytes) 240011201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7355408 # Cumulative packet size per connected master and slave (bytes) 240110535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 240210535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 240311201Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7513637 # Cumulative packet size per connected master and slave (bytes) 240411201Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 37181500 # Layer occupancy (ticks) 240510535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 240611201Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) 240710535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 240811201Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 8500 # Layer occupancy (ticks) 240910535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 241011201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 241110535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 241210535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 241310535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 241411201Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) 241510535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 241611201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 241710535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 241811201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 241910535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 242011201Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 242110535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 242210535SN/Asystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 242310535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 242411201Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 26640000 # Layer occupancy (ticks) 242510535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 242611201Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 168000 # Layer occupancy (ticks) 242710535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 242811201Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 37419000 # Layer occupancy (ticks) 242910535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 243011201Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 122000 # Layer occupancy (ticks) 243110535SN/Asystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 243211201Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 566572505 # Layer occupancy (ticks) 243310535SN/Asystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 243411201Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 30500 # Layer occupancy (ticks) 243510535SN/Asystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 243611201Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 93098000 # Layer occupancy (ticks) 243710535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 243811201Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 148204000 # Layer occupancy (ticks) 243910535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 244010892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 244110535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 244211201Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115869 # number of replacements 244311201Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.294988 # Cycle average of tags in use 244411201Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 4 # Total number of references to valid blocks. 244511201Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115885 # Sample count of references to valid blocks. 244611201Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000035 # Average number of references to valid blocks. 244711201Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9206093766000 # Cycle when the warmup percentage was hit. 244811201Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.821408 # Average occupied blocks per requestor 244911201Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.473580 # Average occupied blocks per requestor 245011201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.238838 # Average percentage of cache occupancy 245111201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.467099 # Average percentage of cache occupancy 245211201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.705937 # Average percentage of cache occupancy 245310535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 245410535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 245510535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 245611201Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1043293 # Number of tag accesses 245711201Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1043293 # Number of data accesses 245810535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 245911201Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8898 # number of ReadReq misses 246011201Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8935 # number of ReadReq misses 246110535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 246210535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 246311201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 246411201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 246510535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 246611201Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8898 # number of demand (read+write) misses 246711201Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8938 # number of demand (read+write) misses 246810535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 246911201Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8898 # number of overall misses 247011201Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8938 # number of overall misses 247111201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 247211201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1681517592 # number of ReadReq miss cycles 247311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1686717092 # number of ReadReq miss cycles 247410726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 247510726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 247611201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 14021691413 # number of WriteLineReq miss cycles 247711201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 14021691413 # number of WriteLineReq miss cycles 247811201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles 247911201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1681517592 # number of demand (read+write) miss cycles 248011201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1687086092 # number of demand (read+write) miss cycles 248111201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles 248211201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1681517592 # number of overall miss cycles 248311201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1687086092 # number of overall miss cycles 248410535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 248511201Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8898 # number of ReadReq accesses(hits+misses) 248611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8935 # number of ReadReq accesses(hits+misses) 248710535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 248810535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 248911201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 249011201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 249110535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 249211201Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8898 # number of demand (read+write) accesses 249311201Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8938 # number of demand (read+write) accesses 249410535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 249511201Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8898 # number of overall (read+write) accesses 249611201Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8938 # number of overall (read+write) accesses 249710535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 249810535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 249910535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 250010535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 250110535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 250210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 250310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 250410535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 250510535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 250610535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 250710535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 250810535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 250910535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 251011201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 251111201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 188977.027647 # average ReadReq miss latency 251211201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 188776.395299 # average ReadReq miss latency 251310726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 251410726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 251511201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 131063.443253 # average WriteLineReq miss latency 251611201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 131063.443253 # average WriteLineReq miss latency 251711201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 251811201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency 251911201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 188754.317744 # average overall miss latency 252011201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 252111201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency 252211201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 188754.317744 # average overall miss latency 252311201Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 36073 # number of cycles access was blocked 252410535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 252511201Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3617 # number of cycles access was blocked 252610535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 252711201Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.973182 # average number of cycles each access was blocked 252810535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 252910585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 253010535SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 253111201Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106957 # number of writebacks 253211201Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106957 # number of writebacks 253310535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 253411201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8898 # number of ReadReq MSHR misses 253511201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8935 # number of ReadReq MSHR misses 253610535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 253710535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 253811201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 253911201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 254010535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 254111201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8898 # number of demand (read+write) MSHR misses 254211201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8938 # number of demand (read+write) MSHR misses 254310535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 254411201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8898 # number of overall MSHR misses 254511201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8938 # number of overall MSHR misses 254611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 254711201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1236617592 # number of ReadReq MSHR miss cycles 254811201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1239967092 # number of ReadReq MSHR miss cycles 254910892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 255010892Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 255111201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8672491413 # number of WriteLineReq MSHR miss cycles 255211201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8672491413 # number of WriteLineReq MSHR miss cycles 255311201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles 255411201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1236617592 # number of demand (read+write) MSHR miss cycles 255511201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1240186092 # number of demand (read+write) MSHR miss cycles 255611201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles 255711201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1236617592 # number of overall MSHR miss cycles 255811201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1240186092 # number of overall MSHR miss cycles 255910535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 256010535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 256110535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 256210535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 256310535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 256410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 256510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 256610535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 256710535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 256810535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 256910535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 257010535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 257110535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 257211201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 257311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138977.027647 # average ReadReq mshr miss latency 257411201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 138776.395299 # average ReadReq mshr miss latency 257510892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 257610892Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 257711201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 81063.443253 # average WriteLineReq mshr miss latency 257811201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 81063.443253 # average WriteLineReq mshr miss latency 257911201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 258011201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency 258111201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency 258211201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 258311201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency 258411201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency 258510535SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 258611201Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1210264 # number of replacements 258711201Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62755.466878 # Cycle average of tags in use 258811201Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 5212344 # Total number of references to valid blocks. 258911201Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1269955 # Sample count of references to valid blocks. 259011201Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 4.104353 # Average number of references to valid blocks. 259110892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 259211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 23285.968480 # Average occupied blocks per requestor 259311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 218.650031 # Average occupied blocks per requestor 259411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 386.944281 # Average occupied blocks per requestor 259511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4588.836094 # Average occupied blocks per requestor 259611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 10476.813165 # Average occupied blocks per requestor 259711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 13833.010748 # Average occupied blocks per requestor 259811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 53.974082 # Average occupied blocks per requestor 259911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 79.219380 # Average occupied blocks per requestor 260011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3039.104298 # Average occupied blocks per requestor 260111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 3132.206690 # Average occupied blocks per requestor 260211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3660.739630 # Average occupied blocks per requestor 260311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.355316 # Average percentage of cache occupancy 260411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.003336 # Average percentage of cache occupancy 260511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.005904 # Average percentage of cache occupancy 260611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.070020 # Average percentage of cache occupancy 260711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.159863 # Average percentage of cache occupancy 260811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.211075 # Average percentage of cache occupancy 260911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000824 # Average percentage of cache occupancy 261011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.001209 # Average percentage of cache occupancy 261111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.046373 # Average percentage of cache occupancy 261211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.047794 # Average percentage of cache occupancy 261311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055858 # Average percentage of cache occupancy 261411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.957572 # Average percentage of cache occupancy 261511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10565 # Occupied blocks per task id 261611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id 261711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 48895 # Occupied blocks per task id 261811201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id 261911201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 159 # Occupied blocks per task id 262011201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 1447 # Occupied blocks per task id 262111201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 8916 # Occupied blocks per task id 262211201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 262311201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id 262411201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 262511201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id 262611201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1774 # Occupied blocks per task id 262711201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 10274 # Occupied blocks per task id 262811201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 36522 # Occupied blocks per task id 262911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.161209 # Percentage of cache occupancy per task id 263011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id 263111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.746078 # Percentage of cache occupancy per task id 263211201Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 66950820 # Number of tag accesses 263311201Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 66950820 # Number of data accesses 263411201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2504481 # number of WritebackDirty hits 263511201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2504481 # number of WritebackDirty hits 263611201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 166895 # number of UpgradeReq hits 263711201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 113960 # number of UpgradeReq hits 263811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 280855 # number of UpgradeReq hits 263911201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 38875 # number of SCUpgradeReq hits 264011201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 34247 # number of SCUpgradeReq hits 264111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 73122 # number of SCUpgradeReq hits 264211201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 158326 # number of ReadExReq hits 264311201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 166214 # number of ReadExReq hits 264411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 324540 # number of ReadExReq hits 264511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5191 # number of ReadSharedReq hits 264611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 4009 # number of ReadSharedReq hits 264711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 435451 # number of ReadSharedReq hits 264811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 562405 # number of ReadSharedReq hits 264911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296765 # number of ReadSharedReq hits 265011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5208 # number of ReadSharedReq hits 265111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4285 # number of ReadSharedReq hits 265211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 382834 # number of ReadSharedReq hits 265311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 480125 # number of ReadSharedReq hits 265411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 262665 # number of ReadSharedReq hits 265511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2438938 # number of ReadSharedReq hits 265611201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 5191 # number of demand (read+write) hits 265711201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4009 # number of demand (read+write) hits 265811201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 435451 # number of demand (read+write) hits 265911201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 720731 # number of demand (read+write) hits 266011201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 296765 # number of demand (read+write) hits 266111201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits 266211201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4285 # number of demand (read+write) hits 266311201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 382834 # number of demand (read+write) hits 266411201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 646339 # number of demand (read+write) hits 266511201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 262665 # number of demand (read+write) hits 266611201Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2763478 # number of demand (read+write) hits 266711201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 5191 # number of overall hits 266811201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4009 # number of overall hits 266911201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 435451 # number of overall hits 267011201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 720731 # number of overall hits 267111201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 296765 # number of overall hits 267211201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits 267311201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4285 # number of overall hits 267411201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 382834 # number of overall hits 267511201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 646339 # number of overall hits 267611201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 262665 # number of overall hits 267711201Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2763478 # number of overall hits 267811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 67422 # number of UpgradeReq misses 267911201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 57259 # number of UpgradeReq misses 268011201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 124681 # number of UpgradeReq misses 268111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 14532 # number of SCUpgradeReq misses 268211201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 11014 # number of SCUpgradeReq misses 268311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 25546 # number of SCUpgradeReq misses 268411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 480698 # number of ReadExReq misses 268511201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 148334 # number of ReadExReq misses 268611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 629032 # number of ReadExReq misses 268711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1519 # number of ReadSharedReq misses 268811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 1645 # number of ReadSharedReq misses 268911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 47029 # number of ReadSharedReq misses 269011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 136142 # number of ReadSharedReq misses 269111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 207239 # number of ReadSharedReq misses 269211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1062 # number of ReadSharedReq misses 269311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 1011 # number of ReadSharedReq misses 269411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 38755 # number of ReadSharedReq misses 269511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 73388 # number of ReadSharedReq misses 269611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 139305 # number of ReadSharedReq misses 269711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 647095 # number of ReadSharedReq misses 269811201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1519 # number of demand (read+write) misses 269911201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1645 # number of demand (read+write) misses 270011201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 47029 # number of demand (read+write) misses 270111201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 616840 # number of demand (read+write) misses 270211201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 207239 # number of demand (read+write) misses 270311201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1062 # number of demand (read+write) misses 270411201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 1011 # number of demand (read+write) misses 270511201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 38755 # number of demand (read+write) misses 270611201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 221722 # number of demand (read+write) misses 270711201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 139305 # number of demand (read+write) misses 270811201Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1276127 # number of demand (read+write) misses 270911201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1519 # number of overall misses 271011201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1645 # number of overall misses 271111201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 47029 # number of overall misses 271211201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 616840 # number of overall misses 271311201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 207239 # number of overall misses 271411201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1062 # number of overall misses 271511201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 1011 # number of overall misses 271611201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 38755 # number of overall misses 271711201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 221722 # number of overall misses 271811201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 139305 # number of overall misses 271911201Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1276127 # number of overall misses 272011201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 993921500 # number of UpgradeReq miss cycles 272111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 971150500 # number of UpgradeReq miss cycles 272211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 1965072000 # number of UpgradeReq miss cycles 272311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 192356500 # number of SCUpgradeReq miss cycles 272411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 170135500 # number of SCUpgradeReq miss cycles 272511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 362492000 # number of SCUpgradeReq miss cycles 272611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 63553941500 # number of ReadExReq miss cycles 272711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 19410172500 # number of ReadExReq miss cycles 272811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 82964114000 # number of ReadExReq miss cycles 272911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 210107500 # number of ReadSharedReq miss cycles 273011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 226821000 # number of ReadSharedReq miss cycles 273111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 6321092000 # number of ReadSharedReq miss cycles 273211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 18616948500 # number of ReadSharedReq miss cycles 273311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 33395811187 # number of ReadSharedReq miss cycles 273411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 146053000 # number of ReadSharedReq miss cycles 273511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 143461000 # number of ReadSharedReq miss cycles 273611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 5220292500 # number of ReadSharedReq miss cycles 273711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 10187553500 # number of ReadSharedReq miss cycles 273811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22750846819 # number of ReadSharedReq miss cycles 273911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 97218987006 # number of ReadSharedReq miss cycles 274011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 210107500 # number of demand (read+write) miss cycles 274111201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 226821000 # number of demand (read+write) miss cycles 274211201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 6321092000 # number of demand (read+write) miss cycles 274311201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 82170890000 # number of demand (read+write) miss cycles 274411201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33395811187 # number of demand (read+write) miss cycles 274511201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 146053000 # number of demand (read+write) miss cycles 274611201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 143461000 # number of demand (read+write) miss cycles 274711201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 5220292500 # number of demand (read+write) miss cycles 274811201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 29597726000 # number of demand (read+write) miss cycles 274911201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22750846819 # number of demand (read+write) miss cycles 275011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 180183101006 # number of demand (read+write) miss cycles 275111201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 210107500 # number of overall miss cycles 275211201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 226821000 # number of overall miss cycles 275311201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 6321092000 # number of overall miss cycles 275411201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 82170890000 # number of overall miss cycles 275511201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 33395811187 # number of overall miss cycles 275611201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 146053000 # number of overall miss cycles 275711201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 143461000 # number of overall miss cycles 275811201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 5220292500 # number of overall miss cycles 275911201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 29597726000 # number of overall miss cycles 276011201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22750846819 # number of overall miss cycles 276111201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 180183101006 # number of overall miss cycles 276211201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2504481 # number of WritebackDirty accesses(hits+misses) 276311201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2504481 # number of WritebackDirty accesses(hits+misses) 276411201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 234317 # number of UpgradeReq accesses(hits+misses) 276511201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 171219 # number of UpgradeReq accesses(hits+misses) 276611201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 405536 # number of UpgradeReq accesses(hits+misses) 276711201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 53407 # number of SCUpgradeReq accesses(hits+misses) 276811201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 45261 # number of SCUpgradeReq accesses(hits+misses) 276911201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 98668 # number of SCUpgradeReq accesses(hits+misses) 277011201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 639024 # number of ReadExReq accesses(hits+misses) 277111201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 314548 # number of ReadExReq accesses(hits+misses) 277211201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 953572 # number of ReadExReq accesses(hits+misses) 277311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 6710 # number of ReadSharedReq accesses(hits+misses) 277411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5654 # number of ReadSharedReq accesses(hits+misses) 277511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 482480 # number of ReadSharedReq accesses(hits+misses) 277611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 698547 # number of ReadSharedReq accesses(hits+misses) 277711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 504004 # number of ReadSharedReq accesses(hits+misses) 277811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 6270 # number of ReadSharedReq accesses(hits+misses) 277911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5296 # number of ReadSharedReq accesses(hits+misses) 278011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 421589 # number of ReadSharedReq accesses(hits+misses) 278111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 553513 # number of ReadSharedReq accesses(hits+misses) 278211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 401970 # number of ReadSharedReq accesses(hits+misses) 278311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 3086033 # number of ReadSharedReq accesses(hits+misses) 278411201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 6710 # number of demand (read+write) accesses 278511201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 5654 # number of demand (read+write) accesses 278611201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 482480 # number of demand (read+write) accesses 278711201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1337571 # number of demand (read+write) accesses 278811201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 504004 # number of demand (read+write) accesses 278911201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 6270 # number of demand (read+write) accesses 279011201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 5296 # number of demand (read+write) accesses 279111201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 421589 # number of demand (read+write) accesses 279211201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 868061 # number of demand (read+write) accesses 279311201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 401970 # number of demand (read+write) accesses 279411201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4039605 # number of demand (read+write) accesses 279511201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 6710 # number of overall (read+write) accesses 279611201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 5654 # number of overall (read+write) accesses 279711201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 482480 # number of overall (read+write) accesses 279811201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1337571 # number of overall (read+write) accesses 279911201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 504004 # number of overall (read+write) accesses 280011201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 6270 # number of overall (read+write) accesses 280111201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 5296 # number of overall (read+write) accesses 280211201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 421589 # number of overall (read+write) accesses 280311201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 868061 # number of overall (read+write) accesses 280411201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 401970 # number of overall (read+write) accesses 280511201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4039605 # number of overall (read+write) accesses 280611201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.287738 # miss rate for UpgradeReq accesses 280711201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.334420 # miss rate for UpgradeReq accesses 280811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.307447 # miss rate for UpgradeReq accesses 280911201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.272099 # miss rate for SCUpgradeReq accesses 281011201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.243344 # miss rate for SCUpgradeReq accesses 281111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.258909 # miss rate for SCUpgradeReq accesses 281211201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.752238 # miss rate for ReadExReq accesses 281311201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.471578 # miss rate for ReadExReq accesses 281411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.659659 # miss rate for ReadExReq accesses 281511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.226379 # miss rate for ReadSharedReq accesses 281611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.290944 # miss rate for ReadSharedReq accesses 281711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097473 # miss rate for ReadSharedReq accesses 281811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194893 # miss rate for ReadSharedReq accesses 281911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.411185 # miss rate for ReadSharedReq accesses 282011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.169378 # miss rate for ReadSharedReq accesses 282111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.190899 # miss rate for ReadSharedReq accesses 282211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.091926 # miss rate for ReadSharedReq accesses 282311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.132586 # miss rate for ReadSharedReq accesses 282411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.346556 # miss rate for ReadSharedReq accesses 282511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.209685 # miss rate for ReadSharedReq accesses 282611201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.226379 # miss rate for demand accesses 282711201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.290944 # miss rate for demand accesses 282811201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.097473 # miss rate for demand accesses 282911201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.461164 # miss rate for demand accesses 283011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.411185 # miss rate for demand accesses 283111201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.169378 # miss rate for demand accesses 283211201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.190899 # miss rate for demand accesses 283311201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.091926 # miss rate for demand accesses 283411201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.255422 # miss rate for demand accesses 283511201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.346556 # miss rate for demand accesses 283611201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.315904 # miss rate for demand accesses 283711201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.226379 # miss rate for overall accesses 283811201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.290944 # miss rate for overall accesses 283911201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.097473 # miss rate for overall accesses 284011201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.461164 # miss rate for overall accesses 284111201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.411185 # miss rate for overall accesses 284211201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.169378 # miss rate for overall accesses 284311201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.190899 # miss rate for overall accesses 284411201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.091926 # miss rate for overall accesses 284511201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.255422 # miss rate for overall accesses 284611201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.346556 # miss rate for overall accesses 284711201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.315904 # miss rate for overall accesses 284811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14741.797929 # average UpgradeReq miss latency 284911201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16960.661206 # average UpgradeReq miss latency 285011201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 15760.797555 # average UpgradeReq miss latency 285111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13236.753372 # average SCUpgradeReq miss latency 285211201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15447.203559 # average SCUpgradeReq miss latency 285311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 14189.775307 # average SCUpgradeReq miss latency 285411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 132211.786818 # average ReadExReq miss latency 285511201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 130854.507395 # average ReadExReq miss latency 285611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 131891.722520 # average ReadExReq miss latency 285711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138319.618170 # average ReadSharedReq miss latency 285811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 137885.106383 # average ReadSharedReq miss latency 285911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134408.386315 # average ReadSharedReq miss latency 286011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136746.547722 # average ReadSharedReq miss latency 286111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315 # average ReadSharedReq miss latency 286211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 137526.365348 # average ReadSharedReq miss latency 286311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141900.098912 # average ReadSharedReq miss latency 286411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134699.845181 # average ReadSharedReq miss latency 286511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138817.701804 # average ReadSharedReq miss latency 286611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964 # average ReadSharedReq miss latency 286711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 150239.125640 # average ReadSharedReq miss latency 286811201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138319.618170 # average overall miss latency 286911201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 137885.106383 # average overall miss latency 287011201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 134408.386315 # average overall miss latency 287111201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 133212.648337 # average overall miss latency 287211201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315 # average overall miss latency 287311201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 137526.365348 # average overall miss latency 287411201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 141900.098912 # average overall miss latency 287511201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 134699.845181 # average overall miss latency 287611201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 133490.253561 # average overall miss latency 287711201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964 # average overall miss latency 287811201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 141195.273673 # average overall miss latency 287911201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138319.618170 # average overall miss latency 288011201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 137885.106383 # average overall miss latency 288111201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 134408.386315 # average overall miss latency 288211201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 133212.648337 # average overall miss latency 288311201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315 # average overall miss latency 288411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137526.365348 # average overall miss latency 288511201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 141900.098912 # average overall miss latency 288611201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 134699.845181 # average overall miss latency 288711201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 133490.253561 # average overall miss latency 288811201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964 # average overall miss latency 288911201Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 141195.273673 # average overall miss latency 289011201Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 366 # number of cycles access was blocked 289110515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 289211201Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 6 # number of cycles access was blocked 289310515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 289411201Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked 289510515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 289610515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 289710515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 289811201Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 971265 # number of writebacks 289911201Sandreas.hansson@arm.comsystem.l2c.writebacks::total 971265 # number of writebacks 290011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.inst 78 # number of ReadSharedReq MSHR hits 290111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu0.data 8 # number of ReadSharedReq MSHR hits 290211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.inst 112 # number of ReadSharedReq MSHR hits 290311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::cpu1.data 26 # number of ReadSharedReq MSHR hits 290411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_hits::total 224 # number of ReadSharedReq MSHR hits 290511201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 78 # number of demand (read+write) MSHR hits 290611201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 8 # number of demand (read+write) MSHR hits 290711201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 112 # number of demand (read+write) MSHR hits 290811201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 26 # number of demand (read+write) MSHR hits 290911201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 224 # number of demand (read+write) MSHR hits 291011201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 78 # number of overall MSHR hits 291111201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 8 # number of overall MSHR hits 291211201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 112 # number of overall MSHR hits 291311201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 26 # number of overall MSHR hits 291411201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 224 # number of overall MSHR hits 291511201Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::writebacks 38370 # number of CleanEvict MSHR misses 291611201Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_misses::total 38370 # number of CleanEvict MSHR misses 291711201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 67422 # number of UpgradeReq MSHR misses 291811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 57259 # number of UpgradeReq MSHR misses 291911201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 124681 # number of UpgradeReq MSHR misses 292011201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 14532 # number of SCUpgradeReq MSHR misses 292111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11014 # number of SCUpgradeReq MSHR misses 292211201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 25546 # number of SCUpgradeReq MSHR misses 292311201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 480698 # number of ReadExReq MSHR misses 292411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 148334 # number of ReadExReq MSHR misses 292511201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 629032 # number of ReadExReq MSHR misses 292611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1519 # number of ReadSharedReq MSHR misses 292711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1645 # number of ReadSharedReq MSHR misses 292811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.inst 46951 # number of ReadSharedReq MSHR misses 292911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.data 136134 # number of ReadSharedReq MSHR misses 293011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 207239 # number of ReadSharedReq MSHR misses 293111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1062 # number of ReadSharedReq MSHR misses 293211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1011 # number of ReadSharedReq MSHR misses 293311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.inst 38643 # number of ReadSharedReq MSHR misses 293411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.data 73362 # number of ReadSharedReq MSHR misses 293511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 139305 # number of ReadSharedReq MSHR misses 293611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_misses::total 646871 # number of ReadSharedReq MSHR misses 293711201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1519 # number of demand (read+write) MSHR misses 293811201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1645 # number of demand (read+write) MSHR misses 293911201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 46951 # number of demand (read+write) MSHR misses 294011201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 616832 # number of demand (read+write) MSHR misses 294111201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 207239 # number of demand (read+write) MSHR misses 294211201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 1062 # 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mshr miss rate for UpgradeReq accesses 303111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.307447 # mshr miss rate for UpgradeReq accesses 303211201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.272099 # mshr miss rate for SCUpgradeReq accesses 303311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.243344 # mshr miss rate for SCUpgradeReq accesses 303411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.258909 # mshr miss rate for SCUpgradeReq accesses 303511201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.752238 # mshr miss rate for ReadExReq accesses 303611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.471578 # mshr miss rate for ReadExReq accesses 303711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.659659 # mshr miss rate for ReadExReq accesses 303811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.226379 # 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mshr miss rate for overall accesses 306311201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.461158 # mshr miss rate for overall accesses 306411201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411185 # mshr miss rate for overall accesses 306511201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.169378 # mshr miss rate for overall accesses 306611201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.190899 # mshr miss rate for overall accesses 306711201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.091660 # mshr miss rate for overall accesses 306811201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.255392 # mshr miss rate for overall accesses 306911201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.346556 # mshr miss rate for overall accesses 307011201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.315848 # mshr miss rate for overall accesses 307111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73808.148676 # average UpgradeReq mshr miss latency 307211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73501.082799 # average UpgradeReq mshr miss latency 307311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 73667.130517 # average UpgradeReq mshr miss latency 307411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76654.176989 # average SCUpgradeReq mshr miss latency 307511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76510.668240 # average SCUpgradeReq mshr miss latency 307611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76592.304079 # average SCUpgradeReq mshr miss latency 307711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122211.786818 # average ReadExReq mshr miss latency 307811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120854.507395 # average ReadExReq mshr miss latency 307911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 121891.722520 # average ReadExReq mshr miss latency 308011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average ReadSharedReq mshr miss latency 308111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average ReadSharedReq mshr miss latency 308211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average ReadSharedReq mshr miss latency 308311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126748.428019 # average ReadSharedReq mshr miss latency 308411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average ReadSharedReq mshr miss latency 308511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average ReadSharedReq mshr miss latency 308611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average ReadSharedReq mshr miss latency 308711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average ReadSharedReq mshr miss latency 308811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128826.061176 # average ReadSharedReq mshr miss latency 308911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average ReadSharedReq mshr miss latency 309011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140249.842714 # average ReadSharedReq mshr miss latency 309111201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average overall mshr miss latency 309211201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average overall mshr miss latency 309311201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average overall mshr miss latency 309411201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 123213.017483 # average overall mshr miss latency 309511201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average overall mshr miss latency 309611201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average overall mshr miss latency 309711201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average overall mshr miss latency 309811201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average overall mshr miss latency 309911201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 123492.394991 # average overall mshr miss latency 310011201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average overall mshr miss latency 310111201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 131199.119373 # average overall mshr miss latency 310211201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average overall mshr miss latency 310311201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average overall mshr miss latency 310411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average overall mshr miss latency 310511201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 123213.017483 # average overall mshr miss latency 310611201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average overall mshr miss latency 310711201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average overall mshr miss latency 310811201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average overall mshr miss latency 310911201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average overall mshr miss latency 311011201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 123492.394991 # average overall mshr miss latency 311111201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average overall mshr miss latency 311211201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 131199.119373 # average overall mshr miss latency 311311201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency 311411201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146258.531276 # average ReadReq mshr uncacheable latency 311511201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average ReadReq mshr uncacheable latency 311611201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155577.788132 # average ReadReq mshr uncacheable latency 311711201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131258.418927 # average ReadReq mshr uncacheable latency 311811201Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145118.029007 # average WriteReq mshr uncacheable latency 311911201Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159414.235190 # average WriteReq mshr uncacheable latency 312011201Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153388.833474 # average WriteReq mshr uncacheable latency 312111201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency 312211201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145673.001433 # average overall mshr uncacheable latency 312311201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average overall mshr uncacheable latency 312411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157454.974150 # average overall mshr uncacheable latency 312511201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 138376.408746 # average overall mshr uncacheable latency 312610515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 312711201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 82463 # Transaction distribution 312811201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 738269 # Transaction distribution 312911201Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 39099 # Transaction distribution 313011201Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 39099 # Transaction distribution 313111201Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1078222 # Transaction distribution 313211201Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 196131 # Transaction distribution 313311201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 410883 # Transaction distribution 313411201Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 321341 # Transaction distribution 313511201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 158448 # Transaction distribution 313611201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 644070 # Transaction distribution 313711201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 620815 # Transaction distribution 313811201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 655806 # Transaction distribution 313911201Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106983 # Transaction distribution 314011201Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106983 # Transaction distribution 314111201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123128 # Packet count per connected master and slave (bytes) 314210535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 314311201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28306 # Packet count per connected master and slave (bytes) 314411201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4701222 # Packet count per connected master and slave (bytes) 314511201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 4852748 # Packet count per connected master and slave (bytes) 314611201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342712 # Packet count per connected master and slave (bytes) 314711201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 342712 # Packet count per connected master and slave (bytes) 314811201Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5195460 # Packet count per connected master and slave (bytes) 314911201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156143 # Cumulative packet size per connected master and slave (bytes) 315010535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 315111201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56612 # Cumulative packet size per connected master and slave (bytes) 315211201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143440556 # Cumulative packet size per connected master and slave (bytes) 315311201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 143653515 # Cumulative packet size per connected master and slave (bytes) 315411201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262336 # Cumulative packet size per connected master and slave (bytes) 315511201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7262336 # Cumulative packet size per connected master and slave (bytes) 315611201Sandreas.hansson@arm.comsystem.membus.pkt_size::total 150915851 # Cumulative packet size per connected master and slave (bytes) 315711201Sandreas.hansson@arm.comsystem.membus.snoops 600183 # Total snoops (count) 315811201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3537604 # Request fanout histogram 315910535SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 316010535SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 316110535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 316210535SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 316311201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3537604 100.00% 100.00% # Request fanout histogram 316410535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 316510535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 316610535SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 316710535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 316811201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3537604 # Request fanout histogram 316911201Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 101645000 # Layer occupancy (ticks) 317010535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 317111138Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 317210535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 317311201Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 23516499 # Layer occupancy (ticks) 317410535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 317511201Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 7437675124 # Layer occupancy (ticks) 317610535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 317711201Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 7217345032 # Layer occupancy (ticks) 317810535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 317911201Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 228825593 # Layer occupancy (ticks) 318010535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 318110515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 318210515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 318310515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 318410515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 318510515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 318610515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 318710515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 318810515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 318910515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 319011201Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) 319110515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 319210515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 319310515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 319411201Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) 319510515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 319610515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 319710515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 319810515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 319910515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 320010515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 320110515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 320210515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 320310515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 320410515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 320510515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 320610515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 320710515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 320810515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 320910515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 321010515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 321110515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 321210515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 321310515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 321410515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 321510515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 321610515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 321710515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 321810515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 321910515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 322010515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 322110515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 322210515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 322311103Snilay@cs.wisc.edusystem.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 322411014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 322511014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 322611014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 322711014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 322811014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 322911014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 323011014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 323111014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 323211014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 323311201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 10517449 # Total number of requests made to the snoop filter. 323411201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5725465 # Number of requests hitting in the snoop filter with a single holder of the requested data. 323511201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1766756 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 323611201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 114752 # Total number of snoops made to the snoop filter. 323711201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 104186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 323811201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 10566 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 323911201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 82465 # Transaction distribution 324011201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 3940978 # Transaction distribution 324111201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 39099 # Transaction distribution 324211201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 39099 # Transaction distribution 324311201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 3582727 # Transaction distribution 324411201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1240251 # Transaction distribution 324511201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 683521 # Transaction distribution 324611201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 394463 # Transaction distribution 324711201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1077983 # Transaction distribution 324811201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 128 # Transaction distribution 324911201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution 325011201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1083401 # Transaction distribution 325111201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1083400 # Transaction distribution 325211201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3865739 # Transaction distribution 325311201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 106983 # Transaction distribution 325411201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8168699 # Packet count per connected master and slave (bytes) 325511201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6135080 # Packet count per connected master and slave (bytes) 325611201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 14303779 # Packet count per connected master and slave (bytes) 325711201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 247232417 # Cumulative packet size per connected master and slave (bytes) 325811201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 172105066 # Cumulative packet size per connected master and slave (bytes) 325911201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 419337483 # Cumulative packet size per connected master and slave (bytes) 326011201Sandreas.hansson@arm.comsystem.toL2Bus.snoops 2918298 # Total snoops (count) 326111201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 7581961 # Request fanout histogram 326211201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.362851 # Request fanout histogram 326311201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.483712 # Request fanout histogram 326410515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 326511201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 4841404 63.85% 63.85% # Request fanout histogram 326611201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 2729991 36.01% 99.86% # Request fanout histogram 326711201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 10566 0.14% 100.00% # Request fanout histogram 326810515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 326911138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 327010515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 327111201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 7581961 # Request fanout histogram 327211201Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 8230397518 # Layer occupancy (ticks) 327310515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 327411201Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2646637 # Layer occupancy (ticks) 327510515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 327611201Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 4512530115 # Layer occupancy (ticks) 327710515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 327811201Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 3554923231 # Layer occupancy (ticks) 327910515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 328010515SN/A 328110515SN/A---------- End Simulation Statistics ---------- 3282