stats.txt revision 11201
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.602568 # Number of seconds simulated 4sim_ticks 47602567962500 # Number of ticks simulated 5final_tick 47602567962500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 587112 # Simulator instruction rate (inst/s) 8host_op_rate 690746 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32025707663 # Simulator tick rate (ticks/s) 10host_mem_usage 784812 # Number of bytes of host memory used 11host_seconds 1486.39 # Real time elapsed on the host 12sim_insts 872675802 # Number of instructions simulated 13sim_ops 1026715135 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 97216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 105280 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3176436 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 39189384 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 13261312 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 67968 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 64704 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2473528 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 13920528 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 8902656 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 417088 # Number of bytes read from this memory 27system.physmem.bytes_read::total 81676100 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 3176436 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2473528 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 5649964 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 69006208 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 69026792 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1519 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1645 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 90039 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 612347 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 207208 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1062 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1011 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 38737 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 217521 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 139104 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6517 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1316710 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1078222 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1080796 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2042 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 2212 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 66728 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 823262 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 278584 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 1428 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 51962 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 292432 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 187020 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 8762 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1715792 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 66728 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 51962 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 118690 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1449632 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 432 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1450064 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1449632 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2042 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 2212 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 66728 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 823694 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 278584 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 1428 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 51962 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 292432 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 187020 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 8762 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3165856 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1316710 # Number of read requests accepted 84system.physmem.writeReqs 1080796 # Number of write requests accepted 85system.physmem.readBursts 1316710 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1080796 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 84239104 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 30336 # Total number of bytes read from write queue 89system.physmem.bytesWritten 69025088 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 81676100 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 69026792 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 474 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 461546 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 74138 # Per bank write bursts 96system.physmem.perBankRdBursts::1 82827 # Per bank write bursts 97system.physmem.perBankRdBursts::2 74957 # Per bank write bursts 98system.physmem.perBankRdBursts::3 82122 # Per bank write bursts 99system.physmem.perBankRdBursts::4 83077 # Per bank write bursts 100system.physmem.perBankRdBursts::5 87558 # Per bank write bursts 101system.physmem.perBankRdBursts::6 81167 # Per bank write bursts 102system.physmem.perBankRdBursts::7 84127 # Per bank write bursts 103system.physmem.perBankRdBursts::8 76730 # Per bank write bursts 104system.physmem.perBankRdBursts::9 122410 # Per bank write bursts 105system.physmem.perBankRdBursts::10 70954 # Per bank write bursts 106system.physmem.perBankRdBursts::11 80684 # Per bank write bursts 107system.physmem.perBankRdBursts::12 75912 # Per bank write bursts 108system.physmem.perBankRdBursts::13 81292 # Per bank write bursts 109system.physmem.perBankRdBursts::14 78761 # Per bank write bursts 110system.physmem.perBankRdBursts::15 79520 # Per bank write bursts 111system.physmem.perBankWrBursts::0 61777 # Per bank write bursts 112system.physmem.perBankWrBursts::1 69166 # Per bank write bursts 113system.physmem.perBankWrBursts::2 64147 # Per bank write bursts 114system.physmem.perBankWrBursts::3 68304 # Per bank write bursts 115system.physmem.perBankWrBursts::4 69323 # Per bank write bursts 116system.physmem.perBankWrBursts::5 73404 # Per bank write bursts 117system.physmem.perBankWrBursts::6 67894 # Per bank write bursts 118system.physmem.perBankWrBursts::7 70420 # Per bank write bursts 119system.physmem.perBankWrBursts::8 65275 # Per bank write bursts 120system.physmem.perBankWrBursts::9 69986 # Per bank write bursts 121system.physmem.perBankWrBursts::10 62072 # Per bank write bursts 122system.physmem.perBankWrBursts::11 68038 # Per bank write bursts 123system.physmem.perBankWrBursts::12 64002 # Per bank write bursts 124system.physmem.perBankWrBursts::13 68951 # Per bank write bursts 125system.physmem.perBankWrBursts::14 67347 # Per bank write bursts 126system.physmem.perBankWrBursts::15 68411 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 25 # Number of times write queue was full causing retry 129system.physmem.totGap 47602564597000 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 43195 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1273485 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1078222 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 1098528 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 69154 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 30759 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 26336 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 22457 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 19787 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 17170 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 15034 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 11894 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 1995 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 874 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 575 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 323 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 240 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 218 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 164 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 144 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 18244 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 20496 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 46518 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 53470 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 57648 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 60710 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 64016 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 65226 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 67393 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 67733 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 70106 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 73801 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 68996 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 68981 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 71721 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 66784 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 63773 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 62218 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 1690 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 1098 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 827 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 666 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 614 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 508 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 438 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 398 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 362 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 382 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 307 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 354 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 298 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 278 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 304 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 281 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 321 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 243 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 138 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 165 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 150 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 94 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 99 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 78 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 84 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 70 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 845861 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 181.192513 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 111.718720 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 240.356894 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 524023 61.95% 61.95% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 157589 18.63% 80.58% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 52244 6.18% 86.76% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 27763 3.28% 90.04% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 18582 2.20% 92.24% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 11693 1.38% 93.62% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 8942 1.06% 94.68% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 9176 1.08% 95.76% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 35849 4.24% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 845861 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 60416 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 21.786182 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 329.918437 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 60413 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::77824-81919 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 60416 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 60416 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 17.851513 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.268088 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 7.277078 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 56734 93.91% 93.91% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 1553 2.57% 96.48% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 255 0.42% 96.90% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 285 0.47% 97.37% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 70 0.12% 97.49% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 285 0.47% 97.96% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 159 0.26% 98.22% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 94 0.16% 98.38% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 78 0.13% 98.51% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 106 0.18% 98.68% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 41 0.07% 98.75% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 61 0.10% 98.85% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 428 0.71% 99.56% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 38 0.06% 99.62% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 49 0.08% 99.70% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 117 0.19% 99.90% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 11 0.02% 99.91% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 24 0.04% 99.97% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 3 0.00% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::152-155 3 0.00% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::156-159 5 0.01% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::total 60416 # Writes before turning the bus around for reads 299system.physmem.totQLat 28673044871 # Total ticks spent queuing 300system.physmem.totMemAccLat 53352469871 # Total ticks spent from burst creation until serviced by the DRAM 301system.physmem.totBusLat 6581180000 # Total ticks spent in databus transfers 302system.physmem.avgQLat 21784.12 # Average queueing delay per DRAM burst 303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 304system.physmem.avgMemAccLat 40534.12 # Average memory access latency per DRAM burst 305system.physmem.avgRdBW 1.77 # Average DRAM read bandwidth in MiByte/s 306system.physmem.avgWrBW 1.45 # Average achieved write bandwidth in MiByte/s 307system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s 308system.physmem.avgWrBWSys 1.45 # Average system write bandwidth in MiByte/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 310system.physmem.busUtil 0.03 # Data bus utilization in percentage 311system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 312system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 313system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing 314system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing 315system.physmem.readRowHits 1054044 # Number of row buffer hits during reads 316system.physmem.writeRowHits 494841 # Number of row buffer hits during writes 317system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads 318system.physmem.writeRowHitRate 45.88 # Row buffer hit rate for writes 319system.physmem.avgGap 19855034.61 # Average gap between requests 320system.physmem.pageHitRate 64.68 # Row buffer hit rate, read and write combined 321system.physmem_0.actEnergy 3265088400 # Energy for activate commands per rank (pJ) 322system.physmem_0.preEnergy 1781546250 # Energy for precharge commands per rank (pJ) 323system.physmem_0.readEnergy 5069789400 # Energy for read commands per rank (pJ) 324system.physmem_0.writeEnergy 3527867520 # Energy for write commands per rank (pJ) 325system.physmem_0.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ) 326system.physmem_0.actBackEnergy 1219382745750 # Energy for active background per rank (pJ) 327system.physmem_0.preBackEnergy 27491903982750 # Energy for precharge background per rank (pJ) 328system.physmem_0.totalEnergy 31834099035270 # Total energy per rank (pJ) 329system.physmem_0.averagePower 668.747581 # Core power per rank (mW) 330system.physmem_0.memoryStateTime::IDLE 45734675361714 # Time in different power states 331system.physmem_0.memoryStateTime::REF 1589554200000 # Time in different power states 332system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 333system.physmem_0.memoryStateTime::ACT 278338023286 # Time in different power states 334system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 335system.physmem_1.actEnergy 3129537600 # Energy for activate commands per rank (pJ) 336system.physmem_1.preEnergy 1707585000 # Energy for precharge commands per rank (pJ) 337system.physmem_1.readEnergy 5196804600 # Energy for read commands per rank (pJ) 338system.physmem_1.writeEnergy 3460818960 # Energy for write commands per rank (pJ) 339system.physmem_1.refreshEnergy 3109168015200 # Energy for refresh commands per rank (pJ) 340system.physmem_1.actBackEnergy 1215349697925 # Energy for active background per rank (pJ) 341system.physmem_1.preBackEnergy 27495441752250 # Energy for precharge background per rank (pJ) 342system.physmem_1.totalEnergy 31833454211535 # Total energy per rank (pJ) 343system.physmem_1.averagePower 668.734035 # Core power per rank (mW) 344system.physmem_1.memoryStateTime::IDLE 45740562014248 # Time in different power states 345system.physmem_1.memoryStateTime::REF 1589554200000 # Time in different power states 346system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 347system.physmem_1.memoryStateTime::ACT 272450963752 # Time in different power states 348system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 349system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 357system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 362system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 375system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 376system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 377system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 378system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 379system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 380system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 381system.cpu_clk_domain.clock 500 # Clock period in ticks 382system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 391system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 392system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 393system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 394system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 395system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 396system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 398system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 400system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 401system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 402system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 403system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 404system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 405system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 406system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 407system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 408system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 409system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 410system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 411system.cpu0.dtb.walker.walks 111926 # Table walker walks requested 412system.cpu0.dtb.walker.walksLong 111926 # Table walker walks initiated with long descriptors 413system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10169 # Level at which table walker walks with long descriptors terminate 414system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 86471 # Level at which table walker walks with long descriptors terminate 415system.cpu0.dtb.walker.walksSquashedBefore 18 # Table walks squashed before starting 416system.cpu0.dtb.walker.walkWaitTime::samples 111908 # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::mean 0.232334 # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::stdev 77.721788 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::0-2047 111907 100.00% 100.00% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::total 111908 # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkCompletionTime::samples 96658 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::mean 23040.705374 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::gmean 21274.900589 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::stdev 18509.319790 # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::0-65535 95612 98.92% 98.92% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::65536-131071 152 0.16% 99.08% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::131072-196607 763 0.79% 99.86% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::196608-262143 18 0.02% 99.88% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.92% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::327680-393215 23 0.02% 99.95% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::393216-458751 37 0.04% 99.99% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::total 96658 # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walksPending::samples 444719432 # Table walker pending requests distribution 439system.cpu0.dtb.walker.walksPending::mean -3.785405 # Table walker pending requests distribution 440system.cpu0.dtb.walker.walksPending::0 2128162704 478.54% 478.54% # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::1 -1683443272 -378.54% 100.00% # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::total 444719432 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walkPageSizes::4K 86471 89.48% 89.48% # Table walker page sizes translated 444system.cpu0.dtb.walker.walkPageSizes::2M 10169 10.52% 100.00% # Table walker page sizes translated 445system.cpu0.dtb.walker.walkPageSizes::total 96640 # Table walker page sizes translated 446system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 111926 # Table walker requests started/completed, data/inst 447system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 448system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 111926 # Table walker requests started/completed, data/inst 449system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96640 # Table walker requests started/completed, data/inst 450system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 451system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96640 # Table walker requests started/completed, data/inst 452system.cpu0.dtb.walker.walkRequestOrigin::total 208566 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.inst_hits 0 # ITB inst hits 454system.cpu0.dtb.inst_misses 0 # ITB inst misses 455system.cpu0.dtb.read_hits 87929647 # DTB read hits 456system.cpu0.dtb.read_misses 85158 # DTB read misses 457system.cpu0.dtb.write_hits 79744109 # DTB write hits 458system.cpu0.dtb.write_misses 26768 # DTB write misses 459system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 460system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 461system.cpu0.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID 462system.cpu0.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 463system.cpu0.dtb.flush_entries 37859 # Number of entries that have been flushed from TLB 464system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 465system.cpu0.dtb.prefetch_faults 3884 # Number of TLB faults due to prefetch 466system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu0.dtb.perms_faults 10087 # Number of TLB faults due to permissions restrictions 468system.cpu0.dtb.read_accesses 88014805 # DTB read accesses 469system.cpu0.dtb.write_accesses 79770877 # DTB write accesses 470system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 471system.cpu0.dtb.hits 167673756 # DTB hits 472system.cpu0.dtb.misses 111926 # DTB misses 473system.cpu0.dtb.accesses 167785682 # DTB accesses 474system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 475system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 483system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 484system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 485system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 486system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 487system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 488system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 489system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 490system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 491system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 492system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 493system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 494system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 495system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 496system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 497system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 498system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 499system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 500system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 501system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 502system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 503system.cpu0.itb.walker.walks 61252 # Table walker walks requested 504system.cpu0.itb.walker.walksLong 61252 # Table walker walks initiated with long descriptors 505system.cpu0.itb.walker.walksLongTerminationLevel::Level2 842 # Level at which table walker walks with long descriptors terminate 506system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54849 # Level at which table walker walks with long descriptors terminate 507system.cpu0.itb.walker.walkWaitTime::samples 61252 # Table walker wait (enqueue to first request) latency 508system.cpu0.itb.walker.walkWaitTime::0 61252 100.00% 100.00% # Table walker wait (enqueue to first request) latency 509system.cpu0.itb.walker.walkWaitTime::total 61252 # Table walker wait (enqueue to first request) latency 510system.cpu0.itb.walker.walkCompletionTime::samples 55691 # Table walker service (enqueue to completion) latency 511system.cpu0.itb.walker.walkCompletionTime::mean 26308.021045 # Table walker service (enqueue to completion) latency 512system.cpu0.itb.walker.walkCompletionTime::gmean 23499.981275 # Table walker service (enqueue to completion) latency 513system.cpu0.itb.walker.walkCompletionTime::stdev 25689.449100 # Table walker service (enqueue to completion) latency 514system.cpu0.itb.walker.walkCompletionTime::0-65535 54619 98.08% 98.08% # Table walker service (enqueue to completion) latency 515system.cpu0.itb.walker.walkCompletionTime::65536-131071 42 0.08% 98.15% # Table walker service (enqueue to completion) latency 516system.cpu0.itb.walker.walkCompletionTime::131072-196607 884 1.59% 99.74% # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::196608-262143 24 0.04% 99.78% # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.09% 99.87% # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.90% # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::393216-458751 35 0.06% 99.96% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::total 55691 # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walksPending::samples 1979242204 # Table walker pending requests distribution 527system.cpu0.itb.walker.walksPending::0 1979242204 100.00% 100.00% # Table walker pending requests distribution 528system.cpu0.itb.walker.walksPending::total 1979242204 # Table walker pending requests distribution 529system.cpu0.itb.walker.walkPageSizes::4K 54849 98.49% 98.49% # Table walker page sizes translated 530system.cpu0.itb.walker.walkPageSizes::2M 842 1.51% 100.00% # Table walker page sizes translated 531system.cpu0.itb.walker.walkPageSizes::total 55691 # Table walker page sizes translated 532system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 533system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61252 # Table walker requests started/completed, data/inst 534system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61252 # Table walker requests started/completed, data/inst 535system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 536system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55691 # Table walker requests started/completed, data/inst 537system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55691 # Table walker requests started/completed, data/inst 538system.cpu0.itb.walker.walkRequestOrigin::total 116943 # Table walker requests started/completed, data/inst 539system.cpu0.itb.inst_hits 467202921 # ITB inst hits 540system.cpu0.itb.inst_misses 61252 # ITB inst misses 541system.cpu0.itb.read_hits 0 # DTB read hits 542system.cpu0.itb.read_misses 0 # DTB read misses 543system.cpu0.itb.write_hits 0 # DTB write hits 544system.cpu0.itb.write_misses 0 # DTB write misses 545system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 546system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 547system.cpu0.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID 548system.cpu0.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 549system.cpu0.itb.flush_entries 27100 # Number of entries that have been flushed from TLB 550system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 551system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 552system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 553system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 554system.cpu0.itb.read_accesses 0 # DTB read accesses 555system.cpu0.itb.write_accesses 0 # DTB write accesses 556system.cpu0.itb.inst_accesses 467264173 # ITB inst accesses 557system.cpu0.itb.hits 467202921 # DTB hits 558system.cpu0.itb.misses 61252 # DTB misses 559system.cpu0.itb.accesses 467264173 # DTB accesses 560system.cpu0.numCycles 95205135902 # number of cpu cycles simulated 561system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 562system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 563system.cpu0.kern.inst.arm 0 # number of arm instructions executed 564system.cpu0.kern.inst.quiesce 5123 # number of quiesce instructions executed 565system.cpu0.committedInsts 466948479 # Number of instructions committed 566system.cpu0.committedOps 548389991 # Number of ops (including micro ops) committed 567system.cpu0.num_int_alu_accesses 504092161 # Number of integer alu accesses 568system.cpu0.num_fp_alu_accesses 464416 # Number of float alu accesses 569system.cpu0.num_func_calls 27983491 # number of times a function call or return occured 570system.cpu0.num_conditional_control_insts 70438282 # number of instructions that are conditional controls 571system.cpu0.num_int_insts 504092161 # number of integer instructions 572system.cpu0.num_fp_insts 464416 # number of float instructions 573system.cpu0.num_int_register_reads 728885661 # number of times the integer registers were read 574system.cpu0.num_int_register_writes 399652952 # number of times the integer registers were written 575system.cpu0.num_fp_register_reads 772857 # number of times the floating registers were read 576system.cpu0.num_fp_register_writes 344936 # number of times the floating registers were written 577system.cpu0.num_cc_register_reads 120908457 # number of times the CC registers were read 578system.cpu0.num_cc_register_writes 120465396 # number of times the CC registers were written 579system.cpu0.num_mem_refs 167663327 # number of memory refs 580system.cpu0.num_load_insts 87924608 # Number of load instructions 581system.cpu0.num_store_insts 79738719 # Number of store instructions 582system.cpu0.num_idle_cycles 93943889977.646729 # Number of idle cycles 583system.cpu0.num_busy_cycles 1261245924.353277 # Number of busy cycles 584system.cpu0.not_idle_fraction 0.013248 # Percentage of non-idle cycles 585system.cpu0.idle_fraction 0.986752 # Percentage of idle cycles 586system.cpu0.Branches 104008564 # Number of branches fetched 587system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 588system.cpu0.op_class::IntAlu 379698158 69.20% 69.20% # Class of executed instruction 589system.cpu0.op_class::IntMult 1212773 0.22% 69.42% # Class of executed instruction 590system.cpu0.op_class::IntDiv 66852 0.01% 69.43% # Class of executed instruction 591system.cpu0.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction 592system.cpu0.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction 593system.cpu0.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction 594system.cpu0.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction 595system.cpu0.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction 596system.cpu0.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction 597system.cpu0.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction 598system.cpu0.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction 599system.cpu0.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction 600system.cpu0.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction 601system.cpu0.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction 602system.cpu0.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction 603system.cpu0.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction 604system.cpu0.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction 605system.cpu0.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction 606system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction 607system.cpu0.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction 608system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.43% # Class of executed instruction 609system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction 610system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.43% # Class of executed instruction 611system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.43% # Class of executed instruction 612system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction 613system.cpu0.op_class::SimdFloatMisc 46447 0.01% 69.44% # Class of executed instruction 614system.cpu0.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction 615system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction 616system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction 617system.cpu0.op_class::MemRead 87924608 16.02% 85.47% # Class of executed instruction 618system.cpu0.op_class::MemWrite 79738719 14.53% 100.00% # Class of executed instruction 619system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 620system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 621system.cpu0.op_class::total 548687557 # Class of executed instruction 622system.cpu0.dcache.tags.replacements 5767473 # number of replacements 623system.cpu0.dcache.tags.tagsinuse 506.102777 # Cycle average of tags in use 624system.cpu0.dcache.tags.total_refs 161665939 # Total number of references to valid blocks. 625system.cpu0.dcache.tags.sampled_refs 5767985 # Sample count of references to valid blocks. 626system.cpu0.dcache.tags.avg_refs 28.028148 # Average number of references to valid blocks. 627system.cpu0.dcache.tags.warmup_cycle 6293818000 # Cycle when the warmup percentage was hit. 628system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.102777 # Average occupied blocks per requestor 629system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988482 # Average percentage of cache occupancy 630system.cpu0.dcache.tags.occ_percent::total 0.988482 # Average percentage of cache occupancy 631system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 632system.cpu0.dcache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 633system.cpu0.dcache.tags.age_task_id_blocks_1024::1 336 # Occupied blocks per task id 634system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id 635system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 636system.cpu0.dcache.tags.tag_accesses 341141490 # Number of tag accesses 637system.cpu0.dcache.tags.data_accesses 341141490 # Number of data accesses 638system.cpu0.dcache.ReadReq_hits::cpu0.data 81909684 # number of ReadReq hits 639system.cpu0.dcache.ReadReq_hits::total 81909684 # number of ReadReq hits 640system.cpu0.dcache.WriteReq_hits::cpu0.data 75364450 # number of WriteReq hits 641system.cpu0.dcache.WriteReq_hits::total 75364450 # number of WriteReq hits 642system.cpu0.dcache.SoftPFReq_hits::cpu0.data 195602 # number of SoftPFReq hits 643system.cpu0.dcache.SoftPFReq_hits::total 195602 # number of SoftPFReq hits 644system.cpu0.dcache.WriteLineReq_hits::cpu0.data 139312 # number of WriteLineReq hits 645system.cpu0.dcache.WriteLineReq_hits::total 139312 # number of WriteLineReq hits 646system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1827663 # number of LoadLockedReq hits 647system.cpu0.dcache.LoadLockedReq_hits::total 1827663 # number of LoadLockedReq hits 648system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798607 # number of StoreCondReq hits 649system.cpu0.dcache.StoreCondReq_hits::total 1798607 # number of StoreCondReq hits 650system.cpu0.dcache.demand_hits::cpu0.data 157274134 # number of demand (read+write) hits 651system.cpu0.dcache.demand_hits::total 157274134 # number of demand (read+write) hits 652system.cpu0.dcache.overall_hits::cpu0.data 157469736 # number of overall hits 653system.cpu0.dcache.overall_hits::total 157469736 # number of overall hits 654system.cpu0.dcache.ReadReq_misses::cpu0.data 3156555 # number of ReadReq misses 655system.cpu0.dcache.ReadReq_misses::total 3156555 # number of ReadReq misses 656system.cpu0.dcache.WriteReq_misses::cpu0.data 1440320 # number of WriteReq misses 657system.cpu0.dcache.WriteReq_misses::total 1440320 # number of WriteReq misses 658system.cpu0.dcache.SoftPFReq_misses::cpu0.data 651795 # number of SoftPFReq misses 659system.cpu0.dcache.SoftPFReq_misses::total 651795 # number of SoftPFReq misses 660system.cpu0.dcache.WriteLineReq_misses::cpu0.data 776738 # number of WriteLineReq misses 661system.cpu0.dcache.WriteLineReq_misses::total 776738 # number of WriteLineReq misses 662system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172749 # number of LoadLockedReq misses 663system.cpu0.dcache.LoadLockedReq_misses::total 172749 # number of LoadLockedReq misses 664system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200464 # number of StoreCondReq misses 665system.cpu0.dcache.StoreCondReq_misses::total 200464 # number of StoreCondReq misses 666system.cpu0.dcache.demand_misses::cpu0.data 4596875 # number of demand (read+write) misses 667system.cpu0.dcache.demand_misses::total 4596875 # number of demand (read+write) misses 668system.cpu0.dcache.overall_misses::cpu0.data 5248670 # number of overall misses 669system.cpu0.dcache.overall_misses::total 5248670 # number of overall misses 670system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 52100226500 # number of ReadReq miss cycles 671system.cpu0.dcache.ReadReq_miss_latency::total 52100226500 # number of ReadReq miss cycles 672system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36687284500 # number of WriteReq miss cycles 673system.cpu0.dcache.WriteReq_miss_latency::total 36687284500 # number of WriteReq miss cycles 674system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 65915448000 # number of WriteLineReq miss cycles 675system.cpu0.dcache.WriteLineReq_miss_latency::total 65915448000 # number of WriteLineReq miss cycles 676system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2830376000 # number of LoadLockedReq miss cycles 677system.cpu0.dcache.LoadLockedReq_miss_latency::total 2830376000 # number of LoadLockedReq miss cycles 678system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5792176500 # number of StoreCondReq miss cycles 679system.cpu0.dcache.StoreCondReq_miss_latency::total 5792176500 # number of StoreCondReq miss cycles 680system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4797000 # number of StoreCondFailReq miss cycles 681system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4797000 # number of StoreCondFailReq miss cycles 682system.cpu0.dcache.demand_miss_latency::cpu0.data 88787511000 # number of demand (read+write) miss cycles 683system.cpu0.dcache.demand_miss_latency::total 88787511000 # number of demand (read+write) miss cycles 684system.cpu0.dcache.overall_miss_latency::cpu0.data 88787511000 # number of overall miss cycles 685system.cpu0.dcache.overall_miss_latency::total 88787511000 # number of overall miss cycles 686system.cpu0.dcache.ReadReq_accesses::cpu0.data 85066239 # number of ReadReq accesses(hits+misses) 687system.cpu0.dcache.ReadReq_accesses::total 85066239 # number of ReadReq accesses(hits+misses) 688system.cpu0.dcache.WriteReq_accesses::cpu0.data 76804770 # number of WriteReq accesses(hits+misses) 689system.cpu0.dcache.WriteReq_accesses::total 76804770 # number of WriteReq accesses(hits+misses) 690system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 847397 # number of SoftPFReq accesses(hits+misses) 691system.cpu0.dcache.SoftPFReq_accesses::total 847397 # number of SoftPFReq accesses(hits+misses) 692system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 916050 # number of WriteLineReq accesses(hits+misses) 693system.cpu0.dcache.WriteLineReq_accesses::total 916050 # number of WriteLineReq accesses(hits+misses) 694system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2000412 # number of LoadLockedReq accesses(hits+misses) 695system.cpu0.dcache.LoadLockedReq_accesses::total 2000412 # number of LoadLockedReq accesses(hits+misses) 696system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1999071 # number of StoreCondReq accesses(hits+misses) 697system.cpu0.dcache.StoreCondReq_accesses::total 1999071 # number of StoreCondReq accesses(hits+misses) 698system.cpu0.dcache.demand_accesses::cpu0.data 161871009 # number of demand (read+write) accesses 699system.cpu0.dcache.demand_accesses::total 161871009 # number of demand (read+write) accesses 700system.cpu0.dcache.overall_accesses::cpu0.data 162718406 # number of overall (read+write) accesses 701system.cpu0.dcache.overall_accesses::total 162718406 # number of overall (read+write) accesses 702system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037107 # miss rate for ReadReq accesses 703system.cpu0.dcache.ReadReq_miss_rate::total 0.037107 # miss rate for ReadReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018753 # miss rate for WriteReq accesses 705system.cpu0.dcache.WriteReq_miss_rate::total 0.018753 # miss rate for WriteReq accesses 706system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.769173 # miss rate for SoftPFReq accesses 707system.cpu0.dcache.SoftPFReq_miss_rate::total 0.769173 # miss rate for SoftPFReq accesses 708system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.847921 # miss rate for WriteLineReq accesses 709system.cpu0.dcache.WriteLineReq_miss_rate::total 0.847921 # miss rate for WriteLineReq accesses 710system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086357 # miss rate for LoadLockedReq accesses 711system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086357 # miss rate for LoadLockedReq accesses 712system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100279 # miss rate for StoreCondReq accesses 713system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100279 # miss rate for StoreCondReq accesses 714system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028398 # miss rate for demand accesses 715system.cpu0.dcache.demand_miss_rate::total 0.028398 # miss rate for demand accesses 716system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032256 # miss rate for overall accesses 717system.cpu0.dcache.overall_miss_rate::total 0.032256 # miss rate for overall accesses 718system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16505.407477 # average ReadReq miss latency 719system.cpu0.dcache.ReadReq_avg_miss_latency::total 16505.407477 # average ReadReq miss latency 720system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25471.620543 # average WriteReq miss latency 721system.cpu0.dcache.WriteReq_avg_miss_latency::total 25471.620543 # average WriteReq miss latency 722system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 84861.881355 # average WriteLineReq miss latency 723system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 84861.881355 # average WriteLineReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16384.326393 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16384.326393 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28893.848771 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28893.848771 # average StoreCondReq miss latency 728system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 729system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 730system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19314.754262 # average overall miss latency 731system.cpu0.dcache.demand_avg_miss_latency::total 19314.754262 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16916.192293 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::total 16916.192293 # average overall miss latency 734system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 740system.cpu0.dcache.fast_writes 0 # number of fast writes performed 741system.cpu0.dcache.cache_copies 0 # number of cache copies performed 742system.cpu0.dcache.writebacks::writebacks 5767473 # number of writebacks 743system.cpu0.dcache.writebacks::total 5767473 # number of writebacks 744system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 27282 # number of ReadReq MSHR hits 745system.cpu0.dcache.ReadReq_mshr_hits::total 27282 # number of ReadReq MSHR hits 746system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21266 # number of WriteReq MSHR hits 747system.cpu0.dcache.WriteReq_mshr_hits::total 21266 # number of WriteReq MSHR hits 748system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44626 # number of LoadLockedReq MSHR hits 749system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44626 # number of LoadLockedReq MSHR hits 750system.cpu0.dcache.demand_mshr_hits::cpu0.data 48548 # number of demand (read+write) MSHR hits 751system.cpu0.dcache.demand_mshr_hits::total 48548 # number of demand (read+write) MSHR hits 752system.cpu0.dcache.overall_mshr_hits::cpu0.data 48548 # number of overall MSHR hits 753system.cpu0.dcache.overall_mshr_hits::total 48548 # number of overall MSHR hits 754system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3129273 # number of ReadReq MSHR misses 755system.cpu0.dcache.ReadReq_mshr_misses::total 3129273 # number of ReadReq MSHR misses 756system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1419054 # number of WriteReq MSHR misses 757system.cpu0.dcache.WriteReq_mshr_misses::total 1419054 # number of WriteReq MSHR misses 758system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 650511 # number of SoftPFReq MSHR misses 759system.cpu0.dcache.SoftPFReq_mshr_misses::total 650511 # number of SoftPFReq MSHR misses 760system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 776738 # number of WriteLineReq MSHR misses 761system.cpu0.dcache.WriteLineReq_mshr_misses::total 776738 # number of WriteLineReq MSHR misses 762system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 128123 # number of LoadLockedReq MSHR misses 763system.cpu0.dcache.LoadLockedReq_mshr_misses::total 128123 # number of LoadLockedReq MSHR misses 764system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200464 # number of StoreCondReq MSHR misses 765system.cpu0.dcache.StoreCondReq_mshr_misses::total 200464 # number of StoreCondReq MSHR misses 766system.cpu0.dcache.demand_mshr_misses::cpu0.data 4548327 # number of demand (read+write) MSHR misses 767system.cpu0.dcache.demand_mshr_misses::total 4548327 # number of demand (read+write) MSHR misses 768system.cpu0.dcache.overall_mshr_misses::cpu0.data 5198838 # number of overall MSHR misses 769system.cpu0.dcache.overall_mshr_misses::total 5198838 # number of overall MSHR misses 770system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15619 # number of ReadReq MSHR uncacheable 771system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15619 # number of ReadReq MSHR uncacheable 772system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16479 # number of WriteReq MSHR uncacheable 773system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16479 # number of WriteReq MSHR uncacheable 774system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32098 # number of overall MSHR uncacheable misses 775system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32098 # number of overall MSHR uncacheable misses 776system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 47104061500 # number of ReadReq MSHR miss cycles 777system.cpu0.dcache.ReadReq_mshr_miss_latency::total 47104061500 # number of ReadReq MSHR miss cycles 778system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34681725000 # number of WriteReq MSHR miss cycles 779system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34681725000 # number of WriteReq MSHR miss cycles 780system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 15920895000 # number of SoftPFReq MSHR miss cycles 781system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 15920895000 # number of SoftPFReq MSHR miss cycles 782system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 65138711000 # number of WriteLineReq MSHR miss cycles 783system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 65138711000 # number of WriteLineReq MSHR miss cycles 784system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1795303000 # number of LoadLockedReq MSHR miss cycles 785system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1795303000 # number of LoadLockedReq MSHR miss cycles 786system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5591766500 # number of StoreCondReq MSHR miss cycles 787system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5591766500 # number of StoreCondReq MSHR miss cycles 788system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4743000 # number of StoreCondFailReq MSHR miss cycles 789system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4743000 # number of StoreCondFailReq MSHR miss cycles 790system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 81785786500 # number of demand (read+write) MSHR miss cycles 791system.cpu0.dcache.demand_mshr_miss_latency::total 81785786500 # number of demand (read+write) MSHR miss cycles 792system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97706681500 # number of overall MSHR miss cycles 793system.cpu0.dcache.overall_mshr_miss_latency::total 97706681500 # number of overall MSHR miss cycles 794system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2690935500 # number of ReadReq MSHR uncacheable cycles 795system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2690935500 # number of ReadReq MSHR uncacheable cycles 796system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2795849000 # number of WriteReq MSHR uncacheable cycles 797system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2795849000 # number of WriteReq MSHR uncacheable cycles 798system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5486784500 # number of overall MSHR uncacheable cycles 799system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5486784500 # number of overall MSHR uncacheable cycles 800system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036786 # mshr miss rate for ReadReq accesses 801system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036786 # mshr miss rate for ReadReq accesses 802system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018476 # mshr miss rate for WriteReq accesses 803system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018476 # mshr miss rate for WriteReq accesses 804system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.767658 # mshr miss rate for SoftPFReq accesses 805system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767658 # mshr miss rate for SoftPFReq accesses 806system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.847921 # mshr miss rate for WriteLineReq accesses 807system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.847921 # mshr miss rate for WriteLineReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064048 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064048 # mshr miss rate for LoadLockedReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100279 # mshr miss rate for StoreCondReq accesses 811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100279 # mshr miss rate for StoreCondReq accesses 812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028098 # mshr miss rate for demand accesses 813system.cpu0.dcache.demand_mshr_miss_rate::total 0.028098 # mshr miss rate for demand accesses 814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031950 # mshr miss rate for overall accesses 815system.cpu0.dcache.overall_mshr_miss_rate::total 0.031950 # mshr miss rate for overall accesses 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15052.717197 # average ReadReq mshr miss latency 817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15052.717197 # average ReadReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24440.031880 # average WriteReq mshr miss latency 819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24440.031880 # average WriteReq mshr miss latency 820system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24474.443937 # average SoftPFReq mshr miss latency 821system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24474.443937 # average SoftPFReq mshr miss latency 822system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 83861.882643 # average WriteLineReq mshr miss latency 823system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 83861.882643 # average WriteLineReq mshr miss latency 824system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14012.339705 # average LoadLockedReq mshr miss latency 825system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14012.339705 # average LoadLockedReq mshr miss latency 826system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27894.118146 # average StoreCondReq mshr miss latency 827system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27894.118146 # average StoreCondReq mshr miss latency 828system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 829system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 830system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17981.509795 # average overall mshr miss latency 831system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17981.509795 # average overall mshr miss latency 832system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18793.946166 # average overall mshr miss latency 833system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18793.946166 # average overall mshr miss latency 834system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172286.029835 # average ReadReq mshr uncacheable latency 835system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172286.029835 # average ReadReq mshr uncacheable latency 836system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 169661.326537 # average WriteReq mshr uncacheable latency 837system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169661.326537 # average WriteReq mshr uncacheable latency 838system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 170938.516418 # average overall mshr uncacheable latency 839system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 170938.516418 # average overall mshr uncacheable latency 840system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 841system.cpu0.icache.tags.replacements 5175196 # number of replacements 842system.cpu0.icache.tags.tagsinuse 511.827248 # Cycle average of tags in use 843system.cpu0.icache.tags.total_refs 462027213 # Total number of references to valid blocks. 844system.cpu0.icache.tags.sampled_refs 5175708 # Sample count of references to valid blocks. 845system.cpu0.icache.tags.avg_refs 89.268408 # Average number of references to valid blocks. 846system.cpu0.icache.tags.warmup_cycle 59167640000 # Cycle when the warmup percentage was hit. 847system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.827248 # Average occupied blocks per requestor 848system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999663 # Average percentage of cache occupancy 849system.cpu0.icache.tags.occ_percent::total 0.999663 # Average percentage of cache occupancy 850system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 851system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 852system.cpu0.icache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id 853system.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id 854system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 855system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 856system.cpu0.icache.tags.tag_accesses 939581550 # Number of tag accesses 857system.cpu0.icache.tags.data_accesses 939581550 # Number of data accesses 858system.cpu0.icache.ReadReq_hits::cpu0.inst 462027213 # number of ReadReq hits 859system.cpu0.icache.ReadReq_hits::total 462027213 # number of ReadReq hits 860system.cpu0.icache.demand_hits::cpu0.inst 462027213 # number of demand (read+write) hits 861system.cpu0.icache.demand_hits::total 462027213 # number of demand (read+write) hits 862system.cpu0.icache.overall_hits::cpu0.inst 462027213 # number of overall hits 863system.cpu0.icache.overall_hits::total 462027213 # number of overall hits 864system.cpu0.icache.ReadReq_misses::cpu0.inst 5175708 # number of ReadReq misses 865system.cpu0.icache.ReadReq_misses::total 5175708 # number of ReadReq misses 866system.cpu0.icache.demand_misses::cpu0.inst 5175708 # number of demand (read+write) misses 867system.cpu0.icache.demand_misses::total 5175708 # number of demand (read+write) misses 868system.cpu0.icache.overall_misses::cpu0.inst 5175708 # number of overall misses 869system.cpu0.icache.overall_misses::total 5175708 # number of overall misses 870system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 57336545500 # number of ReadReq miss cycles 871system.cpu0.icache.ReadReq_miss_latency::total 57336545500 # number of ReadReq miss cycles 872system.cpu0.icache.demand_miss_latency::cpu0.inst 57336545500 # number of demand (read+write) miss cycles 873system.cpu0.icache.demand_miss_latency::total 57336545500 # number of demand (read+write) miss cycles 874system.cpu0.icache.overall_miss_latency::cpu0.inst 57336545500 # number of overall miss cycles 875system.cpu0.icache.overall_miss_latency::total 57336545500 # number of overall miss cycles 876system.cpu0.icache.ReadReq_accesses::cpu0.inst 467202921 # number of ReadReq accesses(hits+misses) 877system.cpu0.icache.ReadReq_accesses::total 467202921 # number of ReadReq accesses(hits+misses) 878system.cpu0.icache.demand_accesses::cpu0.inst 467202921 # number of demand (read+write) accesses 879system.cpu0.icache.demand_accesses::total 467202921 # number of demand (read+write) accesses 880system.cpu0.icache.overall_accesses::cpu0.inst 467202921 # number of overall (read+write) accesses 881system.cpu0.icache.overall_accesses::total 467202921 # number of overall (read+write) accesses 882system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011078 # miss rate for ReadReq accesses 883system.cpu0.icache.ReadReq_miss_rate::total 0.011078 # miss rate for ReadReq accesses 884system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011078 # miss rate for demand accesses 885system.cpu0.icache.demand_miss_rate::total 0.011078 # miss rate for demand accesses 886system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011078 # miss rate for overall accesses 887system.cpu0.icache.overall_miss_rate::total 0.011078 # miss rate for overall accesses 888system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11078.010100 # average ReadReq miss latency 889system.cpu0.icache.ReadReq_avg_miss_latency::total 11078.010100 # average ReadReq miss latency 890system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11078.010100 # average overall miss latency 891system.cpu0.icache.demand_avg_miss_latency::total 11078.010100 # average overall miss latency 892system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11078.010100 # average overall miss latency 893system.cpu0.icache.overall_avg_miss_latency::total 11078.010100 # average overall miss latency 894system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 895system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 896system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 897system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 898system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 899system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 900system.cpu0.icache.fast_writes 0 # number of fast writes performed 901system.cpu0.icache.cache_copies 0 # number of cache copies performed 902system.cpu0.icache.writebacks::writebacks 5175196 # number of writebacks 903system.cpu0.icache.writebacks::total 5175196 # number of writebacks 904system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5175708 # number of ReadReq MSHR misses 905system.cpu0.icache.ReadReq_mshr_misses::total 5175708 # number of ReadReq MSHR misses 906system.cpu0.icache.demand_mshr_misses::cpu0.inst 5175708 # number of demand (read+write) MSHR misses 907system.cpu0.icache.demand_mshr_misses::total 5175708 # number of demand (read+write) MSHR misses 908system.cpu0.icache.overall_mshr_misses::cpu0.inst 5175708 # number of overall MSHR misses 909system.cpu0.icache.overall_mshr_misses::total 5175708 # number of overall MSHR misses 910system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 911system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 912system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 913system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 914system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 54748691500 # number of ReadReq MSHR miss cycles 915system.cpu0.icache.ReadReq_mshr_miss_latency::total 54748691500 # number of ReadReq MSHR miss cycles 916system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 54748691500 # number of demand (read+write) MSHR miss cycles 917system.cpu0.icache.demand_mshr_miss_latency::total 54748691500 # number of demand (read+write) MSHR miss cycles 918system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 54748691500 # number of overall MSHR miss cycles 919system.cpu0.icache.overall_mshr_miss_latency::total 54748691500 # number of overall MSHR miss cycles 920system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of ReadReq MSHR uncacheable cycles 921system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5954209000 # number of ReadReq MSHR uncacheable cycles 922system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 5954209000 # number of overall MSHR uncacheable cycles 923system.cpu0.icache.overall_mshr_uncacheable_latency::total 5954209000 # number of overall MSHR uncacheable cycles 924system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for ReadReq accesses 925system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011078 # mshr miss rate for ReadReq accesses 926system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for demand accesses 927system.cpu0.icache.demand_mshr_miss_rate::total 0.011078 # mshr miss rate for demand accesses 928system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011078 # mshr miss rate for overall accesses 929system.cpu0.icache.overall_mshr_miss_rate::total 0.011078 # mshr miss rate for overall accesses 930system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average ReadReq mshr miss latency 931system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10578.010100 # average ReadReq mshr miss latency 932system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency 933system.cpu0.icache.demand_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency 934system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10578.010100 # average overall mshr miss latency 935system.cpu0.icache.overall_avg_mshr_miss_latency::total 10578.010100 # average overall mshr miss latency 936system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average ReadReq mshr uncacheable latency 937system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138068.614493 # average ReadReq mshr uncacheable latency 938system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138068.614493 # average overall mshr uncacheable latency 939system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138068.614493 # average overall mshr uncacheable latency 940system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 941system.cpu0.l2cache.prefetcher.num_hwpf_issued 7857654 # number of hwpf issued 942system.cpu0.l2cache.prefetcher.pfIdentified 7857701 # number of prefetch candidates identified 943system.cpu0.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue 944system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 945system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 946system.cpu0.l2cache.prefetcher.pfSpanPage 1019611 # number of prefetches not generated due to page crossing 947system.cpu0.l2cache.tags.replacements 2391891 # number of replacements 948system.cpu0.l2cache.tags.tagsinuse 16167.019190 # Cycle average of tags in use 949system.cpu0.l2cache.tags.total_refs 15476667 # Total number of references to valid blocks. 950system.cpu0.l2cache.tags.sampled_refs 2407580 # Sample count of references to valid blocks. 951system.cpu0.l2cache.tags.avg_refs 6.428309 # Average number of references to valid blocks. 952system.cpu0.l2cache.tags.warmup_cycle 8764179000 # Cycle when the warmup percentage was hit. 953system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.445219 # Average occupied blocks per requestor 954system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.058428 # Average occupied blocks per requestor 955system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 79.612606 # Average occupied blocks per requestor 956system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 747.902937 # Average occupied blocks per requestor 957system.cpu0.l2cache.tags.occ_percent::writebacks 0.932522 # Average percentage of cache occupancy 958system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003727 # Average percentage of cache occupancy 959system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004859 # Average percentage of cache occupancy 960system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.045648 # Average percentage of cache occupancy 961system.cpu0.l2cache.tags.occ_percent::total 0.986757 # Average percentage of cache occupancy 962system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1309 # Occupied blocks per task id 963system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 964system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14303 # Occupied blocks per task id 965system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 143 # Occupied blocks per task id 966system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 161 # Occupied blocks per task id 967system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 649 # Occupied blocks per task id 968system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 356 # Occupied blocks per task id 969system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 28 # Occupied blocks per task id 970system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id 971system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id 972system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 973system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 827 # Occupied blocks per task id 974system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4392 # Occupied blocks per task id 975system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6793 # Occupied blocks per task id 976system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2165 # Occupied blocks per task id 977system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079895 # Percentage of cache occupancy per task id 978system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 979system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.872986 # Percentage of cache occupancy per task id 980system.cpu0.l2cache.tags.tag_accesses 371635811 # Number of tag accesses 981system.cpu0.l2cache.tags.data_accesses 371635811 # Number of data accesses 982system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 264720 # number of ReadReq hits 983system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157843 # number of ReadReq hits 984system.cpu0.l2cache.ReadReq_hits::total 422563 # number of ReadReq hits 985system.cpu0.l2cache.WritebackDirty_hits::writebacks 3807067 # number of WritebackDirty hits 986system.cpu0.l2cache.WritebackDirty_hits::total 3807067 # number of WritebackDirty hits 987system.cpu0.l2cache.WritebackClean_hits::writebacks 7134877 # number of WritebackClean hits 988system.cpu0.l2cache.WritebackClean_hits::total 7134877 # number of WritebackClean hits 989system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 457 # number of UpgradeReq hits 990system.cpu0.l2cache.UpgradeReq_hits::total 457 # number of UpgradeReq hits 991system.cpu0.l2cache.ReadExReq_hits::cpu0.data 928109 # number of ReadExReq hits 992system.cpu0.l2cache.ReadExReq_hits::total 928109 # number of ReadExReq hits 993system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4693228 # number of ReadCleanReq hits 994system.cpu0.l2cache.ReadCleanReq_hits::total 4693228 # number of ReadCleanReq hits 995system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2960524 # number of ReadSharedReq hits 996system.cpu0.l2cache.ReadSharedReq_hits::total 2960524 # number of ReadSharedReq hits 997system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 208597 # number of InvalidateReq hits 998system.cpu0.l2cache.InvalidateReq_hits::total 208597 # number of InvalidateReq hits 999system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 264720 # number of demand (read+write) hits 1000system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157843 # number of demand (read+write) hits 1001system.cpu0.l2cache.demand_hits::cpu0.inst 4693228 # number of demand (read+write) hits 1002system.cpu0.l2cache.demand_hits::cpu0.data 3888633 # number of demand (read+write) hits 1003system.cpu0.l2cache.demand_hits::total 9004424 # number of demand (read+write) hits 1004system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 264720 # number of overall hits 1005system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157843 # number of overall hits 1006system.cpu0.l2cache.overall_hits::cpu0.inst 4693228 # number of overall hits 1007system.cpu0.l2cache.overall_hits::cpu0.data 3888633 # number of overall hits 1008system.cpu0.l2cache.overall_hits::total 9004424 # number of overall hits 1009system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10067 # number of ReadReq misses 1010system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8203 # number of ReadReq misses 1011system.cpu0.l2cache.ReadReq_misses::total 18270 # number of ReadReq misses 1012system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 246628 # number of UpgradeReq misses 1013system.cpu0.l2cache.UpgradeReq_misses::total 246628 # number of UpgradeReq misses 1014system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200453 # number of SCUpgradeReq misses 1015system.cpu0.l2cache.SCUpgradeReq_misses::total 200453 # number of SCUpgradeReq misses 1016system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses 1017system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses 1018system.cpu0.l2cache.ReadExReq_misses::cpu0.data 262909 # number of ReadExReq misses 1019system.cpu0.l2cache.ReadExReq_misses::total 262909 # number of ReadExReq misses 1020system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 482480 # number of ReadCleanReq misses 1021system.cpu0.l2cache.ReadCleanReq_misses::total 482480 # number of ReadCleanReq misses 1022system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 947383 # number of ReadSharedReq misses 1023system.cpu0.l2cache.ReadSharedReq_misses::total 947383 # number of ReadSharedReq misses 1024system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 566022 # number of InvalidateReq misses 1025system.cpu0.l2cache.InvalidateReq_misses::total 566022 # number of InvalidateReq misses 1026system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10067 # number of demand (read+write) misses 1027system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8203 # number of demand (read+write) misses 1028system.cpu0.l2cache.demand_misses::cpu0.inst 482480 # number of demand (read+write) misses 1029system.cpu0.l2cache.demand_misses::cpu0.data 1210292 # number of demand (read+write) misses 1030system.cpu0.l2cache.demand_misses::total 1711042 # number of demand (read+write) misses 1031system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10067 # number of overall misses 1032system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8203 # number of overall misses 1033system.cpu0.l2cache.overall_misses::cpu0.inst 482480 # number of overall misses 1034system.cpu0.l2cache.overall_misses::cpu0.data 1210292 # number of overall misses 1035system.cpu0.l2cache.overall_misses::total 1711042 # number of overall misses 1036system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 425309500 # number of ReadReq miss cycles 1037system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 392962000 # number of ReadReq miss cycles 1038system.cpu0.l2cache.ReadReq_miss_latency::total 818271500 # number of ReadReq miss cycles 1039system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3546049000 # number of UpgradeReq miss cycles 1040system.cpu0.l2cache.UpgradeReq_miss_latency::total 3546049000 # number of UpgradeReq miss cycles 1041system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2066053000 # number of SCUpgradeReq miss cycles 1042system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2066053000 # number of SCUpgradeReq miss cycles 1043system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4661500 # number of SCUpgradeFailReq miss cycles 1044system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4661500 # number of SCUpgradeFailReq miss cycles 1045system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16748515499 # number of ReadExReq miss cycles 1046system.cpu0.l2cache.ReadExReq_miss_latency::total 16748515499 # number of ReadExReq miss cycles 1047system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 18800277000 # number of ReadCleanReq miss cycles 1048system.cpu0.l2cache.ReadCleanReq_miss_latency::total 18800277000 # number of ReadCleanReq miss cycles 1049system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 39672427000 # number of ReadSharedReq miss cycles 1050system.cpu0.l2cache.ReadSharedReq_miss_latency::total 39672427000 # number of ReadSharedReq miss cycles 1051system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 62566205500 # number of InvalidateReq miss cycles 1052system.cpu0.l2cache.InvalidateReq_miss_latency::total 62566205500 # number of InvalidateReq miss cycles 1053system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 425309500 # number of demand (read+write) miss cycles 1054system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 392962000 # number of demand (read+write) miss cycles 1055system.cpu0.l2cache.demand_miss_latency::cpu0.inst 18800277000 # number of demand (read+write) miss cycles 1056system.cpu0.l2cache.demand_miss_latency::cpu0.data 56420942499 # number of demand (read+write) miss cycles 1057system.cpu0.l2cache.demand_miss_latency::total 76039490999 # number of demand (read+write) miss cycles 1058system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 425309500 # number of overall miss cycles 1059system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 392962000 # number of overall miss cycles 1060system.cpu0.l2cache.overall_miss_latency::cpu0.inst 18800277000 # number of overall miss cycles 1061system.cpu0.l2cache.overall_miss_latency::cpu0.data 56420942499 # number of overall miss cycles 1062system.cpu0.l2cache.overall_miss_latency::total 76039490999 # number of overall miss cycles 1063system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 274787 # number of ReadReq accesses(hits+misses) 1064system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 166046 # number of ReadReq accesses(hits+misses) 1065system.cpu0.l2cache.ReadReq_accesses::total 440833 # number of ReadReq accesses(hits+misses) 1066system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3807067 # number of WritebackDirty accesses(hits+misses) 1067system.cpu0.l2cache.WritebackDirty_accesses::total 3807067 # number of WritebackDirty accesses(hits+misses) 1068system.cpu0.l2cache.WritebackClean_accesses::writebacks 7134877 # number of WritebackClean accesses(hits+misses) 1069system.cpu0.l2cache.WritebackClean_accesses::total 7134877 # number of WritebackClean accesses(hits+misses) 1070system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 247085 # number of UpgradeReq accesses(hits+misses) 1071system.cpu0.l2cache.UpgradeReq_accesses::total 247085 # number of UpgradeReq accesses(hits+misses) 1072system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200453 # number of SCUpgradeReq accesses(hits+misses) 1073system.cpu0.l2cache.SCUpgradeReq_accesses::total 200453 # number of SCUpgradeReq accesses(hits+misses) 1074system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) 1075system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) 1076system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1191018 # number of ReadExReq accesses(hits+misses) 1077system.cpu0.l2cache.ReadExReq_accesses::total 1191018 # number of ReadExReq accesses(hits+misses) 1078system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5175708 # number of ReadCleanReq accesses(hits+misses) 1079system.cpu0.l2cache.ReadCleanReq_accesses::total 5175708 # number of ReadCleanReq accesses(hits+misses) 1080system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3907907 # number of ReadSharedReq accesses(hits+misses) 1081system.cpu0.l2cache.ReadSharedReq_accesses::total 3907907 # number of ReadSharedReq accesses(hits+misses) 1082system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 774619 # number of InvalidateReq accesses(hits+misses) 1083system.cpu0.l2cache.InvalidateReq_accesses::total 774619 # number of InvalidateReq accesses(hits+misses) 1084system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 274787 # number of demand (read+write) accesses 1085system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 166046 # number of demand (read+write) accesses 1086system.cpu0.l2cache.demand_accesses::cpu0.inst 5175708 # number of demand (read+write) accesses 1087system.cpu0.l2cache.demand_accesses::cpu0.data 5098925 # number of demand (read+write) accesses 1088system.cpu0.l2cache.demand_accesses::total 10715466 # number of demand (read+write) accesses 1089system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 274787 # number of overall (read+write) accesses 1090system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 166046 # number of overall (read+write) accesses 1091system.cpu0.l2cache.overall_accesses::cpu0.inst 5175708 # number of overall (read+write) accesses 1092system.cpu0.l2cache.overall_accesses::cpu0.data 5098925 # number of overall (read+write) accesses 1093system.cpu0.l2cache.overall_accesses::total 10715466 # number of overall (read+write) accesses 1094system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.036636 # miss rate for ReadReq accesses 1095system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049402 # miss rate for ReadReq accesses 1096system.cpu0.l2cache.ReadReq_miss_rate::total 0.041444 # miss rate for ReadReq accesses 1097system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998150 # miss rate for UpgradeReq accesses 1098system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998150 # miss rate for UpgradeReq accesses 1099system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1100system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1101system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1102system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1103system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.220743 # miss rate for ReadExReq accesses 1104system.cpu0.l2cache.ReadExReq_miss_rate::total 0.220743 # miss rate for ReadExReq accesses 1105system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.093220 # miss rate for ReadCleanReq accesses 1106system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.093220 # miss rate for ReadCleanReq accesses 1107system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.242427 # miss rate for ReadSharedReq accesses 1108system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.242427 # miss rate for ReadSharedReq accesses 1109system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.730710 # miss rate for InvalidateReq accesses 1110system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.730710 # miss rate for InvalidateReq accesses 1111system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.036636 # miss rate for demand accesses 1112system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049402 # miss rate for demand accesses 1113system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.093220 # miss rate for demand accesses 1114system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237362 # miss rate for demand accesses 1115system.cpu0.l2cache.demand_miss_rate::total 0.159680 # miss rate for demand accesses 1116system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.036636 # miss rate for overall accesses 1117system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049402 # miss rate for overall accesses 1118system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.093220 # miss rate for overall accesses 1119system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237362 # miss rate for overall accesses 1120system.cpu0.l2cache.overall_miss_rate::total 0.159680 # miss rate for overall accesses 1121system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 42247.889143 # average ReadReq miss latency 1122system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47904.669024 # average ReadReq miss latency 1123system.cpu0.l2cache.ReadReq_avg_miss_latency::total 44787.712096 # average ReadReq miss latency 1124system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 14378.128193 # average UpgradeReq miss latency 1125system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 14378.128193 # average UpgradeReq miss latency 1126system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10306.919827 # average SCUpgradeReq miss latency 1127system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10306.919827 # average SCUpgradeReq miss latency 1128system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 423772.727273 # average SCUpgradeFailReq miss latency 1129system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 423772.727273 # average SCUpgradeFailReq miss latency 1130system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63704.610717 # average ReadExReq miss latency 1131system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63704.610717 # average ReadExReq miss latency 1132system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38965.919831 # average ReadCleanReq miss latency 1133system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38965.919831 # average ReadCleanReq miss latency 1134system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41875.806300 # average ReadSharedReq miss latency 1135system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41875.806300 # average ReadSharedReq miss latency 1136system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 110536.702637 # average InvalidateReq miss latency 1137system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 110536.702637 # average InvalidateReq miss latency 1138system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 42247.889143 # average overall miss latency 1139system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47904.669024 # average overall miss latency 1140system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38965.919831 # average overall miss latency 1141system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 46617.628224 # average overall miss latency 1142system.cpu0.l2cache.demand_avg_miss_latency::total 44440.458504 # average overall miss latency 1143system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 42247.889143 # average overall miss latency 1144system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47904.669024 # average overall miss latency 1145system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38965.919831 # average overall miss latency 1146system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 46617.628224 # average overall miss latency 1147system.cpu0.l2cache.overall_avg_miss_latency::total 44440.458504 # average overall miss latency 1148system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1149system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1150system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1151system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1152system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1153system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1154system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1155system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1156system.cpu0.l2cache.writebacks::writebacks 1521426 # number of writebacks 1157system.cpu0.l2cache.writebacks::total 1521426 # number of writebacks 1158system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5411 # number of ReadExReq MSHR hits 1159system.cpu0.l2cache.ReadExReq_mshr_hits::total 5411 # number of ReadExReq MSHR hits 1160system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 533 # number of ReadSharedReq MSHR hits 1161system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 533 # number of ReadSharedReq MSHR hits 1162system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5944 # number of demand (read+write) MSHR hits 1163system.cpu0.l2cache.demand_mshr_hits::total 5944 # number of demand (read+write) MSHR hits 1164system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5944 # number of overall MSHR hits 1165system.cpu0.l2cache.overall_mshr_hits::total 5944 # number of overall MSHR hits 1166system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10067 # number of ReadReq MSHR misses 1167system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8203 # number of ReadReq MSHR misses 1168system.cpu0.l2cache.ReadReq_mshr_misses::total 18270 # number of ReadReq MSHR misses 1169system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 721686 # number of HardPFReq MSHR misses 1170system.cpu0.l2cache.HardPFReq_mshr_misses::total 721686 # number of HardPFReq MSHR misses 1171system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 246628 # number of UpgradeReq MSHR misses 1172system.cpu0.l2cache.UpgradeReq_mshr_misses::total 246628 # number of UpgradeReq MSHR misses 1173system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 200453 # number of SCUpgradeReq MSHR misses 1174system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 200453 # number of SCUpgradeReq MSHR misses 1175system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses 1176system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses 1177system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 257498 # number of ReadExReq MSHR misses 1178system.cpu0.l2cache.ReadExReq_mshr_misses::total 257498 # number of ReadExReq MSHR misses 1179system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 482480 # number of ReadCleanReq MSHR misses 1180system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 482480 # number of ReadCleanReq MSHR misses 1181system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 946850 # number of ReadSharedReq MSHR misses 1182system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 946850 # number of ReadSharedReq MSHR misses 1183system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 566022 # number of InvalidateReq MSHR misses 1184system.cpu0.l2cache.InvalidateReq_mshr_misses::total 566022 # number of InvalidateReq MSHR misses 1185system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10067 # number of demand (read+write) MSHR misses 1186system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8203 # number of demand (read+write) MSHR misses 1187system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 482480 # number of demand (read+write) MSHR misses 1188system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1204348 # number of demand (read+write) MSHR misses 1189system.cpu0.l2cache.demand_mshr_misses::total 1705098 # number of demand (read+write) MSHR misses 1190system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10067 # number of overall MSHR misses 1191system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8203 # number of overall MSHR misses 1192system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 482480 # number of overall MSHR misses 1193system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1204348 # number of overall MSHR misses 1194system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 721686 # number of overall MSHR misses 1195system.cpu0.l2cache.overall_mshr_misses::total 2426784 # number of overall MSHR misses 1196system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 1197system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15619 # number of ReadReq MSHR uncacheable 1198system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 58744 # number of ReadReq MSHR uncacheable 1199system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16479 # number of WriteReq MSHR uncacheable 1200system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16479 # number of WriteReq MSHR uncacheable 1201system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 1202system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 32098 # number of overall MSHR uncacheable misses 1203system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 75223 # number of overall MSHR uncacheable misses 1204system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 364907500 # number of ReadReq MSHR miss cycles 1205system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 343744000 # number of ReadReq MSHR miss cycles 1206system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 708651500 # number of ReadReq MSHR miss cycles 1207system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38668799279 # number of HardPFReq MSHR miss cycles 1208system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38668799279 # number of HardPFReq MSHR miss cycles 1209system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7913903000 # number of UpgradeReq MSHR miss cycles 1210system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7913903000 # number of UpgradeReq MSHR miss cycles 1211system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4087252500 # number of SCUpgradeReq MSHR miss cycles 1212system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4087252500 # number of SCUpgradeReq MSHR miss cycles 1213system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4337500 # number of SCUpgradeFailReq MSHR miss cycles 1214system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4337500 # number of SCUpgradeFailReq MSHR miss cycles 1215system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14600636999 # number of ReadExReq MSHR miss cycles 1216system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14600636999 # number of ReadExReq MSHR miss cycles 1217system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 15905397000 # number of ReadCleanReq MSHR miss cycles 1218system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 15905397000 # number of ReadCleanReq MSHR miss cycles 1219system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 33944380000 # number of ReadSharedReq MSHR miss cycles 1220system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 33944380000 # number of ReadSharedReq MSHR miss cycles 1221system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 59170079500 # number of InvalidateReq MSHR miss cycles 1222system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 59170079500 # number of InvalidateReq MSHR miss cycles 1223system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 364907500 # number of demand (read+write) MSHR miss cycles 1224system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 343744000 # number of demand (read+write) MSHR miss cycles 1225system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15905397000 # number of demand (read+write) MSHR miss cycles 1226system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 48545016999 # number of demand (read+write) MSHR miss cycles 1227system.cpu0.l2cache.demand_mshr_miss_latency::total 65159065499 # number of demand (read+write) MSHR miss cycles 1228system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 364907500 # number of overall MSHR miss cycles 1229system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 343744000 # number of overall MSHR miss cycles 1230system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15905397000 # number of overall MSHR miss cycles 1231system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 48545016999 # number of overall MSHR miss cycles 1232system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38668799279 # number of overall MSHR miss cycles 1233system.cpu0.l2cache.overall_mshr_miss_latency::total 103827864778 # number of overall MSHR miss cycles 1234system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of ReadReq MSHR uncacheable cycles 1235system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2565627500 # number of ReadReq MSHR uncacheable cycles 1236system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8196399000 # number of ReadReq MSHR uncacheable cycles 1237system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2671857000 # number of WriteReq MSHR uncacheable cycles 1238system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2671857000 # number of WriteReq MSHR uncacheable cycles 1239system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 5630771500 # number of overall MSHR uncacheable cycles 1240system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5237484500 # number of overall MSHR uncacheable cycles 1241system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10868256000 # number of overall MSHR uncacheable cycles 1242system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.036636 # mshr miss rate for ReadReq accesses 1243system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049402 # mshr miss rate for ReadReq accesses 1244system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.041444 # mshr miss rate for ReadReq accesses 1245system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1246system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1247system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998150 # mshr miss rate for UpgradeReq accesses 1248system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998150 # mshr miss rate for UpgradeReq accesses 1249system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1250system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1251system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1252system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1253system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216200 # mshr miss rate for ReadExReq accesses 1254system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216200 # mshr miss rate for ReadExReq accesses 1255system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.093220 # mshr miss rate for ReadCleanReq accesses 1256system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093220 # mshr miss rate for ReadCleanReq accesses 1257system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242291 # mshr miss rate for ReadSharedReq accesses 1258system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242291 # mshr miss rate for ReadSharedReq accesses 1259system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.730710 # mshr miss rate for InvalidateReq accesses 1260system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.730710 # mshr miss rate for InvalidateReq accesses 1261system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.036636 # mshr miss rate for demand accesses 1262system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049402 # mshr miss rate for demand accesses 1263system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.093220 # mshr miss rate for demand accesses 1264system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.236196 # mshr miss rate for demand accesses 1265system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159125 # mshr miss rate for demand accesses 1266system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.036636 # mshr miss rate for overall accesses 1267system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049402 # mshr miss rate for overall accesses 1268system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.093220 # mshr miss rate for overall accesses 1269system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.236196 # mshr miss rate for overall accesses 1270system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1271system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226475 # mshr miss rate for overall accesses 1272system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average ReadReq mshr miss latency 1273system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average ReadReq mshr miss latency 1274system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38787.712096 # average ReadReq mshr miss latency 1275system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average HardPFReq mshr miss latency 1276system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53581.196364 # average HardPFReq mshr miss latency 1277system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 32088.420617 # average UpgradeReq mshr miss latency 1278system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32088.420617 # average UpgradeReq mshr miss latency 1279system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.078971 # average SCUpgradeReq mshr miss latency 1280system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20390.078971 # average SCUpgradeReq mshr miss latency 1281system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 394318.181818 # average SCUpgradeFailReq mshr miss latency 1282system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 394318.181818 # average SCUpgradeFailReq mshr miss latency 1283system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56701.943312 # average ReadExReq mshr miss latency 1284system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56701.943312 # average ReadExReq mshr miss latency 1285system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average ReadCleanReq mshr miss latency 1286system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32965.919831 # average ReadCleanReq mshr miss latency 1287system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35849.796694 # average ReadSharedReq mshr miss latency 1288system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35849.796694 # average ReadSharedReq mshr miss latency 1289system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 104536.713237 # average InvalidateReq mshr miss latency 1290system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 104536.713237 # average InvalidateReq mshr miss latency 1291system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency 1292system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency 1293system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency 1294system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency 1295system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 38214.264224 # average overall mshr miss latency 1296system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36247.889143 # average overall mshr miss latency 1297system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 41904.669024 # average overall mshr miss latency 1298system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32965.919831 # average overall mshr miss latency 1299system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40308.131038 # average overall mshr miss latency 1300system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53581.196364 # average overall mshr miss latency 1301system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 42784.139329 # average overall mshr miss latency 1302system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average ReadReq mshr uncacheable latency 1303system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164263.237083 # average ReadReq mshr uncacheable latency 1304system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139527.424077 # average ReadReq mshr uncacheable latency 1305system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162137.083561 # average WriteReq mshr uncacheable latency 1306system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162137.083561 # average WriteReq mshr uncacheable latency 1307system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130568.614493 # average overall mshr uncacheable latency 1308system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 163171.677363 # average overall mshr uncacheable latency 1309system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144480.491339 # average overall mshr uncacheable latency 1310system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1311system.cpu0.toL2Bus.snoop_filter.tot_requests 22685684 # Total number of requests made to the snoop filter. 1312system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11636633 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1313system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 725 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1314system.cpu0.toL2Bus.snoop_filter.tot_snoops 1868386 # Total number of snoops made to the snoop filter. 1315system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1868205 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1316system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 181 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1317system.cpu0.toL2Bus.trans_dist::ReadReq 566458 # Transaction distribution 1318system.cpu0.toL2Bus.trans_dist::ReadResp 9760546 # Transaction distribution 1319system.cpu0.toL2Bus.trans_dist::WriteReq 16479 # Transaction distribution 1320system.cpu0.toL2Bus.trans_dist::WriteResp 16479 # Transaction distribution 1321system.cpu0.toL2Bus.trans_dist::WritebackDirty 5331858 # Transaction distribution 1322system.cpu0.toL2Bus.trans_dist::WritebackClean 7134877 # Transaction distribution 1323system.cpu0.toL2Bus.trans_dist::CleanEvict 2347214 # Transaction distribution 1324system.cpu0.toL2Bus.trans_dist::HardPFReq 886122 # Transaction distribution 1325system.cpu0.toL2Bus.trans_dist::UpgradeReq 438453 # Transaction distribution 1326system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361903 # Transaction distribution 1327system.cpu0.toL2Bus.trans_dist::UpgradeResp 524601 # Transaction distribution 1328system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 85 # Transaction distribution 1329system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution 1330system.cpu0.toL2Bus.trans_dist::ReadExReq 1264261 # Transaction distribution 1331system.cpu0.toL2Bus.trans_dist::ReadExResp 1203854 # Transaction distribution 1332system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5175708 # Transaction distribution 1333system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4797612 # Transaction distribution 1334system.cpu0.toL2Bus.trans_dist::InvalidateReq 779730 # Transaction distribution 1335system.cpu0.toL2Bus.trans_dist::InvalidateResp 774618 # Transaction distribution 1336system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15612584 # Packet count per connected master and slave (bytes) 1337system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18673898 # Packet count per connected master and slave (bytes) 1338system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 348811 # Packet count per connected master and slave (bytes) 1339system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 599734 # Packet count per connected master and slave (bytes) 1340system.cpu0.toL2Bus.pkt_count::total 35235027 # Packet count per connected master and slave (bytes) 1341system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662612564 # Cumulative packet size per connected master and slave (bytes) 1342system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 703409885 # Cumulative packet size per connected master and slave (bytes) 1343system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328368 # Cumulative packet size per connected master and slave (bytes) 1344system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2198296 # Cumulative packet size per connected master and slave (bytes) 1345system.cpu0.toL2Bus.pkt_size::total 1369549113 # Cumulative packet size per connected master and slave (bytes) 1346system.cpu0.toL2Bus.snoops 6346450 # Total snoops (count) 1347system.cpu0.toL2Bus.snoop_fanout::samples 18158816 # Request fanout histogram 1348system.cpu0.toL2Bus.snoop_fanout::mean 0.116500 # Request fanout histogram 1349system.cpu0.toL2Bus.snoop_fanout::stdev 0.320855 # Request fanout histogram 1350system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1351system.cpu0.toL2Bus.snoop_fanout::0 16043491 88.35% 88.35% # Request fanout histogram 1352system.cpu0.toL2Bus.snoop_fanout::1 2115144 11.65% 100.00% # Request fanout histogram 1353system.cpu0.toL2Bus.snoop_fanout::2 181 0.00% 100.00% # Request fanout histogram 1354system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1355system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1356system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1357system.cpu0.toL2Bus.snoop_fanout::total 18158816 # Request fanout histogram 1358system.cpu0.toL2Bus.reqLayer0.occupancy 22462112497 # Layer occupancy (ticks) 1359system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1360system.cpu0.toL2Bus.snoopLayer0.occupancy 223807892 # Layer occupancy (ticks) 1361system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1362system.cpu0.toL2Bus.respLayer0.occupancy 7806687000 # Layer occupancy (ticks) 1363system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1364system.cpu0.toL2Bus.respLayer1.occupancy 8283648998 # Layer occupancy (ticks) 1365system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1366system.cpu0.toL2Bus.respLayer2.occupancy 182765499 # Layer occupancy (ticks) 1367system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1368system.cpu0.toL2Bus.respLayer3.occupancy 324947000 # Layer occupancy (ticks) 1369system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1370system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1371system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1372system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1373system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1374system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1375system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1376system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1377system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1378system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1379system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1380system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1381system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1382system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1383system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1384system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1385system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1386system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1387system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1388system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1389system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1390system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1391system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1392system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1393system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1394system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1395system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1396system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1397system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1398system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1399system.cpu1.dtb.walker.walks 92112 # Table walker walks requested 1400system.cpu1.dtb.walker.walksLong 92112 # Table walker walks initiated with long descriptors 1401system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 7185 # Level at which table walker walks with long descriptors terminate 1402system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 70441 # Level at which table walker walks with long descriptors terminate 1403system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting 1404system.cpu1.dtb.walker.walkWaitTime::samples 92107 # Table walker wait (enqueue to first request) latency 1405system.cpu1.dtb.walker.walkWaitTime::mean 0.086856 # Table walker wait (enqueue to first request) latency 1406system.cpu1.dtb.walker.walkWaitTime::stdev 26.359895 # Table walker wait (enqueue to first request) latency 1407system.cpu1.dtb.walker.walkWaitTime::0-511 92106 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1408system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1409system.cpu1.dtb.walker.walkWaitTime::total 92107 # Table walker wait (enqueue to first request) latency 1410system.cpu1.dtb.walker.walkCompletionTime::samples 77631 # Table walker service (enqueue to completion) latency 1411system.cpu1.dtb.walker.walkCompletionTime::mean 22794.154397 # Table walker service (enqueue to completion) latency 1412system.cpu1.dtb.walker.walkCompletionTime::gmean 21108.718713 # Table walker service (enqueue to completion) latency 1413system.cpu1.dtb.walker.walkCompletionTime::stdev 17037.529740 # Table walker service (enqueue to completion) latency 1414system.cpu1.dtb.walker.walkCompletionTime::0-65535 76846 98.99% 98.99% # Table walker service (enqueue to completion) latency 1415system.cpu1.dtb.walker.walkCompletionTime::65536-131071 174 0.22% 99.21% # Table walker service (enqueue to completion) latency 1416system.cpu1.dtb.walker.walkCompletionTime::131072-196607 527 0.68% 99.89% # Table walker service (enqueue to completion) latency 1417system.cpu1.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.91% # Table walker service (enqueue to completion) latency 1418system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.95% # Table walker service (enqueue to completion) latency 1419system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.96% # Table walker service (enqueue to completion) latency 1420system.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.02% 99.99% # Table walker service (enqueue to completion) latency 1421system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1422system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 1423system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1424system.cpu1.dtb.walker.walkCompletionTime::total 77631 # Table walker service (enqueue to completion) latency 1425system.cpu1.dtb.walker.walksPending::samples -5456316576 # Table walker pending requests distribution 1426system.cpu1.dtb.walker.walksPending::mean 0.616394 # Table walker pending requests distribution 1427system.cpu1.dtb.walker.walksPending::stdev 0.486264 # Table walker pending requests distribution 1428system.cpu1.dtb.walker.walksPending::0 -2093077220 38.36% 38.36% # Table walker pending requests distribution 1429system.cpu1.dtb.walker.walksPending::1 -3363239356 61.64% 100.00% # Table walker pending requests distribution 1430system.cpu1.dtb.walker.walksPending::total -5456316576 # Table walker pending requests distribution 1431system.cpu1.dtb.walker.walkPageSizes::4K 70442 90.74% 90.74% # Table walker page sizes translated 1432system.cpu1.dtb.walker.walkPageSizes::2M 7185 9.26% 100.00% # Table walker page sizes translated 1433system.cpu1.dtb.walker.walkPageSizes::total 77627 # Table walker page sizes translated 1434system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92112 # Table walker requests started/completed, data/inst 1435system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1436system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92112 # Table walker requests started/completed, data/inst 1437system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 77627 # Table walker requests started/completed, data/inst 1438system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1439system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 77627 # Table walker requests started/completed, data/inst 1440system.cpu1.dtb.walker.walkRequestOrigin::total 169739 # Table walker requests started/completed, data/inst 1441system.cpu1.dtb.inst_hits 0 # ITB inst hits 1442system.cpu1.dtb.inst_misses 0 # ITB inst misses 1443system.cpu1.dtb.read_hits 76812549 # DTB read hits 1444system.cpu1.dtb.read_misses 67403 # DTB read misses 1445system.cpu1.dtb.write_hits 69811450 # DTB write hits 1446system.cpu1.dtb.write_misses 24709 # DTB write misses 1447system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1448system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1449system.cpu1.dtb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID 1450system.cpu1.dtb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 1451system.cpu1.dtb.flush_entries 34729 # Number of entries that have been flushed from TLB 1452system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1453system.cpu1.dtb.prefetch_faults 4304 # Number of TLB faults due to prefetch 1454system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1455system.cpu1.dtb.perms_faults 9295 # Number of TLB faults due to permissions restrictions 1456system.cpu1.dtb.read_accesses 76879952 # DTB read accesses 1457system.cpu1.dtb.write_accesses 69836159 # DTB write accesses 1458system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1459system.cpu1.dtb.hits 146623999 # DTB hits 1460system.cpu1.dtb.misses 92112 # DTB misses 1461system.cpu1.dtb.accesses 146716111 # DTB accesses 1462system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1463system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1464system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1465system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1466system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1467system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1468system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1469system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1470system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1471system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1472system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1473system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1474system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1475system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1476system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1477system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1478system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1479system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1480system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1481system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1482system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1483system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1484system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1485system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1486system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1487system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1488system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1489system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1490system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1491system.cpu1.itb.walker.walks 54749 # Table walker walks requested 1492system.cpu1.itb.walker.walksLong 54749 # Table walker walks initiated with long descriptors 1493system.cpu1.itb.walker.walksLongTerminationLevel::Level2 360 # Level at which table walker walks with long descriptors terminate 1494system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate 1495system.cpu1.itb.walker.walkWaitTime::samples 54749 # Table walker wait (enqueue to first request) latency 1496system.cpu1.itb.walker.walkWaitTime::0 54749 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1497system.cpu1.itb.walker.walkWaitTime::total 54749 # Table walker wait (enqueue to first request) latency 1498system.cpu1.itb.walker.walkCompletionTime::samples 49571 # Table walker service (enqueue to completion) latency 1499system.cpu1.itb.walker.walkCompletionTime::mean 25509.592302 # Table walker service (enqueue to completion) latency 1500system.cpu1.itb.walker.walkCompletionTime::gmean 23251.815503 # Table walker service (enqueue to completion) latency 1501system.cpu1.itb.walker.walkCompletionTime::stdev 21686.807401 # Table walker service (enqueue to completion) latency 1502system.cpu1.itb.walker.walkCompletionTime::0-65535 48865 98.58% 98.58% # Table walker service (enqueue to completion) latency 1503system.cpu1.itb.walker.walkCompletionTime::65536-131071 34 0.07% 98.64% # Table walker service (enqueue to completion) latency 1504system.cpu1.itb.walker.walkCompletionTime::131072-196607 581 1.17% 99.82% # Table walker service (enqueue to completion) latency 1505system.cpu1.itb.walker.walkCompletionTime::196608-262143 14 0.03% 99.84% # Table walker service (enqueue to completion) latency 1506system.cpu1.itb.walker.walkCompletionTime::262144-327679 29 0.06% 99.90% # Table walker service (enqueue to completion) latency 1507system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.03% 99.94% # Table walker service (enqueue to completion) latency 1508system.cpu1.itb.walker.walkCompletionTime::393216-458751 25 0.05% 99.99% # Table walker service (enqueue to completion) latency 1509system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 1510system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1511system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1512system.cpu1.itb.walker.walkCompletionTime::total 49571 # Table walker service (enqueue to completion) latency 1513system.cpu1.itb.walker.walksPending::samples -2103779220 # Table walker pending requests distribution 1514system.cpu1.itb.walker.walksPending::0 -2103779220 100.00% 100.00% # Table walker pending requests distribution 1515system.cpu1.itb.walker.walksPending::total -2103779220 # Table walker pending requests distribution 1516system.cpu1.itb.walker.walkPageSizes::4K 49211 99.27% 99.27% # Table walker page sizes translated 1517system.cpu1.itb.walker.walkPageSizes::2M 360 0.73% 100.00% # Table walker page sizes translated 1518system.cpu1.itb.walker.walkPageSizes::total 49571 # Table walker page sizes translated 1519system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1520system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 54749 # Table walker requests started/completed, data/inst 1521system.cpu1.itb.walker.walkRequestOrigin_Requested::total 54749 # Table walker requests started/completed, data/inst 1522system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1523system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49571 # Table walker requests started/completed, data/inst 1524system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49571 # Table walker requests started/completed, data/inst 1525system.cpu1.itb.walker.walkRequestOrigin::total 104320 # Table walker requests started/completed, data/inst 1526system.cpu1.itb.inst_hits 406021553 # ITB inst hits 1527system.cpu1.itb.inst_misses 54749 # ITB inst misses 1528system.cpu1.itb.read_hits 0 # DTB read hits 1529system.cpu1.itb.read_misses 0 # DTB read misses 1530system.cpu1.itb.write_hits 0 # DTB write hits 1531system.cpu1.itb.write_misses 0 # DTB write misses 1532system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1533system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1534system.cpu1.itb.flush_tlb_mva_asid 39890 # Number of times TLB was flushed by MVA & ASID 1535system.cpu1.itb.flush_tlb_asid 1034 # Number of times TLB was flushed by ASID 1536system.cpu1.itb.flush_entries 24319 # Number of entries that have been flushed from TLB 1537system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1538system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1539system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1540system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1541system.cpu1.itb.read_accesses 0 # DTB read accesses 1542system.cpu1.itb.write_accesses 0 # DTB write accesses 1543system.cpu1.itb.inst_accesses 406076302 # ITB inst accesses 1544system.cpu1.itb.hits 406021553 # DTB hits 1545system.cpu1.itb.misses 54749 # DTB misses 1546system.cpu1.itb.accesses 406076302 # DTB accesses 1547system.cpu1.numCycles 95205135925 # number of cpu cycles simulated 1548system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1549system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1550system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1551system.cpu1.kern.inst.quiesce 14029 # number of quiesce instructions executed 1552system.cpu1.committedInsts 405727323 # Number of instructions committed 1553system.cpu1.committedOps 478325144 # Number of ops (including micro ops) committed 1554system.cpu1.num_int_alu_accesses 439907771 # Number of integer alu accesses 1555system.cpu1.num_fp_alu_accesses 446670 # Number of float alu accesses 1556system.cpu1.num_func_calls 24605699 # number of times a function call or return occured 1557system.cpu1.num_conditional_control_insts 61596178 # number of instructions that are conditional controls 1558system.cpu1.num_int_insts 439907771 # number of integer instructions 1559system.cpu1.num_fp_insts 446670 # number of float instructions 1560system.cpu1.num_int_register_reads 637924838 # number of times the integer registers were read 1561system.cpu1.num_int_register_writes 348926241 # number of times the integer registers were written 1562system.cpu1.num_fp_register_reads 708486 # number of times the floating registers were read 1563system.cpu1.num_fp_register_writes 403472 # number of times the floating registers were written 1564system.cpu1.num_cc_register_reads 104772444 # number of times the CC registers were read 1565system.cpu1.num_cc_register_writes 104573998 # number of times the CC registers were written 1566system.cpu1.num_mem_refs 146614371 # number of memory refs 1567system.cpu1.num_load_insts 76808885 # Number of load instructions 1568system.cpu1.num_store_insts 69805486 # Number of store instructions 1569system.cpu1.num_idle_cycles 94195407146.248016 # Number of idle cycles 1570system.cpu1.num_busy_cycles 1009728778.751979 # Number of busy cycles 1571system.cpu1.not_idle_fraction 0.010606 # Percentage of non-idle cycles 1572system.cpu1.idle_fraction 0.989394 # Percentage of idle cycles 1573system.cpu1.Branches 90553045 # Number of branches fetched 1574system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 1575system.cpu1.op_class::IntAlu 330876771 69.13% 69.13% # Class of executed instruction 1576system.cpu1.op_class::IntMult 1002715 0.21% 69.34% # Class of executed instruction 1577system.cpu1.op_class::IntDiv 57816 0.01% 69.35% # Class of executed instruction 1578system.cpu1.op_class::FloatAdd 0 0.00% 69.35% # Class of executed instruction 1579system.cpu1.op_class::FloatCmp 0 0.00% 69.35% # Class of executed instruction 1580system.cpu1.op_class::FloatCvt 0 0.00% 69.35% # Class of executed instruction 1581system.cpu1.op_class::FloatMult 0 0.00% 69.35% # Class of executed instruction 1582system.cpu1.op_class::FloatDiv 0 0.00% 69.35% # Class of executed instruction 1583system.cpu1.op_class::FloatSqrt 0 0.00% 69.35% # Class of executed instruction 1584system.cpu1.op_class::SimdAdd 0 0.00% 69.35% # Class of executed instruction 1585system.cpu1.op_class::SimdAddAcc 0 0.00% 69.35% # Class of executed instruction 1586system.cpu1.op_class::SimdAlu 0 0.00% 69.35% # Class of executed instruction 1587system.cpu1.op_class::SimdCmp 0 0.00% 69.35% # Class of executed instruction 1588system.cpu1.op_class::SimdCvt 0 0.00% 69.35% # Class of executed instruction 1589system.cpu1.op_class::SimdMisc 0 0.00% 69.35% # Class of executed instruction 1590system.cpu1.op_class::SimdMult 0 0.00% 69.35% # Class of executed instruction 1591system.cpu1.op_class::SimdMultAcc 0 0.00% 69.35% # Class of executed instruction 1592system.cpu1.op_class::SimdShift 0 0.00% 69.35% # Class of executed instruction 1593system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.35% # Class of executed instruction 1594system.cpu1.op_class::SimdSqrt 0 0.00% 69.35% # Class of executed instruction 1595system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.35% # Class of executed instruction 1596system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.35% # Class of executed instruction 1597system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.35% # Class of executed instruction 1598system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.35% # Class of executed instruction 1599system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.35% # Class of executed instruction 1600system.cpu1.op_class::SimdFloatMisc 67767 0.01% 69.37% # Class of executed instruction 1601system.cpu1.op_class::SimdFloatMult 0 0.00% 69.37% # Class of executed instruction 1602system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.37% # Class of executed instruction 1603system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.37% # Class of executed instruction 1604system.cpu1.op_class::MemRead 76808885 16.05% 85.42% # Class of executed instruction 1605system.cpu1.op_class::MemWrite 69805486 14.58% 100.00% # Class of executed instruction 1606system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1607system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1608system.cpu1.op_class::total 478619483 # Class of executed instruction 1609system.cpu1.dcache.tags.replacements 4731492 # number of replacements 1610system.cpu1.dcache.tags.tagsinuse 440.215275 # Cycle average of tags in use 1611system.cpu1.dcache.tags.total_refs 141682703 # Total number of references to valid blocks. 1612system.cpu1.dcache.tags.sampled_refs 4732003 # Sample count of references to valid blocks. 1613system.cpu1.dcache.tags.avg_refs 29.941381 # Average number of references to valid blocks. 1614system.cpu1.dcache.tags.warmup_cycle 8408412782000 # Cycle when the warmup percentage was hit. 1615system.cpu1.dcache.tags.occ_blocks::cpu1.data 440.215275 # Average occupied blocks per requestor 1616system.cpu1.dcache.tags.occ_percent::cpu1.data 0.859795 # Average percentage of cache occupancy 1617system.cpu1.dcache.tags.occ_percent::total 0.859795 # Average percentage of cache occupancy 1618system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 1619system.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 1620system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id 1621system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 1622system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 1623system.cpu1.dcache.tags.tag_accesses 297963795 # Number of tag accesses 1624system.cpu1.dcache.tags.data_accesses 297963795 # Number of data accesses 1625system.cpu1.dcache.ReadReq_hits::cpu1.data 71617652 # number of ReadReq hits 1626system.cpu1.dcache.ReadReq_hits::total 71617652 # number of ReadReq hits 1627system.cpu1.dcache.WriteReq_hits::cpu1.data 66171444 # number of WriteReq hits 1628system.cpu1.dcache.WriteReq_hits::total 66171444 # number of WriteReq hits 1629system.cpu1.dcache.SoftPFReq_hits::cpu1.data 174206 # number of SoftPFReq hits 1630system.cpu1.dcache.SoftPFReq_hits::total 174206 # number of SoftPFReq hits 1631system.cpu1.dcache.WriteLineReq_hits::cpu1.data 185116 # number of WriteLineReq hits 1632system.cpu1.dcache.WriteLineReq_hits::total 185116 # number of WriteLineReq hits 1633system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1590024 # number of LoadLockedReq hits 1634system.cpu1.dcache.LoadLockedReq_hits::total 1590024 # number of LoadLockedReq hits 1635system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1548743 # number of StoreCondReq hits 1636system.cpu1.dcache.StoreCondReq_hits::total 1548743 # number of StoreCondReq hits 1637system.cpu1.dcache.demand_hits::cpu1.data 137789096 # number of demand (read+write) hits 1638system.cpu1.dcache.demand_hits::total 137789096 # number of demand (read+write) hits 1639system.cpu1.dcache.overall_hits::cpu1.data 137963302 # number of overall hits 1640system.cpu1.dcache.overall_hits::total 137963302 # number of overall hits 1641system.cpu1.dcache.ReadReq_misses::cpu1.data 2694357 # number of ReadReq misses 1642system.cpu1.dcache.ReadReq_misses::total 2694357 # number of ReadReq misses 1643system.cpu1.dcache.WriteReq_misses::cpu1.data 1213090 # number of WriteReq misses 1644system.cpu1.dcache.WriteReq_misses::total 1213090 # number of WriteReq misses 1645system.cpu1.dcache.SoftPFReq_misses::cpu1.data 558664 # number of SoftPFReq misses 1646system.cpu1.dcache.SoftPFReq_misses::total 558664 # number of SoftPFReq misses 1647system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466794 # number of WriteLineReq misses 1648system.cpu1.dcache.WriteLineReq_misses::total 466794 # number of WriteLineReq misses 1649system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 154053 # number of LoadLockedReq misses 1650system.cpu1.dcache.LoadLockedReq_misses::total 154053 # number of LoadLockedReq misses 1651system.cpu1.dcache.StoreCondReq_misses::cpu1.data 194127 # number of StoreCondReq misses 1652system.cpu1.dcache.StoreCondReq_misses::total 194127 # number of StoreCondReq misses 1653system.cpu1.dcache.demand_misses::cpu1.data 3907447 # number of demand (read+write) misses 1654system.cpu1.dcache.demand_misses::total 3907447 # number of demand (read+write) misses 1655system.cpu1.dcache.overall_misses::cpu1.data 4466111 # number of overall misses 1656system.cpu1.dcache.overall_misses::total 4466111 # number of overall misses 1657system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 40157954500 # number of ReadReq miss cycles 1658system.cpu1.dcache.ReadReq_miss_latency::total 40157954500 # number of ReadReq miss cycles 1659system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 28157091500 # number of WriteReq miss cycles 1660system.cpu1.dcache.WriteReq_miss_latency::total 28157091500 # number of WriteReq miss cycles 1661system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20750751000 # number of WriteLineReq miss cycles 1662system.cpu1.dcache.WriteLineReq_miss_latency::total 20750751000 # number of WriteLineReq miss cycles 1663system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2380134500 # number of LoadLockedReq miss cycles 1664system.cpu1.dcache.LoadLockedReq_miss_latency::total 2380134500 # number of LoadLockedReq miss cycles 1665system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5345117000 # number of StoreCondReq miss cycles 1666system.cpu1.dcache.StoreCondReq_miss_latency::total 5345117000 # number of StoreCondReq miss cycles 1667system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6929500 # number of StoreCondFailReq miss cycles 1668system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6929500 # number of StoreCondFailReq miss cycles 1669system.cpu1.dcache.demand_miss_latency::cpu1.data 68315046000 # number of demand (read+write) miss cycles 1670system.cpu1.dcache.demand_miss_latency::total 68315046000 # number of demand (read+write) miss cycles 1671system.cpu1.dcache.overall_miss_latency::cpu1.data 68315046000 # number of overall miss cycles 1672system.cpu1.dcache.overall_miss_latency::total 68315046000 # number of overall miss cycles 1673system.cpu1.dcache.ReadReq_accesses::cpu1.data 74312009 # number of ReadReq accesses(hits+misses) 1674system.cpu1.dcache.ReadReq_accesses::total 74312009 # number of ReadReq accesses(hits+misses) 1675system.cpu1.dcache.WriteReq_accesses::cpu1.data 67384534 # number of WriteReq accesses(hits+misses) 1676system.cpu1.dcache.WriteReq_accesses::total 67384534 # number of WriteReq accesses(hits+misses) 1677system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 732870 # number of SoftPFReq accesses(hits+misses) 1678system.cpu1.dcache.SoftPFReq_accesses::total 732870 # number of SoftPFReq accesses(hits+misses) 1679system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 651910 # number of WriteLineReq accesses(hits+misses) 1680system.cpu1.dcache.WriteLineReq_accesses::total 651910 # number of WriteLineReq accesses(hits+misses) 1681system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1744077 # number of LoadLockedReq accesses(hits+misses) 1682system.cpu1.dcache.LoadLockedReq_accesses::total 1744077 # number of LoadLockedReq accesses(hits+misses) 1683system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1742870 # number of StoreCondReq accesses(hits+misses) 1684system.cpu1.dcache.StoreCondReq_accesses::total 1742870 # number of StoreCondReq accesses(hits+misses) 1685system.cpu1.dcache.demand_accesses::cpu1.data 141696543 # number of demand (read+write) accesses 1686system.cpu1.dcache.demand_accesses::total 141696543 # number of demand (read+write) accesses 1687system.cpu1.dcache.overall_accesses::cpu1.data 142429413 # number of overall (read+write) accesses 1688system.cpu1.dcache.overall_accesses::total 142429413 # number of overall (read+write) accesses 1689system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036257 # miss rate for ReadReq accesses 1690system.cpu1.dcache.ReadReq_miss_rate::total 0.036257 # miss rate for ReadReq accesses 1691system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018002 # miss rate for WriteReq accesses 1692system.cpu1.dcache.WriteReq_miss_rate::total 0.018002 # miss rate for WriteReq accesses 1693system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.762296 # miss rate for SoftPFReq accesses 1694system.cpu1.dcache.SoftPFReq_miss_rate::total 0.762296 # miss rate for SoftPFReq accesses 1695system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.716041 # miss rate for WriteLineReq accesses 1696system.cpu1.dcache.WriteLineReq_miss_rate::total 0.716041 # miss rate for WriteLineReq accesses 1697system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088329 # miss rate for LoadLockedReq accesses 1698system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088329 # miss rate for LoadLockedReq accesses 1699system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111384 # miss rate for StoreCondReq accesses 1700system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111384 # miss rate for StoreCondReq accesses 1701system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027576 # miss rate for demand accesses 1702system.cpu1.dcache.demand_miss_rate::total 0.027576 # miss rate for demand accesses 1703system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031357 # miss rate for overall accesses 1704system.cpu1.dcache.overall_miss_rate::total 0.031357 # miss rate for overall accesses 1705system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14904.466817 # average ReadReq miss latency 1706system.cpu1.dcache.ReadReq_avg_miss_latency::total 14904.466817 # average ReadReq miss latency 1707system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23211.049057 # average WriteReq miss latency 1708system.cpu1.dcache.WriteReq_avg_miss_latency::total 23211.049057 # average WriteReq miss latency 1709system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 44453.765473 # average WriteLineReq miss latency 1710system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 44453.765473 # average WriteLineReq miss latency 1711system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15450.101588 # average LoadLockedReq miss latency 1712system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15450.101588 # average LoadLockedReq miss latency 1713system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27534.124568 # average StoreCondReq miss latency 1714system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27534.124568 # average StoreCondReq miss latency 1715system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1716system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1717system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17483.294335 # average overall miss latency 1718system.cpu1.dcache.demand_avg_miss_latency::total 17483.294335 # average overall miss latency 1719system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.316191 # average overall miss latency 1720system.cpu1.dcache.overall_avg_miss_latency::total 15296.316191 # average overall miss latency 1721system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1722system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1723system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1724system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1725system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1726system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1727system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1728system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1729system.cpu1.dcache.writebacks::writebacks 4731492 # number of writebacks 1730system.cpu1.dcache.writebacks::total 4731492 # number of writebacks 1731system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13909 # number of ReadReq MSHR hits 1732system.cpu1.dcache.ReadReq_mshr_hits::total 13909 # number of ReadReq MSHR hits 1733system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 323 # number of WriteReq MSHR hits 1734system.cpu1.dcache.WriteReq_mshr_hits::total 323 # number of WriteReq MSHR hits 1735system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44168 # number of LoadLockedReq MSHR hits 1736system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44168 # number of LoadLockedReq MSHR hits 1737system.cpu1.dcache.demand_mshr_hits::cpu1.data 14232 # number of demand (read+write) MSHR hits 1738system.cpu1.dcache.demand_mshr_hits::total 14232 # number of demand (read+write) MSHR hits 1739system.cpu1.dcache.overall_mshr_hits::cpu1.data 14232 # number of overall MSHR hits 1740system.cpu1.dcache.overall_mshr_hits::total 14232 # number of overall MSHR hits 1741system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2680448 # number of ReadReq MSHR misses 1742system.cpu1.dcache.ReadReq_mshr_misses::total 2680448 # number of ReadReq MSHR misses 1743system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1212767 # number of WriteReq MSHR misses 1744system.cpu1.dcache.WriteReq_mshr_misses::total 1212767 # number of WriteReq MSHR misses 1745system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 558664 # number of SoftPFReq MSHR misses 1746system.cpu1.dcache.SoftPFReq_mshr_misses::total 558664 # number of SoftPFReq MSHR misses 1747system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466794 # number of WriteLineReq MSHR misses 1748system.cpu1.dcache.WriteLineReq_mshr_misses::total 466794 # number of WriteLineReq MSHR misses 1749system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109885 # number of LoadLockedReq MSHR misses 1750system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109885 # number of LoadLockedReq MSHR misses 1751system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 194127 # number of StoreCondReq MSHR misses 1752system.cpu1.dcache.StoreCondReq_mshr_misses::total 194127 # number of StoreCondReq MSHR misses 1753system.cpu1.dcache.demand_mshr_misses::cpu1.data 3893215 # number of demand (read+write) MSHR misses 1754system.cpu1.dcache.demand_mshr_misses::total 3893215 # number of demand (read+write) MSHR misses 1755system.cpu1.dcache.overall_mshr_misses::cpu1.data 4451879 # number of overall MSHR misses 1756system.cpu1.dcache.overall_mshr_misses::total 4451879 # number of overall MSHR misses 1757system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 23611 # number of ReadReq MSHR uncacheable 1758system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23611 # number of ReadReq MSHR uncacheable 1759system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22620 # number of WriteReq MSHR uncacheable 1760system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22620 # number of WriteReq MSHR uncacheable 1761system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 46231 # number of overall MSHR uncacheable misses 1762system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46231 # number of overall MSHR uncacheable misses 1763system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36382655000 # number of ReadReq MSHR miss cycles 1764system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36382655000 # number of ReadReq MSHR miss cycles 1765system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26928760500 # number of WriteReq MSHR miss cycles 1766system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26928760500 # number of WriteReq MSHR miss cycles 1767system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12609688500 # number of SoftPFReq MSHR miss cycles 1768system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12609688500 # number of SoftPFReq MSHR miss cycles 1769system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 20283957000 # number of WriteLineReq MSHR miss cycles 1770system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 20283957000 # number of WriteLineReq MSHR miss cycles 1771system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1540230500 # number of LoadLockedReq MSHR miss cycles 1772system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1540230500 # number of LoadLockedReq MSHR miss cycles 1773system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5151064000 # number of StoreCondReq MSHR miss cycles 1774system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5151064000 # number of StoreCondReq MSHR miss cycles 1775system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6855500 # number of StoreCondFailReq MSHR miss cycles 1776system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6855500 # number of StoreCondFailReq MSHR miss cycles 1777system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63311415500 # number of demand (read+write) MSHR miss cycles 1778system.cpu1.dcache.demand_mshr_miss_latency::total 63311415500 # number of demand (read+write) MSHR miss cycles 1779system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75921104000 # number of overall MSHR miss cycles 1780system.cpu1.dcache.overall_mshr_miss_latency::total 75921104000 # number of overall MSHR miss cycles 1781system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4287453000 # number of ReadReq MSHR uncacheable cycles 1782system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4287453000 # number of ReadReq MSHR uncacheable cycles 1783system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 4160988000 # number of WriteReq MSHR uncacheable cycles 1784system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 4160988000 # number of WriteReq MSHR uncacheable cycles 1785system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8448441000 # number of overall MSHR uncacheable cycles 1786system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8448441000 # number of overall MSHR uncacheable cycles 1787system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036070 # mshr miss rate for ReadReq accesses 1788system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036070 # mshr miss rate for ReadReq accesses 1789system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017998 # mshr miss rate for WriteReq accesses 1790system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017998 # mshr miss rate for WriteReq accesses 1791system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.762296 # mshr miss rate for SoftPFReq accesses 1792system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.762296 # mshr miss rate for SoftPFReq accesses 1793system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716041 # mshr miss rate for WriteLineReq accesses 1794system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.716041 # mshr miss rate for WriteLineReq accesses 1795system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063005 # mshr miss rate for LoadLockedReq accesses 1796system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063005 # mshr miss rate for LoadLockedReq accesses 1797system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111384 # mshr miss rate for StoreCondReq accesses 1798system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111384 # mshr miss rate for StoreCondReq accesses 1799system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027476 # mshr miss rate for demand accesses 1800system.cpu1.dcache.demand_mshr_miss_rate::total 0.027476 # mshr miss rate for demand accesses 1801system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031257 # mshr miss rate for overall accesses 1802system.cpu1.dcache.overall_mshr_miss_rate::total 0.031257 # mshr miss rate for overall accesses 1803system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13573.348560 # average ReadReq mshr miss latency 1804system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13573.348560 # average ReadReq mshr miss latency 1805system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22204.397465 # average WriteReq mshr miss latency 1806system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22204.397465 # average WriteReq mshr miss latency 1807system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22571.149206 # average SoftPFReq mshr miss latency 1808system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22571.149206 # average SoftPFReq mshr miss latency 1809system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 43453.765473 # average WriteLineReq mshr miss latency 1810system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 43453.765473 # average WriteLineReq mshr miss latency 1811system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14016.749329 # average LoadLockedReq mshr miss latency 1812system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14016.749329 # average LoadLockedReq mshr miss latency 1813system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26534.505762 # average StoreCondReq mshr miss latency 1814system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26534.505762 # average StoreCondReq mshr miss latency 1815system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1816system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1817system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16261.987971 # average overall mshr miss latency 1818system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16261.987971 # average overall mshr miss latency 1819system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17053.721361 # average overall mshr miss latency 1820system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17053.721361 # average overall mshr miss latency 1821system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181587.099233 # average ReadReq mshr uncacheable latency 1822system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181587.099233 # average ReadReq mshr uncacheable latency 1823system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 183951.724138 # average WriteReq mshr uncacheable latency 1824system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 183951.724138 # average WriteReq mshr uncacheable latency 1825system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182744.067833 # average overall mshr uncacheable latency 1826system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182744.067833 # average overall mshr uncacheable latency 1827system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1828system.cpu1.icache.tags.replacements 4831573 # number of replacements 1829system.cpu1.icache.tags.tagsinuse 495.969883 # Cycle average of tags in use 1830system.cpu1.icache.tags.total_refs 401189463 # Total number of references to valid blocks. 1831system.cpu1.icache.tags.sampled_refs 4832085 # Sample count of references to valid blocks. 1832system.cpu1.icache.tags.avg_refs 83.026160 # Average number of references to valid blocks. 1833system.cpu1.icache.tags.warmup_cycle 8408381586000 # Cycle when the warmup percentage was hit. 1834system.cpu1.icache.tags.occ_blocks::cpu1.inst 495.969883 # Average occupied blocks per requestor 1835system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968691 # Average percentage of cache occupancy 1836system.cpu1.icache.tags.occ_percent::total 0.968691 # Average percentage of cache occupancy 1837system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1838system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 1839system.cpu1.icache.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id 1840system.cpu1.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id 1841system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1842system.cpu1.icache.tags.tag_accesses 816875196 # Number of tag accesses 1843system.cpu1.icache.tags.data_accesses 816875196 # Number of data accesses 1844system.cpu1.icache.ReadReq_hits::cpu1.inst 401189463 # number of ReadReq hits 1845system.cpu1.icache.ReadReq_hits::total 401189463 # number of ReadReq hits 1846system.cpu1.icache.demand_hits::cpu1.inst 401189463 # number of demand (read+write) hits 1847system.cpu1.icache.demand_hits::total 401189463 # number of demand (read+write) hits 1848system.cpu1.icache.overall_hits::cpu1.inst 401189463 # number of overall hits 1849system.cpu1.icache.overall_hits::total 401189463 # number of overall hits 1850system.cpu1.icache.ReadReq_misses::cpu1.inst 4832090 # number of ReadReq misses 1851system.cpu1.icache.ReadReq_misses::total 4832090 # number of ReadReq misses 1852system.cpu1.icache.demand_misses::cpu1.inst 4832090 # number of demand (read+write) misses 1853system.cpu1.icache.demand_misses::total 4832090 # number of demand (read+write) misses 1854system.cpu1.icache.overall_misses::cpu1.inst 4832090 # number of overall misses 1855system.cpu1.icache.overall_misses::total 4832090 # number of overall misses 1856system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 52408341000 # number of ReadReq miss cycles 1857system.cpu1.icache.ReadReq_miss_latency::total 52408341000 # number of ReadReq miss cycles 1858system.cpu1.icache.demand_miss_latency::cpu1.inst 52408341000 # number of demand (read+write) miss cycles 1859system.cpu1.icache.demand_miss_latency::total 52408341000 # number of demand (read+write) miss cycles 1860system.cpu1.icache.overall_miss_latency::cpu1.inst 52408341000 # number of overall miss cycles 1861system.cpu1.icache.overall_miss_latency::total 52408341000 # number of overall miss cycles 1862system.cpu1.icache.ReadReq_accesses::cpu1.inst 406021553 # number of ReadReq accesses(hits+misses) 1863system.cpu1.icache.ReadReq_accesses::total 406021553 # number of ReadReq accesses(hits+misses) 1864system.cpu1.icache.demand_accesses::cpu1.inst 406021553 # number of demand (read+write) accesses 1865system.cpu1.icache.demand_accesses::total 406021553 # number of demand (read+write) accesses 1866system.cpu1.icache.overall_accesses::cpu1.inst 406021553 # number of overall (read+write) accesses 1867system.cpu1.icache.overall_accesses::total 406021553 # number of overall (read+write) accesses 1868system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011901 # miss rate for ReadReq accesses 1869system.cpu1.icache.ReadReq_miss_rate::total 0.011901 # miss rate for ReadReq accesses 1870system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011901 # miss rate for demand accesses 1871system.cpu1.icache.demand_miss_rate::total 0.011901 # miss rate for demand accesses 1872system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011901 # miss rate for overall accesses 1873system.cpu1.icache.overall_miss_rate::total 0.011901 # miss rate for overall accesses 1874system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10845.895047 # average ReadReq miss latency 1875system.cpu1.icache.ReadReq_avg_miss_latency::total 10845.895047 # average ReadReq miss latency 1876system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency 1877system.cpu1.icache.demand_avg_miss_latency::total 10845.895047 # average overall miss latency 1878system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10845.895047 # average overall miss latency 1879system.cpu1.icache.overall_avg_miss_latency::total 10845.895047 # average overall miss latency 1880system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1881system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1882system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1883system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1884system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1885system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1886system.cpu1.icache.fast_writes 0 # number of fast writes performed 1887system.cpu1.icache.cache_copies 0 # number of cache copies performed 1888system.cpu1.icache.writebacks::writebacks 4831573 # number of writebacks 1889system.cpu1.icache.writebacks::total 4831573 # number of writebacks 1890system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4832090 # number of ReadReq MSHR misses 1891system.cpu1.icache.ReadReq_mshr_misses::total 4832090 # number of ReadReq MSHR misses 1892system.cpu1.icache.demand_mshr_misses::cpu1.inst 4832090 # number of demand (read+write) MSHR misses 1893system.cpu1.icache.demand_mshr_misses::total 4832090 # number of demand (read+write) MSHR misses 1894system.cpu1.icache.overall_mshr_misses::cpu1.inst 4832090 # number of overall MSHR misses 1895system.cpu1.icache.overall_mshr_misses::total 4832090 # number of overall MSHR misses 1896system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1897system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1898system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1899system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1900system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49992296000 # number of ReadReq MSHR miss cycles 1901system.cpu1.icache.ReadReq_mshr_miss_latency::total 49992296000 # number of ReadReq MSHR miss cycles 1902system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49992296000 # number of demand (read+write) MSHR miss cycles 1903system.cpu1.icache.demand_mshr_miss_latency::total 49992296000 # number of demand (read+write) MSHR miss cycles 1904system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49992296000 # number of overall MSHR miss cycles 1905system.cpu1.icache.overall_mshr_miss_latency::total 49992296000 # number of overall MSHR miss cycles 1906system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14799500 # number of ReadReq MSHR uncacheable cycles 1907system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14799500 # number of ReadReq MSHR uncacheable cycles 1908system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14799500 # number of overall MSHR uncacheable cycles 1909system.cpu1.icache.overall_mshr_uncacheable_latency::total 14799500 # number of overall MSHR uncacheable cycles 1910system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for ReadReq accesses 1911system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011901 # mshr miss rate for ReadReq accesses 1912system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for demand accesses 1913system.cpu1.icache.demand_mshr_miss_rate::total 0.011901 # mshr miss rate for demand accesses 1914system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011901 # mshr miss rate for overall accesses 1915system.cpu1.icache.overall_mshr_miss_rate::total 0.011901 # mshr miss rate for overall accesses 1916system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average ReadReq mshr miss latency 1917system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10345.895047 # average ReadReq mshr miss latency 1918system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average overall mshr miss latency 1919system.cpu1.icache.demand_avg_mshr_miss_latency::total 10345.895047 # average overall mshr miss latency 1920system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10345.895047 # average overall mshr miss latency 1921system.cpu1.icache.overall_avg_mshr_miss_latency::total 10345.895047 # average overall mshr miss latency 1922system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average ReadReq mshr uncacheable latency 1923system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 134540.909091 # average ReadReq mshr uncacheable latency 1924system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 134540.909091 # average overall mshr uncacheable latency 1925system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 134540.909091 # average overall mshr uncacheable latency 1926system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1927system.cpu1.l2cache.prefetcher.num_hwpf_issued 6380299 # number of hwpf issued 1928system.cpu1.l2cache.prefetcher.pfIdentified 6380331 # number of prefetch candidates identified 1929system.cpu1.l2cache.prefetcher.pfBufferHit 28 # number of redundant prefetches already in prefetch queue 1930system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1931system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1932system.cpu1.l2cache.prefetcher.pfSpanPage 802101 # number of prefetches not generated due to page crossing 1933system.cpu1.l2cache.tags.replacements 1778912 # number of replacements 1934system.cpu1.l2cache.tags.tagsinuse 13269.685648 # Cycle average of tags in use 1935system.cpu1.l2cache.tags.total_refs 14051315 # Total number of references to valid blocks. 1936system.cpu1.l2cache.tags.sampled_refs 1794926 # Sample count of references to valid blocks. 1937system.cpu1.l2cache.tags.avg_refs 7.828353 # Average number of references to valid blocks. 1938system.cpu1.l2cache.tags.warmup_cycle 10084696105000 # Cycle when the warmup percentage was hit. 1939system.cpu1.l2cache.tags.occ_blocks::writebacks 12213.003078 # Average occupied blocks per requestor 1940system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 33.894206 # Average occupied blocks per requestor 1941system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 34.650770 # Average occupied blocks per requestor 1942system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 988.137594 # Average occupied blocks per requestor 1943system.cpu1.l2cache.tags.occ_percent::writebacks 0.745423 # Average percentage of cache occupancy 1944system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002069 # Average percentage of cache occupancy 1945system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002115 # Average percentage of cache occupancy 1946system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060311 # Average percentage of cache occupancy 1947system.cpu1.l2cache.tags.occ_percent::total 0.809917 # Average percentage of cache occupancy 1948system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1110 # Occupied blocks per task id 1949system.cpu1.l2cache.tags.occ_task_id_blocks::1023 86 # Occupied blocks per task id 1950system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14818 # Occupied blocks per task id 1951system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 1952system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 249 # Occupied blocks per task id 1953system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 669 # Occupied blocks per task id 1954system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 184 # Occupied blocks per task id 1955system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 1956system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 72 # Occupied blocks per task id 1957system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1958system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 1959system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 972 # Occupied blocks per task id 1960system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4464 # Occupied blocks per task id 1961system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8114 # Occupied blocks per task id 1962system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1200 # Occupied blocks per task id 1963system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.067749 # Percentage of cache occupancy per task id 1964system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005249 # Percentage of cache occupancy per task id 1965system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.904419 # Percentage of cache occupancy per task id 1966system.cpu1.l2cache.tags.tag_accesses 324313053 # Number of tag accesses 1967system.cpu1.l2cache.tags.data_accesses 324313053 # Number of data accesses 1968system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 211999 # number of ReadReq hits 1969system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140481 # number of ReadReq hits 1970system.cpu1.l2cache.ReadReq_hits::total 352480 # number of ReadReq hits 1971system.cpu1.l2cache.WritebackDirty_hits::writebacks 2988895 # number of WritebackDirty hits 1972system.cpu1.l2cache.WritebackDirty_hits::total 2988895 # number of WritebackDirty hits 1973system.cpu1.l2cache.WritebackClean_hits::writebacks 6573071 # number of WritebackClean hits 1974system.cpu1.l2cache.WritebackClean_hits::total 6573071 # number of WritebackClean hits 1975system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 239 # number of UpgradeReq hits 1976system.cpu1.l2cache.UpgradeReq_hits::total 239 # number of UpgradeReq hits 1977system.cpu1.l2cache.ReadExReq_hits::cpu1.data 778234 # number of ReadExReq hits 1978system.cpu1.l2cache.ReadExReq_hits::total 778234 # number of ReadExReq hits 1979system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4410501 # number of ReadCleanReq hits 1980system.cpu1.l2cache.ReadCleanReq_hits::total 4410501 # number of ReadCleanReq hits 1981system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2517428 # number of ReadSharedReq hits 1982system.cpu1.l2cache.ReadSharedReq_hits::total 2517428 # number of ReadSharedReq hits 1983system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 200602 # number of InvalidateReq hits 1984system.cpu1.l2cache.InvalidateReq_hits::total 200602 # number of InvalidateReq hits 1985system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 211999 # number of demand (read+write) hits 1986system.cpu1.l2cache.demand_hits::cpu1.itb.walker 140481 # number of demand (read+write) hits 1987system.cpu1.l2cache.demand_hits::cpu1.inst 4410501 # number of demand (read+write) hits 1988system.cpu1.l2cache.demand_hits::cpu1.data 3295662 # number of demand (read+write) hits 1989system.cpu1.l2cache.demand_hits::total 8058643 # number of demand (read+write) hits 1990system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 211999 # number of overall hits 1991system.cpu1.l2cache.overall_hits::cpu1.itb.walker 140481 # number of overall hits 1992system.cpu1.l2cache.overall_hits::cpu1.inst 4410501 # number of overall hits 1993system.cpu1.l2cache.overall_hits::cpu1.data 3295662 # number of overall hits 1994system.cpu1.l2cache.overall_hits::total 8058643 # number of overall hits 1995system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9285 # number of ReadReq misses 1996system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7506 # number of ReadReq misses 1997system.cpu1.l2cache.ReadReq_misses::total 16791 # number of ReadReq misses 1998system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 201343 # number of UpgradeReq misses 1999system.cpu1.l2cache.UpgradeReq_misses::total 201343 # number of UpgradeReq misses 2000system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 194101 # number of SCUpgradeReq misses 2001system.cpu1.l2cache.SCUpgradeReq_misses::total 194101 # number of SCUpgradeReq misses 2002system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 26 # number of SCUpgradeFailReq misses 2003system.cpu1.l2cache.SCUpgradeFailReq_misses::total 26 # number of SCUpgradeFailReq misses 2004system.cpu1.l2cache.ReadExReq_misses::cpu1.data 235513 # number of ReadExReq misses 2005system.cpu1.l2cache.ReadExReq_misses::total 235513 # number of ReadExReq misses 2006system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 421589 # number of ReadCleanReq misses 2007system.cpu1.l2cache.ReadCleanReq_misses::total 421589 # number of ReadCleanReq misses 2008system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 831569 # number of ReadSharedReq misses 2009system.cpu1.l2cache.ReadSharedReq_misses::total 831569 # number of ReadSharedReq misses 2010system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 263822 # number of InvalidateReq misses 2011system.cpu1.l2cache.InvalidateReq_misses::total 263822 # number of InvalidateReq misses 2012system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9285 # number of demand (read+write) misses 2013system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7506 # number of demand (read+write) misses 2014system.cpu1.l2cache.demand_misses::cpu1.inst 421589 # number of demand (read+write) misses 2015system.cpu1.l2cache.demand_misses::cpu1.data 1067082 # number of demand (read+write) misses 2016system.cpu1.l2cache.demand_misses::total 1505462 # number of demand (read+write) misses 2017system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9285 # number of overall misses 2018system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7506 # number of overall misses 2019system.cpu1.l2cache.overall_misses::cpu1.inst 421589 # number of overall misses 2020system.cpu1.l2cache.overall_misses::cpu1.data 1067082 # number of overall misses 2021system.cpu1.l2cache.overall_misses::total 1505462 # number of overall misses 2022system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 349092500 # number of ReadReq miss cycles 2023system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 301051000 # number of ReadReq miss cycles 2024system.cpu1.l2cache.ReadReq_miss_latency::total 650143500 # number of ReadReq miss cycles 2025system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3162483500 # number of UpgradeReq miss cycles 2026system.cpu1.l2cache.UpgradeReq_miss_latency::total 3162483500 # number of UpgradeReq miss cycles 2027system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1860693500 # number of SCUpgradeReq miss cycles 2028system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1860693500 # number of SCUpgradeReq miss cycles 2029system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6744500 # number of SCUpgradeFailReq miss cycles 2030system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6744500 # number of SCUpgradeFailReq miss cycles 2031system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12440298999 # number of ReadExReq miss cycles 2032system.cpu1.l2cache.ReadExReq_miss_latency::total 12440298999 # number of ReadExReq miss cycles 2033system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 16234081000 # number of ReadCleanReq miss cycles 2034system.cpu1.l2cache.ReadCleanReq_miss_latency::total 16234081000 # number of ReadCleanReq miss cycles 2035system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 29105216000 # number of ReadSharedReq miss cycles 2036system.cpu1.l2cache.ReadSharedReq_miss_latency::total 29105216000 # number of ReadSharedReq miss cycles 2037system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 18219271500 # number of InvalidateReq miss cycles 2038system.cpu1.l2cache.InvalidateReq_miss_latency::total 18219271500 # number of InvalidateReq miss cycles 2039system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 349092500 # number of demand (read+write) miss cycles 2040system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 301051000 # number of demand (read+write) miss cycles 2041system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16234081000 # number of demand (read+write) miss cycles 2042system.cpu1.l2cache.demand_miss_latency::cpu1.data 41545514999 # number of demand (read+write) miss cycles 2043system.cpu1.l2cache.demand_miss_latency::total 58429739499 # number of demand (read+write) miss cycles 2044system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 349092500 # number of overall miss cycles 2045system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 301051000 # number of overall miss cycles 2046system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16234081000 # number of overall miss cycles 2047system.cpu1.l2cache.overall_miss_latency::cpu1.data 41545514999 # number of overall miss cycles 2048system.cpu1.l2cache.overall_miss_latency::total 58429739499 # number of overall miss cycles 2049system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 221284 # number of ReadReq accesses(hits+misses) 2050system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 147987 # number of ReadReq accesses(hits+misses) 2051system.cpu1.l2cache.ReadReq_accesses::total 369271 # number of ReadReq accesses(hits+misses) 2052system.cpu1.l2cache.WritebackDirty_accesses::writebacks 2988895 # number of WritebackDirty accesses(hits+misses) 2053system.cpu1.l2cache.WritebackDirty_accesses::total 2988895 # number of WritebackDirty accesses(hits+misses) 2054system.cpu1.l2cache.WritebackClean_accesses::writebacks 6573071 # number of WritebackClean accesses(hits+misses) 2055system.cpu1.l2cache.WritebackClean_accesses::total 6573071 # number of WritebackClean accesses(hits+misses) 2056system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 201582 # number of UpgradeReq accesses(hits+misses) 2057system.cpu1.l2cache.UpgradeReq_accesses::total 201582 # number of UpgradeReq accesses(hits+misses) 2058system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 194101 # number of SCUpgradeReq accesses(hits+misses) 2059system.cpu1.l2cache.SCUpgradeReq_accesses::total 194101 # number of SCUpgradeReq accesses(hits+misses) 2060system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 26 # number of SCUpgradeFailReq accesses(hits+misses) 2061system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 26 # number of SCUpgradeFailReq accesses(hits+misses) 2062system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1013747 # number of ReadExReq accesses(hits+misses) 2063system.cpu1.l2cache.ReadExReq_accesses::total 1013747 # number of ReadExReq accesses(hits+misses) 2064system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4832090 # number of ReadCleanReq accesses(hits+misses) 2065system.cpu1.l2cache.ReadCleanReq_accesses::total 4832090 # number of ReadCleanReq accesses(hits+misses) 2066system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3348997 # number of ReadSharedReq accesses(hits+misses) 2067system.cpu1.l2cache.ReadSharedReq_accesses::total 3348997 # number of ReadSharedReq accesses(hits+misses) 2068system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 464424 # number of InvalidateReq accesses(hits+misses) 2069system.cpu1.l2cache.InvalidateReq_accesses::total 464424 # number of InvalidateReq accesses(hits+misses) 2070system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 221284 # number of demand (read+write) accesses 2071system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 147987 # number of demand (read+write) accesses 2072system.cpu1.l2cache.demand_accesses::cpu1.inst 4832090 # number of demand (read+write) accesses 2073system.cpu1.l2cache.demand_accesses::cpu1.data 4362744 # number of demand (read+write) accesses 2074system.cpu1.l2cache.demand_accesses::total 9564105 # number of demand (read+write) accesses 2075system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 221284 # number of overall (read+write) accesses 2076system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 147987 # number of overall (read+write) accesses 2077system.cpu1.l2cache.overall_accesses::cpu1.inst 4832090 # number of overall (read+write) accesses 2078system.cpu1.l2cache.overall_accesses::cpu1.data 4362744 # number of overall (read+write) accesses 2079system.cpu1.l2cache.overall_accesses::total 9564105 # number of overall (read+write) accesses 2080system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041960 # miss rate for ReadReq accesses 2081system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.050721 # miss rate for ReadReq accesses 2082system.cpu1.l2cache.ReadReq_miss_rate::total 0.045471 # miss rate for ReadReq accesses 2083system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998814 # miss rate for UpgradeReq accesses 2084system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998814 # miss rate for UpgradeReq accesses 2085system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2086system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2087system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2088system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2089system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.232319 # miss rate for ReadExReq accesses 2090system.cpu1.l2cache.ReadExReq_miss_rate::total 0.232319 # miss rate for ReadExReq accesses 2091system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.087248 # miss rate for ReadCleanReq accesses 2092system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.087248 # miss rate for ReadCleanReq accesses 2093system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.248304 # miss rate for ReadSharedReq accesses 2094system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.248304 # miss rate for ReadSharedReq accesses 2095system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.568063 # miss rate for InvalidateReq accesses 2096system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.568063 # miss rate for InvalidateReq accesses 2097system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.041960 # miss rate for demand accesses 2098system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.050721 # miss rate for demand accesses 2099system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.087248 # miss rate for demand accesses 2100system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244590 # miss rate for demand accesses 2101system.cpu1.l2cache.demand_miss_rate::total 0.157408 # miss rate for demand accesses 2102system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.041960 # miss rate for overall accesses 2103system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.050721 # miss rate for overall accesses 2104system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.087248 # miss rate for overall accesses 2105system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244590 # miss rate for overall accesses 2106system.cpu1.l2cache.overall_miss_rate::total 0.157408 # miss rate for overall accesses 2107system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37597.469036 # average ReadReq miss latency 2108system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40108.046896 # average ReadReq miss latency 2109system.cpu1.l2cache.ReadReq_avg_miss_latency::total 38719.760586 # average ReadReq miss latency 2110system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15706.945362 # average UpgradeReq miss latency 2111system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15706.945362 # average UpgradeReq miss latency 2112system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9586.212848 # average SCUpgradeReq miss latency 2113system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9586.212848 # average SCUpgradeReq miss latency 2114system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 259403.846154 # average SCUpgradeFailReq miss latency 2115system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 259403.846154 # average SCUpgradeFailReq miss latency 2116system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52822.132957 # average ReadExReq miss latency 2117system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52822.132957 # average ReadExReq miss latency 2118system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38506.889411 # average ReadCleanReq miss latency 2119system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38506.889411 # average ReadCleanReq miss latency 2120system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 35000.361966 # average ReadSharedReq miss latency 2121system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 35000.361966 # average ReadSharedReq miss latency 2122system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69058.954522 # average InvalidateReq miss latency 2123system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69058.954522 # average InvalidateReq miss latency 2124system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37597.469036 # average overall miss latency 2125system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40108.046896 # average overall miss latency 2126system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38506.889411 # average overall miss latency 2127system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38933.760479 # average overall miss latency 2128system.cpu1.l2cache.demand_avg_miss_latency::total 38811.832845 # average overall miss latency 2129system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37597.469036 # average overall miss latency 2130system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40108.046896 # average overall miss latency 2131system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38506.889411 # average overall miss latency 2132system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38933.760479 # average overall miss latency 2133system.cpu1.l2cache.overall_avg_miss_latency::total 38811.832845 # average overall miss latency 2134system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2135system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2136system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2137system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2138system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2139system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2140system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2141system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2142system.cpu1.l2cache.writebacks::writebacks 983057 # number of writebacks 2143system.cpu1.l2cache.writebacks::total 983057 # number of writebacks 2144system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3912 # number of ReadExReq MSHR hits 2145system.cpu1.l2cache.ReadExReq_mshr_hits::total 3912 # number of ReadExReq MSHR hits 2146system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 475 # number of ReadSharedReq MSHR hits 2147system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 475 # number of ReadSharedReq MSHR hits 2148system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 1 # number of InvalidateReq MSHR hits 2149system.cpu1.l2cache.InvalidateReq_mshr_hits::total 1 # number of InvalidateReq MSHR hits 2150system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4387 # number of demand (read+write) MSHR hits 2151system.cpu1.l2cache.demand_mshr_hits::total 4387 # number of demand (read+write) MSHR hits 2152system.cpu1.l2cache.overall_mshr_hits::cpu1.data 4387 # number of overall MSHR hits 2153system.cpu1.l2cache.overall_mshr_hits::total 4387 # number of overall MSHR hits 2154system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9285 # number of ReadReq MSHR misses 2155system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7506 # number of ReadReq MSHR misses 2156system.cpu1.l2cache.ReadReq_mshr_misses::total 16791 # number of ReadReq MSHR misses 2157system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 603476 # number of HardPFReq MSHR misses 2158system.cpu1.l2cache.HardPFReq_mshr_misses::total 603476 # number of HardPFReq MSHR misses 2159system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 201343 # number of UpgradeReq MSHR misses 2160system.cpu1.l2cache.UpgradeReq_mshr_misses::total 201343 # number of UpgradeReq MSHR misses 2161system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 194101 # number of SCUpgradeReq MSHR misses 2162system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 194101 # number of SCUpgradeReq MSHR misses 2163system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 26 # number of SCUpgradeFailReq MSHR misses 2164system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 26 # number of SCUpgradeFailReq MSHR misses 2165system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 231601 # number of ReadExReq MSHR misses 2166system.cpu1.l2cache.ReadExReq_mshr_misses::total 231601 # number of ReadExReq MSHR misses 2167system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 421589 # number of ReadCleanReq MSHR misses 2168system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 421589 # number of ReadCleanReq MSHR misses 2169system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 831094 # number of ReadSharedReq MSHR misses 2170system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 831094 # number of ReadSharedReq MSHR misses 2171system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 263821 # number of InvalidateReq MSHR misses 2172system.cpu1.l2cache.InvalidateReq_mshr_misses::total 263821 # number of InvalidateReq MSHR misses 2173system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9285 # number of demand (read+write) MSHR misses 2174system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7506 # number of demand (read+write) MSHR misses 2175system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 421589 # number of demand (read+write) MSHR misses 2176system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1062695 # number of demand (read+write) MSHR misses 2177system.cpu1.l2cache.demand_mshr_misses::total 1501075 # number of demand (read+write) MSHR misses 2178system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9285 # number of overall MSHR misses 2179system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7506 # number of overall MSHR misses 2180system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 421589 # number of overall MSHR misses 2181system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1062695 # number of overall MSHR misses 2182system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 603476 # number of overall MSHR misses 2183system.cpu1.l2cache.overall_mshr_misses::total 2104551 # number of overall MSHR misses 2184system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2185system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 23611 # number of ReadReq MSHR uncacheable 2186system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23721 # number of ReadReq MSHR uncacheable 2187system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 22620 # number of WriteReq MSHR uncacheable 2188system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 22620 # number of WriteReq MSHR uncacheable 2189system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2190system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 46231 # number of overall MSHR uncacheable misses 2191system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 46341 # number of overall MSHR uncacheable misses 2192system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 293382500 # number of ReadReq MSHR miss cycles 2193system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 256015000 # number of ReadReq MSHR miss cycles 2194system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 549397500 # number of ReadReq MSHR miss cycles 2195system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27540952434 # number of HardPFReq MSHR miss cycles 2196system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 27540952434 # number of HardPFReq MSHR miss cycles 2197system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 6429356000 # number of UpgradeReq MSHR miss cycles 2198system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 6429356000 # number of UpgradeReq MSHR miss cycles 2199system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3693933999 # number of SCUpgradeReq MSHR miss cycles 2200system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3693933999 # number of SCUpgradeReq MSHR miss cycles 2201system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6300500 # number of SCUpgradeFailReq MSHR miss cycles 2202system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6300500 # number of SCUpgradeFailReq MSHR miss cycles 2203system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10580800999 # number of ReadExReq MSHR miss cycles 2204system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10580800999 # number of ReadExReq MSHR miss cycles 2205system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13704547000 # number of ReadCleanReq MSHR miss cycles 2206system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13704547000 # number of ReadCleanReq MSHR miss cycles 2207system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24076200000 # number of ReadSharedReq MSHR miss cycles 2208system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24076200000 # number of ReadSharedReq MSHR miss cycles 2209system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16636263000 # number of InvalidateReq MSHR miss cycles 2210system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16636263000 # number of InvalidateReq MSHR miss cycles 2211system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 293382500 # number of demand (read+write) MSHR miss cycles 2212system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 256015000 # number of demand (read+write) MSHR miss cycles 2213system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13704547000 # number of demand (read+write) MSHR miss cycles 2214system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34657000999 # number of demand (read+write) MSHR miss cycles 2215system.cpu1.l2cache.demand_mshr_miss_latency::total 48910945499 # number of demand (read+write) MSHR miss cycles 2216system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 293382500 # number of overall MSHR miss cycles 2217system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 256015000 # number of overall MSHR miss cycles 2218system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13704547000 # number of overall MSHR miss cycles 2219system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34657000999 # number of overall MSHR miss cycles 2220system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27540952434 # number of overall MSHR miss cycles 2221system.cpu1.l2cache.overall_mshr_miss_latency::total 76451897933 # number of overall MSHR miss cycles 2222system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13974500 # number of ReadReq MSHR uncacheable cycles 2223system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 4098070000 # number of ReadReq MSHR uncacheable cycles 2224system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 4112044500 # number of ReadReq MSHR uncacheable cycles 2225system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3990752000 # number of WriteReq MSHR uncacheable cycles 2226system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3990752000 # number of WriteReq MSHR uncacheable cycles 2227system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 13974500 # number of overall MSHR uncacheable cycles 2228system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 8088822000 # number of overall MSHR uncacheable cycles 2229system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 8102796500 # number of overall MSHR uncacheable cycles 2230system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for ReadReq accesses 2231system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for ReadReq accesses 2232system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.045471 # mshr miss rate for ReadReq accesses 2233system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2234system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2235system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998814 # mshr miss rate for UpgradeReq accesses 2236system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998814 # mshr miss rate for UpgradeReq accesses 2237system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2238system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2239system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2240system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2241system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.228460 # mshr miss rate for ReadExReq accesses 2242system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.228460 # mshr miss rate for ReadExReq accesses 2243system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for ReadCleanReq accesses 2244system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.087248 # mshr miss rate for ReadCleanReq accesses 2245system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248162 # mshr miss rate for ReadSharedReq accesses 2246system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248162 # mshr miss rate for ReadSharedReq accesses 2247system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.568061 # mshr miss rate for InvalidateReq accesses 2248system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.568061 # mshr miss rate for InvalidateReq accesses 2249system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for demand accesses 2250system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for demand accesses 2251system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for demand accesses 2252system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243584 # mshr miss rate for demand accesses 2253system.cpu1.l2cache.demand_mshr_miss_rate::total 0.156949 # mshr miss rate for demand accesses 2254system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041960 # mshr miss rate for overall accesses 2255system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050721 # mshr miss rate for overall accesses 2256system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.087248 # mshr miss rate for overall accesses 2257system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243584 # mshr miss rate for overall accesses 2258system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2259system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220047 # mshr miss rate for overall accesses 2260system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average ReadReq mshr miss latency 2261system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average ReadReq mshr miss latency 2262system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 32719.760586 # average ReadReq mshr miss latency 2263system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average HardPFReq mshr miss latency 2264system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45637.195902 # average HardPFReq mshr miss latency 2265system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31932.354241 # average UpgradeReq mshr miss latency 2266system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31932.354241 # average UpgradeReq mshr miss latency 2267system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19030.989016 # average SCUpgradeReq mshr miss latency 2268system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19030.989016 # average SCUpgradeReq mshr miss latency 2269system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242326.923077 # average SCUpgradeFailReq mshr miss latency 2270system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242326.923077 # average SCUpgradeFailReq mshr miss latency 2271system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.471993 # average ReadExReq mshr miss latency 2272system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.471993 # average ReadExReq mshr miss latency 2273system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average ReadCleanReq mshr miss latency 2274system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32506.889411 # average ReadCleanReq mshr miss latency 2275system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28969.286266 # average ReadSharedReq mshr miss latency 2276system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28969.286266 # average ReadSharedReq mshr miss latency 2277system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63058.903575 # average InvalidateReq mshr miss latency 2278system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63058.903575 # average InvalidateReq mshr miss latency 2279system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency 2280system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency 2281system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency 2282system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency 2283system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32583.945172 # average overall mshr miss latency 2284system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31597.469036 # average overall mshr miss latency 2285system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34108.046896 # average overall mshr miss latency 2286system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32506.889411 # average overall mshr miss latency 2287system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32612.368553 # average overall mshr miss latency 2288system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45637.195902 # average overall mshr miss latency 2289system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36326.940014 # average overall mshr miss latency 2290system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average ReadReq mshr uncacheable latency 2291system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173566.134429 # average ReadReq mshr uncacheable latency 2292system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 173350.385734 # average ReadReq mshr uncacheable latency 2293system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176425.817860 # average WriteReq mshr uncacheable latency 2294system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176425.817860 # average WriteReq mshr uncacheable latency 2295system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127040.909091 # average overall mshr uncacheable latency 2296system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174965.326296 # average overall mshr uncacheable latency 2297system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174851.567726 # average overall mshr uncacheable latency 2298system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2299system.cpu1.toL2Bus.snoop_filter.tot_requests 19832170 # Total number of requests made to the snoop filter. 2300system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10173061 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2301system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1095 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2302system.cpu1.toL2Bus.snoop_filter.tot_snoops 1632026 # Total number of snoops made to the snoop filter. 2303system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1631848 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2304system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 178 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2305system.cpu1.toL2Bus.trans_dist::ReadReq 456067 # Transaction distribution 2306system.cpu1.toL2Bus.trans_dist::ReadResp 8724452 # Transaction distribution 2307system.cpu1.toL2Bus.trans_dist::WriteReq 22620 # Transaction distribution 2308system.cpu1.toL2Bus.trans_dist::WriteResp 22620 # Transaction distribution 2309system.cpu1.toL2Bus.trans_dist::WritebackDirty 3978006 # Transaction distribution 2310system.cpu1.toL2Bus.trans_dist::WritebackClean 6573071 # Transaction distribution 2311system.cpu1.toL2Bus.trans_dist::CleanEvict 2099842 # Transaction distribution 2312system.cpu1.toL2Bus.trans_dist::HardPFReq 741149 # Transaction distribution 2313system.cpu1.toL2Bus.trans_dist::UpgradeReq 395876 # Transaction distribution 2314system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358205 # Transaction distribution 2315system.cpu1.toL2Bus.trans_dist::UpgradeResp 460652 # Transaction distribution 2316system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution 2317system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution 2318system.cpu1.toL2Bus.trans_dist::ReadExReq 1084167 # Transaction distribution 2319system.cpu1.toL2Bus.trans_dist::ReadExResp 1021480 # Transaction distribution 2320system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4832090 # Transaction distribution 2321system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4231593 # Transaction distribution 2322system.cpu1.toL2Bus.trans_dist::InvalidateReq 474723 # Transaction distribution 2323system.cpu1.toL2Bus.trans_dist::InvalidateResp 464424 # Transaction distribution 2324system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14495311 # Packet count per connected master and slave (bytes) 2325system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15429373 # Packet count per connected master and slave (bytes) 2326system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 311743 # Packet count per connected master and slave (bytes) 2327system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 489874 # Packet count per connected master and slave (bytes) 2328system.cpu1.toL2Bus.pkt_count::total 30726301 # Packet count per connected master and slave (bytes) 2329system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 618432504 # Cumulative packet size per connected master and slave (bytes) 2330system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588237954 # Cumulative packet size per connected master and slave (bytes) 2331system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1183896 # Cumulative packet size per connected master and slave (bytes) 2332system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1770272 # Cumulative packet size per connected master and slave (bytes) 2333system.cpu1.toL2Bus.pkt_size::total 1209624626 # Cumulative packet size per connected master and slave (bytes) 2334system.cpu1.toL2Bus.snoops 5375046 # Total snoops (count) 2335system.cpu1.toL2Bus.snoop_fanout::samples 15685523 # Request fanout histogram 2336system.cpu1.toL2Bus.snoop_fanout::mean 0.117781 # Request fanout histogram 2337system.cpu1.toL2Bus.snoop_fanout::stdev 0.322383 # Request fanout histogram 2338system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2339system.cpu1.toL2Bus.snoop_fanout::0 13838252 88.22% 88.22% # Request fanout histogram 2340system.cpu1.toL2Bus.snoop_fanout::1 1847093 11.78% 100.00% # Request fanout histogram 2341system.cpu1.toL2Bus.snoop_fanout::2 178 0.00% 100.00% # Request fanout histogram 2342system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2343system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2344system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2345system.cpu1.toL2Bus.snoop_fanout::total 15685523 # Request fanout histogram 2346system.cpu1.toL2Bus.reqLayer0.occupancy 19622729498 # Layer occupancy (ticks) 2347system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2348system.cpu1.toL2Bus.snoopLayer0.occupancy 175341179 # Layer occupancy (ticks) 2349system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2350system.cpu1.toL2Bus.respLayer0.occupancy 7248245000 # Layer occupancy (ticks) 2351system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2352system.cpu1.toL2Bus.respLayer1.occupancy 7009474930 # Layer occupancy (ticks) 2353system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2354system.cpu1.toL2Bus.respLayer2.occupancy 163756499 # Layer occupancy (ticks) 2355system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2356system.cpu1.toL2Bus.respLayer3.occupancy 268590000 # Layer occupancy (ticks) 2357system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2358system.iobus.trans_dist::ReadReq 40469 # Transaction distribution 2359system.iobus.trans_dist::ReadResp 40469 # Transaction distribution 2360system.iobus.trans_dist::WriteReq 137017 # Transaction distribution 2361system.iobus.trans_dist::WriteResp 137017 # Transaction distribution 2362system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47986 # Packet count per connected master and slave (bytes) 2363system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2364system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2365system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2366system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2367system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2368system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2369system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2370system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2371system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2372system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) 2373system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2374system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2375system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2376system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2377system.iobus.pkt_count_system.bridge.master::total 123128 # Packet count per connected master and slave (bytes) 2378system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231764 # Packet count per connected master and slave (bytes) 2379system.iobus.pkt_count_system.realview.ide.dma::total 231764 # Packet count per connected master and slave (bytes) 2380system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2381system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2382system.iobus.pkt_count::total 354972 # Packet count per connected master and slave (bytes) 2383system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48006 # Cumulative packet size per connected master and slave (bytes) 2384system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2385system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2386system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2387system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2388system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2389system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2390system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2391system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2392system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2393system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) 2394system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2395system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2396system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2397system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2398system.iobus.pkt_size_system.bridge.master::total 156143 # Cumulative packet size per connected master and slave (bytes) 2399system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355408 # Cumulative packet size per connected master and slave (bytes) 2400system.iobus.pkt_size_system.realview.ide.dma::total 7355408 # Cumulative packet size per connected master and slave (bytes) 2401system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2402system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2403system.iobus.pkt_size::total 7513637 # Cumulative packet size per connected master and slave (bytes) 2404system.iobus.reqLayer0.occupancy 37181500 # Layer occupancy (ticks) 2405system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2406system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) 2407system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2408system.iobus.reqLayer2.occupancy 8500 # Layer occupancy (ticks) 2409system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2410system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) 2411system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2412system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2413system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2414system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) 2415system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2416system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) 2417system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2418system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2419system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2420system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 2421system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2422system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2423system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2424system.iobus.reqLayer23.occupancy 26640000 # Layer occupancy (ticks) 2425system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2426system.iobus.reqLayer24.occupancy 168000 # Layer occupancy (ticks) 2427system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2428system.iobus.reqLayer25.occupancy 37419000 # Layer occupancy (ticks) 2429system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2430system.iobus.reqLayer26.occupancy 122000 # Layer occupancy (ticks) 2431system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2432system.iobus.reqLayer27.occupancy 566572505 # Layer occupancy (ticks) 2433system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2434system.iobus.reqLayer28.occupancy 30500 # Layer occupancy (ticks) 2435system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2436system.iobus.respLayer0.occupancy 93098000 # Layer occupancy (ticks) 2437system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2438system.iobus.respLayer3.occupancy 148204000 # Layer occupancy (ticks) 2439system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2440system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2441system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2442system.iocache.tags.replacements 115869 # number of replacements 2443system.iocache.tags.tagsinuse 11.294988 # Cycle average of tags in use 2444system.iocache.tags.total_refs 4 # Total number of references to valid blocks. 2445system.iocache.tags.sampled_refs 115885 # Sample count of references to valid blocks. 2446system.iocache.tags.avg_refs 0.000035 # Average number of references to valid blocks. 2447system.iocache.tags.warmup_cycle 9206093766000 # Cycle when the warmup percentage was hit. 2448system.iocache.tags.occ_blocks::realview.ethernet 3.821408 # Average occupied blocks per requestor 2449system.iocache.tags.occ_blocks::realview.ide 7.473580 # Average occupied blocks per requestor 2450system.iocache.tags.occ_percent::realview.ethernet 0.238838 # Average percentage of cache occupancy 2451system.iocache.tags.occ_percent::realview.ide 0.467099 # Average percentage of cache occupancy 2452system.iocache.tags.occ_percent::total 0.705937 # Average percentage of cache occupancy 2453system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2454system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2455system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2456system.iocache.tags.tag_accesses 1043293 # Number of tag accesses 2457system.iocache.tags.data_accesses 1043293 # Number of data accesses 2458system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2459system.iocache.ReadReq_misses::realview.ide 8898 # number of ReadReq misses 2460system.iocache.ReadReq_misses::total 8935 # number of ReadReq misses 2461system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2462system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2463system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2464system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 2465system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2466system.iocache.demand_misses::realview.ide 8898 # number of demand (read+write) misses 2467system.iocache.demand_misses::total 8938 # number of demand (read+write) misses 2468system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2469system.iocache.overall_misses::realview.ide 8898 # number of overall misses 2470system.iocache.overall_misses::total 8938 # number of overall misses 2471system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 2472system.iocache.ReadReq_miss_latency::realview.ide 1681517592 # number of ReadReq miss cycles 2473system.iocache.ReadReq_miss_latency::total 1686717092 # number of ReadReq miss cycles 2474system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2475system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2476system.iocache.WriteLineReq_miss_latency::realview.ide 14021691413 # number of WriteLineReq miss cycles 2477system.iocache.WriteLineReq_miss_latency::total 14021691413 # number of WriteLineReq miss cycles 2478system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles 2479system.iocache.demand_miss_latency::realview.ide 1681517592 # number of demand (read+write) miss cycles 2480system.iocache.demand_miss_latency::total 1687086092 # number of demand (read+write) miss cycles 2481system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles 2482system.iocache.overall_miss_latency::realview.ide 1681517592 # number of overall miss cycles 2483system.iocache.overall_miss_latency::total 1687086092 # number of overall miss cycles 2484system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2485system.iocache.ReadReq_accesses::realview.ide 8898 # number of ReadReq accesses(hits+misses) 2486system.iocache.ReadReq_accesses::total 8935 # number of ReadReq accesses(hits+misses) 2487system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2488system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2489system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2490system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2491system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2492system.iocache.demand_accesses::realview.ide 8898 # number of demand (read+write) accesses 2493system.iocache.demand_accesses::total 8938 # number of demand (read+write) accesses 2494system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2495system.iocache.overall_accesses::realview.ide 8898 # number of overall (read+write) accesses 2496system.iocache.overall_accesses::total 8938 # number of overall (read+write) accesses 2497system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2498system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2499system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2500system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2501system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2502system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2503system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2504system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2505system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2506system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2507system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2508system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2509system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2510system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 2511system.iocache.ReadReq_avg_miss_latency::realview.ide 188977.027647 # average ReadReq miss latency 2512system.iocache.ReadReq_avg_miss_latency::total 188776.395299 # average ReadReq miss latency 2513system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2514system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2515system.iocache.WriteLineReq_avg_miss_latency::realview.ide 131063.443253 # average WriteLineReq miss latency 2516system.iocache.WriteLineReq_avg_miss_latency::total 131063.443253 # average WriteLineReq miss latency 2517system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2518system.iocache.demand_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency 2519system.iocache.demand_avg_miss_latency::total 188754.317744 # average overall miss latency 2520system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2521system.iocache.overall_avg_miss_latency::realview.ide 188977.027647 # average overall miss latency 2522system.iocache.overall_avg_miss_latency::total 188754.317744 # average overall miss latency 2523system.iocache.blocked_cycles::no_mshrs 36073 # number of cycles access was blocked 2524system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2525system.iocache.blocked::no_mshrs 3617 # number of cycles access was blocked 2526system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2527system.iocache.avg_blocked_cycles::no_mshrs 9.973182 # average number of cycles each access was blocked 2528system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2529system.iocache.fast_writes 0 # number of fast writes performed 2530system.iocache.cache_copies 0 # number of cache copies performed 2531system.iocache.writebacks::writebacks 106957 # number of writebacks 2532system.iocache.writebacks::total 106957 # number of writebacks 2533system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2534system.iocache.ReadReq_mshr_misses::realview.ide 8898 # number of ReadReq MSHR misses 2535system.iocache.ReadReq_mshr_misses::total 8935 # number of ReadReq MSHR misses 2536system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2537system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2538system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2539system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 2540system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2541system.iocache.demand_mshr_misses::realview.ide 8898 # number of demand (read+write) MSHR misses 2542system.iocache.demand_mshr_misses::total 8938 # number of demand (read+write) MSHR misses 2543system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2544system.iocache.overall_mshr_misses::realview.ide 8898 # number of overall MSHR misses 2545system.iocache.overall_mshr_misses::total 8938 # number of overall MSHR misses 2546system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 2547system.iocache.ReadReq_mshr_miss_latency::realview.ide 1236617592 # number of ReadReq MSHR miss cycles 2548system.iocache.ReadReq_mshr_miss_latency::total 1239967092 # number of ReadReq MSHR miss cycles 2549system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2550system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2551system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8672491413 # number of WriteLineReq MSHR miss cycles 2552system.iocache.WriteLineReq_mshr_miss_latency::total 8672491413 # number of WriteLineReq MSHR miss cycles 2553system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles 2554system.iocache.demand_mshr_miss_latency::realview.ide 1236617592 # number of demand (read+write) MSHR miss cycles 2555system.iocache.demand_mshr_miss_latency::total 1240186092 # number of demand (read+write) MSHR miss cycles 2556system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles 2557system.iocache.overall_mshr_miss_latency::realview.ide 1236617592 # number of overall MSHR miss cycles 2558system.iocache.overall_mshr_miss_latency::total 1240186092 # number of overall MSHR miss cycles 2559system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2560system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2561system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2562system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2563system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2564system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2565system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2566system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2567system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2568system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2569system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2570system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2571system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2572system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 2573system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138977.027647 # average ReadReq mshr miss latency 2574system.iocache.ReadReq_avg_mshr_miss_latency::total 138776.395299 # average ReadReq mshr miss latency 2575system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2576system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2577system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 81063.443253 # average WriteLineReq mshr miss latency 2578system.iocache.WriteLineReq_avg_mshr_miss_latency::total 81063.443253 # average WriteLineReq mshr miss latency 2579system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2580system.iocache.demand_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency 2581system.iocache.demand_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency 2582system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2583system.iocache.overall_avg_mshr_miss_latency::realview.ide 138977.027647 # average overall mshr miss latency 2584system.iocache.overall_avg_mshr_miss_latency::total 138754.317744 # average overall mshr miss latency 2585system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2586system.l2c.tags.replacements 1210264 # number of replacements 2587system.l2c.tags.tagsinuse 62755.466878 # Cycle average of tags in use 2588system.l2c.tags.total_refs 5212344 # Total number of references to valid blocks. 2589system.l2c.tags.sampled_refs 1269955 # Sample count of references to valid blocks. 2590system.l2c.tags.avg_refs 4.104353 # Average number of references to valid blocks. 2591system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2592system.l2c.tags.occ_blocks::writebacks 23285.968480 # Average occupied blocks per requestor 2593system.l2c.tags.occ_blocks::cpu0.dtb.walker 218.650031 # Average occupied blocks per requestor 2594system.l2c.tags.occ_blocks::cpu0.itb.walker 386.944281 # Average occupied blocks per requestor 2595system.l2c.tags.occ_blocks::cpu0.inst 4588.836094 # Average occupied blocks per requestor 2596system.l2c.tags.occ_blocks::cpu0.data 10476.813165 # Average occupied blocks per requestor 2597system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 13833.010748 # Average occupied blocks per requestor 2598system.l2c.tags.occ_blocks::cpu1.dtb.walker 53.974082 # Average occupied blocks per requestor 2599system.l2c.tags.occ_blocks::cpu1.itb.walker 79.219380 # Average occupied blocks per requestor 2600system.l2c.tags.occ_blocks::cpu1.inst 3039.104298 # Average occupied blocks per requestor 2601system.l2c.tags.occ_blocks::cpu1.data 3132.206690 # Average occupied blocks per requestor 2602system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3660.739630 # Average occupied blocks per requestor 2603system.l2c.tags.occ_percent::writebacks 0.355316 # Average percentage of cache occupancy 2604system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003336 # Average percentage of cache occupancy 2605system.l2c.tags.occ_percent::cpu0.itb.walker 0.005904 # Average percentage of cache occupancy 2606system.l2c.tags.occ_percent::cpu0.inst 0.070020 # Average percentage of cache occupancy 2607system.l2c.tags.occ_percent::cpu0.data 0.159863 # Average percentage of cache occupancy 2608system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.211075 # Average percentage of cache occupancy 2609system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000824 # Average percentage of cache occupancy 2610system.l2c.tags.occ_percent::cpu1.itb.walker 0.001209 # Average percentage of cache occupancy 2611system.l2c.tags.occ_percent::cpu1.inst 0.046373 # Average percentage of cache occupancy 2612system.l2c.tags.occ_percent::cpu1.data 0.047794 # Average percentage of cache occupancy 2613system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055858 # Average percentage of cache occupancy 2614system.l2c.tags.occ_percent::total 0.957572 # Average percentage of cache occupancy 2615system.l2c.tags.occ_task_id_blocks::1022 10565 # Occupied blocks per task id 2616system.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id 2617system.l2c.tags.occ_task_id_blocks::1024 48895 # Occupied blocks per task id 2618system.l2c.tags.age_task_id_blocks_1022::1 43 # Occupied blocks per task id 2619system.l2c.tags.age_task_id_blocks_1022::2 159 # Occupied blocks per task id 2620system.l2c.tags.age_task_id_blocks_1022::3 1447 # Occupied blocks per task id 2621system.l2c.tags.age_task_id_blocks_1022::4 8916 # Occupied blocks per task id 2622system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 2623system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id 2624system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 2625system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id 2626system.l2c.tags.age_task_id_blocks_1024::2 1774 # Occupied blocks per task id 2627system.l2c.tags.age_task_id_blocks_1024::3 10274 # Occupied blocks per task id 2628system.l2c.tags.age_task_id_blocks_1024::4 36522 # Occupied blocks per task id 2629system.l2c.tags.occ_task_id_percent::1022 0.161209 # Percentage of cache occupancy per task id 2630system.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id 2631system.l2c.tags.occ_task_id_percent::1024 0.746078 # Percentage of cache occupancy per task id 2632system.l2c.tags.tag_accesses 66950820 # Number of tag accesses 2633system.l2c.tags.data_accesses 66950820 # Number of data accesses 2634system.l2c.WritebackDirty_hits::writebacks 2504481 # number of WritebackDirty hits 2635system.l2c.WritebackDirty_hits::total 2504481 # number of WritebackDirty hits 2636system.l2c.UpgradeReq_hits::cpu0.data 166895 # number of UpgradeReq hits 2637system.l2c.UpgradeReq_hits::cpu1.data 113960 # number of UpgradeReq hits 2638system.l2c.UpgradeReq_hits::total 280855 # number of UpgradeReq hits 2639system.l2c.SCUpgradeReq_hits::cpu0.data 38875 # number of SCUpgradeReq hits 2640system.l2c.SCUpgradeReq_hits::cpu1.data 34247 # number of SCUpgradeReq hits 2641system.l2c.SCUpgradeReq_hits::total 73122 # number of SCUpgradeReq hits 2642system.l2c.ReadExReq_hits::cpu0.data 158326 # number of ReadExReq hits 2643system.l2c.ReadExReq_hits::cpu1.data 166214 # number of ReadExReq hits 2644system.l2c.ReadExReq_hits::total 324540 # number of ReadExReq hits 2645system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5191 # number of ReadSharedReq hits 2646system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4009 # number of ReadSharedReq hits 2647system.l2c.ReadSharedReq_hits::cpu0.inst 435451 # number of ReadSharedReq hits 2648system.l2c.ReadSharedReq_hits::cpu0.data 562405 # number of ReadSharedReq hits 2649system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296765 # number of ReadSharedReq hits 2650system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5208 # number of ReadSharedReq hits 2651system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4285 # number of ReadSharedReq hits 2652system.l2c.ReadSharedReq_hits::cpu1.inst 382834 # number of ReadSharedReq hits 2653system.l2c.ReadSharedReq_hits::cpu1.data 480125 # number of ReadSharedReq hits 2654system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 262665 # number of ReadSharedReq hits 2655system.l2c.ReadSharedReq_hits::total 2438938 # number of ReadSharedReq hits 2656system.l2c.demand_hits::cpu0.dtb.walker 5191 # number of demand (read+write) hits 2657system.l2c.demand_hits::cpu0.itb.walker 4009 # number of demand (read+write) hits 2658system.l2c.demand_hits::cpu0.inst 435451 # number of demand (read+write) hits 2659system.l2c.demand_hits::cpu0.data 720731 # number of demand (read+write) hits 2660system.l2c.demand_hits::cpu0.l2cache.prefetcher 296765 # number of demand (read+write) hits 2661system.l2c.demand_hits::cpu1.dtb.walker 5208 # number of demand (read+write) hits 2662system.l2c.demand_hits::cpu1.itb.walker 4285 # number of demand (read+write) hits 2663system.l2c.demand_hits::cpu1.inst 382834 # number of demand (read+write) hits 2664system.l2c.demand_hits::cpu1.data 646339 # number of demand (read+write) hits 2665system.l2c.demand_hits::cpu1.l2cache.prefetcher 262665 # number of demand (read+write) hits 2666system.l2c.demand_hits::total 2763478 # number of demand (read+write) hits 2667system.l2c.overall_hits::cpu0.dtb.walker 5191 # number of overall hits 2668system.l2c.overall_hits::cpu0.itb.walker 4009 # number of overall hits 2669system.l2c.overall_hits::cpu0.inst 435451 # number of overall hits 2670system.l2c.overall_hits::cpu0.data 720731 # number of overall hits 2671system.l2c.overall_hits::cpu0.l2cache.prefetcher 296765 # number of overall hits 2672system.l2c.overall_hits::cpu1.dtb.walker 5208 # number of overall hits 2673system.l2c.overall_hits::cpu1.itb.walker 4285 # number of overall hits 2674system.l2c.overall_hits::cpu1.inst 382834 # number of overall hits 2675system.l2c.overall_hits::cpu1.data 646339 # number of overall hits 2676system.l2c.overall_hits::cpu1.l2cache.prefetcher 262665 # number of overall hits 2677system.l2c.overall_hits::total 2763478 # number of overall hits 2678system.l2c.UpgradeReq_misses::cpu0.data 67422 # number of UpgradeReq misses 2679system.l2c.UpgradeReq_misses::cpu1.data 57259 # number of UpgradeReq misses 2680system.l2c.UpgradeReq_misses::total 124681 # number of UpgradeReq misses 2681system.l2c.SCUpgradeReq_misses::cpu0.data 14532 # number of SCUpgradeReq misses 2682system.l2c.SCUpgradeReq_misses::cpu1.data 11014 # number of SCUpgradeReq misses 2683system.l2c.SCUpgradeReq_misses::total 25546 # number of SCUpgradeReq misses 2684system.l2c.ReadExReq_misses::cpu0.data 480698 # number of ReadExReq misses 2685system.l2c.ReadExReq_misses::cpu1.data 148334 # number of ReadExReq misses 2686system.l2c.ReadExReq_misses::total 629032 # number of ReadExReq misses 2687system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1519 # number of ReadSharedReq misses 2688system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1645 # number of ReadSharedReq misses 2689system.l2c.ReadSharedReq_misses::cpu0.inst 47029 # number of ReadSharedReq misses 2690system.l2c.ReadSharedReq_misses::cpu0.data 136142 # number of ReadSharedReq misses 2691system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 207239 # number of ReadSharedReq misses 2692system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1062 # number of ReadSharedReq misses 2693system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1011 # number of ReadSharedReq misses 2694system.l2c.ReadSharedReq_misses::cpu1.inst 38755 # number of ReadSharedReq misses 2695system.l2c.ReadSharedReq_misses::cpu1.data 73388 # number of ReadSharedReq misses 2696system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 139305 # number of ReadSharedReq misses 2697system.l2c.ReadSharedReq_misses::total 647095 # number of ReadSharedReq misses 2698system.l2c.demand_misses::cpu0.dtb.walker 1519 # number of demand (read+write) misses 2699system.l2c.demand_misses::cpu0.itb.walker 1645 # number of demand (read+write) misses 2700system.l2c.demand_misses::cpu0.inst 47029 # number of demand (read+write) misses 2701system.l2c.demand_misses::cpu0.data 616840 # number of demand (read+write) misses 2702system.l2c.demand_misses::cpu0.l2cache.prefetcher 207239 # number of demand (read+write) misses 2703system.l2c.demand_misses::cpu1.dtb.walker 1062 # number of demand (read+write) misses 2704system.l2c.demand_misses::cpu1.itb.walker 1011 # number of demand (read+write) misses 2705system.l2c.demand_misses::cpu1.inst 38755 # number of demand (read+write) misses 2706system.l2c.demand_misses::cpu1.data 221722 # number of demand (read+write) misses 2707system.l2c.demand_misses::cpu1.l2cache.prefetcher 139305 # number of demand (read+write) misses 2708system.l2c.demand_misses::total 1276127 # number of demand (read+write) misses 2709system.l2c.overall_misses::cpu0.dtb.walker 1519 # number of overall misses 2710system.l2c.overall_misses::cpu0.itb.walker 1645 # number of overall misses 2711system.l2c.overall_misses::cpu0.inst 47029 # number of overall misses 2712system.l2c.overall_misses::cpu0.data 616840 # number of overall misses 2713system.l2c.overall_misses::cpu0.l2cache.prefetcher 207239 # number of overall misses 2714system.l2c.overall_misses::cpu1.dtb.walker 1062 # number of overall misses 2715system.l2c.overall_misses::cpu1.itb.walker 1011 # number of overall misses 2716system.l2c.overall_misses::cpu1.inst 38755 # number of overall misses 2717system.l2c.overall_misses::cpu1.data 221722 # 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number of ReadSharedReq miss cycles 2739system.l2c.ReadSharedReq_miss_latency::total 97218987006 # number of ReadSharedReq miss cycles 2740system.l2c.demand_miss_latency::cpu0.dtb.walker 210107500 # number of demand (read+write) miss cycles 2741system.l2c.demand_miss_latency::cpu0.itb.walker 226821000 # number of demand (read+write) miss cycles 2742system.l2c.demand_miss_latency::cpu0.inst 6321092000 # number of demand (read+write) miss cycles 2743system.l2c.demand_miss_latency::cpu0.data 82170890000 # number of demand (read+write) miss cycles 2744system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 33395811187 # number of demand (read+write) miss cycles 2745system.l2c.demand_miss_latency::cpu1.dtb.walker 146053000 # number of demand (read+write) miss cycles 2746system.l2c.demand_miss_latency::cpu1.itb.walker 143461000 # number of demand (read+write) miss cycles 2747system.l2c.demand_miss_latency::cpu1.inst 5220292500 # number of demand (read+write) miss cycles 2748system.l2c.demand_miss_latency::cpu1.data 29597726000 # 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number of overall miss cycles 2760system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22750846819 # number of overall miss cycles 2761system.l2c.overall_miss_latency::total 180183101006 # number of overall miss cycles 2762system.l2c.WritebackDirty_accesses::writebacks 2504481 # number of WritebackDirty accesses(hits+misses) 2763system.l2c.WritebackDirty_accesses::total 2504481 # number of WritebackDirty accesses(hits+misses) 2764system.l2c.UpgradeReq_accesses::cpu0.data 234317 # number of UpgradeReq accesses(hits+misses) 2765system.l2c.UpgradeReq_accesses::cpu1.data 171219 # number of UpgradeReq accesses(hits+misses) 2766system.l2c.UpgradeReq_accesses::total 405536 # number of UpgradeReq accesses(hits+misses) 2767system.l2c.SCUpgradeReq_accesses::cpu0.data 53407 # number of SCUpgradeReq accesses(hits+misses) 2768system.l2c.SCUpgradeReq_accesses::cpu1.data 45261 # number of SCUpgradeReq accesses(hits+misses) 2769system.l2c.SCUpgradeReq_accesses::total 98668 # number of SCUpgradeReq accesses(hits+misses) 2770system.l2c.ReadExReq_accesses::cpu0.data 639024 # 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number of ReadSharedReq accesses(hits+misses) 2781system.l2c.ReadSharedReq_accesses::cpu1.data 553513 # number of ReadSharedReq accesses(hits+misses) 2782system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 401970 # number of ReadSharedReq accesses(hits+misses) 2783system.l2c.ReadSharedReq_accesses::total 3086033 # number of ReadSharedReq accesses(hits+misses) 2784system.l2c.demand_accesses::cpu0.dtb.walker 6710 # number of demand (read+write) accesses 2785system.l2c.demand_accesses::cpu0.itb.walker 5654 # number of demand (read+write) accesses 2786system.l2c.demand_accesses::cpu0.inst 482480 # number of demand (read+write) accesses 2787system.l2c.demand_accesses::cpu0.data 1337571 # number of demand (read+write) accesses 2788system.l2c.demand_accesses::cpu0.l2cache.prefetcher 504004 # number of demand (read+write) accesses 2789system.l2c.demand_accesses::cpu1.dtb.walker 6270 # number of demand (read+write) accesses 2790system.l2c.demand_accesses::cpu1.itb.walker 5296 # number of demand (read+write) accesses 2791system.l2c.demand_accesses::cpu1.inst 421589 # number of demand (read+write) accesses 2792system.l2c.demand_accesses::cpu1.data 868061 # number of demand (read+write) accesses 2793system.l2c.demand_accesses::cpu1.l2cache.prefetcher 401970 # number of demand (read+write) accesses 2794system.l2c.demand_accesses::total 4039605 # number of demand (read+write) accesses 2795system.l2c.overall_accesses::cpu0.dtb.walker 6710 # number of overall (read+write) accesses 2796system.l2c.overall_accesses::cpu0.itb.walker 5654 # number of overall (read+write) accesses 2797system.l2c.overall_accesses::cpu0.inst 482480 # number of overall (read+write) accesses 2798system.l2c.overall_accesses::cpu0.data 1337571 # number of overall (read+write) accesses 2799system.l2c.overall_accesses::cpu0.l2cache.prefetcher 504004 # number of overall (read+write) accesses 2800system.l2c.overall_accesses::cpu1.dtb.walker 6270 # number of overall (read+write) accesses 2801system.l2c.overall_accesses::cpu1.itb.walker 5296 # number of overall (read+write) accesses 2802system.l2c.overall_accesses::cpu1.inst 421589 # number of overall (read+write) accesses 2803system.l2c.overall_accesses::cpu1.data 868061 # number of overall (read+write) accesses 2804system.l2c.overall_accesses::cpu1.l2cache.prefetcher 401970 # number of overall (read+write) accesses 2805system.l2c.overall_accesses::total 4039605 # number of overall (read+write) accesses 2806system.l2c.UpgradeReq_miss_rate::cpu0.data 0.287738 # miss rate for UpgradeReq accesses 2807system.l2c.UpgradeReq_miss_rate::cpu1.data 0.334420 # miss rate for UpgradeReq accesses 2808system.l2c.UpgradeReq_miss_rate::total 0.307447 # miss rate for UpgradeReq accesses 2809system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.272099 # miss rate for SCUpgradeReq accesses 2810system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.243344 # miss rate for SCUpgradeReq accesses 2811system.l2c.SCUpgradeReq_miss_rate::total 0.258909 # miss rate for SCUpgradeReq accesses 2812system.l2c.ReadExReq_miss_rate::cpu0.data 0.752238 # miss rate for ReadExReq accesses 2813system.l2c.ReadExReq_miss_rate::cpu1.data 0.471578 # miss rate for ReadExReq accesses 2814system.l2c.ReadExReq_miss_rate::total 0.659659 # miss rate for ReadExReq accesses 2815system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.226379 # miss rate for ReadSharedReq accesses 2816system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.290944 # miss rate for ReadSharedReq accesses 2817system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.097473 # miss rate for ReadSharedReq accesses 2818system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.194893 # miss rate for ReadSharedReq accesses 2819system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.411185 # miss rate for ReadSharedReq accesses 2820system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.169378 # miss rate for ReadSharedReq accesses 2821system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.190899 # miss rate for ReadSharedReq accesses 2822system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.091926 # miss rate for ReadSharedReq accesses 2823system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.132586 # miss rate for ReadSharedReq accesses 2824system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.346556 # miss rate for ReadSharedReq accesses 2825system.l2c.ReadSharedReq_miss_rate::total 0.209685 # miss rate for ReadSharedReq accesses 2826system.l2c.demand_miss_rate::cpu0.dtb.walker 0.226379 # miss rate for demand accesses 2827system.l2c.demand_miss_rate::cpu0.itb.walker 0.290944 # miss rate for demand accesses 2828system.l2c.demand_miss_rate::cpu0.inst 0.097473 # miss rate for demand accesses 2829system.l2c.demand_miss_rate::cpu0.data 0.461164 # miss rate for demand accesses 2830system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.411185 # miss rate for demand accesses 2831system.l2c.demand_miss_rate::cpu1.dtb.walker 0.169378 # miss rate for demand accesses 2832system.l2c.demand_miss_rate::cpu1.itb.walker 0.190899 # miss rate for demand accesses 2833system.l2c.demand_miss_rate::cpu1.inst 0.091926 # miss rate for demand accesses 2834system.l2c.demand_miss_rate::cpu1.data 0.255422 # miss rate for demand accesses 2835system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.346556 # miss rate for demand accesses 2836system.l2c.demand_miss_rate::total 0.315904 # miss rate for demand accesses 2837system.l2c.overall_miss_rate::cpu0.dtb.walker 0.226379 # miss rate for overall accesses 2838system.l2c.overall_miss_rate::cpu0.itb.walker 0.290944 # miss rate for overall accesses 2839system.l2c.overall_miss_rate::cpu0.inst 0.097473 # miss rate for overall accesses 2840system.l2c.overall_miss_rate::cpu0.data 0.461164 # miss rate for overall accesses 2841system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.411185 # miss rate for overall accesses 2842system.l2c.overall_miss_rate::cpu1.dtb.walker 0.169378 # miss rate for overall accesses 2843system.l2c.overall_miss_rate::cpu1.itb.walker 0.190899 # miss rate for overall accesses 2844system.l2c.overall_miss_rate::cpu1.inst 0.091926 # miss rate for overall accesses 2845system.l2c.overall_miss_rate::cpu1.data 0.255422 # miss rate for overall accesses 2846system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.346556 # miss rate for overall accesses 2847system.l2c.overall_miss_rate::total 0.315904 # miss rate for overall accesses 2848system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 14741.797929 # average UpgradeReq miss latency 2849system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16960.661206 # average UpgradeReq miss latency 2850system.l2c.UpgradeReq_avg_miss_latency::total 15760.797555 # average UpgradeReq miss latency 2851system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 13236.753372 # average SCUpgradeReq miss latency 2852system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15447.203559 # average SCUpgradeReq miss latency 2853system.l2c.SCUpgradeReq_avg_miss_latency::total 14189.775307 # average SCUpgradeReq miss latency 2854system.l2c.ReadExReq_avg_miss_latency::cpu0.data 132211.786818 # average ReadExReq miss latency 2855system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130854.507395 # average ReadExReq miss latency 2856system.l2c.ReadExReq_avg_miss_latency::total 131891.722520 # average ReadExReq miss latency 2857system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 138319.618170 # average ReadSharedReq miss latency 2858system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 137885.106383 # average ReadSharedReq miss latency 2859system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134408.386315 # average ReadSharedReq miss latency 2860system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136746.547722 # average ReadSharedReq miss latency 2861system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315 # average ReadSharedReq miss latency 2862system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 137526.365348 # average ReadSharedReq miss latency 2863system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141900.098912 # average ReadSharedReq miss latency 2864system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134699.845181 # average ReadSharedReq miss latency 2865system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 138817.701804 # average ReadSharedReq miss latency 2866system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964 # 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average overall miss latency 2877system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964 # average overall miss latency 2878system.l2c.demand_avg_miss_latency::total 141195.273673 # average overall miss latency 2879system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138319.618170 # average overall miss latency 2880system.l2c.overall_avg_miss_latency::cpu0.itb.walker 137885.106383 # average overall miss latency 2881system.l2c.overall_avg_miss_latency::cpu0.inst 134408.386315 # average overall miss latency 2882system.l2c.overall_avg_miss_latency::cpu0.data 133212.648337 # average overall miss latency 2883system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 161146.363315 # average overall miss latency 2884system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 137526.365348 # average overall miss latency 2885system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141900.098912 # average overall miss latency 2886system.l2c.overall_avg_miss_latency::cpu1.inst 134699.845181 # average overall miss latency 2887system.l2c.overall_avg_miss_latency::cpu1.data 133490.253561 # average overall miss latency 2888system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 163316.799964 # average overall miss latency 2889system.l2c.overall_avg_miss_latency::total 141195.273673 # average overall miss latency 2890system.l2c.blocked_cycles::no_mshrs 366 # number of cycles access was blocked 2891system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2892system.l2c.blocked::no_mshrs 6 # number of cycles access was blocked 2893system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2894system.l2c.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked 2895system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2896system.l2c.fast_writes 0 # number of fast writes performed 2897system.l2c.cache_copies 0 # number of cache copies performed 2898system.l2c.writebacks::writebacks 971265 # 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number of overall MSHR misses 2956system.l2c.overall_mshr_misses::cpu1.data 221696 # number of overall MSHR misses 2957system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 139305 # number of overall MSHR misses 2958system.l2c.overall_mshr_misses::total 1275903 # number of overall MSHR misses 2959system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 2960system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15619 # number of ReadReq MSHR uncacheable 2961system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2962system.l2c.ReadReq_mshr_uncacheable::cpu1.data 23609 # number of ReadReq MSHR uncacheable 2963system.l2c.ReadReq_mshr_uncacheable::total 82463 # number of ReadReq MSHR uncacheable 2964system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16479 # number of WriteReq MSHR uncacheable 2965system.l2c.WriteReq_mshr_uncacheable::cpu1.data 22620 # number of WriteReq MSHR uncacheable 2966system.l2c.WriteReq_mshr_uncacheable::total 39099 # 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number of overall MSHR miss cycles 3004system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 210371000 # number of overall MSHR miss cycles 3005system.l2c.overall_mshr_miss_latency::cpu0.inst 5842188000 # number of overall MSHR miss cycles 3006system.l2c.overall_mshr_miss_latency::cpu0.data 76001732000 # number of overall MSHR miss cycles 3007system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 31323421187 # number of overall MSHR miss cycles 3008system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 135433000 # number of overall MSHR miss cycles 3009system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 133351000 # number of overall MSHR miss cycles 3010system.l2c.overall_mshr_miss_latency::cpu1.inst 4820369500 # number of overall MSHR miss cycles 3011system.l2c.overall_mshr_miss_latency::cpu1.data 27377770000 # number of overall MSHR miss cycles 3012system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21357796819 # number of overall MSHR miss cycles 3013system.l2c.overall_mshr_miss_latency::total 167397350006 # number of overall MSHR miss cycles 3014system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of ReadReq MSHR uncacheable cycles 3015system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2284412000 # number of ReadReq MSHR uncacheable cycles 3016system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 11994000 # number of ReadReq MSHR uncacheable cycles 3017system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3673036000 # number of ReadReq MSHR uncacheable cycles 3018system.l2c.ReadReq_mshr_uncacheable_latency::total 10823963000 # number of ReadReq MSHR uncacheable cycles 3019system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2391400000 # number of WriteReq MSHR uncacheable cycles 3020system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3605950000 # number of WriteReq MSHR uncacheable cycles 3021system.l2c.WriteReq_mshr_uncacheable_latency::total 5997350000 # number of WriteReq MSHR uncacheable cycles 3022system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 4854521000 # number of overall MSHR uncacheable cycles 3023system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4675812000 # number of overall MSHR uncacheable cycles 3024system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 11994000 # number of overall MSHR uncacheable cycles 3025system.l2c.overall_mshr_uncacheable_latency::cpu1.data 7278986000 # number of overall MSHR uncacheable cycles 3026system.l2c.overall_mshr_uncacheable_latency::total 16821313000 # number of overall MSHR uncacheable cycles 3027system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3028system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3029system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.287738 # mshr miss rate for UpgradeReq accesses 3030system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.334420 # mshr miss rate for UpgradeReq accesses 3031system.l2c.UpgradeReq_mshr_miss_rate::total 0.307447 # mshr miss rate for UpgradeReq accesses 3032system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.272099 # mshr miss rate for SCUpgradeReq accesses 3033system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.243344 # mshr miss rate for SCUpgradeReq accesses 3034system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.258909 # mshr miss rate for SCUpgradeReq accesses 3035system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.752238 # mshr miss rate for ReadExReq accesses 3036system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.471578 # mshr miss rate for ReadExReq accesses 3037system.l2c.ReadExReq_mshr_miss_rate::total 0.659659 # mshr miss rate for ReadExReq accesses 3038system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.226379 # mshr miss rate for ReadSharedReq accesses 3039system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.290944 # mshr miss rate for ReadSharedReq accesses 3040system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.097312 # mshr miss rate for ReadSharedReq accesses 3041system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.194882 # mshr miss rate for ReadSharedReq accesses 3042system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411185 # mshr miss rate for ReadSharedReq accesses 3043system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.169378 # mshr miss rate for ReadSharedReq accesses 3044system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.190899 # mshr miss rate for ReadSharedReq accesses 3045system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.091660 # mshr miss rate for ReadSharedReq accesses 3046system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.132539 # mshr miss rate for ReadSharedReq accesses 3047system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.346556 # mshr miss rate for ReadSharedReq accesses 3048system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209612 # mshr miss rate for ReadSharedReq accesses 3049system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.226379 # mshr miss rate for demand accesses 3050system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.290944 # mshr miss rate for demand accesses 3051system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097312 # mshr miss rate for demand accesses 3052system.l2c.demand_mshr_miss_rate::cpu0.data 0.461158 # mshr miss rate for demand accesses 3053system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411185 # mshr miss rate for demand accesses 3054system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.169378 # mshr miss rate for demand accesses 3055system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.190899 # mshr miss rate for demand accesses 3056system.l2c.demand_mshr_miss_rate::cpu1.inst 0.091660 # mshr miss rate for demand accesses 3057system.l2c.demand_mshr_miss_rate::cpu1.data 0.255392 # mshr miss rate for demand accesses 3058system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.346556 # mshr miss rate for demand accesses 3059system.l2c.demand_mshr_miss_rate::total 0.315848 # mshr miss rate for demand accesses 3060system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.226379 # mshr miss rate for overall accesses 3061system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.290944 # mshr miss rate for overall accesses 3062system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097312 # mshr miss rate for overall accesses 3063system.l2c.overall_mshr_miss_rate::cpu0.data 0.461158 # mshr miss rate for overall accesses 3064system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411185 # mshr miss rate for overall accesses 3065system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.169378 # mshr miss rate for overall accesses 3066system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.190899 # mshr miss rate for overall accesses 3067system.l2c.overall_mshr_miss_rate::cpu1.inst 0.091660 # mshr miss rate for overall accesses 3068system.l2c.overall_mshr_miss_rate::cpu1.data 0.255392 # mshr miss rate for overall accesses 3069system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.346556 # mshr miss rate for overall accesses 3070system.l2c.overall_mshr_miss_rate::total 0.315848 # mshr miss rate for overall accesses 3071system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73808.148676 # average UpgradeReq mshr miss latency 3072system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73501.082799 # average UpgradeReq mshr miss latency 3073system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73667.130517 # average UpgradeReq mshr miss latency 3074system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76654.176989 # average SCUpgradeReq mshr miss latency 3075system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76510.668240 # average SCUpgradeReq mshr miss latency 3076system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76592.304079 # average SCUpgradeReq mshr miss latency 3077system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 122211.786818 # average ReadExReq mshr miss latency 3078system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120854.507395 # average ReadExReq mshr miss latency 3079system.l2c.ReadExReq_avg_mshr_miss_latency::total 121891.722520 # average ReadExReq mshr miss latency 3080system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average ReadSharedReq mshr miss latency 3081system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average ReadSharedReq mshr miss latency 3082system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average ReadSharedReq mshr miss latency 3083system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126748.428019 # average ReadSharedReq mshr miss latency 3084system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average ReadSharedReq mshr miss latency 3085system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average ReadSharedReq mshr miss latency 3086system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average ReadSharedReq mshr miss latency 3087system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average ReadSharedReq mshr miss latency 3088system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128826.061176 # average ReadSharedReq mshr miss latency 3089system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average ReadSharedReq mshr miss latency 3090system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 140249.842714 # average ReadSharedReq mshr miss latency 3091system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average overall mshr miss latency 3092system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average overall mshr miss latency 3093system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average overall mshr miss latency 3094system.l2c.demand_avg_mshr_miss_latency::cpu0.data 123213.017483 # average overall mshr miss latency 3095system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average overall mshr miss latency 3096system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average overall mshr miss latency 3097system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average overall mshr miss latency 3098system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average overall mshr miss latency 3099system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123492.394991 # average overall mshr miss latency 3100system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average overall mshr miss latency 3101system.l2c.demand_avg_mshr_miss_latency::total 131199.119373 # average overall mshr miss latency 3102system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128319.618170 # average overall mshr miss latency 3103system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127885.106383 # average overall mshr miss latency 3104system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124431.598901 # average overall mshr miss latency 3105system.l2c.overall_avg_mshr_miss_latency::cpu0.data 123213.017483 # average overall mshr miss latency 3106system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 151146.363315 # average overall mshr miss latency 3107system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127526.365348 # average overall mshr miss latency 3108system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131900.098912 # average overall mshr miss latency 3109system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124741.078591 # average overall mshr miss latency 3110system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123492.394991 # average overall mshr miss latency 3111system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 153316.799964 # average overall mshr miss latency 3112system.l2c.overall_avg_mshr_miss_latency::total 131199.119373 # average overall mshr miss latency 3113system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average ReadReq mshr uncacheable latency 3114system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 146258.531276 # average ReadReq mshr uncacheable latency 3115system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average ReadReq mshr uncacheable latency 3116system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 155577.788132 # average ReadReq mshr uncacheable latency 3117system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131258.418927 # average ReadReq mshr uncacheable latency 3118system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145118.029007 # average WriteReq mshr uncacheable latency 3119system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159414.235190 # average WriteReq mshr uncacheable latency 3120system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153388.833474 # average WriteReq mshr uncacheable latency 3121system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112568.602899 # average overall mshr uncacheable latency 3122system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 145673.001433 # average overall mshr uncacheable latency 3123system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 109036.363636 # average overall mshr uncacheable latency 3124system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 157454.974150 # average overall mshr uncacheable latency 3125system.l2c.overall_avg_mshr_uncacheable_latency::total 138376.408746 # average overall mshr uncacheable latency 3126system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3127system.membus.trans_dist::ReadReq 82463 # Transaction distribution 3128system.membus.trans_dist::ReadResp 738269 # Transaction distribution 3129system.membus.trans_dist::WriteReq 39099 # Transaction distribution 3130system.membus.trans_dist::WriteResp 39099 # Transaction distribution 3131system.membus.trans_dist::WritebackDirty 1078222 # Transaction distribution 3132system.membus.trans_dist::CleanEvict 196131 # Transaction distribution 3133system.membus.trans_dist::UpgradeReq 410883 # Transaction distribution 3134system.membus.trans_dist::SCUpgradeReq 321341 # Transaction distribution 3135system.membus.trans_dist::UpgradeResp 158448 # Transaction distribution 3136system.membus.trans_dist::ReadExReq 644070 # Transaction distribution 3137system.membus.trans_dist::ReadExResp 620815 # Transaction distribution 3138system.membus.trans_dist::ReadSharedReq 655806 # Transaction distribution 3139system.membus.trans_dist::InvalidateReq 106983 # Transaction distribution 3140system.membus.trans_dist::InvalidateResp 106983 # Transaction distribution 3141system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123128 # Packet count per connected master and slave (bytes) 3142system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3143system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28306 # Packet count per connected master and slave (bytes) 3144system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4701222 # Packet count per connected master and slave (bytes) 3145system.membus.pkt_count_system.l2c.mem_side::total 4852748 # Packet count per connected master and slave (bytes) 3146system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342712 # Packet count per connected master and slave (bytes) 3147system.membus.pkt_count_system.iocache.mem_side::total 342712 # Packet count per connected master and slave (bytes) 3148system.membus.pkt_count::total 5195460 # Packet count per connected master and slave (bytes) 3149system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156143 # Cumulative packet size per connected master and slave (bytes) 3150system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3151system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56612 # Cumulative packet size per connected master and slave (bytes) 3152system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 143440556 # Cumulative packet size per connected master and slave (bytes) 3153system.membus.pkt_size_system.l2c.mem_side::total 143653515 # Cumulative packet size per connected master and slave (bytes) 3154system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7262336 # Cumulative packet size per connected master and slave (bytes) 3155system.membus.pkt_size_system.iocache.mem_side::total 7262336 # Cumulative packet size per connected master and slave (bytes) 3156system.membus.pkt_size::total 150915851 # Cumulative packet size per connected master and slave (bytes) 3157system.membus.snoops 600183 # Total snoops (count) 3158system.membus.snoop_fanout::samples 3537604 # Request fanout histogram 3159system.membus.snoop_fanout::mean 1 # Request fanout histogram 3160system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3161system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3162system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3163system.membus.snoop_fanout::1 3537604 100.00% 100.00% # Request fanout histogram 3164system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3165system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3166system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3167system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3168system.membus.snoop_fanout::total 3537604 # Request fanout histogram 3169system.membus.reqLayer0.occupancy 101645000 # Layer occupancy (ticks) 3170system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3171system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 3172system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3173system.membus.reqLayer2.occupancy 23516499 # Layer occupancy (ticks) 3174system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3175system.membus.reqLayer5.occupancy 7437675124 # Layer occupancy (ticks) 3176system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3177system.membus.respLayer2.occupancy 7217345032 # Layer occupancy (ticks) 3178system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3179system.membus.respLayer3.occupancy 228825593 # Layer occupancy (ticks) 3180system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3181system.realview.ethernet.txBytes 966 # Bytes Transmitted 3182system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3183system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3184system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3185system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3186system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3187system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3188system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3189system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3190system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s) 3191system.realview.ethernet.totPackets 3 # Total Packets 3192system.realview.ethernet.totBytes 966 # Total Bytes 3193system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3194system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s) 3195system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3196system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3197system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3198system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3199system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3200system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3201system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3202system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3203system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3204system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3205system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3206system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3207system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3208system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3209system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3210system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3211system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3212system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3213system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3214system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3215system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3216system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3217system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3218system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3219system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3220system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3221system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3222system.realview.ethernet.droppedPackets 0 # number of packets dropped 3223system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 3224system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 3225system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 3226system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 3227system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 3228system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 3229system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 3230system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 3231system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 3232system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 3233system.toL2Bus.snoop_filter.tot_requests 10517449 # Total number of requests made to the snoop filter. 3234system.toL2Bus.snoop_filter.hit_single_requests 5725465 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3235system.toL2Bus.snoop_filter.hit_multi_requests 1766756 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3236system.toL2Bus.snoop_filter.tot_snoops 114752 # Total number of snoops made to the snoop filter. 3237system.toL2Bus.snoop_filter.hit_single_snoops 104186 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3238system.toL2Bus.snoop_filter.hit_multi_snoops 10566 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3239system.toL2Bus.trans_dist::ReadReq 82465 # Transaction distribution 3240system.toL2Bus.trans_dist::ReadResp 3940978 # Transaction distribution 3241system.toL2Bus.trans_dist::WriteReq 39099 # Transaction distribution 3242system.toL2Bus.trans_dist::WriteResp 39099 # Transaction distribution 3243system.toL2Bus.trans_dist::WritebackDirty 3582727 # Transaction distribution 3244system.toL2Bus.trans_dist::CleanEvict 1240251 # Transaction distribution 3245system.toL2Bus.trans_dist::UpgradeReq 683521 # Transaction distribution 3246system.toL2Bus.trans_dist::SCUpgradeReq 394463 # Transaction distribution 3247system.toL2Bus.trans_dist::UpgradeResp 1077983 # Transaction distribution 3248system.toL2Bus.trans_dist::SCUpgradeFailReq 128 # Transaction distribution 3249system.toL2Bus.trans_dist::UpgradeFailResp 128 # Transaction distribution 3250system.toL2Bus.trans_dist::ReadExReq 1083401 # Transaction distribution 3251system.toL2Bus.trans_dist::ReadExResp 1083400 # Transaction distribution 3252system.toL2Bus.trans_dist::ReadSharedReq 3865739 # Transaction distribution 3253system.toL2Bus.trans_dist::InvalidateReq 106983 # Transaction distribution 3254system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8168699 # Packet count per connected master and slave (bytes) 3255system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6135080 # Packet count per connected master and slave (bytes) 3256system.toL2Bus.pkt_count::total 14303779 # Packet count per connected master and slave (bytes) 3257system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 247232417 # Cumulative packet size per connected master and slave (bytes) 3258system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 172105066 # Cumulative packet size per connected master and slave (bytes) 3259system.toL2Bus.pkt_size::total 419337483 # Cumulative packet size per connected master and slave (bytes) 3260system.toL2Bus.snoops 2918298 # Total snoops (count) 3261system.toL2Bus.snoop_fanout::samples 7581961 # Request fanout histogram 3262system.toL2Bus.snoop_fanout::mean 0.362851 # Request fanout histogram 3263system.toL2Bus.snoop_fanout::stdev 0.483712 # Request fanout histogram 3264system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3265system.toL2Bus.snoop_fanout::0 4841404 63.85% 63.85% # Request fanout histogram 3266system.toL2Bus.snoop_fanout::1 2729991 36.01% 99.86% # Request fanout histogram 3267system.toL2Bus.snoop_fanout::2 10566 0.14% 100.00% # Request fanout histogram 3268system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3269system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3270system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3271system.toL2Bus.snoop_fanout::total 7581961 # Request fanout histogram 3272system.toL2Bus.reqLayer0.occupancy 8230397518 # Layer occupancy (ticks) 3273system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3274system.toL2Bus.snoopLayer0.occupancy 2646637 # Layer occupancy (ticks) 3275system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3276system.toL2Bus.respLayer0.occupancy 4512530115 # Layer occupancy (ticks) 3277system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3278system.toL2Bus.respLayer1.occupancy 3554923231 # Layer occupancy (ticks) 3279system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3280 3281---------- End Simulation Statistics ---------- 3282