stats.txt revision 11754
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 311754Sandreas.hansson@arm.comsim_seconds 47.177074 # Number of seconds simulated 411754Sandreas.hansson@arm.comsim_ticks 47177073828000 # Number of ticks simulated 511754Sandreas.hansson@arm.comfinal_tick 47177073828000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 1523218 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 1791835 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 73539001789 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 696552 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 641.52 # Real time elapsed on the host 1211754Sandreas.hansson@arm.comsim_insts 977181439 # Number of instructions simulated 1311754Sandreas.hansson@arm.comsim_ops 1149505972 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1611754Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 1711754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 157952 # Number of bytes read from this memory 1811754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 131712 # Number of bytes read from this memory 1911754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 4192628 # Number of bytes read from this memory 2011754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 35968392 # Number of bytes read from this memory 2111754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 222400 # Number of bytes read from this memory 2211754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 221568 # Number of bytes read from this memory 2311754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3097544 # Number of bytes read from this memory 2411754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 39307632 # Number of bytes read from this memory 2511754Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 413888 # Number of bytes read from this memory 2611754Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 83713716 # Number of bytes read from this memory 2711754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 4192628 # Number of instructions bytes read from this memory 2811754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3097544 # Number of instructions bytes read from this memory 2911754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 7290172 # Number of instructions bytes read from this memory 3011754Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 102127744 # Number of bytes written to this memory 3110827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3210585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3311754Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 102148328 # Number of bytes written to this memory 3411754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2468 # Number of read requests responded to by this memory 3511754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2058 # Number of read requests responded to by this memory 3611754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 105917 # Number of read requests responded to by this memory 3711754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 562019 # Number of read requests responded to by this memory 3811754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3475 # Number of read requests responded to by this memory 3911754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3462 # Number of read requests responded to by this memory 4011754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 48506 # Number of read requests responded to by this memory 4111754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 614198 # Number of read requests responded to by this memory 4211754Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6467 # Number of read requests responded to by this memory 4311754Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1348570 # Number of read requests responded to by this memory 4411754Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1595746 # Number of write requests responded to by this memory 4510827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4610585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4711754Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1598320 # Number of write requests responded to by this memory 4811754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3348 # Total read bandwidth from this memory (bytes/s) 4911754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2792 # Total read bandwidth from this memory (bytes/s) 5011754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 88870 # Total read bandwidth from this memory (bytes/s) 5111754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 762413 # Total read bandwidth from this memory (bytes/s) 5211754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4714 # Total read bandwidth from this memory (bytes/s) 5311754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4697 # Total read bandwidth from this memory (bytes/s) 5411754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 65658 # Total read bandwidth from this memory (bytes/s) 5511754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 833194 # Total read bandwidth from this memory (bytes/s) 5611754Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8773 # Total read bandwidth from this memory (bytes/s) 5711754Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1774458 # Total read bandwidth from this memory (bytes/s) 5811754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 88870 # Instruction read bandwidth from this memory (bytes/s) 5911754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 65658 # Instruction read bandwidth from this memory (bytes/s) 6011754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 154528 # Instruction read bandwidth from this memory (bytes/s) 6111754Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2164775 # Write bandwidth from this memory (bytes/s) 6211754Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) 6310585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6411754Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2165211 # Write bandwidth from this memory (bytes/s) 6511754Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2164775 # Total bandwidth to/from this memory (bytes/s) 6611754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3348 # Total bandwidth to/from this memory (bytes/s) 6711754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2792 # Total bandwidth to/from this memory (bytes/s) 6811754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 88870 # Total bandwidth to/from this memory (bytes/s) 6911754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 762849 # Total bandwidth to/from this memory (bytes/s) 7011754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4714 # Total bandwidth to/from this memory (bytes/s) 7111754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4697 # Total bandwidth to/from this memory (bytes/s) 7211754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 65658 # Total bandwidth to/from this memory (bytes/s) 7311754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 833194 # Total bandwidth to/from this memory (bytes/s) 7411754Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8773 # Total bandwidth to/from this memory (bytes/s) 7511754Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3939669 # Total bandwidth to/from this memory (bytes/s) 7611754Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 7710515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8410515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8910515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 9010515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 10110515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10210515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10311754Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 10411754Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 10511754Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 10610585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10710585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10810585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10910585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 11010585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 11110585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 11210515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 11311754Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 11610628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11710628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 11810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 11910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 12010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 12110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 13010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 13110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 13210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 13310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 13410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 13510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 14010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 14110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 14210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 14311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 14411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 123270 # Table walker walks requested 14511754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 123270 # Table walker walks initiated with long descriptors 14611754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 123270 # Table walker wait (enqueue to first request) latency 14711754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 123270 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14811754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 123270 # Table walker wait (enqueue to first request) latency 14910628SN/Asystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 15010628SN/Asystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 15110628SN/Asystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 15211754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 94962 90.03% 90.03% # Table walker page sizes translated 15311754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 10516 9.97% 100.00% # Table walker page sizes translated 15411754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 105478 # Table walker page sizes translated 15511754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123270 # Table walker requests started/completed, data/inst 15610628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15711754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123270 # Table walker requests started/completed, data/inst 15811754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 105478 # Table walker requests started/completed, data/inst 15910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 16011754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 105478 # Table walker requests started/completed, data/inst 16111754Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 228748 # Table walker requests started/completed, data/inst 16210585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 16310585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 16411754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 90958252 # DTB read hits 16511754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 87293 # DTB read misses 16611754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 84301704 # DTB write hits 16711754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 35977 # DTB write misses 16810585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 16910585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 17011754Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 17110585SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 17211754Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 35878 # Number of entries that have been flushed from TLB 17310585SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 17411754Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 5554 # Number of TLB faults due to prefetch 17510585SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 17611754Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 10284 # Number of TLB faults due to permissions restrictions 17711754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 91045545 # DTB read accesses 17811754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 84337681 # DTB write accesses 17910585SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 18011754Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 175259956 # DTB hits 18111754Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 123270 # DTB misses 18211754Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 175383226 # DTB accesses 18311754Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 18410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 18510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 18610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 18710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 18810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 19010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 19110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 19210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 19310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 19410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 19510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 19610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 19710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 19810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 20010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 20110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 20210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 20310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 20410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 20510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 20610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 20710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 21010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 21110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 21210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 21311754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 21411754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 60279 # Table walker walks requested 21511754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 60279 # Table walker walks initiated with long descriptors 21611754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 60279 # Table walker wait (enqueue to first request) latency 21711754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 60279 100.00% 100.00% # Table walker wait (enqueue to first request) latency 21811754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 60279 # Table walker wait (enqueue to first request) latency 21910628SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 22010628SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 22110628SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 22211754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 54211 98.84% 98.84% # Table walker page sizes translated 22311754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 635 1.16% 100.00% # Table walker page sizes translated 22411754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 54846 # Table walker page sizes translated 22510628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 22611754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60279 # Table walker requests started/completed, data/inst 22711754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 60279 # Table walker requests started/completed, data/inst 22810628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 22911754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54846 # Table walker requests started/completed, data/inst 23011754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 54846 # Table walker requests started/completed, data/inst 23111754Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 115125 # Table walker requests started/completed, data/inst 23211754Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 489463139 # ITB inst hits 23311754Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 60279 # ITB inst misses 23410585SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 23510585SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 23610585SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 23710585SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 23810585SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23910585SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 24011754Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 24110585SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 24211754Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 24716 # Number of entries that have been flushed from TLB 24310585SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 24410585SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 24510585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 24610585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 24710585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 24810585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 24911754Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 489523418 # ITB inst accesses 25011754Sandreas.hansson@arm.comsystem.cpu0.itb.hits 489463139 # DTB hits 25111754Sandreas.hansson@arm.comsystem.cpu0.itb.misses 60279 # DTB misses 25211754Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 489523418 # DTB accesses 25311754Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 26258 # Number of power state transitions 25411754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 13129 # Distribution of time spent in the clock gated state 25511754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 3571424062.507959 # Distribution of time spent in the clock gated state 25611754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 90351330790.457672 # Distribution of time spent in the clock gated state 25711754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 3131 23.85% 23.85% # Distribution of time spent in the clock gated state 25811754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 9971 75.95% 99.79% # Distribution of time spent in the clock gated state 25911530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 3 0.02% 99.82% # Distribution of time spent in the clock gated state 26011530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.83% # Distribution of time spent in the clock gated state 26111530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 26211754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state 26311754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 26411754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 26511754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 26611754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 26711530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state 26811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 26911754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 7510114609000 # Distribution of time spent in the clock gated state 27011754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 13129 # Distribution of time spent in the clock gated state 27111754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 287847311333 # Cumulative time (in ticks) in various power states 27211754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 46889226516667 # Cumulative time (in ticks) in various power states 27311754Sandreas.hansson@arm.comsystem.cpu0.numCycles 94354160786 # number of cpu cycles simulated 27410585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 27510585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 27611167Sjthestness@gmail.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 27711754Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 13129 # number of quiesce instructions executed 27811754Sandreas.hansson@arm.comsystem.cpu0.committedInsts 489228722 # Number of instructions committed 27911754Sandreas.hansson@arm.comsystem.cpu0.committedOps 575357792 # Number of ops (including micro ops) committed 28011754Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 527304848 # Number of integer alu accesses 28111754Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 518985 # Number of float alu accesses 28211754Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 28507888 # number of times a function call or return occured 28311754Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 75158499 # number of instructions that are conditional controls 28411754Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 527304848 # number of integer instructions 28511754Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 518985 # number of float instructions 28611754Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 772493030 # number of times the integer registers were read 28711754Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 418386904 # number of times the integer registers were written 28811754Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 837696 # number of times the floating registers were read 28911754Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 439396 # number of times the floating registers were written 29011754Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 131494560 # number of times the CC registers were read 29111754Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 131170441 # number of times the CC registers were written 29211754Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 175360180 # number of memory refs 29311754Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 91031152 # Number of load instructions 29411754Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 84329028 # Number of store instructions 29511754Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93778466083.220322 # Number of idle cycles 29611754Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 575694702.779680 # Number of busy cycles 29711754Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.006101 # Percentage of non-idle cycles 29811754Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.993899 # Percentage of idle cycles 29911754Sandreas.hansson@arm.comsystem.cpu0.Branches 109461640 # Number of branches fetched 30010585SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 30111754Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 398983706 69.31% 69.31% # Class of executed instruction 30211754Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1214289 0.21% 69.52% # Class of executed instruction 30311754Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 59472 0.01% 69.53% # Class of executed instruction 30411754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 8 0.00% 69.53% # Class of executed instruction 30511754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 13 0.00% 69.53% # Class of executed instruction 30611754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 21 0.00% 69.53% # Class of executed instruction 30711754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction 30811754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMultAcc 0 0.00% 69.53% # Class of executed instruction 30911754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction 31011754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMisc 72490 0.01% 69.54% # Class of executed instruction 31111754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 31211754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 31311754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 31411754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 31511754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 31611754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 31711754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 31811754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 31911754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 32011754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 32111754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 32211754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 32311754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction 32411754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 32511754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction 32611754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction 32711754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 32811754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 69.54% # Class of executed instruction 32911754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction 33011754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction 33111754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction 33211754Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 90970869 15.80% 85.34% # Class of executed instruction 33311754Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 83942858 14.58% 99.92% # Class of executed instruction 33411754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemRead 60283 0.01% 99.93% # Class of executed instruction 33511754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemWrite 386170 0.07% 100.00% # Class of executed instruction 33610585SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 33710585SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 33811754Sandreas.hansson@arm.comsystem.cpu0.op_class::total 575690180 # Class of executed instruction 33911754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 34011754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 6169123 # number of replacements 34111754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 502.902441 # Cycle average of tags in use 34211754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 169021316 # Total number of references to valid blocks. 34311754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 6169635 # Sample count of references to valid blocks. 34411754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.395675 # Average number of references to valid blocks. 34510827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 34611754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 502.902441 # Average occupied blocks per requestor 34711754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.982231 # Average percentage of cache occupancy 34811754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.982231 # Average percentage of cache occupancy 34910585SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 35011754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 35111754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 35211754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 35310585SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 35411754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 356856913 # Number of tag accesses 35511754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 356856913 # Number of data accesses 35611754Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 35711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 84588460 # number of ReadReq hits 35811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 84588460 # number of ReadReq hits 35911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 79569773 # number of WriteReq hits 36011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 79569773 # number of WriteReq hits 36111754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 213774 # number of SoftPFReq hits 36211754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 213774 # number of SoftPFReq hits 36311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 259782 # number of WriteLineReq hits 36411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 259782 # number of WriteLineReq hits 36511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2069774 # number of LoadLockedReq hits 36611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2069774 # number of LoadLockedReq hits 36711754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2033350 # number of StoreCondReq hits 36811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2033350 # number of StoreCondReq hits 36911754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 164418015 # number of demand (read+write) hits 37011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 164418015 # number of demand (read+write) hits 37111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 164631789 # number of overall hits 37211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 164631789 # number of overall hits 37311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3250756 # number of ReadReq misses 37411754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3250756 # number of ReadReq misses 37511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1461940 # number of WriteReq misses 37611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1461940 # number of WriteReq misses 37711754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 763460 # number of SoftPFReq misses 37811754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 763460 # number of SoftPFReq misses 37911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 814949 # number of WriteLineReq misses 38011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 814949 # number of WriteLineReq misses 38111754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 115689 # number of LoadLockedReq misses 38211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 115689 # number of LoadLockedReq misses 38311754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 151036 # number of StoreCondReq misses 38411754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 151036 # number of StoreCondReq misses 38511754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 5527645 # number of demand (read+write) misses 38611754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 5527645 # number of demand (read+write) misses 38711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 6291105 # number of overall misses 38811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 6291105 # number of overall misses 38911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 87839216 # number of ReadReq accesses(hits+misses) 39011754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 87839216 # number of ReadReq accesses(hits+misses) 39111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 81031713 # number of WriteReq accesses(hits+misses) 39211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 81031713 # number of WriteReq accesses(hits+misses) 39311754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 977234 # number of SoftPFReq accesses(hits+misses) 39411754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 977234 # number of SoftPFReq accesses(hits+misses) 39511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1074731 # number of WriteLineReq accesses(hits+misses) 39611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1074731 # number of WriteLineReq accesses(hits+misses) 39711754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185463 # number of LoadLockedReq accesses(hits+misses) 39811754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2185463 # number of LoadLockedReq accesses(hits+misses) 39911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184386 # number of StoreCondReq accesses(hits+misses) 40011754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 2184386 # number of StoreCondReq accesses(hits+misses) 40111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 169945660 # number of demand (read+write) accesses 40211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 169945660 # number of demand (read+write) accesses 40311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 170922894 # number of overall (read+write) accesses 40411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 170922894 # number of overall (read+write) accesses 40511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.037008 # miss rate for ReadReq accesses 40611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.037008 # miss rate for ReadReq accesses 40711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018042 # miss rate for WriteReq accesses 40811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018042 # miss rate for WriteReq accesses 40911754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781246 # miss rate for SoftPFReq accesses 41011754Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.781246 # miss rate for SoftPFReq accesses 41111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.758282 # miss rate for WriteLineReq accesses 41211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.758282 # miss rate for WriteLineReq accesses 41311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052936 # miss rate for LoadLockedReq accesses 41411754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052936 # miss rate for LoadLockedReq accesses 41511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.069143 # miss rate for StoreCondReq accesses 41611754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.069143 # miss rate for StoreCondReq accesses 41711754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.032526 # miss rate for demand accesses 41811754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.032526 # miss rate for demand accesses 41911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.036807 # miss rate for overall accesses 42011754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.036807 # miss rate for overall accesses 42110585SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 42210585SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 42310585SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 42410585SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 42510585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 42610585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 42711754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 6169123 # number of writebacks 42811754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 6169123 # number of writebacks 42911754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 43011754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5445857 # number of replacements 43111754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use 43211754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 484071611 # Total number of references to valid blocks. 43311754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5446369 # Sample count of references to valid blocks. 43411754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 88.879694 # Average number of references to valid blocks. 43511570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 5759898000 # Cycle when the warmup percentage was hit. 43611754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor 43710585SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 43810585SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 43910585SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 44011754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id 44111754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id 44211754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 44311570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 44410585SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 44511754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 984482344 # Number of tag accesses 44611754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 984482344 # Number of data accesses 44711754Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 44811754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 484071611 # number of ReadReq hits 44911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 484071611 # number of ReadReq hits 45011754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 484071611 # number of demand (read+write) hits 45111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 484071611 # number of demand (read+write) hits 45211754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 484071611 # number of overall hits 45311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 484071611 # number of overall hits 45411754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5446374 # number of ReadReq misses 45511754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5446374 # number of ReadReq misses 45611754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5446374 # number of demand (read+write) misses 45711754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 5446374 # number of demand (read+write) misses 45811754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5446374 # number of overall misses 45911754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5446374 # number of overall misses 46011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 489517985 # number of ReadReq accesses(hits+misses) 46111754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 489517985 # number of ReadReq accesses(hits+misses) 46211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 489517985 # number of demand (read+write) accesses 46311754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 489517985 # number of demand (read+write) accesses 46411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 489517985 # number of overall (read+write) accesses 46511754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 489517985 # number of overall (read+write) accesses 46611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011126 # miss rate for ReadReq accesses 46711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011126 # miss rate for ReadReq accesses 46811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011126 # miss rate for demand accesses 46911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011126 # miss rate for demand accesses 47011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011126 # miss rate for overall accesses 47111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011126 # miss rate for overall accesses 47210585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 47310585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 47410585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 47510585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 47610585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 47710585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 47811754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 5445857 # number of writebacks 47911754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 5445857 # number of writebacks 48011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 48110628SN/Asystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 48210628SN/Asystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 48310628SN/Asystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 48410628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 48510628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 48610628SN/Asystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 48711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 48811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2533357 # number of replacements 48911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15711.685213 # Cycle average of tags in use 49011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 9303903 # Total number of references to valid blocks. 49111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2548994 # Sample count of references to valid blocks. 49211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 3.650029 # Average number of references to valid blocks. 49310585SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 49411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15660.837363 # Average occupied blocks per requestor 49511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.957912 # Average occupied blocks per requestor 49611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.889938 # Average occupied blocks per requestor 49711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.955862 # Average percentage of cache occupancy 49811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001890 # Average percentage of cache occupancy 49911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001214 # Average percentage of cache occupancy 50011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.958965 # Average percentage of cache occupancy 50111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id 50211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15585 # Occupied blocks per task id 50311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 50411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id 50511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 50611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 50711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id 50811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2073 # Occupied blocks per task id 50911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5396 # Occupied blocks per task id 51011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5335 # Occupied blocks per task id 51111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2374 # Occupied blocks per task id 51211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id 51311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.951233 # Percentage of cache occupancy per task id 51411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 396876772 # Number of tag accesses 51511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 396876772 # Number of data accesses 51611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 51711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 281069 # number of ReadReq hits 51811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 152429 # number of ReadReq hits 51911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 433498 # number of ReadReq hits 52011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 4385344 # number of WritebackDirty hits 52111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 4385344 # number of WritebackDirty hits 52211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 7228256 # number of WritebackClean hits 52311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 7228256 # number of WritebackClean hits 52411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 628811 # number of ReadExReq hits 52511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 628811 # number of ReadExReq hits 52611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4957899 # number of ReadCleanReq hits 52711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 4957899 # number of ReadCleanReq hits 52811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2920611 # number of ReadSharedReq hits 52911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2920611 # number of ReadSharedReq hits 53011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 215443 # number of InvalidateReq hits 53111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 215443 # number of InvalidateReq hits 53211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 281069 # number of demand (read+write) hits 53311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 152429 # number of demand (read+write) hits 53411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4957899 # number of demand (read+write) hits 53511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3549422 # number of demand (read+write) hits 53611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 8940819 # number of demand (read+write) hits 53711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 281069 # number of overall hits 53811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 152429 # number of overall hits 53911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4957899 # number of overall hits 54011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3549422 # number of overall hits 54111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 8940819 # number of overall hits 54211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 20714 # number of ReadReq misses 54311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10073 # number of ReadReq misses 54411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 30787 # number of ReadReq misses 54511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 134964 # number of UpgradeReq misses 54611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 134964 # number of UpgradeReq misses 54711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 151036 # number of SCUpgradeReq misses 54811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 151036 # number of SCUpgradeReq misses 54911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 698165 # number of ReadExReq misses 55011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 698165 # number of ReadExReq misses 55111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 488475 # number of ReadCleanReq misses 55211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 488475 # number of ReadCleanReq misses 55311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1209294 # number of ReadSharedReq misses 55411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 1209294 # number of ReadSharedReq misses 55511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 599506 # number of InvalidateReq misses 55611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 599506 # number of InvalidateReq misses 55711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 20714 # number of demand (read+write) misses 55811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 10073 # number of demand (read+write) misses 55911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 488475 # number of demand (read+write) misses 56011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1907459 # number of demand (read+write) misses 56111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2426721 # number of demand (read+write) misses 56211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 20714 # number of overall misses 56311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 10073 # number of overall misses 56411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 488475 # number of overall misses 56511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1907459 # number of overall misses 56611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2426721 # number of overall misses 56711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 301783 # number of ReadReq accesses(hits+misses) 56811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 162502 # number of ReadReq accesses(hits+misses) 56911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 464285 # number of ReadReq accesses(hits+misses) 57011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 4385344 # number of WritebackDirty accesses(hits+misses) 57111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 4385344 # number of WritebackDirty accesses(hits+misses) 57211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 7228256 # number of WritebackClean accesses(hits+misses) 57311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 7228256 # number of WritebackClean accesses(hits+misses) 57411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 134964 # number of UpgradeReq accesses(hits+misses) 57511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 134964 # number of UpgradeReq accesses(hits+misses) 57611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 151036 # number of SCUpgradeReq accesses(hits+misses) 57711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 151036 # number of SCUpgradeReq accesses(hits+misses) 57811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1326976 # number of ReadExReq accesses(hits+misses) 57911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1326976 # number of ReadExReq accesses(hits+misses) 58011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5446374 # number of ReadCleanReq accesses(hits+misses) 58111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 5446374 # number of ReadCleanReq accesses(hits+misses) 58211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4129905 # number of ReadSharedReq accesses(hits+misses) 58311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 4129905 # number of ReadSharedReq accesses(hits+misses) 58411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 814949 # number of InvalidateReq accesses(hits+misses) 58511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 814949 # number of InvalidateReq accesses(hits+misses) 58611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 301783 # number of demand (read+write) accesses 58711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 162502 # number of demand (read+write) accesses 58811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5446374 # number of demand (read+write) accesses 58911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5456881 # number of demand (read+write) accesses 59011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 11367540 # number of demand (read+write) accesses 59111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 301783 # number of overall (read+write) accesses 59211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 162502 # number of overall (read+write) accesses 59311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5446374 # number of overall (read+write) accesses 59411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5456881 # number of overall (read+write) accesses 59511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 11367540 # number of overall (read+write) accesses 59611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for ReadReq accesses 59711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.061987 # miss rate for ReadReq accesses 59811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.066311 # miss rate for ReadReq accesses 59911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 60011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 60110585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 60210585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 60311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.526132 # miss rate for ReadExReq accesses 60411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.526132 # miss rate for ReadExReq accesses 60511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.089688 # miss rate for ReadCleanReq accesses 60611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.089688 # miss rate for ReadCleanReq accesses 60711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.292814 # miss rate for ReadSharedReq accesses 60811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.292814 # miss rate for ReadSharedReq accesses 60911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.735636 # miss rate for InvalidateReq accesses 61011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.735636 # miss rate for InvalidateReq accesses 61111754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for demand accesses 61211754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.061987 # miss rate for demand accesses 61311754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.089688 # miss rate for demand accesses 61411754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.349551 # miss rate for demand accesses 61511754Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.213478 # miss rate for demand accesses 61611754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.068639 # miss rate for overall accesses 61711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.061987 # miss rate for overall accesses 61811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.089688 # miss rate for overall accesses 61911754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.349551 # miss rate for overall accesses 62011754Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.213478 # miss rate for overall accesses 62110585SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 62210585SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 62310585SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 62410585SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 62510585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 62610585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 62711754Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1537445 # number of writebacks 62811754Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1537445 # number of writebacks 62911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 23876126 # Total number of requests made to the snoop filter. 63011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 12158327 # Number of requests hitting in the snoop filter with a single holder of the requested data. 63111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1385 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 63211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 304592 # Total number of snoops made to the snoop filter. 63311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 304592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 63411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 63511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 63611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 614484 # Transaction distribution 63711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10190763 # Transaction distribution 63811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 32444 # Transaction distribution 63911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 32444 # Transaction distribution 64011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 4385344 # Transaction distribution 64111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 7229636 # Transaction distribution 64211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 134964 # Transaction distribution 64311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 151036 # Transaction distribution 64411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 286000 # Transaction distribution 64511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1326976 # Transaction distribution 64611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1326976 # Transaction distribution 64711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 5446374 # Transaction distribution 64811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4129905 # Transaction distribution 64911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 814949 # Transaction distribution 65011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 814949 # Transaction distribution 65111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 16424855 # Packet count per connected master and slave (bytes) 65211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19414693 # Packet count per connected master and slave (bytes) 65311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 360152 # Packet count per connected master and slave (bytes) 65411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 717544 # Packet count per connected master and slave (bytes) 65511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 36917244 # Packet count per connected master and slave (bytes) 65611754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 697275284 # Cumulative packet size per connected master and slave (bytes) 65711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 744257581 # Cumulative packet size per connected master and slave (bytes) 65811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1440608 # Cumulative packet size per connected master and slave (bytes) 65911754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2870176 # Cumulative packet size per connected master and slave (bytes) 66011754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1445843649 # Cumulative packet size per connected master and slave (bytes) 66111754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 4732413 # Total snoops (count) 66211754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopTraffic 102900484 # Total snoop traffic (bytes) 66311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 28818191 # Request fanout histogram 66411754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.019582 # Request fanout histogram 66511754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.138557 # Request fanout histogram 66610585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 66711754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 28253885 98.04% 98.04% # Request fanout histogram 66811754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 564306 1.96% 100.00% # Request fanout histogram 66911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 67010585SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 67111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 67211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 67311754Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 28818191 # Request fanout histogram 67411754Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 67510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 67610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 67710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 67910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 68010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68110628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 68210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 68310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 68410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 68510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 68610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 68710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 68810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 68910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 69010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 69110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 69210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 69310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 69410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 69510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 69710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 69810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 69910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 70010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 70110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 70210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 70411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 70511754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 145570 # Table walker walks requested 70611754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 145570 # Table walker walks initiated with long descriptors 70711754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 145570 # Table walker wait (enqueue to first request) latency 70811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 145570 100.00% 100.00% # Table walker wait (enqueue to first request) latency 70911754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 145570 # Table walker wait (enqueue to first request) latency 71011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::samples -274399872 # Table walker pending requests distribution 71111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::0 -274399872 100.00% 100.00% # Table walker pending requests distribution 71211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::total -274399872 # Table walker pending requests distribution 71311754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 112948 88.82% 88.82% # Table walker page sizes translated 71411754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 14218 11.18% 100.00% # Table walker page sizes translated 71511754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 127166 # Table walker page sizes translated 71611754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 145570 # Table walker requests started/completed, data/inst 71710628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71811754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 145570 # Table walker requests started/completed, data/inst 71911754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 127166 # Table walker requests started/completed, data/inst 72010628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72111754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 127166 # Table walker requests started/completed, data/inst 72211754Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 272736 # Table walker requests started/completed, data/inst 72310585SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 72410585SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 72511754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 92188600 # DTB read hits 72611754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 112898 # DTB read misses 72711754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 82869602 # DTB write hits 72811754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 32672 # DTB write misses 72910585SN/Asystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 73010585SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 73111754Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 73210585SN/Asystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 73311754Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 44985 # Number of entries that have been flushed from TLB 73410585SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 73511754Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 4483 # Number of TLB faults due to prefetch 73610585SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 73711754Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 11594 # Number of TLB faults due to permissions restrictions 73811754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 92301498 # DTB read accesses 73911754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 82902274 # DTB write accesses 74010585SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 74111754Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 175058202 # DTB hits 74211754Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 145570 # DTB misses 74311754Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 175203772 # DTB accesses 74411754Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 74510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 74610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 74810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 74910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 75010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 75210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 75310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 75410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 75510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 75610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 75710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 75810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 75910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 76010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 76110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 76210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 76310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 76410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 76510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 76610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 76710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 76810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 76910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 77010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 77110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 77210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 77310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 77411754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 77511754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 62174 # Table walker walks requested 77611754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 62174 # Table walker walks initiated with long descriptors 77711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 62174 # Table walker wait (enqueue to first request) latency 77811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 62174 100.00% 100.00% # Table walker wait (enqueue to first request) latency 77911754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 62174 # Table walker wait (enqueue to first request) latency 78011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::samples -274400872 # Table walker pending requests distribution 78111570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::0 -274400872 100.00% 100.00% # Table walker pending requests distribution 78211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::total -274400872 # Table walker pending requests distribution 78311754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 55194 99.03% 99.03% # Table walker page sizes translated 78411754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 542 0.97% 100.00% # Table walker page sizes translated 78511754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 55736 # Table walker page sizes translated 78610628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 78711754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62174 # Table walker requests started/completed, data/inst 78811754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 62174 # Table walker requests started/completed, data/inst 78910628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 79011754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55736 # Table walker requests started/completed, data/inst 79111754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 55736 # Table walker requests started/completed, data/inst 79211754Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 117910 # Table walker requests started/completed, data/inst 79311754Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 488205248 # ITB inst hits 79411754Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 62174 # ITB inst misses 79510585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 79610585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 79710585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 79810585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 79910585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 80010585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 80111754Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 49426 # Number of times TLB was flushed by MVA & ASID 80210585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 80311754Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 31602 # Number of entries that have been flushed from TLB 80410585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 80510585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 80610585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 80710585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 80810585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 80910585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 81011754Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 488267422 # ITB inst accesses 81111754Sandreas.hansson@arm.comsystem.cpu1.itb.hits 488205248 # DTB hits 81211754Sandreas.hansson@arm.comsystem.cpu1.itb.misses 62174 # DTB misses 81311754Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 488267422 # DTB accesses 81411754Sandreas.hansson@arm.comsystem.cpu1.numPwrStateTransitions 12500 # Number of power state transitions 81511754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::samples 6250 # Distribution of time spent in the clock gated state 81611754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 7502374904.322560 # Distribution of time spent in the clock gated state 81711754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 140163345879.751923 # Distribution of time spent in the clock gated state 81811754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 4511 72.18% 72.18% # Distribution of time spent in the clock gated state 81911754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 1712 27.39% 99.57% # Distribution of time spent in the clock gated state 82011754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.11% 99.68% # Distribution of time spent in the clock gated state 82111754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state 82211754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state 82311754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.05% 99.76% # Distribution of time spent in the clock gated state 82411754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state 82511754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state 82611754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::overflows 13 0.21% 100.00% # Distribution of time spent in the clock gated state 82711570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 82811754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 7033264907012 # Distribution of time spent in the clock gated state 82911754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::total 6250 # Distribution of time spent in the clock gated state 83011754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 287230675984 # Cumulative time (in ticks) in various power states 83111754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 46889843152016 # Cumulative time (in ticks) in various power states 83211754Sandreas.hansson@arm.comsystem.cpu1.numCycles 94354153907 # number of cpu cycles simulated 83310585SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 83410585SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 83511167Sjthestness@gmail.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 83611754Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 6250 # number of quiesce instructions executed 83711754Sandreas.hansson@arm.comsystem.cpu1.committedInsts 487952717 # Number of instructions committed 83811754Sandreas.hansson@arm.comsystem.cpu1.committedOps 574148180 # Number of ops (including micro ops) committed 83911754Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 526945204 # Number of integer alu accesses 84011754Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 380393 # Number of float alu accesses 84111754Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 28766283 # number of times a function call or return occured 84211754Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 74749330 # number of instructions that are conditional controls 84311754Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 526945204 # number of integer instructions 84411754Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 380393 # number of float instructions 84511754Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 777937433 # number of times the integer registers were read 84611754Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 419402413 # number of times the integer registers were written 84711754Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 618522 # number of times the floating registers were read 84811754Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 309432 # number of times the floating registers were written 84911754Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 129016491 # number of times the CC registers were read 85011754Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 128726040 # number of times the CC registers were written 85111754Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 175180123 # number of memory refs 85211754Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 92288401 # Number of load instructions 85311754Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 82891722 # Number of store instructions 85411754Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 93779692516.971710 # Number of idle cycles 85511754Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 574461390.028282 # Number of busy cycles 85611754Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.006088 # Percentage of non-idle cycles 85711754Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.993912 # Percentage of idle cycles 85811754Sandreas.hansson@arm.comsystem.cpu1.Branches 108727125 # Number of branches fetched 85910585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 86011754Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 398021787 69.29% 69.29% # Class of executed instruction 86111754Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 1155567 0.20% 69.49% # Class of executed instruction 86211754Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 62024 0.01% 69.50% # Class of executed instruction 86311754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction 86411754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction 86511754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction 86611754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction 86711754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMultAcc 0 0.00% 69.50% # Class of executed instruction 86811754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction 86911754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMisc 37076 0.01% 69.51% # Class of executed instruction 87011754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction 87111754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction 87211754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction 87311754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction 87411754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction 87511754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction 87611754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction 87711754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction 87811754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction 87911754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction 88011754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction 88111754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction 88211754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction 88311754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction 88411754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction 88511754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction 88611754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction 88711754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 69.51% # Class of executed instruction 88811754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 88911754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 89011754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 89111754Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 92237466 16.06% 85.56% # Class of executed instruction 89211754Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 82599340 14.38% 99.94% # Class of executed instruction 89311754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemRead 50935 0.01% 99.95% # Class of executed instruction 89411754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemWrite 292382 0.05% 100.00% # Class of executed instruction 89510585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 89610585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 89711754Sandreas.hansson@arm.comsystem.cpu1.op_class::total 574456577 # Class of executed instruction 89811754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 89911754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 6056013 # number of replacements 90011754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 439.385542 # Cycle average of tags in use 90111754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 169014740 # Total number of references to valid blocks. 90211754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 6056525 # Sample count of references to valid blocks. 90311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 27.906223 # Average number of references to valid blocks. 90411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8470277781000 # Cycle when the warmup percentage was hit. 90511754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 439.385542 # Average occupied blocks per requestor 90611754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.858175 # Average percentage of cache occupancy 90711754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.858175 # Average percentage of cache occupancy 90811754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 90911754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id 91011754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id 91111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 91211754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 91311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 356467951 # Number of tag accesses 91411754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 356467951 # Number of data accesses 91511754Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 91611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 85651314 # number of ReadReq hits 91711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 85651314 # number of ReadReq hits 91811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 78663816 # number of WriteReq hits 91911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 78663816 # number of WriteReq hits 92011754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 189367 # number of SoftPFReq hits 92111754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 189367 # number of SoftPFReq hits 92211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 66166 # number of WriteLineReq hits 92311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 66166 # number of WriteLineReq hits 92411754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2074874 # number of LoadLockedReq hits 92511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 2074874 # number of LoadLockedReq hits 92611754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2069738 # number of StoreCondReq hits 92711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 2069738 # number of StoreCondReq hits 92811754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 164381296 # number of demand (read+write) hits 92911754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 164381296 # number of demand (read+write) hits 93011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 164570663 # number of overall hits 93111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 164570663 # number of overall hits 93211754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3417226 # number of ReadReq misses 93311754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3417226 # number of ReadReq misses 93411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1481686 # number of WriteReq misses 93511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1481686 # number of WriteReq misses 93611754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 799274 # number of SoftPFReq misses 93711754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 799274 # number of SoftPFReq misses 93811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 443256 # number of WriteLineReq misses 93911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 443256 # number of WriteLineReq misses 94011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150141 # number of LoadLockedReq misses 94111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 150141 # number of LoadLockedReq misses 94211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 154039 # number of StoreCondReq misses 94311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 154039 # number of StoreCondReq misses 94411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 5342168 # number of demand (read+write) misses 94511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 5342168 # number of demand (read+write) misses 94611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 6141442 # number of overall misses 94711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 6141442 # number of overall misses 94811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 89068540 # number of ReadReq accesses(hits+misses) 94911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 89068540 # number of ReadReq accesses(hits+misses) 95011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 80145502 # number of WriteReq accesses(hits+misses) 95111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 80145502 # number of WriteReq accesses(hits+misses) 95211754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 988641 # number of SoftPFReq accesses(hits+misses) 95311754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 988641 # number of SoftPFReq accesses(hits+misses) 95411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 509422 # number of WriteLineReq accesses(hits+misses) 95511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 509422 # number of WriteLineReq accesses(hits+misses) 95611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2225015 # number of LoadLockedReq accesses(hits+misses) 95711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2225015 # number of LoadLockedReq accesses(hits+misses) 95811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2223777 # number of StoreCondReq accesses(hits+misses) 95911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2223777 # number of StoreCondReq accesses(hits+misses) 96011754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 169723464 # number of demand (read+write) accesses 96111754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 169723464 # number of demand (read+write) accesses 96211754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 170712105 # number of overall (read+write) accesses 96311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 170712105 # number of overall (read+write) accesses 96411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038366 # miss rate for ReadReq accesses 96511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.038366 # miss rate for ReadReq accesses 96611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018487 # miss rate for WriteReq accesses 96711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018487 # miss rate for WriteReq accesses 96811754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808457 # miss rate for SoftPFReq accesses 96911754Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.808457 # miss rate for SoftPFReq accesses 97011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.870116 # miss rate for WriteLineReq accesses 97111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.870116 # miss rate for WriteLineReq accesses 97211754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067479 # miss rate for LoadLockedReq accesses 97311754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067479 # miss rate for LoadLockedReq accesses 97411754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.069269 # miss rate for StoreCondReq accesses 97511754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.069269 # miss rate for StoreCondReq accesses 97611754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.031476 # miss rate for demand accesses 97711754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.031476 # miss rate for demand accesses 97811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.035975 # miss rate for overall accesses 97911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.035975 # miss rate for overall accesses 98010585SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 98110585SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 98210585SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 98310585SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 98410585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 98510585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 98611754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 6056013 # number of writebacks 98711754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 6056013 # number of writebacks 98811754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 98911754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 4848965 # number of replacements 99011754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 496.412961 # Cycle average of tags in use 99111754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 483411507 # Total number of references to valid blocks. 99211754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 4849477 # Sample count of references to valid blocks. 99311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 99.683225 # Average number of references to valid blocks. 99411570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 8470205818500 # Cycle when the warmup percentage was hit. 99511754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412961 # Average occupied blocks per requestor 99611754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy 99711754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy 99810585SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 99911754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 100011754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id 100111570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 146 # Occupied blocks per task id 100210585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 100311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 981371445 # Number of tag accesses 100411754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 981371445 # Number of data accesses 100511754Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 100611754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 483411507 # number of ReadReq hits 100711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 483411507 # number of ReadReq hits 100811754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 483411507 # number of demand (read+write) hits 100911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 483411507 # number of demand (read+write) hits 101011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 483411507 # number of overall hits 101111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 483411507 # number of overall hits 101211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4849477 # number of ReadReq misses 101311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 4849477 # number of ReadReq misses 101411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4849477 # number of demand (read+write) misses 101511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 4849477 # number of demand (read+write) misses 101611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4849477 # number of overall misses 101711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 4849477 # number of overall misses 101811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 488260984 # number of ReadReq accesses(hits+misses) 101911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 488260984 # number of ReadReq accesses(hits+misses) 102011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 488260984 # number of demand (read+write) accesses 102111754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 488260984 # number of demand (read+write) accesses 102211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 488260984 # number of overall (read+write) accesses 102311754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 488260984 # number of overall (read+write) accesses 102411754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009932 # miss rate for ReadReq accesses 102511754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009932 # miss rate for ReadReq accesses 102611754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009932 # miss rate for demand accesses 102711754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009932 # miss rate for demand accesses 102811754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009932 # miss rate for overall accesses 102911754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009932 # miss rate for overall accesses 103010585SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 103110585SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 103210585SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 103310585SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 103410585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 103510585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 103611754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 4848965 # number of writebacks 103711754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 4848965 # number of writebacks 103811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 103910628SN/Asystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 104010628SN/Asystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 104110628SN/Asystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 104210628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 104310628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 104410628SN/Asystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 104511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 104611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2230269 # number of replacements 104711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13059.321303 # Cycle average of tags in use 104811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 8938644 # Total number of references to valid blocks. 104911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2245943 # Sample count of references to valid blocks. 105011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 3.979907 # Average number of references to valid blocks. 105111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 105211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 13021.698131 # Average occupied blocks per requestor 105311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 21.453000 # Average occupied blocks per requestor 105411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 16.170172 # Average occupied blocks per requestor 105511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.794781 # Average percentage of cache occupancy 105611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001309 # Average percentage of cache occupancy 105711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000987 # Average percentage of cache occupancy 105811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.797078 # Average percentage of cache occupancy 105911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id 106011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15589 # Occupied blocks per task id 106111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 106211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 106311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id 106411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 106511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id 106611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id 106711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2501 # Occupied blocks per task id 106811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7586 # Occupied blocks per task id 106911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3485 # Occupied blocks per task id 107011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1787 # Occupied blocks per task id 107111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id 107211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.951477 # Percentage of cache occupancy per task id 107311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 374536552 # Number of tag accesses 107411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 374536552 # Number of data accesses 107511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 107611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 340661 # number of ReadReq hits 107711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 155597 # number of ReadReq hits 107811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 496258 # number of ReadReq hits 107911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 4122422 # number of WritebackDirty hits 108011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 4122422 # number of WritebackDirty hits 108111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 6782171 # number of WritebackClean hits 108211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 6782171 # number of WritebackClean hits 108311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 622232 # number of ReadExReq hits 108411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 622232 # number of ReadExReq hits 108511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4374488 # number of ReadCleanReq hits 108611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 4374488 # number of ReadCleanReq hits 108711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3137655 # number of ReadSharedReq hits 108811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3137655 # number of ReadSharedReq hits 108911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 166849 # number of InvalidateReq hits 109011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 166849 # number of InvalidateReq hits 109111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 340661 # number of demand (read+write) hits 109211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 155597 # number of demand (read+write) hits 109311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4374488 # number of demand (read+write) hits 109411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3759887 # number of demand (read+write) hits 109511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8630633 # number of demand (read+write) hits 109611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 340661 # number of overall hits 109711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 155597 # number of overall hits 109811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4374488 # number of overall hits 109911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3759887 # number of overall hits 110011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8630633 # number of overall hits 110111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 22356 # number of ReadReq misses 110211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 11279 # number of ReadReq misses 110311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 33635 # number of ReadReq misses 110411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145163 # number of UpgradeReq misses 110511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 145163 # number of UpgradeReq misses 110611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 154039 # number of SCUpgradeReq misses 110711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 154039 # number of SCUpgradeReq misses 110811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 714291 # number of ReadExReq misses 110911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 714291 # number of ReadExReq misses 111011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 474989 # number of ReadCleanReq misses 111111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 474989 # number of ReadCleanReq misses 111211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1228986 # number of ReadSharedReq misses 111311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1228986 # number of ReadSharedReq misses 111411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 276407 # number of InvalidateReq misses 111511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 276407 # number of InvalidateReq misses 111611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 22356 # number of demand (read+write) misses 111711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 11279 # number of demand (read+write) misses 111811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 474989 # number of demand (read+write) misses 111911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1943277 # number of demand (read+write) misses 112011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 2451901 # number of demand (read+write) misses 112111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 22356 # number of overall misses 112211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 11279 # number of overall misses 112311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 474989 # number of overall misses 112411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1943277 # number of overall misses 112511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 2451901 # number of overall misses 112611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 363017 # number of ReadReq accesses(hits+misses) 112711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 166876 # number of ReadReq accesses(hits+misses) 112811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 529893 # number of ReadReq accesses(hits+misses) 112911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 4122422 # number of WritebackDirty accesses(hits+misses) 113011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 4122422 # number of WritebackDirty accesses(hits+misses) 113111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 6782171 # number of WritebackClean accesses(hits+misses) 113211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 6782171 # number of WritebackClean accesses(hits+misses) 113311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 145163 # number of UpgradeReq accesses(hits+misses) 113411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 145163 # number of UpgradeReq accesses(hits+misses) 113511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 154039 # number of SCUpgradeReq accesses(hits+misses) 113611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 154039 # number of SCUpgradeReq accesses(hits+misses) 113711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1336523 # number of ReadExReq accesses(hits+misses) 113811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1336523 # number of ReadExReq accesses(hits+misses) 113911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 4849477 # number of ReadCleanReq accesses(hits+misses) 114011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 4849477 # number of ReadCleanReq accesses(hits+misses) 114111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4366641 # number of ReadSharedReq accesses(hits+misses) 114211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4366641 # number of ReadSharedReq accesses(hits+misses) 114311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 443256 # number of InvalidateReq accesses(hits+misses) 114411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 443256 # number of InvalidateReq accesses(hits+misses) 114511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 363017 # number of demand (read+write) accesses 114611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 166876 # number of demand (read+write) accesses 114711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4849477 # number of demand (read+write) accesses 114811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5703164 # number of demand (read+write) accesses 114911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 11082534 # number of demand (read+write) accesses 115011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 363017 # number of overall (read+write) accesses 115111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 166876 # number of overall (read+write) accesses 115211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4849477 # number of overall (read+write) accesses 115311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5703164 # number of overall (read+write) accesses 115411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 11082534 # number of overall (read+write) accesses 115511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for ReadReq accesses 115611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.067589 # miss rate for ReadReq accesses 115711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.063475 # miss rate for ReadReq accesses 115811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 115911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 116010585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 116110585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 116211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.534440 # miss rate for ReadExReq accesses 116311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.534440 # miss rate for ReadExReq accesses 116411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097946 # miss rate for ReadCleanReq accesses 116511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097946 # miss rate for ReadCleanReq accesses 116611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.281449 # miss rate for ReadSharedReq accesses 116711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.281449 # miss rate for ReadSharedReq accesses 116811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.623583 # miss rate for InvalidateReq accesses 116911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.623583 # miss rate for InvalidateReq accesses 117011754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for demand accesses 117111754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.067589 # miss rate for demand accesses 117211754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097946 # miss rate for demand accesses 117311754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.340737 # miss rate for demand accesses 117411754Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.221240 # miss rate for demand accesses 117511754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.061584 # miss rate for overall accesses 117611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.067589 # miss rate for overall accesses 117711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097946 # miss rate for overall accesses 117811754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.340737 # miss rate for overall accesses 117911754Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.221240 # miss rate for overall accesses 118010585SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 118110585SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 118210585SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 118310585SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 118410585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 118510585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 118611754Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1226637 # number of writebacks 118711754Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1226637 # number of writebacks 118811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 22478068 # Total number of requests made to the snoop filter. 118911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 11482434 # Number of requests hitting in the snoop filter with a single holder of the requested data. 119011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 385 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 119111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 282472 # Total number of snoops made to the snoop filter. 119211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 282472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 119311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 119411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 119511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 614190 # Transaction distribution 119611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9830308 # Transaction distribution 119711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 6354 # Transaction distribution 119811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 6354 # Transaction distribution 119911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4122422 # Transaction distribution 120011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 6782556 # Transaction distribution 120111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 145163 # Transaction distribution 120211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 154039 # Transaction distribution 120311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 299202 # Transaction distribution 120411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1336523 # Transaction distribution 120511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1336523 # Transaction distribution 120611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 4849477 # Transaction distribution 120711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 4366641 # Transaction distribution 120811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 443256 # Transaction distribution 120911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 443256 # Transaction distribution 121011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14548179 # Packet count per connected master and slave (bytes) 121111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18972689 # Packet count per connected master and slave (bytes) 121211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371656 # Packet count per connected master and slave (bytes) 121311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 843740 # Packet count per connected master and slave (bytes) 121411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 34736264 # Packet count per connected master and slave (bytes) 121511754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 620700808 # Cumulative packet size per connected master and slave (bytes) 121611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 752625722 # Cumulative packet size per connected master and slave (bytes) 121711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1486624 # Cumulative packet size per connected master and slave (bytes) 121811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3374960 # Cumulative packet size per connected master and slave (bytes) 121911754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1378188114 # Cumulative packet size per connected master and slave (bytes) 122011754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 4390439 # Total snoops (count) 122111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopTraffic 84812544 # Total snoop traffic (bytes) 122211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 27053766 # Request fanout histogram 122311754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.020745 # Request fanout histogram 122411754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.142530 # Request fanout histogram 122510585SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 122611754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 26492533 97.93% 97.93% # Request fanout histogram 122711754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 561233 2.07% 100.00% # Request fanout histogram 122811754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 122910585SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 123011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 123111754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 123211754Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 27053766 # Request fanout histogram 123311754Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 123411754Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40293 # Transaction distribution 123511754Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40293 # Transaction distribution 123611754Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136632 # Transaction distribution 123711754Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136632 # Transaction distribution 123811754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47630 # Packet count per connected master and slave (bytes) 123910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 124011245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 124110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 124210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 124310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 124410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 124510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 124610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 124710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 124810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 124910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 125010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 125111754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122564 # Packet count per connected master and slave (bytes) 125211754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231206 # Packet count per connected master and slave (bytes) 125311754Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231206 # Packet count per connected master and slave (bytes) 125410585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 125510585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 125611754Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353850 # Packet count per connected master and slave (bytes) 125711754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47650 # Cumulative packet size per connected master and slave (bytes) 125810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 125911245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 126010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 126110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 126210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 126310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 126410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 126510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 126610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 126710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 126810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 126910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 127011754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155671 # Cumulative packet size per connected master and slave (bytes) 127111754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338840 # Cumulative packet size per connected master and slave (bytes) 127211754Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338840 # Cumulative packet size per connected master and slave (bytes) 127310585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 127410585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 127511754Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496597 # Cumulative packet size per connected master and slave (bytes) 127611754Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 127711754Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115584 # number of replacements 127811754Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.285245 # Cycle average of tags in use 127910585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 128011754Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115600 # Sample count of references to valid blocks. 128110585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 128211570SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 9107772860509 # Cycle when the warmup percentage was hit. 128311754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 3.859437 # Average occupied blocks per requestor 128411754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 7.425808 # Average occupied blocks per requestor 128511754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.241215 # Average percentage of cache occupancy 128611754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.464113 # Average percentage of cache occupancy 128711754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.705328 # Average percentage of cache occupancy 128810585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 128910585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 129010585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 129111754Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040784 # Number of tag accesses 129211754Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040784 # Number of data accesses 129311754Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 129410585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 129511754Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8875 # number of ReadReq misses 129611754Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8912 # number of ReadReq misses 129710585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 129810585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 129910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 130010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 130110585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 130211754Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 115603 # number of demand (read+write) misses 130311754Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 115643 # number of demand (read+write) misses 130410585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 130511754Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 115603 # number of overall misses 130611754Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 115643 # number of overall misses 130710585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 130811754Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8875 # number of ReadReq accesses(hits+misses) 130911754Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8912 # number of ReadReq accesses(hits+misses) 131010585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 131110585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 131210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 131310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 131410585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 131511754Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 115603 # number of demand (read+write) accesses 131611754Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 115643 # number of demand (read+write) accesses 131710585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 131811754Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 115603 # number of overall (read+write) accesses 131911754Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 115643 # number of overall (read+write) accesses 132010585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 132110585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 132210585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 132310585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 132410585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 132510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 132610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 132710585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 132810585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 132910585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 133010585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 133110585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 133210585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 133310585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 133410585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 133510585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 133610585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 133710585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 133810585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 133910585SN/Asystem.iocache.writebacks::writebacks 106694 # number of writebacks 134010585SN/Asystem.iocache.writebacks::total 106694 # number of writebacks 134111754Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 134211754Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1923250 # number of replacements 134311754Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65186.498545 # Cycle average of tags in use 134411754Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 5749330 # Total number of references to valid blocks. 134511754Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1985687 # Sample count of references to valid blocks. 134611754Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.895386 # Average number of references to valid blocks. 134711606Sandreas.sandberg@arm.comsystem.l2c.tags.warmup_cycle 477350500 # Cycle when the warmup percentage was hit. 134811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 10983.634083 # Average occupied blocks per requestor 134911754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 57.375221 # Average occupied blocks per requestor 135011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 60.020702 # Average occupied blocks per requestor 135111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3162.214163 # Average occupied blocks per requestor 135211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 16603.028209 # Average occupied blocks per requestor 135311754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 344.016385 # Average occupied blocks per requestor 135411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 410.384147 # Average occupied blocks per requestor 135511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2922.724883 # Average occupied blocks per requestor 135611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 30643.100751 # Average occupied blocks per requestor 135711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.167597 # Average percentage of cache occupancy 135811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000875 # Average percentage of cache occupancy 135911754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000916 # Average percentage of cache occupancy 136011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.048252 # Average percentage of cache occupancy 136111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.253342 # Average percentage of cache occupancy 136211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.005249 # Average percentage of cache occupancy 136311754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006262 # Average percentage of cache occupancy 136411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.044597 # Average percentage of cache occupancy 136511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.467577 # Average percentage of cache occupancy 136611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.994667 # Average percentage of cache occupancy 136711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 241 # Occupied blocks per task id 136811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 62196 # Occupied blocks per task id 136911570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 137011754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 137111754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id 137211754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 137311754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id 137411754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3250 # Occupied blocks per task id 137511754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4725 # Occupied blocks per task id 137611754Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 53923 # Occupied blocks per task id 137711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003677 # Percentage of cache occupancy per task id 137811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.949036 # Percentage of cache occupancy per task id 137911754Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 71541788 # Number of tag accesses 138011754Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 71541788 # Number of data accesses 138111754Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 138211754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2764082 # number of WritebackDirty hits 138311754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2764082 # number of WritebackDirty hits 138411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 56104 # number of UpgradeReq hits 138511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 51044 # number of UpgradeReq hits 138611754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 107148 # number of UpgradeReq hits 138711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 8413 # number of SCUpgradeReq hits 138811754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 7881 # number of SCUpgradeReq hits 138911754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 16294 # number of SCUpgradeReq hits 139011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 200040 # number of ReadExReq hits 139111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 182839 # number of ReadExReq hits 139211754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 382879 # number of ReadExReq hits 139311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12914 # number of ReadSharedReq hits 139411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 5340 # number of ReadSharedReq hits 139511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 425659 # number of ReadSharedReq hits 139611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 696237 # number of ReadSharedReq hits 139711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12397 # number of ReadSharedReq hits 139811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 4498 # number of ReadSharedReq hits 139911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 426584 # number of ReadSharedReq hits 140011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 681796 # number of ReadSharedReq hits 140111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2265425 # number of ReadSharedReq hits 140211754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu0.data 112817 # number of InvalidateReq hits 140311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::cpu1.data 103406 # number of InvalidateReq hits 140411754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_hits::total 216223 # number of InvalidateReq hits 140511754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 12914 # number of demand (read+write) hits 140611754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 5340 # number of demand (read+write) hits 140711754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 425659 # number of demand (read+write) hits 140811754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 896277 # number of demand (read+write) hits 140911754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 12397 # number of demand (read+write) hits 141011754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 4498 # number of demand (read+write) hits 141111754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 426584 # number of demand (read+write) hits 141211754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 864635 # number of demand (read+write) hits 141311754Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2648304 # number of demand (read+write) hits 141411754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 12914 # number of overall hits 141511754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 5340 # number of overall hits 141611754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 425659 # number of overall hits 141711754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 896277 # number of overall hits 141811754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 12397 # number of overall hits 141911754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 4498 # number of overall hits 142011754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 426584 # number of overall hits 142111754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 864635 # number of overall hits 142211754Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2648304 # number of overall hits 142311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 19306 # number of UpgradeReq misses 142411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 23056 # number of UpgradeReq misses 142511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 42362 # number of UpgradeReq misses 142611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 403 # number of SCUpgradeReq misses 142711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 802 # number of SCUpgradeReq misses 142811754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1205 # number of SCUpgradeReq misses 142911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 372703 # number of ReadExReq misses 143011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 418393 # number of ReadExReq misses 143111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 791096 # number of ReadExReq misses 143211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2468 # number of ReadSharedReq misses 143311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2058 # number of ReadSharedReq misses 143411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 62816 # number of ReadSharedReq misses 143511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 191372 # number of ReadSharedReq misses 143611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3475 # number of ReadSharedReq misses 143711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 3462 # number of ReadSharedReq misses 143811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 48405 # number of ReadSharedReq misses 143911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 197388 # number of ReadSharedReq misses 144011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 511444 # number of ReadSharedReq misses 144111754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu0.data 440136 # number of InvalidateReq misses 144211754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::cpu1.data 128597 # number of InvalidateReq misses 144311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_misses::total 568733 # number of InvalidateReq misses 144411754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2468 # number of demand (read+write) misses 144511754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2058 # number of demand (read+write) misses 144611754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 62816 # number of demand (read+write) misses 144711754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 564075 # number of demand (read+write) misses 144811754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3475 # number of demand (read+write) misses 144911754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3462 # number of demand (read+write) misses 145011754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 48405 # number of demand (read+write) misses 145111754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 615781 # number of demand (read+write) misses 145211754Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1302540 # number of demand (read+write) misses 145311754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2468 # number of overall misses 145411754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2058 # number of overall misses 145511754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 62816 # number of overall misses 145611754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 564075 # number of overall misses 145711754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3475 # number of overall misses 145811754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3462 # number of overall misses 145911754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 48405 # number of overall misses 146011754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 615781 # number of overall misses 146111754Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1302540 # number of overall misses 146211754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2764082 # number of WritebackDirty accesses(hits+misses) 146311754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2764082 # number of WritebackDirty accesses(hits+misses) 146411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 75410 # number of UpgradeReq accesses(hits+misses) 146511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 74100 # number of UpgradeReq accesses(hits+misses) 146611754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 149510 # number of UpgradeReq accesses(hits+misses) 146711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 8816 # number of SCUpgradeReq accesses(hits+misses) 146811754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8683 # number of SCUpgradeReq accesses(hits+misses) 146911754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 17499 # number of SCUpgradeReq accesses(hits+misses) 147011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 572743 # number of ReadExReq accesses(hits+misses) 147111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 601232 # number of ReadExReq accesses(hits+misses) 147211754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 1173975 # number of ReadExReq accesses(hits+misses) 147311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15382 # number of ReadSharedReq accesses(hits+misses) 147411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7398 # number of ReadSharedReq accesses(hits+misses) 147511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 488475 # number of ReadSharedReq accesses(hits+misses) 147611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 887609 # number of ReadSharedReq accesses(hits+misses) 147711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15872 # number of ReadSharedReq accesses(hits+misses) 147811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7960 # number of ReadSharedReq accesses(hits+misses) 147911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 474989 # number of ReadSharedReq accesses(hits+misses) 148011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 879184 # number of ReadSharedReq accesses(hits+misses) 148111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 2776869 # number of ReadSharedReq accesses(hits+misses) 148211754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu0.data 552953 # number of InvalidateReq accesses(hits+misses) 148311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::cpu1.data 232003 # number of InvalidateReq accesses(hits+misses) 148411754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_accesses::total 784956 # number of InvalidateReq accesses(hits+misses) 148511754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 15382 # number of demand (read+write) accesses 148611754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 7398 # number of demand (read+write) accesses 148711754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 488475 # number of demand (read+write) accesses 148811754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1460352 # number of demand (read+write) accesses 148911754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 15872 # number of demand (read+write) accesses 149011754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7960 # number of demand (read+write) accesses 149111754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 474989 # number of demand (read+write) accesses 149211754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1480416 # number of demand (read+write) accesses 149311754Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3950844 # number of demand (read+write) accesses 149411754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 15382 # number of overall (read+write) accesses 149511754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 7398 # number of overall (read+write) accesses 149611754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 488475 # number of overall (read+write) accesses 149711754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1460352 # number of overall (read+write) accesses 149811754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 15872 # number of overall (read+write) accesses 149911754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7960 # number of overall (read+write) accesses 150011754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 474989 # number of overall (read+write) accesses 150111754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1480416 # number of overall (read+write) accesses 150211754Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3950844 # number of overall (read+write) accesses 150311754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.256014 # miss rate for UpgradeReq accesses 150411754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.311147 # miss rate for UpgradeReq accesses 150511754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.283339 # miss rate for UpgradeReq accesses 150611754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.045712 # miss rate for SCUpgradeReq accesses 150711754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.092364 # miss rate for SCUpgradeReq accesses 150811754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.068861 # miss rate for SCUpgradeReq accesses 150911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.650733 # miss rate for ReadExReq accesses 151011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.695893 # miss rate for ReadExReq accesses 151111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.673861 # miss rate for ReadExReq accesses 151211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for ReadSharedReq accesses 151311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.278183 # miss rate for ReadSharedReq accesses 151411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.128596 # miss rate for ReadSharedReq accesses 151511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.215604 # miss rate for ReadSharedReq accesses 151611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for ReadSharedReq accesses 151711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.434925 # miss rate for ReadSharedReq accesses 151811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.101908 # miss rate for ReadSharedReq accesses 151911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.224513 # miss rate for ReadSharedReq accesses 152011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.184180 # miss rate for ReadSharedReq accesses 152111754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu0.data 0.795974 # miss rate for InvalidateReq accesses 152211754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::cpu1.data 0.554290 # miss rate for InvalidateReq accesses 152311754Sandreas.hansson@arm.comsystem.l2c.InvalidateReq_miss_rate::total 0.724541 # miss rate for InvalidateReq accesses 152411754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for demand accesses 152511754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.278183 # miss rate for demand accesses 152611754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.128596 # miss rate for demand accesses 152711754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.386260 # miss rate for demand accesses 152811754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for demand accesses 152911754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.434925 # miss rate for demand accesses 153011754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.101908 # miss rate for demand accesses 153111754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.415951 # miss rate for demand accesses 153211754Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.329687 # miss rate for demand accesses 153311754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.160447 # miss rate for overall accesses 153411754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.278183 # miss rate for overall accesses 153511754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.128596 # miss rate for overall accesses 153611754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.386260 # miss rate for overall accesses 153711754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.218939 # miss rate for overall accesses 153811754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.434925 # miss rate for overall accesses 153911754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.101908 # miss rate for overall accesses 154011754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.415951 # miss rate for overall accesses 154111754Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.329687 # miss rate for overall accesses 154210515SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 154310515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 154410515SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 154510515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 154610515SN/Asystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 154710515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 154811754Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1489052 # number of writebacks 154911754Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1489052 # number of writebacks 155011754Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 4378272 # Total number of requests made to the snoop filter. 155111754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 2451994 # Number of requests hitting in the snoop filter with a single holder of the requested data. 155211754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 3422 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 155311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 155411502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 155511502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 155611754Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 155711754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 82126 # Transaction distribution 155811754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 602482 # Transaction distribution 155911570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 38798 # Transaction distribution 156011570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 38798 # Transaction distribution 156111754Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1595746 # Transaction distribution 156211754Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 267406 # Transaction distribution 156311754Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 230305 # Transaction distribution 156411754Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 288781 # Transaction distribution 156511754Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 46602 # Transaction distribution 156611754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 791817 # Transaction distribution 156711754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 788064 # Transaction distribution 156811754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 520356 # Transaction distribution 156911754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 683860 # Transaction distribution 157011754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 675461 # Transaction distribution 157111754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122564 # Packet count per connected master and slave (bytes) 157210585SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 157311754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27546 # Packet count per connected master and slave (bytes) 157411754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6153530 # Packet count per connected master and slave (bytes) 157511754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6303732 # Packet count per connected master and slave (bytes) 157611754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 346870 # Packet count per connected master and slave (bytes) 157711754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 346870 # Packet count per connected master and slave (bytes) 157811754Sandreas.hansson@arm.comsystem.membus.pkt_count::total 6650602 # Packet count per connected master and slave (bytes) 157911754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155671 # Cumulative packet size per connected master and slave (bytes) 158010585SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 158111754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55092 # Cumulative packet size per connected master and slave (bytes) 158211754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 178661596 # Cumulative packet size per connected master and slave (bytes) 158311754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 178872563 # Cumulative packet size per connected master and slave (bytes) 158411754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7398784 # Cumulative packet size per connected master and slave (bytes) 158511754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7398784 # Cumulative packet size per connected master and slave (bytes) 158611754Sandreas.hansson@arm.comsystem.membus.pkt_size::total 186271347 # Cumulative packet size per connected master and slave (bytes) 158710585SN/Asystem.membus.snoops 0 # Total snoops (count) 158811570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 158911754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4499195 # Request fanout histogram 159011754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.007389 # Request fanout histogram 159111754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.085643 # Request fanout histogram 159210585SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 159311754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 4465949 99.26% 99.26% # Request fanout histogram 159411754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 33246 0.74% 100.00% # Request fanout histogram 159510585SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 159610585SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 159711502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 159810585SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 159911754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4499195 # Request fanout histogram 160011754Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 160111754Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 160211754Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 160311754Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 160411754Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 160511754Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 160611754Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 160711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 160811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 160911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 161011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 161111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 161211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 161311754Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 161411754Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 161510515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 161610515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 161710515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 161810515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 161910515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 162010515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 162110515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 162210515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 162310515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 162411754Sandreas.hansson@arm.comsystem.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 162510515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 162610515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 162710515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 162811754Sandreas.hansson@arm.comsystem.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 162910515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 163010515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 163110515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 163210515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 163310515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 163410515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 163510515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 163610515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 163710515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 163810515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 163910515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 164010515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 164110515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 164210515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 164310515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 164410515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 164510515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 164610515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 164710515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 164810515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 164910515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 165010515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 165110515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 165210515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 165310515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 165410515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 165510515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 165610515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 165711754Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 165811754Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 165911754Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 166011754Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 166111754Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 166211754Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 166311754Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 166411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 166511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 166611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 166711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 166811754Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 166911754Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167011754Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167111754Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167211754Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167311754Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167411754Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167511754Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167611754Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167711754Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167811754Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 167911754Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 168011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 11103133 # Total number of requests made to the snoop filter. 168111754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 5636149 # Number of requests hitting in the snoop filter with a single holder of the requested data. 168211754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1803428 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 168311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 289976 # Total number of snoops made to the snoop filter. 168411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 265298 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 168511754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 24678 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 168611754Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000 # Cumulative time (in ticks) in various power states 168711754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 82128 # Transaction distribution 168811754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 3548294 # Transaction distribution 168911570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 38798 # Transaction distribution 169011570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 38798 # Transaction distribution 169111754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 2764082 # Transaction distribution 169211754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1999311 # Transaction distribution 169311754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 334418 # Transaction distribution 169411754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 305075 # Transaction distribution 169511754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 639493 # Transaction distribution 169611754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1358165 # Transaction distribution 169711754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1358165 # Transaction distribution 169811754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 3466166 # Transaction distribution 169911754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 875913 # Transaction distribution 170011754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 875913 # Transaction distribution 170111754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9373855 # Packet count per connected master and slave (bytes) 170211754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8310864 # Packet count per connected master and slave (bytes) 170311754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 17684719 # Packet count per connected master and slave (bytes) 170411754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252267457 # Cumulative packet size per connected master and slave (bytes) 170511754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 233795714 # Cumulative packet size per connected master and slave (bytes) 170611754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 486063171 # Cumulative packet size per connected master and slave (bytes) 170711754Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1971827 # Total snoops (count) 170811754Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 95347072 # Total snoop traffic (bytes) 170911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 13179862 # Request fanout histogram 171011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.305132 # Request fanout histogram 171111754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.464512 # Request fanout histogram 171210515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 171311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 9182942 69.67% 69.67% # Request fanout histogram 171411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3972242 30.14% 99.81% # Request fanout histogram 171511754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 24678 0.19% 100.00% # Request fanout histogram 171610515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 171711138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 171810515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 171911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 13179862 # Request fanout histogram 172010515SN/A 172110515SN/A---------- End Simulation Statistics ---------- 1722