---------- Begin Simulation Statistics ----------
sim_seconds                                 47.177074                       # Number of seconds simulated
sim_ticks                                47177073828000                       # Number of ticks simulated
final_tick                               47177073828000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1523218                       # Simulator instruction rate (inst/s)
host_op_rate                                  1791835                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            73539001789                       # Simulator tick rate (ticks/s)
host_mem_usage                                 696552                       # Number of bytes of host memory used
host_seconds                                   641.52                       # Real time elapsed on the host
sim_insts                                   977181439                       # Number of instructions simulated
sim_ops                                    1149505972                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       157952                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       131712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4192628                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         35968392                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       222400                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker       221568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3097544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         39307632                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        413888                       # Number of bytes read from this memory
system.physmem.bytes_read::total             83713716                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4192628                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3097544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7290172                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks    102127744                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total         102148328                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         2468                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         2058                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst            105917                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            562019                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         3475                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         3462                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             48506                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            614198                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6467                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1348570                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1595746                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1598320                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          3348                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          2792                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               88870                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              762413                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          4714                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          4697                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               65658                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              833194                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8773                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1774458                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          88870                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          65658                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             154528                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2164775                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                436                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                2165211                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2164775                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         3348                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         2792                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              88870                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             762849                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         4714                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         4697                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              65658                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             833194                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8773                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3939669                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           64                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           204                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           64                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          160                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           16                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             46                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                4                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            1                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               4                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   123270                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               123270                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walkWaitTime::samples       123270                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0         123270    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       123270                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0       22846000    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total     22846000                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K        94962     90.03%     90.03% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        10516      9.97%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       105478                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       123270                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       123270                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       105478                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       105478                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       228748                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    90958252                       # DTB read hits
system.cpu0.dtb.read_misses                     87293                       # DTB read misses
system.cpu0.dtb.write_hits                   84301704                       # DTB write hits
system.cpu0.dtb.write_misses                    35977                       # DTB write misses
system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              49426                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   35878                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  5554                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    10284                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                91045545                       # DTB read accesses
system.cpu0.dtb.write_accesses               84337681                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        175259956                       # DTB hits
system.cpu0.dtb.misses                         123270                       # DTB misses
system.cpu0.dtb.accesses                    175383226                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    60279                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                60279                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walkWaitTime::samples        60279                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0          60279    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        60279                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0       22844500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total     22844500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        54211     98.84%     98.84% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M          635      1.16%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        54846                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        60279                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        60279                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        54846                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        54846                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       115125                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   489463139                       # ITB inst hits
system.cpu0.itb.inst_misses                     60279                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              49426                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   24716                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               489523418                       # ITB inst accesses
system.cpu0.itb.hits                        489463139                       # DTB hits
system.cpu0.itb.misses                          60279                       # DTB misses
system.cpu0.itb.accesses                    489523418                       # DTB accesses
system.cpu0.numPwrStateTransitions              26258                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples        13129                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    3571424062.507959                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   90351330790.457672                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3131     23.85%     23.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         9971     75.95%     99.79% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            3      0.02%     99.82% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            2      0.02%     99.83% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            2      0.02%     99.85% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11            2      0.02%     99.86% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           14      0.11%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 7510114609000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total          13129                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   287847311333                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46889226516667                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                     94354160786                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                   13129                       # number of quiesce instructions executed
system.cpu0.committedInsts                  489228722                       # Number of instructions committed
system.cpu0.committedOps                    575357792                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            527304848                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                518985                       # Number of float alu accesses
system.cpu0.num_func_calls                   28507888                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     75158499                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   527304848                       # number of integer instructions
system.cpu0.num_fp_insts                       518985                       # number of float instructions
system.cpu0.num_int_register_reads          772493030                       # number of times the integer registers were read
system.cpu0.num_int_register_writes         418386904                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads              837696                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes             439396                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           131494560                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes          131170441                       # number of times the CC registers were written
system.cpu0.num_mem_refs                    175360180                       # number of memory refs
system.cpu0.num_load_insts                   91031152                       # Number of load instructions
system.cpu0.num_store_insts                  84329028                       # Number of store instructions
system.cpu0.num_idle_cycles              93778466083.220322                       # Number of idle cycles
system.cpu0.num_busy_cycles              575694702.779680                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.006101                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.993899                       # Percentage of idle cycles
system.cpu0.Branches                        109461640                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                    1      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                398983706     69.31%     69.31% # Class of executed instruction
system.cpu0.op_class::IntMult                 1214289      0.21%     69.52% # Class of executed instruction
system.cpu0.op_class::IntDiv                    59472      0.01%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      8      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCmp                     13      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatCvt                     21      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatMultAcc                  0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     69.53% # Class of executed instruction
system.cpu0.op_class::FloatMisc                 72490      0.01%     69.54% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     69.54% # Class of executed instruction
system.cpu0.op_class::MemRead                90970869     15.80%     85.34% # Class of executed instruction
system.cpu0.op_class::MemWrite               83942858     14.58%     99.92% # Class of executed instruction
system.cpu0.op_class::FloatMemRead              60283      0.01%     99.93% # Class of executed instruction
system.cpu0.op_class::FloatMemWrite            386170      0.07%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 575690180                       # Class of executed instruction
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          6169123                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          502.902441                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          169021316                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6169635                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            27.395675                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         33050500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   502.902441                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.982231                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.982231                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          317                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2            3                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        356856913                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       356856913                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     84588460                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       84588460                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     79569773                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      79569773                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       213774                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       213774                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       259782                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       259782                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      2069774                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      2069774                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      2033350                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      2033350                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    164418015                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       164418015                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    164631789                       # number of overall hits
system.cpu0.dcache.overall_hits::total      164631789                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      3250756                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      3250756                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      1461940                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      1461940                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       763460                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       763460                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       814949                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       814949                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       115689                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       115689                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       151036                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       151036                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data      5527645                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total       5527645                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data      6291105                       # number of overall misses
system.cpu0.dcache.overall_misses::total      6291105                       # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data     87839216                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     87839216                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     81031713                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     81031713                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       977234                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       977234                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data      1074731                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total      1074731                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2185463                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2185463                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2184386                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2184386                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    169945660                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    169945660                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    170922894                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    170922894                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.037008                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.037008                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018042                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018042                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.781246                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.781246                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.758282                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.758282                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.052936                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.052936                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.069143                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.069143                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.032526                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.032526                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.036807                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.036807                       # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      6169123                       # number of writebacks
system.cpu0.dcache.writebacks::total          6169123                       # number of writebacks
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          5445857                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.988996                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          484071611                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          5446369                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            88.879694                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       5759898000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.988996                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999979                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          178                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          263                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           70                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        984482344                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       984482344                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    484071611                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      484071611                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    484071611                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       484071611                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    484071611                       # number of overall hits
system.cpu0.icache.overall_hits::total      484071611                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      5446374                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      5446374                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      5446374                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       5446374                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      5446374                       # number of overall misses
system.cpu0.icache.overall_misses::total      5446374                       # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst    489517985                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    489517985                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    489517985                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    489517985                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    489517985                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    489517985                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011126                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011126                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011126                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011126                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011126                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011126                       # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      5445857                       # number of writebacks
system.cpu0.icache.writebacks::total          5445857                       # number of writebacks
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements         2533357                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15711.685213                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           9303903                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2548994                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            3.650029                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle       290949000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15660.837363                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    30.957912                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    19.889938                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.955862                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.001890                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001214                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.958965                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           52                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15585                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           44                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            4                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          407                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         2073                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5396                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         5335                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2374                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.003174                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.951233                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       396876772                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      396876772                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       281069                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       152429                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        433498                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      4385344                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      4385344                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      7228256                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      7228256                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       628811                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       628811                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      4957899                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      4957899                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      2920611                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      2920611                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       215443                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       215443                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       281069                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       152429                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      4957899                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      3549422                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        8940819                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       281069                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       152429                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      4957899                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      3549422                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       8940819                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        20714                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        10073                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        30787                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       134964                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       134964                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       151036                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       151036                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       698165                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       698165                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       488475                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       488475                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1209294                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1209294                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       599506                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       599506                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        20714                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker        10073                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       488475                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1907459                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2426721                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        20714                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker        10073                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       488475                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1907459                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2426721                       # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       301783                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       162502                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       464285                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4385344                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      4385344                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      7228256                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      7228256                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       134964                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       134964                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       151036                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       151036                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1326976                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1326976                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      5446374                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      5446374                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4129905                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4129905                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       814949                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       814949                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       301783                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       162502                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      5446374                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5456881                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     11367540                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       301783                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       162502                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      5446374                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5456881                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     11367540                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.068639                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.061987                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.066311                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.526132                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.526132                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.089688                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.089688                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.292814                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.292814                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.735636                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.735636                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.068639                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.061987                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.089688                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.349551                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.213478                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.068639                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.061987                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.089688                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.349551                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.213478                       # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.writebacks::writebacks      1537445                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1537445                       # number of writebacks
system.cpu0.toL2Bus.snoop_filter.tot_requests     23876126                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     12158327                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1385                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       304592                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       304592                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        614484                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     10190763                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        32444                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        32444                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      4385344                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      7229636                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       134964                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       151036                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       286000                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1326976                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1326976                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      5446374                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      4129905                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       814949                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       814949                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     16424855                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     19414693                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       360152                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side       717544                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         36917244                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    697275284                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    744257581                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1440608                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      2870176                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1445843649                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    4732413                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic            102900484                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples     28818191                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.019582                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.138557                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          28253885     98.04%     98.04% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            564306      1.96%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      28818191                       # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   145570                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               145570                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walkWaitTime::samples       145570                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0         145570    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       145570                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples   -274399872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0     -274399872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total   -274399872                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K       112948     88.82%     88.82% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        14218     11.18%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total       127166                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       145570                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       145570                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data       127166                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total       127166                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       272736                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    92188600                       # DTB read hits
system.cpu1.dtb.read_misses                    112898                       # DTB read misses
system.cpu1.dtb.write_hits                   82869602                       # DTB write hits
system.cpu1.dtb.write_misses                    32672                       # DTB write misses
system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              49426                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   44985                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  4483                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    11594                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                92301498                       # DTB read accesses
system.cpu1.dtb.write_accesses               82902274                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        175058202                       # DTB hits
system.cpu1.dtb.misses                         145570                       # DTB misses
system.cpu1.dtb.accesses                    175203772                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    62174                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                62174                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walkWaitTime::samples        62174                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0          62174    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        62174                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples   -274400872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0     -274400872    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total   -274400872                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        55194     99.03%     99.03% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M          542      0.97%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        55736                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        62174                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        62174                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        55736                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        55736                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       117910                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   488205248                       # ITB inst hits
system.cpu1.itb.inst_misses                     62174                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              49426                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1118                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   31602                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               488267422                       # ITB inst accesses
system.cpu1.itb.hits                        488205248                       # DTB hits
system.cpu1.itb.misses                          62174                       # DTB misses
system.cpu1.itb.accesses                    488267422                       # DTB accesses
system.cpu1.numPwrStateTransitions              12500                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples         6250                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    7502374904.322560                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   140163345879.751923                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         4511     72.18%     72.18% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10         1712     27.39%     99.57% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            7      0.11%     99.68% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.70% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11            1      0.02%     99.71% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            3      0.05%     99.76% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11            1      0.02%     99.78% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11            1      0.02%     99.79% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           13      0.21%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          500                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 7033264907012                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total           6250                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   287230675984                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 46889843152016                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                     94354153907                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    6250                       # number of quiesce instructions executed
system.cpu1.committedInsts                  487952717                       # Number of instructions committed
system.cpu1.committedOps                    574148180                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses            526945204                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                380393                       # Number of float alu accesses
system.cpu1.num_func_calls                   28766283                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts     74749330                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                   526945204                       # number of integer instructions
system.cpu1.num_fp_insts                       380393                       # number of float instructions
system.cpu1.num_int_register_reads          777937433                       # number of times the integer registers were read
system.cpu1.num_int_register_writes         419402413                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads              618522                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes             309432                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           129016491                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes          128726040                       # number of times the CC registers were written
system.cpu1.num_mem_refs                    175180123                       # number of memory refs
system.cpu1.num_load_insts                   92288401                       # Number of load instructions
system.cpu1.num_store_insts                  82891722                       # Number of store instructions
system.cpu1.num_idle_cycles              93779692516.971710                       # Number of idle cycles
system.cpu1.num_busy_cycles              574461390.028282                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.006088                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.993912                       # Percentage of idle cycles
system.cpu1.Branches                        108727125                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                    0      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                398021787     69.29%     69.29% # Class of executed instruction
system.cpu1.op_class::IntMult                 1155567      0.20%     69.49% # Class of executed instruction
system.cpu1.op_class::IntDiv                    62024      0.01%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatMultAcc                  0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.50% # Class of executed instruction
system.cpu1.op_class::FloatMisc                 37076      0.01%     69.51% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc                 0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.51% # Class of executed instruction
system.cpu1.op_class::MemRead                92237466     16.06%     85.56% # Class of executed instruction
system.cpu1.op_class::MemWrite               82599340     14.38%     99.94% # Class of executed instruction
system.cpu1.op_class::FloatMemRead              50935      0.01%     99.95% # Class of executed instruction
system.cpu1.op_class::FloatMemWrite            292382      0.05%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                 574456577                       # Class of executed instruction
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements          6056013                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          439.385542                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          169014740                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          6056525                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            27.906223                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8470277781000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   439.385542                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.858175                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.858175                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0          166                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          345                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2            1                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        356467951                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       356467951                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     85651314                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       85651314                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     78663816                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      78663816                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       189367                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       189367                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data        66166                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total        66166                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      2074874                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      2074874                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      2069738                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      2069738                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    164381296                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       164381296                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    164570663                       # number of overall hits
system.cpu1.dcache.overall_hits::total      164570663                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      3417226                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      3417226                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      1481686                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      1481686                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       799274                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       799274                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       443256                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       443256                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       150141                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       150141                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       154039                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       154039                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data      5342168                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total       5342168                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data      6141442                       # number of overall misses
system.cpu1.dcache.overall_misses::total      6141442                       # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data     89068540                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     89068540                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     80145502                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     80145502                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       988641                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       988641                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       509422                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       509422                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2225015                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2225015                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2223777                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      2223777                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    169723464                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    169723464                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    170712105                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    170712105                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.038366                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.038366                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.018487                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.018487                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.808457                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.808457                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.870116                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.870116                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.067479                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.067479                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.069269                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.069269                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.031476                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.031476                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035975                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.035975                       # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      6056013                       # number of writebacks
system.cpu1.dcache.writebacks::total          6056013                       # number of writebacks
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          4848965                       # number of replacements
system.cpu1.icache.tags.tagsinuse          496.412961                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          483411507                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          4849477                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            99.683225                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8470205818500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   496.412961                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.969557                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.969557                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0           64                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          146                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        981371445                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       981371445                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst    483411507                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      483411507                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    483411507                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       483411507                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    483411507                       # number of overall hits
system.cpu1.icache.overall_hits::total      483411507                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      4849477                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      4849477                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      4849477                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       4849477                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      4849477                       # number of overall misses
system.cpu1.icache.overall_misses::total      4849477                       # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst    488260984                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    488260984                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    488260984                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    488260984                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    488260984                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    488260984                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009932                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.009932                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009932                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.009932                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009932                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.009932                       # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      4848965                       # number of writebacks
system.cpu1.icache.writebacks::total          4848965                       # number of writebacks
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements         2230269                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       13059.321303                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           8938644                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2245943                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            3.979907                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 13021.698131                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    21.453000                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    16.170172                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.794781                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.001309                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000987                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.797078                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           85                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15589                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            1                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           49                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          230                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         2501                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         7586                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         3485                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         1787                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.005188                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.951477                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       374536552                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      374536552                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       340661                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       155597                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        496258                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      4122422                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      4122422                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      6782171                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      6782171                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       622232                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       622232                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      4374488                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      4374488                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      3137655                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      3137655                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       166849                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       166849                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       340661                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       155597                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      4374488                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3759887                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        8630633                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       340661                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       155597                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      4374488                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3759887                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       8630633                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        22356                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker        11279                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        33635                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       145163                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       145163                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       154039                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       154039                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       714291                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       714291                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       474989                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       474989                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data      1228986                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total      1228986                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       276407                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       276407                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        22356                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker        11279                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       474989                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1943277                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      2451901                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        22356                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker        11279                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       474989                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1943277                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      2451901                       # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       363017                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       166876                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       529893                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      4122422                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      4122422                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      6782171                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      6782171                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       145163                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       145163                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       154039                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       154039                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1336523                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1336523                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      4849477                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      4849477                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      4366641                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      4366641                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       443256                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       443256                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       363017                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       166876                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      4849477                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      5703164                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     11082534                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       363017                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       166876                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      4849477                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      5703164                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     11082534                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.061584                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.067589                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.063475                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.534440                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.534440                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.097946                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.097946                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.281449                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.281449                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.623583                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.623583                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.061584                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.067589                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.097946                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.340737                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.221240                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.061584                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.067589                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.097946                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.340737                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.221240                       # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.writebacks::writebacks      1226637                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1226637                       # number of writebacks
system.cpu1.toL2Bus.snoop_filter.tot_requests     22478068                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     11482434                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests          385                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       282472                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       282472                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq        614190                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp      9830308                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         6354                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         6354                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4122422                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      6782556                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       145163                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       154039                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       299202                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1336523                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1336523                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      4849477                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4366641                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       443256                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       443256                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     14548179                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     18972689                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       371656                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side       843740                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         34736264                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    620700808                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    752625722                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1486624                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      3374960                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1378188114                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    4390439                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic             84812544                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples     27053766                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.020745                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.142530                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          26492533     97.93%     97.93% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            561233      2.07%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      27053766                       # Request fanout histogram
system.iobus.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40293                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40293                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136632                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136632                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47630                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122564                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231206                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231206                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353850                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47650                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155671                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7338840                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7338840                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496597                       # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115584                       # number of replacements
system.iocache.tags.tagsinuse               11.285245                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115600                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9107772860509                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.859437                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     7.425808                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.241215                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.464113                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.705328                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040784                       # Number of tag accesses
system.iocache.tags.data_accesses             1040784                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8875                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8912                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115603                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115643                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115603                       # number of overall misses
system.iocache.overall_misses::total           115643                       # number of overall misses
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8875                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8912                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115603                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115643                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115603                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115643                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1923250                       # number of replacements
system.l2c.tags.tagsinuse                65186.498545                       # Cycle average of tags in use
system.l2c.tags.total_refs                    5749330                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1985687                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     2.895386                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                477350500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   10983.634083                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker    57.375221                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker    60.020702                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3162.214163                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    16603.028209                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   344.016385                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   410.384147                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     2922.724883                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data    30643.100751                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.167597                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000875                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000916                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.048252                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.253342                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.005249                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.006262                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.044597                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.467577                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.994667                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023          241                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        62196                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          239                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           27                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         3250                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4725                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        53923                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.003677                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.949036                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 71541788                       # Number of tag accesses
system.l2c.tags.data_accesses                71541788                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks      2764082                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2764082                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data           56104                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data           51044                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              107148                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data          8413                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data          7881                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total             16294                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data           200040                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data           182839                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               382879                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        12914                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         5340                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       425659                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       696237                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        12397                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         4498                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       426584                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       681796                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2265425                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       112817                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       103406                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           216223                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker         12914                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          5340                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              425659                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              896277                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         12397                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          4498                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              426584                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              864635                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2648304                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        12914                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         5340                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             425659                       # number of overall hits
system.l2c.overall_hits::cpu0.data             896277                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        12397                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         4498                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             426584                       # number of overall hits
system.l2c.overall_hits::cpu1.data             864635                       # number of overall hits
system.l2c.overall_hits::total                2648304                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         19306                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         23056                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             42362                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          403                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          802                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1205                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         372703                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data         418393                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             791096                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         2468                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         2058                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        62816                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       191372                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         3475                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         3462                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        48405                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       197388                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total         511444                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       440136                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       128597                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         568733                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         2468                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         2058                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             62816                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            564075                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         3475                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         3462                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             48405                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            615781                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1302540                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         2468                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         2058                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            62816                       # number of overall misses
system.l2c.overall_misses::cpu0.data           564075                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         3475                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         3462                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            48405                       # number of overall misses
system.l2c.overall_misses::cpu1.data           615781                       # number of overall misses
system.l2c.overall_misses::total              1302540                       # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks      2764082                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2764082                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        75410                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data        74100                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          149510                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data         8816                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         8683                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total         17499                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       572743                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       601232                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total          1173975                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        15382                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7398                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       488475                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       887609                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        15872                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         7960                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       474989                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       879184                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      2776869                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       552953                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       232003                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       784956                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        15382                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7398                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          488475                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data         1460352                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        15872                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         7960                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          474989                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data         1480416                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             3950844                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        15382                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7398                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         488475                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data        1460352                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        15872                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         7960                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         474989                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data        1480416                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            3950844                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.256014                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.311147                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.283339                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.045712                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.092364                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.068861                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.650733                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.695893                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.673861                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.160447                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.278183                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.128596                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.215604                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.218939                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.434925                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.101908                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.224513                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.184180                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.795974                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.554290                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.724541                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.160447                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.278183                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.128596                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.386260                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.218939                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.434925                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.101908                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.415951                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.329687                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.160447                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.278183                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.128596                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.386260                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.218939                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.434925                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.101908                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.415951                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.329687                       # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1489052                       # number of writebacks
system.l2c.writebacks::total                  1489052                       # number of writebacks
system.membus.snoop_filter.tot_requests       4378272                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2451994                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3422                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               82126                       # Transaction distribution
system.membus.trans_dist::ReadResp             602482                       # Transaction distribution
system.membus.trans_dist::WriteReq              38798                       # Transaction distribution
system.membus.trans_dist::WriteResp             38798                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1595746                       # Transaction distribution
system.membus.trans_dist::CleanEvict           267406                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           230305                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         288781                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           46602                       # Transaction distribution
system.membus.trans_dist::ReadExReq            791817                       # Transaction distribution
system.membus.trans_dist::ReadExResp           788064                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        520356                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        683860                       # Transaction distribution
system.membus.trans_dist::InvalidateResp       675461                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122564                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           92                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        27546                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      6153530                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      6303732                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       346870                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       346870                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                6650602                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155671                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          204                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        55092                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    178661596                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    178872563                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7398784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7398784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               186271347                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           4499195                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.007389                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.085643                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 4465949     99.26%     99.26% # Request fanout histogram
system.membus.snoop_fanout::1                   33246      0.74%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             4499195                       # Request fanout histogram
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             164                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              164                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     11103133                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      5636149                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1803428                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         289976                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       265298                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        24678                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47177073828000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              82128                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           3548294                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38798                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38798                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      2764082                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         1999311                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          334418                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        305075                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         639493                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq          1358165                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp         1358165                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      3466166                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       875913                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       875913                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      9373855                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8310864                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              17684719                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    252267457                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    233795714                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              486063171                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         1971827                       # Total snoops (count)
system.toL2Bus.snoopTraffic                  95347072                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples         13179862                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.305132                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.464512                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                9182942     69.67%     69.67% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3972242     30.14%     99.81% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  24678      0.19%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total           13179862                       # Request fanout histogram

---------- End Simulation Statistics   ----------