stats.txt revision 10827
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 310726SN/Asim_seconds 47.216814 # Number of seconds simulated 410726SN/Asim_ticks 47216814145000 # Number of ticks simulated 510726SN/Afinal_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710827Sandreas.hansson@arm.comhost_inst_rate 1152960 # Simulator instruction rate (inst/s) 810827Sandreas.hansson@arm.comhost_op_rate 1356355 # Simulator op (including micro ops) rate (op/s) 910827Sandreas.hansson@arm.comhost_tick_rate 55808802200 # Simulator tick rate (ticks/s) 1010827Sandreas.hansson@arm.comhost_mem_usage 723640 # Number of bytes of host memory used 1110827Sandreas.hansson@arm.comhost_seconds 846.05 # Real time elapsed on the host 1210726SN/Asim_insts 975457230 # Number of instructions simulated 1310726SN/Asim_ops 1147538415 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1610827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 152320 # Number of bytes read from this memory 1710726SN/Asystem.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory 1810827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3903156 # Number of bytes read from this memory 1910827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 35201416 # Number of bytes read from this memory 2010827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 222016 # Number of bytes read from this memory 2110827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 221568 # Number of bytes read from this memory 2210827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 2639368 # Number of bytes read from this memory 2310827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 38466864 # Number of bytes read from this memory 2410827Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 412736 # Number of bytes read from this memory 2510827Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 81348148 # Number of bytes read from this memory 2610827Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3903156 # Number of instructions bytes read from this memory 2710827Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 2639368 # Number of instructions bytes read from this memory 2810827Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6542524 # Number of instructions bytes read from this memory 2910827Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 100538752 # Number of bytes written to this memory 3010827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3110585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 100559336 # Number of bytes written to this memory 3310827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2380 # Number of read requests responded to by this memory 3410726SN/Asystem.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory 3510827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 101394 # Number of read requests responded to by this memory 3610827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 550035 # Number of read requests responded to by this memory 3710827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3469 # Number of read requests responded to by this memory 3810827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 3462 # Number of read requests responded to by this memory 3910827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 41347 # Number of read requests responded to by this memory 4010827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 601061 # Number of read requests responded to by this memory 4110827Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6449 # Number of read requests responded to by this memory 4210827Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1311608 # Number of read requests responded to by this memory 4310827Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1570918 # Number of write requests responded to by this memory 4410827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4510585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 4610827Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1573492 # Number of write requests responded to by this memory 4710827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 3226 # Total read bandwidth from this memory (bytes/s) 4810726SN/Asystem.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) 4910827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 82665 # Total read bandwidth from this memory (bytes/s) 5010827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 745527 # Total read bandwidth from this memory (bytes/s) 5110827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4702 # Total read bandwidth from this memory (bytes/s) 5210827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 4693 # Total read bandwidth from this memory (bytes/s) 5310827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 55899 # Total read bandwidth from this memory (bytes/s) 5410827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 814686 # Total read bandwidth from this memory (bytes/s) 5510827Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8741 # Total read bandwidth from this memory (bytes/s) 5610827Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1722864 # Total read bandwidth from this memory (bytes/s) 5710827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 82665 # Instruction read bandwidth from this memory (bytes/s) 5810827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 55899 # Instruction read bandwidth from this memory (bytes/s) 5910827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 138563 # Instruction read bandwidth from this memory (bytes/s) 6010827Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 2129300 # Write bandwidth from this memory (bytes/s) 6110827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 436 # Write bandwidth from this memory (bytes/s) 6210585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6310827Sandreas.hansson@arm.comsystem.physmem.bw_write::total 2129736 # Write bandwidth from this memory (bytes/s) 6410827Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 2129300 # Total bandwidth to/from this memory (bytes/s) 6510827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 3226 # Total bandwidth to/from this memory (bytes/s) 6610726SN/Asystem.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) 6710827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 82665 # Total bandwidth to/from this memory (bytes/s) 6810827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 745963 # Total bandwidth to/from this memory (bytes/s) 6910827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4702 # Total bandwidth to/from this memory (bytes/s) 7010827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 4693 # Total bandwidth to/from this memory (bytes/s) 7110827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 55899 # Total bandwidth to/from this memory (bytes/s) 7210827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 814686 # Total bandwidth to/from this memory (bytes/s) 7310827Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8741 # Total bandwidth to/from this memory (bytes/s) 7410827Sandreas.hansson@arm.comsystem.physmem.bw_total::total 3852600 # Total bandwidth to/from this memory (bytes/s) 7510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 7610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 7710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 7810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 7910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 8010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 8110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 8210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 8310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 8410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 8510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 8610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 8710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 8810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 8910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 9010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 9110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 9210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 9310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 9410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 9510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 9610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 9710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 9810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 9910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 10010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 10110585SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 10210585SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 10310585SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 10410585SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 10510585SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 10610585SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 10710515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 10810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 10910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 11010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 11210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 11310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 11410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 11510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 11610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 11710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 11810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 11910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 12410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 12710585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 12810585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 12910585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13010585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13110585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13210585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13310585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 13410585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 13510585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 13610585SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 13710726SN/Asystem.cpu0.dtb.walker.walks 125229 # Table walker walks requested 13810726SN/Asystem.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors 13910726SN/Asystem.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency 14010726SN/Asystem.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency 14110726SN/Asystem.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency 14210628SN/Asystem.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution 14310628SN/Asystem.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution 14410628SN/Asystem.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution 14510726SN/Asystem.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated 14610726SN/Asystem.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated 14710726SN/Asystem.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated 14810726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst 14910628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15010726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst 15110726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst 15210628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 15310726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst 15410726SN/Asystem.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst 15510585SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 15610585SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 15710726SN/Asystem.cpu0.dtb.read_hits 92662773 # DTB read hits 15810726SN/Asystem.cpu0.dtb.read_misses 88786 # DTB read misses 15910726SN/Asystem.cpu0.dtb.write_hits 85694958 # DTB write hits 16010726SN/Asystem.cpu0.dtb.write_misses 36443 # DTB write misses 16110585SN/Asystem.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 16210585SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 16310726SN/Asystem.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 16410585SN/Asystem.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 16510726SN/Asystem.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB 16610585SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 16710726SN/Asystem.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch 16810585SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16910726SN/Asystem.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions 17010726SN/Asystem.cpu0.dtb.read_accesses 92751559 # DTB read accesses 17110726SN/Asystem.cpu0.dtb.write_accesses 85731401 # DTB write accesses 17210585SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 17310726SN/Asystem.cpu0.dtb.hits 178357731 # DTB hits 17410726SN/Asystem.cpu0.dtb.misses 125229 # DTB misses 17510726SN/Asystem.cpu0.dtb.accesses 178482960 # DTB accesses 17610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 17710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17810628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 17910628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 18010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 18210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 18310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 18410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 18510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 18610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 18710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 18810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 18910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 19010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 19110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 19210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 19310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 19510585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 19610585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 19710585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19810585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19910585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 20010585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 20110585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 20210585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 20310585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 20410585SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 20510726SN/Asystem.cpu0.itb.walker.walks 61377 # Table walker walks requested 20610726SN/Asystem.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors 20710726SN/Asystem.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency 20810726SN/Asystem.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency 20910726SN/Asystem.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency 21010628SN/Asystem.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution 21110628SN/Asystem.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution 21210628SN/Asystem.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution 21310726SN/Asystem.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated 21410726SN/Asystem.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated 21510726SN/Asystem.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated 21610628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 21710726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst 21810726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst 21910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 22010726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst 22110726SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst 22210726SN/Asystem.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst 22310726SN/Asystem.cpu0.itb.inst_hits 497696393 # ITB inst hits 22410726SN/Asystem.cpu0.itb.inst_misses 61377 # ITB inst misses 22510585SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 22610585SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 22710585SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 22810585SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 22910585SN/Asystem.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 23010585SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 23110726SN/Asystem.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 23210585SN/Asystem.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 23310726SN/Asystem.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB 23410585SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 23510585SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 23610585SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23710585SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23810585SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 23910585SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 24010726SN/Asystem.cpu0.itb.inst_accesses 497757770 # ITB inst accesses 24110726SN/Asystem.cpu0.itb.hits 497696393 # DTB hits 24210726SN/Asystem.cpu0.itb.misses 61377 # DTB misses 24310726SN/Asystem.cpu0.itb.accesses 497757770 # DTB accesses 24410726SN/Asystem.cpu0.numCycles 94433641544 # number of cpu cycles simulated 24510585SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 24610585SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 24710726SN/Asystem.cpu0.committedInsts 497466384 # Number of instructions committed 24810726SN/Asystem.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed 24910726SN/Asystem.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses 25010726SN/Asystem.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses 25110726SN/Asystem.cpu0.num_func_calls 28869117 # number of times a function call or return occured 25210726SN/Asystem.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls 25310726SN/Asystem.cpu0.num_int_insts 536103359 # number of integer instructions 25410726SN/Asystem.cpu0.num_fp_insts 526132 # number of float instructions 25510726SN/Asystem.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read 25610726SN/Asystem.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written 25710726SN/Asystem.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read 25810726SN/Asystem.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written 25910726SN/Asystem.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read 26010726SN/Asystem.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written 26110726SN/Asystem.cpu0.num_mem_refs 178459396 # number of memory refs 26210726SN/Asystem.cpu0.num_load_insts 92737001 # Number of load instructions 26310726SN/Asystem.cpu0.num_store_insts 85722395 # Number of store instructions 26410726SN/Asystem.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles 26510726SN/Asystem.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles 26610726SN/Asystem.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles 26710726SN/Asystem.cpu0.idle_fraction 0.993802 # Percentage of idle cycles 26810726SN/Asystem.cpu0.Branches 111287587 # Number of branches fetched 26910585SN/Asystem.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 27010726SN/Asystem.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction 27110726SN/Asystem.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction 27210726SN/Asystem.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction 27310726SN/Asystem.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction 27410726SN/Asystem.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction 27510726SN/Asystem.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction 27610726SN/Asystem.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction 27710726SN/Asystem.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction 27810726SN/Asystem.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction 27910726SN/Asystem.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction 28010726SN/Asystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction 28110726SN/Asystem.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction 28210726SN/Asystem.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction 28310726SN/Asystem.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction 28410726SN/Asystem.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction 28510726SN/Asystem.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction 28610726SN/Asystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction 28710726SN/Asystem.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction 28810726SN/Asystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction 28910726SN/Asystem.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction 29010726SN/Asystem.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction 29110726SN/Asystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction 29210726SN/Asystem.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction 29310726SN/Asystem.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction 29410726SN/Asystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction 29510726SN/Asystem.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction 29610726SN/Asystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction 29710726SN/Asystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction 29810726SN/Asystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction 29910726SN/Asystem.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction 30010726SN/Asystem.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction 30110585SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 30210585SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 30310726SN/Asystem.cpu0.op_class::total 585300003 # Class of executed instruction 30410585SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 30510726SN/Asystem.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed 30610827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 6272773 # number of replacements 30710726SN/Asystem.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use 30810827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 172015769 # Total number of references to valid blocks. 30910827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 6273285 # Sample count of references to valid blocks. 31010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 27.420366 # Average number of references to valid blocks. 31110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. 31210726SN/Asystem.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor 31310726SN/Asystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy 31410726SN/Asystem.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy 31510585SN/Asystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31610726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id 31710726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 31810726SN/Asystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 31910585SN/Asystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 363162250 # Number of tag accesses 32110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 363162250 # Number of data accesses 32210827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 86214909 # number of ReadReq hits 32310827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 86214909 # number of ReadReq hits 32410827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 80919814 # number of WriteReq hits 32510827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 80919814 # number of WriteReq hits 32610827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 215654 # number of SoftPFReq hits 32710827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 215654 # number of SoftPFReq hits 32810726SN/Asystem.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits 32910726SN/Asystem.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits 33010827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076465 # number of LoadLockedReq hits 33110827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 2076465 # number of LoadLockedReq hits 33210827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036713 # number of StoreCondReq hits 33310827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 2036713 # number of StoreCondReq hits 33410827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 167134723 # number of demand (read+write) hits 33510827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 167134723 # number of demand (read+write) hits 33610827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 167350377 # number of overall hits 33710827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 167350377 # number of overall hits 33810827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 3309384 # number of ReadReq misses 33910827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 3309384 # number of ReadReq misses 34010827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1475628 # number of WriteReq misses 34110827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1475628 # number of WriteReq misses 34210827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 772139 # number of SoftPFReq misses 34310827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 772139 # number of SoftPFReq misses 34410726SN/Asystem.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses 34510726SN/Asystem.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses 34610827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119817 # number of LoadLockedReq misses 34710827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 119817 # number of LoadLockedReq misses 34810827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 158430 # number of StoreCondReq misses 34910827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 158430 # number of StoreCondReq misses 35010827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4785012 # number of demand (read+write) misses 35110827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4785012 # number of demand (read+write) misses 35210827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 5557151 # number of overall misses 35310827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 5557151 # number of overall misses 35410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 89524293 # number of ReadReq accesses(hits+misses) 35510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 89524293 # number of ReadReq accesses(hits+misses) 35610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 82395442 # number of WriteReq accesses(hits+misses) 35710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 82395442 # number of WriteReq accesses(hits+misses) 35810726SN/Asystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) 35910726SN/Asystem.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) 36010726SN/Asystem.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses) 36110726SN/Asystem.cpu0.dcache.WriteInvalidateReq_accesses::total 1093720 # number of WriteInvalidateReq accesses(hits+misses) 36210726SN/Asystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) 36310726SN/Asystem.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) 36410726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) 36510726SN/Asystem.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) 36610827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 171919735 # number of demand (read+write) accesses 36710827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 171919735 # number of demand (read+write) accesses 36810827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 172907528 # number of overall (read+write) accesses 36910827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 172907528 # number of overall (read+write) accesses 37010726SN/Asystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses 37110726SN/Asystem.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses 37210827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017909 # miss rate for WriteReq accesses 37310827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.017909 # miss rate for WriteReq accesses 37410827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781681 # miss rate for SoftPFReq accesses 37510827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.781681 # miss rate for SoftPFReq accesses 37610726SN/Asystem.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses 37710726SN/Asystem.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses 37810726SN/Asystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses 37910726SN/Asystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses 38010827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072173 # miss rate for StoreCondReq accesses 38110827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.072173 # miss rate for StoreCondReq accesses 38210827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027833 # miss rate for demand accesses 38310827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.027833 # miss rate for demand accesses 38410726SN/Asystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses 38510726SN/Asystem.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses 38610585SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38710585SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38810585SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 38910585SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39010585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39110585SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39210585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 39310585SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 39410827Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 4471084 # number of writebacks 39510827Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 4471084 # number of writebacks 39610585SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 39710827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5539078 # number of replacements 39810726SN/Asystem.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use 39910827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 492212894 # Total number of references to valid blocks. 40010827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5539590 # Sample count of references to valid blocks. 40110827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 88.853669 # Average number of references to valid blocks. 40210585SN/Asystem.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. 40310726SN/Asystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor 40410585SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy 40510585SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy 40610585SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 40710726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 40810726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 40910726SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id 41010585SN/Asystem.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 41110585SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41210827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 1001044573 # Number of tag accesses 41310827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 1001044573 # Number of data accesses 41410827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 492212894 # number of ReadReq hits 41510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 492212894 # number of ReadReq hits 41610827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 492212894 # number of demand (read+write) hits 41710827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 492212894 # number of demand (read+write) hits 41810827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 492212894 # number of overall hits 41910827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 492212894 # number of overall hits 42010827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5539595 # number of ReadReq misses 42110827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5539595 # number of ReadReq misses 42210827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5539595 # number of demand (read+write) misses 42310827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 5539595 # number of demand (read+write) misses 42410827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5539595 # number of overall misses 42510827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5539595 # number of overall misses 42610726SN/Asystem.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) 42710726SN/Asystem.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) 42810726SN/Asystem.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses 42910726SN/Asystem.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses 43010726SN/Asystem.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses 43110726SN/Asystem.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses 43210726SN/Asystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses 43310726SN/Asystem.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses 43410726SN/Asystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses 43510726SN/Asystem.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses 43610726SN/Asystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses 43710726SN/Asystem.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses 43810585SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 43910585SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 44010585SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 44110585SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 44210585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44310585SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44410585SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 44510585SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 44610585SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 44710628SN/Asystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 44810628SN/Asystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 44910628SN/Asystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 45010628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 45110628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 45210628SN/Asystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 45310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2709460 # number of replacements 45410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16213.748169 # Cycle average of tags in use 45510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 11555205 # Total number of references to valid blocks. 45610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2725459 # Sample count of references to valid blocks. 45710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 4.239728 # Average number of references to valid blocks. 45810585SN/Asystem.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. 45910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 5709.903296 # Average occupied blocks per requestor 46010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 52.786445 # Average occupied blocks per requestor 46110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 57.022731 # Average occupied blocks per requestor 46210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4531.359232 # Average occupied blocks per requestor 46310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 5862.676466 # Average occupied blocks per requestor 46410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.348505 # Average percentage of cache occupancy 46510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003222 # Average percentage of cache occupancy 46610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003480 # Average percentage of cache occupancy 46710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276572 # Average percentage of cache occupancy 46810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.357829 # Average percentage of cache occupancy 46910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.989609 # Average percentage of cache occupancy 47010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 48 # Occupied blocks per task id 47110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15951 # Occupied blocks per task id 47210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 33 # Occupied blocks per task id 47310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 47410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 47510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 234 # Occupied blocks per task id 47610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1167 # Occupied blocks per task id 47710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4590 # Occupied blocks per task id 47810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5333 # Occupied blocks per task id 47910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4627 # Occupied blocks per task id 48010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.002930 # Percentage of cache occupancy per task id 48110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973572 # Percentage of cache occupancy per task id 48210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 278732920 # Number of tag accesses 48310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 278732920 # Number of data accesses 48410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 271204 # number of ReadReq hits 48510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 143552 # number of ReadReq hits 48610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971662 # number of ReadReq hits 48710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.data 2944246 # number of ReadReq hits 48810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 8330664 # number of ReadReq hits 48910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 4471084 # number of Writeback hits 49010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 4471084 # number of Writeback hits 49110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 223142 # number of WriteInvalidateReq hits 49210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_hits::total 223142 # number of WriteInvalidateReq hits 49310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3523 # number of UpgradeReq hits 49410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 3523 # number of UpgradeReq hits 49510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 635192 # number of ReadExReq hits 49610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 635192 # number of ReadExReq hits 49710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 271204 # number of demand (read+write) hits 49810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 143552 # number of demand (read+write) hits 49910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4971662 # number of demand (read+write) hits 50010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3579438 # number of demand (read+write) hits 50110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 8965856 # number of demand (read+write) hits 50210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 271204 # number of overall hits 50310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 143552 # number of overall hits 50410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4971662 # number of overall hits 50510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3579438 # number of overall hits 50610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 8965856 # number of overall hits 50710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11221 # number of ReadReq misses 50810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8442 # number of ReadReq misses 50910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 567933 # number of ReadReq misses 51010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.data 1257094 # number of ReadReq misses 51110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 1844690 # number of ReadReq misses 51210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608192 # number of WriteInvalidateReq misses 51310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::total 608192 # number of WriteInvalidateReq misses 51410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128237 # number of UpgradeReq misses 51510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 128237 # number of UpgradeReq misses 51610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158430 # number of SCUpgradeReq misses 51710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 158430 # number of SCUpgradeReq misses 51810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 709038 # number of ReadExReq misses 51910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 709038 # number of ReadExReq misses 52010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11221 # number of demand (read+write) misses 52110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8442 # number of demand (read+write) misses 52210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 567933 # number of demand (read+write) misses 52310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1966132 # number of demand (read+write) misses 52410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 2553728 # number of demand (read+write) misses 52510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11221 # number of overall misses 52610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8442 # number of overall misses 52710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 567933 # number of overall misses 52810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1966132 # number of overall misses 52910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 2553728 # number of overall misses 53010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 282425 # number of ReadReq accesses(hits+misses) 53110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 151994 # number of ReadReq accesses(hits+misses) 53210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539595 # number of ReadReq accesses(hits+misses) 53310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201340 # number of ReadReq accesses(hits+misses) 53410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 10175354 # number of ReadReq accesses(hits+misses) 53510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 4471084 # number of Writeback accesses(hits+misses) 53610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 4471084 # number of Writeback accesses(hits+misses) 53710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831334 # number of WriteInvalidateReq accesses(hits+misses) 53810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::total 831334 # number of WriteInvalidateReq accesses(hits+misses) 53910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131760 # number of UpgradeReq accesses(hits+misses) 54010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 131760 # number of UpgradeReq accesses(hits+misses) 54110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158430 # number of SCUpgradeReq accesses(hits+misses) 54210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 158430 # number of SCUpgradeReq accesses(hits+misses) 54310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344230 # number of ReadExReq accesses(hits+misses) 54410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1344230 # number of ReadExReq accesses(hits+misses) 54510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 282425 # number of demand (read+write) accesses 54610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 151994 # number of demand (read+write) accesses 54710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5539595 # number of demand (read+write) accesses 54810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5545570 # number of demand (read+write) accesses 54910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 11519584 # number of demand (read+write) accesses 55010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 282425 # number of overall (read+write) accesses 55110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 151994 # number of overall (read+write) accesses 55210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 5539595 # number of overall (read+write) accesses 55310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5545570 # number of overall (read+write) accesses 55410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 11519584 # number of overall (read+write) accesses 55510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for ReadReq accesses 55610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.055542 # miss rate for ReadReq accesses 55710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102522 # miss rate for ReadReq accesses 55810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299213 # miss rate for ReadReq accesses 55910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.181290 # miss rate for ReadReq accesses 56010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731586 # miss rate for WriteInvalidateReq accesses 56110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731586 # miss rate for WriteInvalidateReq accesses 56210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973262 # miss rate for UpgradeReq accesses 56310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973262 # miss rate for UpgradeReq accesses 56410585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 56510585SN/Asystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 56610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527468 # miss rate for ReadExReq accesses 56710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.527468 # miss rate for ReadExReq accesses 56810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for demand accesses 56910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.055542 # miss rate for demand accesses 57010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102522 # miss rate for demand accesses 57110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354541 # miss rate for demand accesses 57210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.221686 # miss rate for demand accesses 57310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039731 # miss rate for overall accesses 57410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.055542 # miss rate for overall accesses 57510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102522 # miss rate for overall accesses 57610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354541 # miss rate for overall accesses 57710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.221686 # miss rate for overall accesses 57810585SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 57910585SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58010585SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 58110585SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 58210585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 58310585SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 58410585SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 58510585SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 58610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1573136 # number of writebacks 58710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1573136 # number of writebacks 58810585SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 58910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 10363944 # Transaction distribution 59010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 10363944 # Transaction distribution 59110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 32419 # Transaction distribution 59210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 32419 # Transaction distribution 59310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 4471084 # Transaction distribution 59410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831334 # Transaction distribution 59510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831334 # Transaction distribution 59610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 131760 # Transaction distribution 59710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158430 # Transaction distribution 59810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 290190 # Transaction distribution 59910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1344230 # Transaction distribution 60010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1344230 # Transaction distribution 60110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165440 # Packet count per connected master and slave (bytes) 60210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17935148 # Packet count per connected master and slave (bytes) 60310726SN/Asystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) 60410726SN/Asystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) 60510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 30195318 # Packet count per connected master and slave (bytes) 60610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706580 # Cumulative packet size per connected master and slave (bytes) 60710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694464585 # Cumulative packet size per connected master and slave (bytes) 60810726SN/Asystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) 60910726SN/Asystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) 61010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1053550085 # Cumulative packet size per connected master and slave (bytes) 61110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 3357578 # Total snoops (count) 61210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 20506010 # Request fanout histogram 61310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 1.181419 # Request fanout histogram 61410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.385365 # Request fanout histogram 61510585SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 61610585SN/Asystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 61710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 16785836 81.86% 81.86% # Request fanout histogram 61810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 3720174 18.14% 100.00% # Request fanout histogram 61910585SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 62010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 62110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 62210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 20506010 # Request fanout histogram 62310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 62410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 62510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 62610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 62710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 62810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 62910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 63010628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 63110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 63210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 63310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 63410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 63510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 63610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 63710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 63810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 63910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 64010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 64110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 64210585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 64310585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 64410585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64510585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 64610585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64710585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 64810585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 64910585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 65010585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 65110585SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 65210726SN/Asystem.cpu1.dtb.walker.walks 144041 # Table walker walks requested 65310726SN/Asystem.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors 65410726SN/Asystem.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency 65510726SN/Asystem.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency 65610726SN/Asystem.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency 65710628SN/Asystem.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution 65810628SN/Asystem.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution 65910628SN/Asystem.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution 66010726SN/Asystem.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated 66110726SN/Asystem.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated 66210726SN/Asystem.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated 66310726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst 66410628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 66510726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst 66610726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst 66710628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 66810726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst 66910726SN/Asystem.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst 67010585SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 67110585SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 67210726SN/Asystem.cpu1.dtb.read_hits 90153061 # DTB read hits 67310726SN/Asystem.cpu1.dtb.read_misses 111753 # DTB read misses 67410726SN/Asystem.cpu1.dtb.write_hits 81132787 # DTB write hits 67510726SN/Asystem.cpu1.dtb.write_misses 32288 # DTB write misses 67610585SN/Asystem.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 67710585SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 67810726SN/Asystem.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 67910585SN/Asystem.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 68010726SN/Asystem.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB 68110585SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 68210726SN/Asystem.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch 68310585SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 68410726SN/Asystem.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions 68510726SN/Asystem.cpu1.dtb.read_accesses 90264814 # DTB read accesses 68610726SN/Asystem.cpu1.dtb.write_accesses 81165075 # DTB write accesses 68710585SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 68810726SN/Asystem.cpu1.dtb.hits 171285848 # DTB hits 68910726SN/Asystem.cpu1.dtb.misses 144041 # DTB misses 69010726SN/Asystem.cpu1.dtb.accesses 171429889 # DTB accesses 69110628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 69210628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 69310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 69510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 69610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 69710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 69910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 70010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 70110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 70210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 70310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 70410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 70510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 70610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 70710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 70810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 70910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 71010585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 71110585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 71210585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 71310585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71410585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 71510585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 71610585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 71710585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 71810585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 71910585SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 72010726SN/Asystem.cpu1.itb.walker.walks 60885 # Table walker walks requested 72110726SN/Asystem.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors 72210726SN/Asystem.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency 72310726SN/Asystem.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency 72410726SN/Asystem.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency 72510628SN/Asystem.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution 72610628SN/Asystem.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution 72710628SN/Asystem.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution 72810726SN/Asystem.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated 72910726SN/Asystem.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated 73010726SN/Asystem.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated 73110628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 73210726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst 73310726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst 73410628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 73510726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst 73610726SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst 73710726SN/Asystem.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst 73810726SN/Asystem.cpu1.itb.inst_hits 478248118 # ITB inst hits 73910726SN/Asystem.cpu1.itb.inst_misses 60885 # ITB inst misses 74010585SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 74110585SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 74210585SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 74310585SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 74410585SN/Asystem.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 74510585SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 74610726SN/Asystem.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID 74710585SN/Asystem.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID 74810726SN/Asystem.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB 74910585SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 75010585SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 75110585SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 75210585SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 75310585SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 75410585SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 75510726SN/Asystem.cpu1.itb.inst_accesses 478309003 # ITB inst accesses 75610726SN/Asystem.cpu1.itb.hits 478248118 # DTB hits 75710726SN/Asystem.cpu1.itb.misses 60885 # DTB misses 75810726SN/Asystem.cpu1.itb.accesses 478309003 # DTB accesses 75910726SN/Asystem.cpu1.numCycles 94433634550 # number of cpu cycles simulated 76010585SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 76110585SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 76210726SN/Asystem.cpu1.committedInsts 477990846 # Number of instructions committed 76310726SN/Asystem.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed 76410726SN/Asystem.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses 76510726SN/Asystem.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses 76610726SN/Asystem.cpu1.num_func_calls 28237407 # number of times a function call or return occured 76710726SN/Asystem.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls 76810726SN/Asystem.cpu1.num_int_insts 516282159 # number of integer instructions 76910726SN/Asystem.cpu1.num_fp_insts 374678 # number of float instructions 77010726SN/Asystem.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read 77110726SN/Asystem.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written 77210726SN/Asystem.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read 77310726SN/Asystem.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written 77410726SN/Asystem.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read 77510726SN/Asystem.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written 77610726SN/Asystem.cpu1.num_mem_refs 171406825 # number of memory refs 77710726SN/Asystem.cpu1.num_load_insts 90251973 # Number of load instructions 77810726SN/Asystem.cpu1.num_store_insts 81154852 # Number of store instructions 77910726SN/Asystem.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles 78010726SN/Asystem.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles 78110726SN/Asystem.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles 78210726SN/Asystem.cpu1.idle_fraction 0.994039 # Percentage of idle cycles 78310726SN/Asystem.cpu1.Branches 106497601 # Number of branches fetched 78410585SN/Asystem.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 78510726SN/Asystem.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction 78610726SN/Asystem.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction 78710726SN/Asystem.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction 78810726SN/Asystem.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction 78910726SN/Asystem.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction 79010726SN/Asystem.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction 79110726SN/Asystem.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction 79210726SN/Asystem.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction 79310726SN/Asystem.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction 79410726SN/Asystem.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction 79510726SN/Asystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction 79610726SN/Asystem.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction 79710726SN/Asystem.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction 79810726SN/Asystem.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction 79910726SN/Asystem.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction 80010726SN/Asystem.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction 80110726SN/Asystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction 80210726SN/Asystem.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction 80310726SN/Asystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction 80410726SN/Asystem.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction 80510726SN/Asystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction 80610726SN/Asystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction 80710726SN/Asystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction 80810726SN/Asystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction 80910726SN/Asystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction 81010726SN/Asystem.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction 81110726SN/Asystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction 81210726SN/Asystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction 81310726SN/Asystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction 81410726SN/Asystem.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction 81510726SN/Asystem.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction 81610585SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 81710585SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 81810726SN/Asystem.cpu1.op_class::total 562879339 # Class of executed instruction 81910585SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 82010726SN/Asystem.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed 82110726SN/Asystem.cpu1.dcache.tags.replacements 5945049 # number of replacements 82210726SN/Asystem.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use 82310726SN/Asystem.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. 82410726SN/Asystem.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks. 82510726SN/Asystem.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks. 82610585SN/Asystem.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. 82710726SN/Asystem.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor 82810726SN/Asystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy 82910726SN/Asystem.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy 83010726SN/Asystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 83110726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 83210726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 83310726SN/Asystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 83410726SN/Asystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 83510726SN/Asystem.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses 83610726SN/Asystem.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses 83710726SN/Asystem.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits 83810726SN/Asystem.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits 83910827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 76990302 # number of WriteReq hits 84010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 76990302 # number of WriteReq hits 84110726SN/Asystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits 84210726SN/Asystem.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits 84310827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63438 # number of WriteInvalidateReq hits 84410827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_hits::total 63438 # number of WriteInvalidateReq hits 84510726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits 84610726SN/Asystem.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits 84710827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048921 # number of StoreCondReq hits 84810827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 2048921 # number of StoreCondReq hits 84910827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 160687866 # number of demand (read+write) hits 85010827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 160687866 # number of demand (read+write) hits 85110827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 160875720 # number of overall hits 85210827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 160875720 # number of overall hits 85310726SN/Asystem.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses 85410726SN/Asystem.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses 85510827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1453174 # number of WriteReq misses 85610827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1453174 # number of WriteReq misses 85710726SN/Asystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses 85810726SN/Asystem.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses 85910827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427061 # number of WriteInvalidateReq misses 86010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_misses::total 427061 # number of WriteInvalidateReq misses 86110726SN/Asystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses 86210726SN/Asystem.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses 86310827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 158828 # number of StoreCondReq misses 86410827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 158828 # number of StoreCondReq misses 86510827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4811396 # number of demand (read+write) misses 86610827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4811396 # number of demand (read+write) misses 86710827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5603747 # number of overall misses 86810827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5603747 # number of overall misses 86910726SN/Asystem.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) 87010726SN/Asystem.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) 87110726SN/Asystem.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) 87210726SN/Asystem.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) 87310726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) 87410726SN/Asystem.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) 87510726SN/Asystem.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses) 87610726SN/Asystem.cpu1.dcache.WriteInvalidateReq_accesses::total 490499 # number of WriteInvalidateReq accesses(hits+misses) 87710726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) 87810726SN/Asystem.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) 87910726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) 88010726SN/Asystem.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses) 88110726SN/Asystem.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses 88210726SN/Asystem.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses 88310726SN/Asystem.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses 88410726SN/Asystem.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses 88510726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses 88610726SN/Asystem.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses 88710726SN/Asystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 # miss rate for WriteReq accesses 88810726SN/Asystem.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses 88910726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses 89010726SN/Asystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses 89110827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870666 # miss rate for WriteInvalidateReq accesses 89210827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870666 # miss rate for WriteInvalidateReq accesses 89310726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses 89410726SN/Asystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses 89510827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071941 # miss rate for StoreCondReq accesses 89610827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.071941 # miss rate for StoreCondReq accesses 89710726SN/Asystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses 89810726SN/Asystem.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses 89910726SN/Asystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses 90010726SN/Asystem.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses 90110585SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 90210585SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 90310585SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 90410585SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 90510585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90610585SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90710585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 90810585SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 90910827Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 4032690 # number of writebacks 91010827Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 4032690 # number of writebacks 91110585SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 91210726SN/Asystem.cpu1.icache.tags.replacements 4741297 # number of replacements 91310726SN/Asystem.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use 91410726SN/Asystem.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. 91510726SN/Asystem.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. 91610726SN/Asystem.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. 91710585SN/Asystem.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. 91810726SN/Asystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor 91910726SN/Asystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy 92010726SN/Asystem.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy 92110585SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 92210585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 92310585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 92410585SN/Asystem.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id 92510585SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 92610726SN/Asystem.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses 92710726SN/Asystem.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses 92810726SN/Asystem.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits 92910726SN/Asystem.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits 93010726SN/Asystem.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits 93110726SN/Asystem.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits 93210726SN/Asystem.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits 93310726SN/Asystem.cpu1.icache.overall_hits::total 473560604 # number of overall hits 93410726SN/Asystem.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses 93510726SN/Asystem.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses 93610726SN/Asystem.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses 93710726SN/Asystem.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses 93810726SN/Asystem.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses 93910726SN/Asystem.cpu1.icache.overall_misses::total 4741809 # number of overall misses 94010726SN/Asystem.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses) 94110726SN/Asystem.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses) 94210726SN/Asystem.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses 94310726SN/Asystem.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses 94410726SN/Asystem.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses 94510726SN/Asystem.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses 94610726SN/Asystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses 94710726SN/Asystem.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses 94810726SN/Asystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses 94910726SN/Asystem.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses 95010726SN/Asystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses 95110726SN/Asystem.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses 95210585SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 95310585SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 95410585SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 95510585SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 95610585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 95710585SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 95810585SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 95910585SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 96010585SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 96110628SN/Asystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 96210628SN/Asystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 96310628SN/Asystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 96410628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 96510628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 96610628SN/Asystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 96710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2276750 # number of replacements 96810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13455.535871 # Cycle average of tags in use 96910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 10863007 # Total number of references to valid blocks. 97010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2292767 # Sample count of references to valid blocks. 97110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 4.737946 # Average number of references to valid blocks. 97210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9713557209000 # Cycle when the warmup percentage was hit. 97310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 5167.508425 # Average occupied blocks per requestor 97410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.262953 # Average occupied blocks per requestor 97510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.675159 # Average occupied blocks per requestor 97610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2849.798557 # Average occupied blocks per requestor 97710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 5285.290777 # Average occupied blocks per requestor 97810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.315400 # Average percentage of cache occupancy 97910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004044 # Average percentage of cache occupancy 98010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005290 # Average percentage of cache occupancy 98110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.173938 # Average percentage of cache occupancy 98210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322589 # Average percentage of cache occupancy 98310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.821261 # Average percentage of cache occupancy 98410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 96 # Occupied blocks per task id 98510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15921 # Occupied blocks per task id 98610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id 98710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 98810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id 98910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 99010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id 99110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 99210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1571 # Occupied blocks per task id 99310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5986 # Occupied blocks per task id 99410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4452 # Occupied blocks per task id 99510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3831 # Occupied blocks per task id 99610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id 99710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.971741 # Percentage of cache occupancy per task id 99810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 254014080 # Number of tag accesses 99910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 254014080 # Number of data accesses 100010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 324472 # number of ReadReq hits 100110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 140015 # number of ReadReq hits 100210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 4218186 # number of ReadReq hits 100310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.data 3058286 # number of ReadReq hits 100410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 7740959 # number of ReadReq hits 100510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 4032690 # number of Writeback hits 100610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 4032690 # number of Writeback hits 100710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161150 # number of WriteInvalidateReq hits 100810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_hits::total 161150 # number of WriteInvalidateReq hits 100910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3831 # number of UpgradeReq hits 101010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 3831 # number of UpgradeReq hits 101110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 614491 # number of ReadExReq hits 101210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 614491 # number of ReadExReq hits 101310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 324472 # number of demand (read+write) hits 101410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 140015 # number of demand (read+write) hits 101510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4218186 # number of demand (read+write) hits 101610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3672777 # number of demand (read+write) hits 101710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8355450 # number of demand (read+write) hits 101810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 324472 # number of overall hits 101910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 140015 # number of overall hits 102010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4218186 # number of overall hits 102110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3672777 # number of overall hits 102210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8355450 # number of overall hits 102310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12267 # number of ReadReq misses 102410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9705 # number of ReadReq misses 102510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 523623 # number of ReadReq misses 102610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.data 1239107 # number of ReadReq misses 102710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 1784702 # number of ReadReq misses 102810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265696 # number of WriteInvalidateReq misses 102910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_misses::total 265696 # number of WriteInvalidateReq misses 103010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133668 # number of UpgradeReq misses 103110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 133668 # number of UpgradeReq misses 103210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158828 # number of SCUpgradeReq misses 103310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 158828 # number of SCUpgradeReq misses 103410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 701399 # number of ReadExReq misses 103510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 701399 # number of ReadExReq misses 103610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12267 # number of demand (read+write) misses 103710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 9705 # number of demand (read+write) misses 103810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 523623 # number of demand (read+write) misses 103910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1940506 # number of demand (read+write) misses 104010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 2486101 # number of demand (read+write) misses 104110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12267 # number of overall misses 104210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 9705 # number of overall misses 104310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 523623 # number of overall misses 104410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1940506 # number of overall misses 104510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 2486101 # number of overall misses 104610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 336739 # number of ReadReq accesses(hits+misses) 104710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149720 # number of ReadReq accesses(hits+misses) 104810726SN/Asystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4741809 # number of ReadReq accesses(hits+misses) 104910726SN/Asystem.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses) 105010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 9525661 # number of ReadReq accesses(hits+misses) 105110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 4032690 # number of Writeback accesses(hits+misses) 105210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 4032690 # number of Writeback accesses(hits+misses) 105310726SN/Asystem.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses) 105410726SN/Asystem.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses) 105510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137499 # number of UpgradeReq accesses(hits+misses) 105610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 137499 # number of UpgradeReq accesses(hits+misses) 105710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158828 # number of SCUpgradeReq accesses(hits+misses) 105810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 158828 # number of SCUpgradeReq accesses(hits+misses) 105910726SN/Asystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) 106010726SN/Asystem.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) 106110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 336739 # number of demand (read+write) accesses 106210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149720 # number of demand (read+write) accesses 106310726SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses 106410726SN/Asystem.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses 106510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 10841551 # number of demand (read+write) accesses 106610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 336739 # number of overall (read+write) accesses 106710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149720 # number of overall (read+write) accesses 106810726SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses 106910726SN/Asystem.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses 107010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 10841551 # number of overall (read+write) accesses 107110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for ReadReq accesses 107210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064821 # miss rate for ReadReq accesses 107310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110427 # miss rate for ReadReq accesses 107410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288339 # miss rate for ReadReq accesses 107510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.187357 # miss rate for ReadReq accesses 107610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.622463 # miss rate for WriteInvalidateReq accesses 107710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.622463 # miss rate for WriteInvalidateReq accesses 107810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.972138 # miss rate for UpgradeReq accesses 107910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.972138 # miss rate for UpgradeReq accesses 108010585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 108110585SN/Asystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 108210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533023 # miss rate for ReadExReq accesses 108310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.533023 # miss rate for ReadExReq accesses 108410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for demand accesses 108510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064821 # miss rate for demand accesses 108610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110427 # miss rate for demand accesses 108710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345699 # miss rate for demand accesses 108810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.229312 # miss rate for demand accesses 108910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036429 # miss rate for overall accesses 109010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064821 # miss rate for overall accesses 109110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110427 # miss rate for overall accesses 109210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345699 # miss rate for overall accesses 109310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.229312 # miss rate for overall accesses 109410585SN/Asystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 109510585SN/Asystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 109610585SN/Asystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 109710585SN/Asystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 109810585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 109910585SN/Asystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 110010585SN/Asystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 110110585SN/Asystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 110210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1183004 # number of writebacks 110310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1183004 # number of writebacks 110410585SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 110510726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution 110610726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution 110710726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution 110810726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution 110910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 4032690 # Transaction distribution 111010726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution 111110726SN/Asystem.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution 111210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 137499 # Transaction distribution 111310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158828 # Transaction distribution 111410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 296327 # Transaction distribution 111510726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution 111610726SN/Asystem.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution 111710726SN/Asystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes) 111810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16731086 # Packet count per connected master and slave (bytes) 111910726SN/Asystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) 112010726SN/Asystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) 112110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 27414408 # Packet count per connected master and slave (bytes) 112210726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) 112310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644698812 # Cumulative packet size per connected master and slave (bytes) 112410726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) 112510726SN/Asystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) 112610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 952972884 # Cumulative packet size per connected master and slave (bytes) 112710827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 3837128 # Total snoops (count) 112810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 19395843 # Request fanout histogram 112910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 1.220254 # Request fanout histogram 113010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.414418 # Request fanout histogram 113110585SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 113210585SN/Asystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 113310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 15123827 77.97% 77.97% # Request fanout histogram 113410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 4272016 22.03% 100.00% # Request fanout histogram 113510585SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 113610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 113710827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 113810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 19395843 # Request fanout histogram 113910726SN/Asystem.iobus.trans_dist::ReadReq 40295 # Transaction distribution 114010726SN/Asystem.iobus.trans_dist::ReadResp 40295 # Transaction distribution 114110726SN/Asystem.iobus.trans_dist::WriteReq 136634 # Transaction distribution 114210726SN/Asystem.iobus.trans_dist::WriteResp 29906 # Transaction distribution 114310585SN/Asystem.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 114410726SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) 114510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 114610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 114710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 114810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 114910585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 115010585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 115110585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 115210585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 115310585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 115410585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 115510585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 115610585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 115710585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 115810585SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 115910726SN/Asystem.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes) 116010726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) 116110726SN/Asystem.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) 116210585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 116310585SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 116410726SN/Asystem.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes) 116510726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes) 116610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 116710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 116810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 116910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 117010585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 117110585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 117210585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 117310585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 117410585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 117510585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 117610585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 117710585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 117810585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 117910585SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 118010726SN/Asystem.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes) 118110726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) 118210726SN/Asystem.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) 118310585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 118410585SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 118510726SN/Asystem.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes) 118610726SN/Asystem.iocache.tags.replacements 115585 # number of replacements 118710726SN/Asystem.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use 118810585SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 118910726SN/Asystem.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. 119010585SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 119110585SN/Asystem.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. 119210726SN/Asystem.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor 119310726SN/Asystem.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor 119410726SN/Asystem.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy 119510726SN/Asystem.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy 119610726SN/Asystem.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy 119710585SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 119810585SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 119910585SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 120010726SN/Asystem.iocache.tags.tag_accesses 1040793 # Number of tag accesses 120110726SN/Asystem.iocache.tags.data_accesses 1040793 # Number of data accesses 120210585SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 120310726SN/Asystem.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses 120410726SN/Asystem.iocache.ReadReq_misses::total 8913 # number of ReadReq misses 120510585SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 120610585SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 120710585SN/Asystem.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 120810585SN/Asystem.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 120910585SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 121010726SN/Asystem.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses 121110726SN/Asystem.iocache.demand_misses::total 8916 # number of demand (read+write) misses 121210585SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 121310726SN/Asystem.iocache.overall_misses::realview.ide 8876 # number of overall misses 121410726SN/Asystem.iocache.overall_misses::total 8916 # number of overall misses 121510585SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 121610726SN/Asystem.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) 121710726SN/Asystem.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) 121810585SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 121910585SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 122010585SN/Asystem.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 122110585SN/Asystem.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 122210585SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 122310726SN/Asystem.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses 122410726SN/Asystem.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses 122510585SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 122610726SN/Asystem.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses 122710726SN/Asystem.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses 122810585SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 122910585SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 123010585SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 123110585SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 123210585SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 123310585SN/Asystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 123410585SN/Asystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 123510585SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 123610585SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 123710585SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 123810585SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 123910585SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 124010585SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 124110585SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 124210585SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 124310585SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 124410585SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 124510585SN/Asystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 124610585SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 124710585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 124810585SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 124910585SN/Asystem.iocache.writebacks::writebacks 106694 # number of writebacks 125010585SN/Asystem.iocache.writebacks::total 106694 # number of writebacks 125110585SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 125210827Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1759191 # number of replacements 125310827Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62867.167491 # Cycle average of tags in use 125410827Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 3704436 # Total number of references to valid blocks. 125510827Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1817948 # Sample count of references to valid blocks. 125610827Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.037702 # Average number of references to valid blocks. 125710827Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 483416500 # Cycle when the warmup percentage was hit. 125810827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 35264.935108 # Average occupied blocks per requestor 125910827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 45.422401 # Average occupied blocks per requestor 126010827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 57.110376 # Average occupied blocks per requestor 126110827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3318.609191 # Average occupied blocks per requestor 126210827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 6952.273283 # Average occupied blocks per requestor 126310827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 314.594733 # Average occupied blocks per requestor 126410827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 425.085194 # Average occupied blocks per requestor 126510827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 2976.403767 # Average occupied blocks per requestor 126610827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 13512.733438 # Average occupied blocks per requestor 126710827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.538100 # Average percentage of cache occupancy 126810827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000693 # Average percentage of cache occupancy 126910827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000871 # Average percentage of cache occupancy 127010827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.050638 # Average percentage of cache occupancy 127110827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.106083 # Average percentage of cache occupancy 127210827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004800 # Average percentage of cache occupancy 127310827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.006486 # Average percentage of cache occupancy 127410827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.045416 # Average percentage of cache occupancy 127510827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.206188 # Average percentage of cache occupancy 127610827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.959277 # Average percentage of cache occupancy 127710827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id 127810827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 58530 # Occupied blocks per task id 127910726SN/Asystem.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 128010585SN/Asystem.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 128110827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 225 # Occupied blocks per task id 128210827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 128310827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id 128410827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3441 # Occupied blocks per task id 128510827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5617 # Occupied blocks per task id 128610827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 48852 # Occupied blocks per task id 128710827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003464 # Percentage of cache occupancy per task id 128810827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.893097 # Percentage of cache occupancy per task id 128910827Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 66366738 # Number of tag accesses 129010827Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 66366738 # Number of data accesses 129110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 6239 # number of ReadReq hits 129210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 4535 # number of ReadReq hits 129310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 509640 # number of ReadReq hits 129410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 744526 # number of ReadReq hits 129510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 5366 # number of ReadReq hits 129610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 3579 # number of ReadReq hits 129710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 482377 # number of ReadReq hits 129810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 691195 # number of ReadReq hits 129910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 2447457 # number of ReadReq hits 130010827Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2756140 # number of Writeback hits 130110827Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2756140 # number of Writeback hits 130210827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::cpu0.data 121071 # number of WriteInvalidateReq hits 130310827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::cpu1.data 98425 # number of WriteInvalidateReq hits 130410827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::total 219496 # number of WriteInvalidateReq hits 130510827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 13420 # number of UpgradeReq hits 130610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 10778 # number of UpgradeReq hits 130710827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 24198 # number of UpgradeReq hits 130810827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 1497 # number of SCUpgradeReq hits 130910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 1278 # number of SCUpgradeReq hits 131010827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 2775 # number of SCUpgradeReq hits 131110827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 202220 # number of ReadExReq hits 131210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 170877 # number of ReadExReq hits 131310827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 373097 # number of ReadExReq hits 131410827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 6239 # number of demand (read+write) hits 131510827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4535 # number of demand (read+write) hits 131610827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 509640 # number of demand (read+write) hits 131710827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 946746 # number of demand (read+write) hits 131810827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5366 # number of demand (read+write) hits 131910827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3579 # number of demand (read+write) hits 132010827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 482377 # number of demand (read+write) hits 132110827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 862072 # number of demand (read+write) hits 132210827Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2820554 # number of demand (read+write) hits 132310827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 6239 # number of overall hits 132410827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4535 # number of overall hits 132510827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 509640 # number of overall hits 132610827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 946746 # number of overall hits 132710827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5366 # number of overall hits 132810827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 3579 # number of overall hits 132910827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 482377 # number of overall hits 133010827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 862072 # number of overall hits 133110827Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2820554 # number of overall hits 133210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 2380 # number of ReadReq misses 133310726SN/Asystem.l2c.ReadReq_misses::cpu0.itb.walker 2011 # number of ReadReq misses 133410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 58293 # number of ReadReq misses 133510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 183599 # number of ReadReq misses 133610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 3469 # number of ReadReq misses 133710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.itb.walker 3462 # number of ReadReq misses 133810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 41246 # number of ReadReq misses 133910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 189649 # number of ReadReq misses 134010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 484109 # number of ReadReq misses 134110827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::cpu0.data 479323 # number of WriteInvalidateReq misses 134210827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::cpu1.data 160634 # number of WriteInvalidateReq misses 134310827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::total 639957 # number of WriteInvalidateReq misses 134410827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 58449 # number of UpgradeReq misses 134510827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 54093 # number of UpgradeReq misses 134610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 112542 # number of UpgradeReq misses 134710827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 7788 # number of SCUpgradeReq misses 134810827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 7462 # number of SCUpgradeReq misses 134910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 15250 # number of SCUpgradeReq misses 135010827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 377640 # number of ReadExReq misses 135110827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 418302 # number of ReadExReq misses 135210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 795942 # number of ReadExReq misses 135310827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2380 # number of demand (read+write) misses 135410726SN/Asystem.l2c.demand_misses::cpu0.itb.walker 2011 # number of demand (read+write) misses 135510827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 58293 # number of demand (read+write) misses 135610827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 561239 # number of demand (read+write) misses 135710827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3469 # number of demand (read+write) misses 135810827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 3462 # number of demand (read+write) misses 135910827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 41246 # number of demand (read+write) misses 136010827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 607951 # number of demand (read+write) misses 136110827Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1280051 # number of demand (read+write) misses 136210827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2380 # number of overall misses 136310726SN/Asystem.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses 136410827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 58293 # number of overall misses 136510827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 561239 # number of overall misses 136610827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3469 # number of overall misses 136710827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 3462 # number of overall misses 136810827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 41246 # number of overall misses 136910827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 607951 # number of overall misses 137010827Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1280051 # number of overall misses 137110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 8619 # number of ReadReq accesses(hits+misses) 137210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 6546 # number of ReadReq accesses(hits+misses) 137310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 567933 # number of ReadReq accesses(hits+misses) 137410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 928125 # number of ReadReq accesses(hits+misses) 137510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 8835 # number of ReadReq accesses(hits+misses) 137610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 7041 # number of ReadReq accesses(hits+misses) 137710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 523623 # number of ReadReq accesses(hits+misses) 137810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 880844 # number of ReadReq accesses(hits+misses) 137910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 2931566 # number of ReadReq accesses(hits+misses) 138010827Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2756140 # number of Writeback accesses(hits+misses) 138110827Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2756140 # number of Writeback accesses(hits+misses) 138210827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu0.data 600394 # number of WriteInvalidateReq accesses(hits+misses) 138310827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu1.data 259059 # number of WriteInvalidateReq accesses(hits+misses) 138410827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::total 859453 # number of WriteInvalidateReq accesses(hits+misses) 138510827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 71869 # number of UpgradeReq accesses(hits+misses) 138610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 64871 # number of UpgradeReq accesses(hits+misses) 138710827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 136740 # number of UpgradeReq accesses(hits+misses) 138810827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 9285 # number of SCUpgradeReq accesses(hits+misses) 138910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 8740 # number of SCUpgradeReq accesses(hits+misses) 139010827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 18025 # number of SCUpgradeReq accesses(hits+misses) 139110827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 579860 # number of ReadExReq accesses(hits+misses) 139210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 589179 # number of ReadExReq accesses(hits+misses) 139310827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 1169039 # number of ReadExReq accesses(hits+misses) 139410827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 8619 # number of demand (read+write) accesses 139510827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6546 # number of demand (read+write) accesses 139610827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 567933 # number of demand (read+write) accesses 139710827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1507985 # number of demand (read+write) accesses 139810827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 8835 # number of demand (read+write) accesses 139910827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 7041 # number of demand (read+write) accesses 140010827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 523623 # number of demand (read+write) accesses 140110827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1470023 # number of demand (read+write) accesses 140210827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4100605 # number of demand (read+write) accesses 140310827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 8619 # number of overall (read+write) accesses 140410827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6546 # number of overall (read+write) accesses 140510827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 567933 # number of overall (read+write) accesses 140610827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1507985 # number of overall (read+write) accesses 140710827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 8835 # number of overall (read+write) accesses 140810827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 7041 # number of overall (read+write) accesses 140910827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 523623 # number of overall (read+write) accesses 141010827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1470023 # number of overall (read+write) accesses 141110827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4100605 # number of overall (read+write) accesses 141210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for ReadReq accesses 141310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.307211 # miss rate for ReadReq accesses 141410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.102641 # miss rate for ReadReq accesses 141510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.197817 # miss rate for ReadReq accesses 141610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for ReadReq accesses 141710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.491692 # miss rate for ReadReq accesses 141810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.078770 # miss rate for ReadReq accesses 141910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.215304 # miss rate for ReadReq accesses 142010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.165137 # miss rate for ReadReq accesses 142110827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.798347 # miss rate for WriteInvalidateReq accesses 142210827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.620067 # miss rate for WriteInvalidateReq accesses 142310827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::total 0.744610 # miss rate for WriteInvalidateReq accesses 142410827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.813271 # miss rate for UpgradeReq accesses 142510827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.833855 # miss rate for UpgradeReq accesses 142610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.823036 # miss rate for UpgradeReq accesses 142710827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.838772 # miss rate for SCUpgradeReq accesses 142810827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.853776 # miss rate for SCUpgradeReq accesses 142910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.846047 # miss rate for SCUpgradeReq accesses 143010827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.651261 # miss rate for ReadExReq accesses 143110827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.709974 # miss rate for ReadExReq accesses 143210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.680852 # miss rate for ReadExReq accesses 143310827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for demand accesses 143410827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.307211 # miss rate for demand accesses 143510827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.102641 # miss rate for demand accesses 143610827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.372178 # miss rate for demand accesses 143710827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for demand accesses 143810827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.491692 # miss rate for demand accesses 143910827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.078770 # miss rate for demand accesses 144010827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.413566 # miss rate for demand accesses 144110827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.312161 # miss rate for demand accesses 144210827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for overall accesses 144310827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.307211 # miss rate for overall accesses 144410827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.102641 # miss rate for overall accesses 144510827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.372178 # miss rate for overall accesses 144610827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for overall accesses 144710827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.491692 # miss rate for overall accesses 144810827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.078770 # miss rate for overall accesses 144910827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.413566 # miss rate for overall accesses 145010827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.312161 # miss rate for overall accesses 145110515SN/Asystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 145210515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 145310515SN/Asystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 145410515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 145510515SN/Asystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 145610515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 145710515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 145810515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 145910827Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1464224 # number of writebacks 146010827Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1464224 # number of writebacks 146110515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 146210827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 575153 # Transaction distribution 146310827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 575153 # Transaction distribution 146410827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38802 # Transaction distribution 146510827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38802 # Transaction distribution 146610827Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1570918 # Transaction distribution 146710827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 742110 # Transaction distribution 146810827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 742110 # Transaction distribution 146910827Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 328170 # Transaction distribution 147010827Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 314483 # Transaction distribution 147110827Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 149857 # Transaction distribution 147210827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 965890 # Transaction distribution 147310827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 778455 # Transaction distribution 147410726SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) 147510585SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 147610726SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) 147710827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6331701 # Packet count per connected master and slave (bytes) 147810827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 6481921 # Packet count per connected master and slave (bytes) 147910726SN/Asystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes) 148010726SN/Asystem.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes) 148110827Sandreas.hansson@arm.comsystem.membus.pkt_count::total 6819903 # Packet count per connected master and slave (bytes) 148210726SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) 148310585SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 148410726SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) 148510827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215372636 # Cumulative packet size per connected master and slave (bytes) 148610827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 215583633 # Cumulative packet size per connected master and slave (bytes) 148710726SN/Asystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes) 148810726SN/Asystem.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes) 148910827Sandreas.hansson@arm.comsystem.membus.pkt_size::total 229813073 # Cumulative packet size per connected master and slave (bytes) 149010585SN/Asystem.membus.snoops 0 # Total snoops (count) 149110827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4535526 # Request fanout histogram 149210585SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 149310585SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 149410585SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 149510585SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 149610827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 4535526 100.00% 100.00% # Request fanout histogram 149710585SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 149810585SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 149910585SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 150010585SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 150110827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4535526 # Request fanout histogram 150210515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 150310515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 150410515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 150510515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 150610515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 150710515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 150810515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 150910515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 151010515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 151110515SN/Asystem.realview.ethernet.totBandwidth 164 # Total Bandwidth (bits/s) 151210515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 151310515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 151410515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 151510515SN/Asystem.realview.ethernet.txBandwidth 164 # Transmit Bandwidth (bits/s) 151610515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 151710515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 151810515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 151910515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 152010515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 152110515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 152210515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 152310515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 152410515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 152510515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 152610515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 152710515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 152810515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 152910515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 153010515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 153110515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 153210515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 153310515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 153410515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 153510515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 153610515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 153710515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 153810515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 153910515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 154010515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 154110515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 154210515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 154310515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 154410827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 3711525 # Transaction distribution 154510827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 3711525 # Transaction distribution 154610827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution 154710827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution 154810827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 2756140 # Transaction distribution 154910827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateReq 859453 # Transaction distribution 155010827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateResp 859453 # Transaction distribution 155110827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 330303 # Transaction distribution 155210827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 317258 # Transaction distribution 155310827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 647561 # Transaction distribution 155410827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1356474 # Transaction distribution 155510827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1356474 # Transaction distribution 155610827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8686436 # Packet count per connected master and slave (bytes) 155710827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7297334 # Packet count per connected master and slave (bytes) 155810827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 15983770 # Packet count per connected master and slave (bytes) 155910827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301115229 # Cumulative packet size per connected master and slave (bytes) 156010827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249782916 # Cumulative packet size per connected master and slave (bytes) 156110827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 550898145 # Cumulative packet size per connected master and slave (bytes) 156210827Sandreas.hansson@arm.comsystem.toL2Bus.snoops 117325 # Total snoops (count) 156310827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 9485599 # Request fanout histogram 156410827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.012192 # Request fanout histogram 156510827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.109740 # Request fanout histogram 156610515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 156710515SN/Asystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 156810827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 9369955 98.78% 98.78% # Request fanout histogram 156910827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 115644 1.22% 100.00% # Request fanout histogram 157010515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 157110515SN/Asystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 157210515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 157310827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 9485599 # Request fanout histogram 157410515SN/A 157510515SN/A---------- End Simulation Statistics ---------- 1576